This commit prevents the device from "hanging" when using lightsleep while
the WiFi chip is active.
Whenever the WiFi chip wants to interrupt the microcontroller to notify it
for a new package, it sets the CYW43_PIN_WL_HOST_WAKE pin to high,
triggering an IRQ. However, as polling the chip cannot happen in an
interrupt handler, it subsequently notifies the pendsv-service to do a poll
as soon as the interrupt handler ended. In order to prevent a new
interrupt from happening immediately afterwards, even before the poll has
run, the IRQ handler disables interrupts from the pin.
The first problem occurs, when a WiFi package arrives while the main loop
is in cyw43-code. In order to prevent concurrent access of the hardware,
the network code blocks pendsv from running again while entering lwIP code.
The same holds for direct cyw43 code (like changing the cyw43-gpios, i.e.
the LED on the Pico W). While the pendsv is disabled, interrupts can still
occur to schedule a poll (and disable further interrupts), but it will not
run. This can happen while the microcontroller is anywhere in rp2040 code.
In order to preserve power while waiting for cyw43 responses,
cyw43_configport.h defines CYW43_DO_IOCTL_WAIT and
CYW43_SDPCM_SEND_COMMON_WAIT to __WFI(). While this might work in most
cases, there are 2 edge cases where it fails:
- When an interrupt has already been received by the cyw43 stack, for
example due to an incoming ethernet packet.
- When the interrupt from the cyw43 response comes before the
microcontroller entered the __WFI() instruction.
When that happens, wfi will just block forever as no further interrupts are
received. The only way to safely use wfi to wake up from an interrupt is
inside a critical section, as this delays interrupts until the wfi is
entered, possibly resuming immediately until interrupts are reenabled and
the interrupt handler is run. Additionally this critical section needs to
check whether the interrupt has already been disabled and pendsv was
triggered, as in such a case, wfi can never be woken up, and needs to be
skipped, because there is already a package from the network chip waiting.
Note that this turns cyw43_yield into a nop (and thereby the cyw43-loops
into busy waits) from the second time onwards, as after the first call, a
pendsv request will definitely be pending. More logic could be added, to
explicitly enable the interrupt in this case.
Regarding lightsleep, this code has a similar problem. When an interrupt
occurs during lightsleep, the IRQ and pendsv handler and thereby poll are
run immediately, with the clocks still disabled, causing the SPI transfers
to fail. If we don't want to add complex logic inside the IRQ handler we
need to protect the whole lightsleep procedure form interrupts with a
critical section, exiting out early if an interrupt is pending for whatever
reason. Only then we can start to shut down clocks and only enable
interrupts when the system is ready again. Other interrupt handlers might
also be happy, that they are only run when the system is fully operational.
Tested on a Pico W, calling machine.lightsleep() within an endless loop and
pinging from the outside.
This required to add two functions down the stack to uart.c and ra.sci.c.
- One for telling, whther the transmission is busy.
- One for reporting the size of the TX buffer.
Tested with a EK-RA6M2 board.
See the previous commit, except in this case the customisation didn't
actually do anything so can just be removed.
This work was funded through GitHub Sponsors.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
This was previously implemented by adding additional members to the
mp_obj_type_t defined for each NIC, which is difficult to do cleanly with
the new object type slots mechanism. The way this works is also not
supported on GCC 8.x and below.
Instead replace it with the type protocol, which is a much simpler way of
achieving the same thing.
This affects the WizNet (in non-LWIP mode) and Nina NIC drivers.
This work was funded through GitHub Sponsors.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
Changes in this commit:
- Clear and mask D2 EXTIs.
- Set correct voltage scaling level for standby mode.
- Disable debug MCU (if debugging is disabled), for all MCU series.
It keeps compatibility with the XIAO bootloader by:
- using Soft Device 7.3.0
- reserving 48k memory for the bootloader.
So on double reset a drive pops for uploading an uf2 image or a nrfutil zip
pkg file. Instructions to create it from a hex file are included. The
bootloader can as well be activated with the touch 1200 option of nrfutil.
The script download_ble_stack.sh has been adapted to get the version 7.3.0
soft device files. It may have to be executed once before building.
The file system is set to 256k and the pin definitions are adapted.
Besides that, it has the common functionality and omissions. The on-board
sensors and additional flash can be supported by Python scripts.
This was introduced by 35fb90bd57, but
it is much simpler and essentially the same to just use
`tud_cdc_n_connected()`.
The only difference is that tud_cdc_n_connected() only checks for DTR,
but this is correct anyway: DTR indicates device presence, RTS indicates
that the host wants to receive data.
Signed-off-by: Damien Tournoud <damien@platform.sh>
usocket_events_deinit will only be available if MICROPY_PY_USOCKET_EVENTS
is enabled (which is only enabled when webrepl is enabled).
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
ADC: The argument of vref=num is an integer. Values for num are:
SAMD21:
0 INT1V 1.0V voltage reference
1 INTVCC0 1/1.48 Analog voltage supply
2 INTVCC1 1/2 Analog voltage supply (only for VDDANA > 2.0V)
3 VREFA External reference
4 VREFB External reference
SAMD51:
0 INTREF internal bandgap reference
1 INTVCC1 Analog voltage supply
2 INTVCC0 1/2 Analog voltage supply (only for VDDANA > 2.0v)
3 AREFA External reference A
4 AREFB External reference B
5 AREFC External reference C (ADC1 only)
DAC: The argument of vref=num is an integer. Suitable values:
SAMD21:
0 INT1V Internal voltage reference
1 VDDANA Analog voltage supply
2 VREFA External reference
SAMD51:
0 INTREF Internal bandgap reference
1 VDDANA Analog voltage supply
2 VREFAU Unbuffered external voltage reference (not buffered in DAC)
4 VREFAB Buffered external voltage reference (buffered in DAC).
Changes in this commit:
- Do not deinit IRQ when uart.deinit() is called with an inactive object.
- Remove using it for the finaliser. There is another machanism for soft
reset, and it is not needed otherwise.
- Do not tag the UART buffers with MP_STATE_PORT, it is not required.
Clearing the DRE flag for the transmit interrupt at the end of a
uart.write() also cleared the RXC flag disabling the receive interrupt.
This commit also changes the flag set/clear mechanism in the driver for SPI
as well, even if it did not cause a problem there. But at least it saves a
few bytes of code.
Applies to both SPI and I2C. The underflow caused high baudrate settings
resulting in the lowest possible baudrate. The overflow resulted in
erratic baudrates, not just the lowest possible.
The datasheet on page 55 shows PF0 (SDA) and PF1 (SCL) are the pins for
I2C2, but these pins do not work. Checking the MBED pinout for the
NUCLEO-F429ZI shows:
I2C1: PB8 (SCL) and PB9 (SDA).
I2C2: PB10 (SCL) and PB11 (SDA).
Both of these work and can be scanned and find devices connected to them.
Signed-off-by: Dale Weber <hybotics.sd@gmail.com>.
This changes the signatures of QSPI write_cmd_data, write_cmd_addr_data and
read_cmd_qaddr_qdata so they return an error code. The softqspi and stm32
hardware qspi driver are updated to follow this new signature. Also the
spiflash driver is updated to use these new return values.
Signed-off-by: Damien George <damien@micropython.org>
The assertion that is added here (to gc.c) fails when running this new test
if ALLOC_TABLE_GAP_BYTE is set to 0.
Signed-off-by: Jeff Epler <jepler@gmail.com>
Signed-off-by: Damien George <damien@micropython.org>
The STM32H7xx HAL LPUART AF macros are missing the number, this HAL is the
only one that's inconsistent in the way it defines LPUART AF macros, so we
only need to define them for H7.
Prior to this commit, only sector 0 was erase/write protected, which may
not be enough to protect all of mboot (especially if mboot lives at a
higher address than the start of flash).
This commit makes sure all internal flash sectors that mboot lives in are
protected from erasing and writing. The linker script must define
_mboot_writable_flash_start for this to work.
Signed-off-by: Damien George <damien@micropython.org>
The original ESP32 only supports timer source clock APB so it doesn't need
and doesn't have a clk_src field.
The ESP32C3 supports timer source clock APB and XTAL so it does have a
clk_src field, and this needs to be configured to get the correct period.
Fixes#8084.
Follow up to 8a91c719 to no longer explicitly disable BLE in
mpconfigport.h.
This work was funded through GitHub Sponsors.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
For STM32L4, hardware I2C can be implemented by using TIMINGR.
This commit enables:
- Use of hardware I2C in machine.I2C.
- Specifying a frequency greater than or equal to 400KHz with pyb.I2C.
For STM32L4 series, the internal sensors are connected to:
- ADC1_IN0: Internal voltage reference
- ADC1_IN17: Temperature sensor
- ADC1_IN18: VBAT battery voltage monitoring
but ADC_CHANNEL_VREFINT, ADC_CHANNEL_VBAT, ADC_CHANNEL_TEMPSENSOR are not
defined as 0, 17, 18.
This commit converts channel 0, 17, 18 to ADC_CHANNEL_x in
adc_get_internal_channel().
Prior to this commit, the actual I2C frequency can be faster than specified
one and it may exceed the I2C's specification for Fast Mode. The frequency
of SCL should be less than or equal to 400KHz in Fast Mode.
This commit fixes this issue for F4 MCUs by rounding up the division in the
frequency calculation.
Excuting the code:
i2c = I2C(1, I2C.CONTROLLER, dma=True)
tmp = i2c.recv(1, i2c_addr)
recv_data = bytearray(56)
i2c.recv(recv_data, i2c_addr)
The second i2c.recv() fails with OSError: [Errno 110] ETIMEDOUT. When
receiving greater than or equal to 2 bytes at first i2c.recv(), the second
i2c.recv() succeeds. This issue does not occur without DMA.
Details of change: when executing I2C with DMA:
- Bit 11 of I2Cx_CR2 (DMA Request Enable) should be 1 to indicate that DMA
transfer is enabled. This bit is set after I2C event interrupt is
enabled in HAL_I2C_Master_Transmit_DMA()/HAL_I2C_Master_Receive_DMA(), so
DMA Request Enable bit might be 0 in IRQHandler.
- In case of data receive:
- When only 1 byte receiption, clear I2Cx_CR1's bit 10 (ACK).
- When only 2 byte receiption, clear I2Cx_CR1's bit 10 (ACK) and set
bit 11 (POS).
- When greater than or equal to 2 byte receiption, bit 12 of I2Cx_CR2
(DMA Last Transfer) should set to generate NACK when DMA transfer
completed.
Otherwise, the I2C bus may be busy after received data from peripheral.
Instead of defining `MICROPY_PY_BTREE` in `mpconfigport.h` we can define
it via CMake similar to how other ports that use Makefiles define it in
`mpconfigport.mk`.
Signed-off-by: David Lechner <david@pybricks.com>
