Commit Graph

19 Commits

Author SHA1 Message Date
Damien George
54f1694ab6 drivers/bus: Rename MP_SPI_ADDR_IS_32B to MICROPY_HW_SPI_ADDR_IS_32BIT.
And allow it to be configured externally, if needed.

Signed-off-by: Damien George <damien@micropython.org>
2022-06-02 14:30:51 +10:00
iabdalkader
32914c53ef stm32/qspi: Workaround for SR set immediately after setting AR.
See issue #5441.  This issue is now reproducible on the Arduino Portenta
H747, QSPI flash PN MX25L12833F.
2022-04-26 22:33:05 +10:00
iabdalkader
5974ac256b stm32/qspi: Wait for a free FIFO location before writing to DR.
Must always check the FIFO before writing to DR.  Without this, this
function hangs on the H747.
2022-04-26 22:32:48 +10:00
iabdalkader
b28839420d stm32/qspi: Support common flash sizes in MPU configuration.
Add MPU configuration for common flash sizes up to 256MiB.
2022-04-26 22:32:29 +10:00
iabdalkader
1dc532019b stm32/qspi: Fix typo in address comment. 2021-12-19 17:48:00 +11:00
Damien George
69661f3343 all: Reformat C and Python source code with tools/codeformat.py.
This is run with uncrustify 0.70.1, and black 19.10b0.
2020-02-28 10:33:03 +11:00
Andrew Leech
30501d3f54 drivers, stm32: Support SPI/QSPI flash chips over 16MB.
With a SPI flash that has more than 16MB, 32-bit addressing is required
rather than the standard 24-bit.  This commit adds support for 32-bit
addressing so that the SPI flash commands (read/write/erase) are selected
automatically depending on the size of the address being used at each
operation.
2020-01-30 13:18:38 +11:00
Damien George
4f2c737b0c stm32/mpu: Save and restore the IRQ state when configuring MPU.
In case IRQs are already disabled during the MPU configuration.

Fixes issue #5152.
2019-10-16 23:12:06 +11:00
Damien George
caabdd99c0 stm32/qspi: Handle bus acquisition.
When going out of memory-mapped mode to do a control transfer to the QSPI
flash, the MPU settings must be changed to forbid access to the memory
mapped region.  And any ongoing transfer (eg memory mapped continuous read)
must be aborted.
2019-07-03 01:27:33 +10:00
Damien George
2034c0a2e3 stm32/qspi: Force a reset of the QSPI peripheral when initialising it.
To ensure it is in a known state on start up.
2019-07-03 01:27:33 +10:00
Damien George
8da39fd182 stm32/qspi: Use MPU to allow access to valid memory-mapped QSPI region.
The Cortex-M7 CPU will do speculative loads from any memory location that
is not explicitly forbidden.  This includes the QSPI memory-mapped region
starting at 0x90000000 and with size 256MiB.  Speculative loads to this
QSPI region may 1) interfere with the QSPI peripheral registers (eg the
address register) if the QSPI is not in memory-mapped mode; 2) attempt to
access data outside the configured size of the QSPI flash when it is in
memory-mapped mode.  Both of these scenarios will lead to issues with the
QSPI peripheral (eg Cortex bus lock up in scenario 2).

To prevent such speculative loads from interfering with the peripheral the
MPU is configured in this commit to restrict access to the QSPI mapped
region: when not memory mapped the entire region is forbidden; when memory
mapped only accesses to the valid flash size are permitted.
2019-07-03 01:27:33 +10:00
Andrew Leech
0c60cb1fc4 stm32/qspi: Set pin speed to very-high and allow to config some options.
The default speed of the QSPI interface is 72Mhz whereas the standard AF
pin speed (high) is only rated to 50Mhz, so increase speed to very-high.
2019-03-08 23:17:50 +11:00
Damien George
f8f2724297 stm32/qspi: Enable sample shift and disable timeout counter.
This makes the QSPI more robust, in particular the timeout counter should
not be used with memory mapped mode (see F7 errata).
2019-03-01 16:15:14 +11:00
Andrew Leech
4daee31706 stm32/qspi: Use static af functions for pin configuration.
This allows qspi pin configuration to work on any supported platform.
2019-02-14 13:42:08 +11:00
Damien George
7f41f73f0f stm32/qspi: Don't require data reads and writes to be a multiple of 4.
Prior to this patch the QSPI driver assumed that the length of all data
reads and writes was a multiple of 4.  This patch allows any length.  Reads
are optimised for speed by using 32-bit transfers when possible, but writes
always use a byte transfer because they only use a single data IO line and
are relatively slow.
2018-06-22 15:07:01 +10:00
Damien George
6f1e857624 stm32/qspi: Don't take the address of pin configuration identifiers.
Taking the address assumes that the pin is an object (eg a struct), but it
could be a literal (eg an int).  Not taking the address makes this driver
more general for other uses.
2018-03-27 20:34:55 +11:00
Damien George
6b51eb22c8 stm32: Consolidate include of genhdr/pins.h to single location in pin.h.
genhdr/pins.h is an internal header file that defines all of the pin
objects and it's cleaner to have pin.h include it (where the struct's for
these objects are defined) rather than an explicit include by every user.
2018-03-27 20:25:24 +11:00
Damien George
1345093401 stm32/qspi: Do an explicit read instead of using memory-mapped mode.
Using an explicit read eliminates the need to invalidate the D-cache after
enabling the memory mapping mode, which takes additional time.
2018-03-11 18:28:48 +11:00
Damien George
adda38cf76 stm32/qspi: Add hardware QSPI driver, with memory-map capability.
It supports the abstract QSPI protocol defined in drivers/bus/qspi.h.
2018-03-03 00:17:08 +11:00