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The major setting is about the PHY interface configuration. The configuration matches the Olimex ESP32 Gateway as well. Tested with esp-idf v4.2.4 and Olimex ESP32 POE boards.
5 lines
132 B
Plaintext
5 lines
132 B
Plaintext
CONFIG_ETH_PHY_INTERFACE_RMII=y
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CONFIG_ETH_RMII_CLK_OUTPUT=y
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CONFIG_ETH_RMII_CLK_OUT_GPIO=17
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CONFIG_LWIP_LOCAL_HOSTNAME="ESP32_POE"
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