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3ef911345c
This patch updates ST's HAL to the latest version, V1.3.0, dated 19 June 2014. Files were copied verbatim from the ST package. Only change was to suppress compiler warning of unused variables in 4 places. A lot of the changes from ST are cosmetic: comments and white space. Some small code changes here and there, and addition of F411 header. Main code change is how SysTick interrupt is set: it now has a configuration variable to set the priority, so we no longer need to work around this (originall in system_stm32f4xx.c).
1057 lines
33 KiB
C
1057 lines
33 KiB
C
/**
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******************************************************************************
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* @file stm32f4xx_hal_nand.c
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* @author MCD Application Team
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* @version V1.1.0
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* @date 19-June-2014
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* @brief NAND HAL module driver.
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* This file provides a generic firmware to drive NAND memories mounted
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* as external device.
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*
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@verbatim
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==============================================================================
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##### How to use this driver #####
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==============================================================================
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[..]
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This driver is a generic layered driver which contains a set of APIs used to
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control NAND flash memories. It uses the FMC/FSMC layer functions to interface
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with NAND devices. This driver is used as follows:
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(+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
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with control and timing parameters for both common and attribute spaces.
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(+) Read NAND flash memory maker and device IDs using the function
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HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
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structure declared by the function caller.
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(+) Access NAND flash memory by read/write operations using the functions
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HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea()
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to read/write page(s)/spare area(s). These functions use specific device
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information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef
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structure. The read/write address information is contained by the Nand_Address_Typedef
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structure passed as parameter.
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(+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
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(+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
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The erase block address information is contained in the Nand_Address_Typedef
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structure passed as parameter.
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(+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
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(+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
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HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
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feature or the function HAL_NAND_GetECC() to get the ECC correction code.
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(+) You can monitor the NAND device HAL state by calling the function
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HAL_NAND_GetState()
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[..]
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(@) This driver is a set of generic APIs which handle standard NAND flash operations.
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If a NAND flash device contains different operations and/or implementations,
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it should be implemented separately.
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@endverbatim
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx_hal.h"
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/** @addtogroup STM32F4xx_HAL_Driver
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* @{
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*/
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/** @defgroup NAND
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* @brief NAND driver modules
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* @{
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*/
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#ifdef HAL_NAND_MODULE_ENABLED
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#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/** @defgroup NAND_Private_Functions
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* @{
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*/
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/** @defgroup NAND_Group1 Initialization and de-initialization functions
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* @brief Initialization and Configuration functions
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*
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@verbatim
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==============================================================================
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##### NAND Initialization and de-initialization functions #####
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==============================================================================
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[..]
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This section provides functions allowing to initialize/de-initialize
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the NAND memory
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@endverbatim
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* @{
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*/
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/**
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* @brief Perform NAND memory Initialization sequence
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* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
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* the configuration information for NAND module.
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* @param ComSpace_Timing: pointer to Common space timing structure
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* @param AttSpace_Timing: pointer to Attribute space timing structure
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
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{
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/* Check the NAND handle state */
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if(hnand == NULL)
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{
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return HAL_ERROR;
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}
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if(hnand->State == HAL_NAND_STATE_RESET)
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{
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/* Initialize the low level hardware (MSP) */
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HAL_NAND_MspInit(hnand);
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}
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/* Initialize NAND control Interface */
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FMC_NAND_Init(hnand->Instance, &(hnand->Init));
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/* Initialize NAND common space timing Interface */
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FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
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/* Initialize NAND attribute space timing Interface */
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FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
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/* Enable the NAND device */
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__FMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
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/* Update the NAND controller state */
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hnand->State = HAL_NAND_STATE_READY;
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return HAL_OK;
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}
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/**
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* @brief Perform NAND memory De-Initialization sequence
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* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
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* the configuration information for NAND module.
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
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{
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/* Initialize the low level hardware (MSP) */
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HAL_NAND_MspDeInit(hnand);
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/* Configure the NAND registers with their reset values */
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FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
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/* Reset the NAND controller state */
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hnand->State = HAL_NAND_STATE_RESET;
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/* Release Lock */
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__HAL_UNLOCK(hnand);
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return HAL_OK;
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}
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/**
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* @brief NAND MSP Init
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* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
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* the configuration information for NAND module.
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* @retval None
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*/
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__weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
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{
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/* NOTE : This function Should not be modified, when the callback is needed,
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the HAL_NAND_MspInit could be implemented in the user file
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*/
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}
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/**
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* @brief NAND MSP DeInit
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* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
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* the configuration information for NAND module.
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* @retval None
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*/
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__weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
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{
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/* NOTE : This function Should not be modified, when the callback is needed,
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the HAL_NAND_MspDeInit could be implemented in the user file
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*/
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}
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/**
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* @brief This function handles NAND device interrupt request.
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* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
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* the configuration information for NAND module.
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* @retval HAL status
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*/
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void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
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{
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/* Check NAND interrupt Rising edge flag */
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if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))
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{
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/* NAND interrupt callback*/
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HAL_NAND_ITCallback(hnand);
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/* Clear NAND interrupt Rising edge pending bit */
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__FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE);
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}
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/* Check NAND interrupt Level flag */
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if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))
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{
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/* NAND interrupt callback*/
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HAL_NAND_ITCallback(hnand);
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/* Clear NAND interrupt Level pending bit */
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__FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL);
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}
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/* Check NAND interrupt Falling edge flag */
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if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))
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{
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/* NAND interrupt callback*/
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HAL_NAND_ITCallback(hnand);
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/* Clear NAND interrupt Falling edge pending bit */
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__FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE);
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}
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/* Check NAND interrupt FIFO empty flag */
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if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))
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{
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/* NAND interrupt callback*/
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HAL_NAND_ITCallback(hnand);
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/* Clear NAND interrupt FIFO empty pending bit */
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__FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT);
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}
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}
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/**
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* @brief NAND interrupt feature callback
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* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
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* the configuration information for NAND module.
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* @retval None
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*/
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__weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
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{
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/* NOTE : This function Should not be modified, when the callback is needed,
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the HAL_NAND_ITCallback could be implemented in the user file
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*/
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}
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/**
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* @}
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*/
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/** @defgroup NAND_Group2 Input and Output functions
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* @brief Input Output and memory control functions
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*
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@verbatim
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==============================================================================
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##### NAND Input and Output functions #####
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==============================================================================
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[..]
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This section provides functions allowing to use and control the NAND
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memory
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@endverbatim
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* @{
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*/
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/**
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* @brief Read the NAND memory electronic signature
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* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
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* the configuration information for NAND module.
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* @param pNAND_ID: NAND ID structure
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
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{
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__IO uint32_t data = 0;
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uint32_t deviceAddress = 0;
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/* Process Locked */
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__HAL_LOCK(hnand);
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/* Check the NAND controller state */
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if(hnand->State == HAL_NAND_STATE_BUSY)
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{
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return HAL_BUSY;
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}
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/* Identify the device address */
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if(hnand->Init.NandBank == FMC_NAND_BANK2)
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{
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deviceAddress = NAND_DEVICE1;
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}
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else
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{
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deviceAddress = NAND_DEVICE2;
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}
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/* Update the NAND controller state */
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hnand->State = HAL_NAND_STATE_BUSY;
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/* Send Read ID command sequence */
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*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_READID;
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*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
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/* Read the electronic signature from NAND flash */
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data = *(__IO uint32_t *)deviceAddress;
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/* Return the data read */
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pNAND_ID->Maker_Id = __ADDR_1st_CYCLE(data);
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pNAND_ID->Device_Id = __ADDR_2nd_CYCLE(data);
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pNAND_ID->Third_Id = __ADDR_3rd_CYCLE(data);
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pNAND_ID->Fourth_Id = __ADDR_4th_CYCLE(data);
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/* Update the NAND controller state */
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hnand->State = HAL_NAND_STATE_READY;
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/* Process unlocked */
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__HAL_UNLOCK(hnand);
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return HAL_OK;
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}
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/**
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* @brief NAND memory reset
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* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
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* the configuration information for NAND module.
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
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{
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uint32_t deviceAddress = 0;
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/* Process Locked */
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__HAL_LOCK(hnand);
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/* Check the NAND controller state */
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if(hnand->State == HAL_NAND_STATE_BUSY)
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{
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return HAL_BUSY;
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}
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/* Identify the device address */
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if(hnand->Init.NandBank == FMC_NAND_BANK2)
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{
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deviceAddress = NAND_DEVICE1;
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}
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else
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{
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deviceAddress = NAND_DEVICE2;
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}
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/* Update the NAND controller state */
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hnand->State = HAL_NAND_STATE_BUSY;
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/* Send NAND reset command */
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*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0xFF;
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/* Update the NAND controller state */
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hnand->State = HAL_NAND_STATE_READY;
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/* Process unlocked */
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__HAL_UNLOCK(hnand);
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return HAL_OK;
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}
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/**
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* @brief Read Page(s) from NAND memory block
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* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
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* the configuration information for NAND module.
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* @param pAddress : pointer to NAND address structure
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* @param pBuffer : pointer to destination read buffer
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* @param NumPageToRead : number of pages to read from block
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
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{
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__IO uint32_t index = 0;
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uint32_t deviceAddress = 0, numPagesRead = 0, nandAddress = 0, addressStatus = NAND_VALID_ADDRESS;
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/* Process Locked */
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__HAL_LOCK(hnand);
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/* Check the NAND controller state */
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if(hnand->State == HAL_NAND_STATE_BUSY)
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{
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return HAL_BUSY;
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}
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/* Identify the device address */
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if(hnand->Init.NandBank == FMC_NAND_BANK2)
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{
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deviceAddress = NAND_DEVICE1;
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}
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else
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{
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deviceAddress = NAND_DEVICE2;
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}
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/* Update the NAND controller state */
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hnand->State = HAL_NAND_STATE_BUSY;
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/* Page(s) read loop */
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while((NumPageToRead != 0) && (addressStatus == NAND_VALID_ADDRESS))
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{
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/* NAND raw address calculation */
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nandAddress = __ARRAY_ADDRESS(pAddress, hnand);
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/* Send read page command sequence */
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*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
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*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
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*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_1st_CYCLE(nandAddress);
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*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_2nd_CYCLE(nandAddress);
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*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_3rd_CYCLE(nandAddress);
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/* for 512 and 1 GB devices, 4th cycle is required */
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if(hnand->Info.BlockNbr > 1024)
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{
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*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_4th_CYCLE(nandAddress);
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}
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*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
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/* Get Data into Buffer */
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for(index = 0 ; index < hnand->Info.PageSize; index++)
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{
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*(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;
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}
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/* Increment read pages number */
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numPagesRead++;
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/* Decrement pages to read */
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NumPageToRead--;
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/* Increment the NAND address */
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HAL_NAND_Address_Inc(hnand, pAddress);
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}
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/* Update the NAND controller state */
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hnand->State = HAL_NAND_STATE_READY;
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/* Process unlocked */
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__HAL_UNLOCK(hnand);
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return HAL_OK;
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}
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/**
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* @brief Write Page(s) to NAND memory block
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* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
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* the configuration information for NAND module.
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* @param pAddress : pointer to NAND address structure
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* @param pBuffer : pointer to source buffer to write
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* @param NumPageToWrite : number of pages to write to block
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
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{
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__IO uint32_t index = 0;
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|
uint32_t tickstart = 0;
|
|
uint32_t deviceAddress = 0 , numPagesWritten = 0, nandAddress = 0, addressStatus = NAND_VALID_ADDRESS;
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hnand);
|
|
|
|
/* Check the NAND controller state */
|
|
if(hnand->State == HAL_NAND_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
|
|
/* Identify the device address */
|
|
if(hnand->Init.NandBank == FMC_NAND_BANK2)
|
|
{
|
|
deviceAddress = NAND_DEVICE1;
|
|
}
|
|
else
|
|
{
|
|
deviceAddress = NAND_DEVICE2;
|
|
}
|
|
|
|
/* Update the NAND controller state */
|
|
hnand->State = HAL_NAND_STATE_BUSY;
|
|
|
|
/* Page(s) write loop */
|
|
while((NumPageToWrite != 0) && (addressStatus == NAND_VALID_ADDRESS))
|
|
{
|
|
/* NAND raw address calculation */
|
|
nandAddress = __ARRAY_ADDRESS(pAddress, hnand);
|
|
|
|
/* Send write page command sequence */
|
|
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
|
|
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
|
|
|
|
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
|
|
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_1st_CYCLE(nandAddress);
|
|
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_2nd_CYCLE(nandAddress);
|
|
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_3rd_CYCLE(nandAddress);
|
|
|
|
/* for 512 and 1 GB devices, 4th cycle is required */
|
|
if(hnand->Info.BlockNbr > 1024)
|
|
{
|
|
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_4th_CYCLE(nandAddress);
|
|
}
|
|
|
|
/* Write data to memory */
|
|
for(index = 0 ; index < hnand->Info.PageSize; index++)
|
|
{
|
|
*(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++;
|
|
}
|
|
|
|
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
|
|
|
|
/* Read status until NAND is ready */
|
|
while(HAL_NAND_Read_Status(hnand) != NAND_READY)
|
|
{
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
|
|
/* Increment written pages number */
|
|
numPagesWritten++;
|
|
|
|
/* Decrement pages to write */
|
|
NumPageToWrite--;
|
|
|
|
/* Increment the NAND address */
|
|
HAL_NAND_Address_Inc(hnand, pAddress);
|
|
|
|
}
|
|
|
|
/* Update the NAND controller state */
|
|
hnand->State = HAL_NAND_STATE_READY;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnand);
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
|
|
/**
|
|
* @brief Read Spare area(s) from NAND memory
|
|
* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
|
|
* the configuration information for NAND module.
|
|
* @param pAddress : pointer to NAND address structure
|
|
* @param pBuffer: pointer to source buffer to write
|
|
* @param NumSpareAreaToRead: Number of spare area to read
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
|
|
{
|
|
__IO uint32_t index = 0;
|
|
uint32_t deviceAddress = 0, numSpareAreaRead = 0, nandAddress = 0, addressStatus = NAND_VALID_ADDRESS;
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hnand);
|
|
|
|
/* Check the NAND controller state */
|
|
if(hnand->State == HAL_NAND_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
|
|
/* Identify the device address */
|
|
if(hnand->Init.NandBank == FMC_NAND_BANK2)
|
|
{
|
|
deviceAddress = NAND_DEVICE1;
|
|
}
|
|
else
|
|
{
|
|
deviceAddress = NAND_DEVICE2;
|
|
}
|
|
|
|
/* Update the NAND controller state */
|
|
hnand->State = HAL_NAND_STATE_BUSY;
|
|
|
|
/* Spare area(s) read loop */
|
|
while((NumSpareAreaToRead != 0) && (addressStatus == NAND_VALID_ADDRESS))
|
|
{
|
|
/* NAND raw address calculation */
|
|
nandAddress = __ARRAY_ADDRESS(pAddress, hnand);
|
|
|
|
/* Send read spare area command sequence */
|
|
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
|
|
|
|
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
|
|
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_1st_CYCLE(nandAddress);
|
|
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_2nd_CYCLE(nandAddress);
|
|
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_3rd_CYCLE(nandAddress);
|
|
|
|
/* for 512 and 1 GB devices, 4th cycle is required */
|
|
if(hnand->Info.BlockNbr > 1024)
|
|
{
|
|
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_4th_CYCLE(nandAddress);
|
|
}
|
|
|
|
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
|
|
|
|
/* Get Data into Buffer */
|
|
for(index = 0 ; index < hnand->Info.SpareAreaSize; index++)
|
|
{
|
|
*(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;
|
|
}
|
|
|
|
/* Increment read spare areas number */
|
|
numSpareAreaRead++;
|
|
|
|
/* Decrement spare areas to read */
|
|
NumSpareAreaToRead--;
|
|
|
|
/* Increment the NAND address */
|
|
HAL_NAND_Address_Inc(hnand, pAddress);
|
|
}
|
|
|
|
/* Update the NAND controller state */
|
|
hnand->State = HAL_NAND_STATE_READY;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnand);
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Write Spare area(s) to NAND memory
|
|
* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
|
|
* the configuration information for NAND module.
|
|
* @param pAddress : pointer to NAND address structure
|
|
* @param pBuffer : pointer to source buffer to write
|
|
* @param NumSpareAreaTowrite : number of spare areas to write to block
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
|
|
{
|
|
__IO uint32_t index = 0;
|
|
uint32_t tickstart = 0;
|
|
uint32_t deviceAddress = 0, numSpareAreaWritten = 0, nandAddress = 0, addressStatus = NAND_VALID_ADDRESS;
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hnand);
|
|
|
|
/* Check the NAND controller state */
|
|
if(hnand->State == HAL_NAND_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
|
|
/* Identify the device address */
|
|
if(hnand->Init.NandBank == FMC_NAND_BANK2)
|
|
{
|
|
deviceAddress = NAND_DEVICE1;
|
|
}
|
|
else
|
|
{
|
|
deviceAddress = NAND_DEVICE2;
|
|
}
|
|
|
|
/* Update the FMC_NAND controller state */
|
|
hnand->State = HAL_NAND_STATE_BUSY;
|
|
|
|
/* Spare area(s) write loop */
|
|
while((NumSpareAreaTowrite != 0) && (addressStatus == NAND_VALID_ADDRESS))
|
|
{
|
|
/* NAND raw address calculation */
|
|
nandAddress = __ARRAY_ADDRESS(pAddress, hnand);
|
|
|
|
/* Send write Spare area command sequence */
|
|
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
|
|
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
|
|
|
|
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
|
|
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_1st_CYCLE(nandAddress);
|
|
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_2nd_CYCLE(nandAddress);
|
|
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_3rd_CYCLE(nandAddress);
|
|
|
|
/* for 512 and 1 GB devices, 4th cycle is required */
|
|
if(hnand->Info.BlockNbr >= 1024)
|
|
{
|
|
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_4th_CYCLE(nandAddress);
|
|
}
|
|
|
|
/* Write data to memory */
|
|
for(index = 0 ; index < hnand->Info.SpareAreaSize; index++)
|
|
{
|
|
*(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++;
|
|
}
|
|
|
|
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
|
|
|
|
|
|
/* Read status until NAND is ready */
|
|
while(HAL_NAND_Read_Status(hnand) != NAND_READY)
|
|
{
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
|
|
/* Increment written spare areas number */
|
|
numSpareAreaWritten++;
|
|
|
|
/* Decrement spare areas to write */
|
|
NumSpareAreaTowrite--;
|
|
|
|
/* Increment the NAND address */
|
|
HAL_NAND_Address_Inc(hnand, pAddress);
|
|
|
|
}
|
|
|
|
/* Update the NAND controller state */
|
|
hnand->State = HAL_NAND_STATE_READY;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnand);
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief NAND memory Block erase
|
|
* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
|
|
* the configuration information for NAND module.
|
|
* @param pAddress : pointer to NAND address structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress)
|
|
{
|
|
uint32_t DeviceAddress = 0;
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hnand);
|
|
|
|
/* Check the NAND controller state */
|
|
if(hnand->State == HAL_NAND_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
|
|
/* Identify the device address */
|
|
if(hnand->Init.NandBank == FMC_NAND_BANK2)
|
|
{
|
|
DeviceAddress = NAND_DEVICE1;
|
|
}
|
|
else
|
|
{
|
|
DeviceAddress = NAND_DEVICE2;
|
|
}
|
|
|
|
/* Update the NAND controller state */
|
|
hnand->State = HAL_NAND_STATE_BUSY;
|
|
|
|
/* Send Erase block command sequence */
|
|
*(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE0;
|
|
|
|
*(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = __ADDR_1st_CYCLE(__ARRAY_ADDRESS(pAddress, hnand));
|
|
*(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = __ADDR_2nd_CYCLE(__ARRAY_ADDRESS(pAddress, hnand));
|
|
*(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = __ADDR_3rd_CYCLE(__ARRAY_ADDRESS(pAddress, hnand));
|
|
|
|
/* for 512 and 1 GB devices, 4th cycle is required */
|
|
if(hnand->Info.BlockNbr >= 1024)
|
|
{
|
|
*(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = __ADDR_4th_CYCLE(__ARRAY_ADDRESS(pAddress, hnand));
|
|
}
|
|
|
|
*(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE1;
|
|
|
|
/* Update the NAND controller state */
|
|
hnand->State = HAL_NAND_STATE_READY;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnand);
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
|
|
/**
|
|
* @brief NAND memory read status
|
|
* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
|
|
* the configuration information for NAND module.
|
|
* @retval NAND status
|
|
*/
|
|
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
|
|
{
|
|
uint32_t data = 0;
|
|
uint32_t DeviceAddress = 0;
|
|
|
|
/* Identify the device address */
|
|
if(hnand->Init.NandBank == FMC_NAND_BANK2)
|
|
{
|
|
DeviceAddress = NAND_DEVICE1;
|
|
}
|
|
else
|
|
{
|
|
DeviceAddress = NAND_DEVICE2;
|
|
}
|
|
|
|
/* Send Read status operation command */
|
|
*(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_STATUS;
|
|
|
|
/* Read status register data */
|
|
data = *(__IO uint8_t *)DeviceAddress;
|
|
|
|
/* Return the status */
|
|
if((data & NAND_ERROR) == NAND_ERROR)
|
|
{
|
|
return NAND_ERROR;
|
|
}
|
|
else if((data & NAND_READY) == NAND_READY)
|
|
{
|
|
return NAND_READY;
|
|
}
|
|
|
|
return NAND_BUSY;
|
|
|
|
}
|
|
|
|
/**
|
|
* @brief Increment the NAND memory address
|
|
* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
|
|
* the configuration information for NAND module.
|
|
* @param pAddress: pointer to NAND adress structure
|
|
* @retval The new status of the increment address operation. It can be:
|
|
* - NAND_VALID_ADDRESS: When the new address is valid address
|
|
* - NAND_INVALID_ADDRESS: When the new address is invalid address
|
|
*/
|
|
uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress)
|
|
{
|
|
uint32_t status = NAND_VALID_ADDRESS;
|
|
|
|
/* Increment page address */
|
|
pAddress->Page++;
|
|
|
|
/* Check NAND address is valid */
|
|
if(pAddress->Page == hnand->Info.BlockSize)
|
|
{
|
|
pAddress->Page = 0;
|
|
pAddress->Block++;
|
|
|
|
if(pAddress->Block == hnand->Info.ZoneSize)
|
|
{
|
|
pAddress->Block = 0;
|
|
pAddress->Zone++;
|
|
|
|
if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr))
|
|
{
|
|
status = NAND_INVALID_ADDRESS;
|
|
}
|
|
}
|
|
}
|
|
|
|
return (status);
|
|
}
|
|
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup NAND_Group3 Control functions
|
|
* @brief management functions
|
|
*
|
|
@verbatim
|
|
==============================================================================
|
|
##### NAND Control functions #####
|
|
==============================================================================
|
|
[..]
|
|
This subsection provides a set of functions allowing to control dynamically
|
|
the NAND interface.
|
|
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
|
|
/**
|
|
* @brief Enables dynamically NAND ECC feature.
|
|
* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
|
|
* the configuration information for NAND module.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
|
|
{
|
|
/* Check the NAND controller state */
|
|
if(hnand->State == HAL_NAND_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
|
|
/* Update the NAND state */
|
|
hnand->State = HAL_NAND_STATE_BUSY;
|
|
|
|
/* Enable ECC feature */
|
|
FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
|
|
|
|
/* Update the NAND state */
|
|
hnand->State = HAL_NAND_STATE_READY;
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
|
|
/**
|
|
* @brief Disables dynamically FMC_NAND ECC feature.
|
|
* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
|
|
* the configuration information for NAND module.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
|
|
{
|
|
/* Check the NAND controller state */
|
|
if(hnand->State == HAL_NAND_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
|
|
/* Update the NAND state */
|
|
hnand->State = HAL_NAND_STATE_BUSY;
|
|
|
|
/* Disable ECC feature */
|
|
FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
|
|
|
|
/* Update the NAND state */
|
|
hnand->State = HAL_NAND_STATE_READY;
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Disables dynamically NAND ECC feature.
|
|
* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
|
|
* the configuration information for NAND module.
|
|
* @param ECCval: pointer to ECC value
|
|
* @param Timeout: maximum timeout to wait
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
|
|
{
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
|
|
/* Check the NAND controller state */
|
|
if(hnand->State == HAL_NAND_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
|
|
/* Update the NAND state */
|
|
hnand->State = HAL_NAND_STATE_BUSY;
|
|
|
|
/* Get NAND ECC value */
|
|
status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
|
|
|
|
/* Update the NAND state */
|
|
hnand->State = HAL_NAND_STATE_READY;
|
|
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
|
|
/** @defgroup NAND_Group4 State functions
|
|
* @brief Peripheral State functions
|
|
*
|
|
@verbatim
|
|
==============================================================================
|
|
##### NAND State functions #####
|
|
==============================================================================
|
|
[..]
|
|
This subsection permits to get in run-time the status of the NAND controller
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and the data flow.
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@endverbatim
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* @{
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*/
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/**
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* @brief return the NAND state
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* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
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* the configuration information for NAND module.
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|
* @retval HAL state
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|
*/
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|
HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
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|
{
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|
return hnand->State;
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}
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|
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|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
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#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
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#endif /* HAL_NAND_MODULE_ENABLED */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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