mirror of
https://github.com/licsber/micropython.git
synced 2024-09-21 01:20:23 +08:00
14cf91f704
Previously the end of the heap was the start (lowest address) of the stack. With the changes in this commit these addresses are now independent, allowing a board to place the heap and stack in separate locations.
450 lines
16 KiB
C
450 lines
16 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2013-2015 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdio.h>
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#include <string.h>
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#include "modmachine.h"
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#include "py/gc.h"
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#include "py/runtime.h"
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#include "py/objstr.h"
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#include "py/mperrno.h"
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#include "py/mphal.h"
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#include "extmod/machine_mem.h"
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#include "extmod/machine_signal.h"
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#include "extmod/machine_pulse.h"
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#include "extmod/machine_i2c.h"
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#include "lib/utils/pyexec.h"
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#include "lib/oofatfs/ff.h"
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#include "extmod/vfs.h"
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#include "extmod/vfs_fat.h"
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#include "gccollect.h"
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#include "irq.h"
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#include "powerctrl.h"
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#include "pybthread.h"
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#include "rng.h"
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#include "storage.h"
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#include "pin.h"
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#include "timer.h"
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#include "usb.h"
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#include "rtc.h"
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#include "i2c.h"
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#include "spi.h"
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#include "uart.h"
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#include "wdt.h"
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#if defined(STM32L4)
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// L4 does not have a POR, so use BOR instead
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#define RCC_CSR_PORRSTF RCC_CSR_BORRSTF
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#endif
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#if defined(STM32H7)
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#define RCC_SR RSR
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#define RCC_SR_IWDGRSTF RCC_RSR_IWDG1RSTF
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#define RCC_SR_WWDGRSTF RCC_RSR_WWDG1RSTF
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#define RCC_SR_PORRSTF RCC_RSR_PORRSTF
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#define RCC_SR_BORRSTF RCC_RSR_BORRSTF
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#define RCC_SR_PINRSTF RCC_RSR_PINRSTF
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#define RCC_SR_RMVF RCC_RSR_RMVF
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#else
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#define RCC_SR CSR
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#define RCC_SR_IWDGRSTF RCC_CSR_IWDGRSTF
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#define RCC_SR_WWDGRSTF RCC_CSR_WWDGRSTF
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#define RCC_SR_PORRSTF RCC_CSR_PORRSTF
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#define RCC_SR_BORRSTF RCC_CSR_BORRSTF
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#define RCC_SR_PINRSTF RCC_CSR_PINRSTF
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#define RCC_SR_RMVF RCC_CSR_RMVF
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#endif
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#define PYB_RESET_SOFT (0)
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#define PYB_RESET_POWER_ON (1)
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#define PYB_RESET_HARD (2)
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#define PYB_RESET_WDT (3)
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#define PYB_RESET_DEEPSLEEP (4)
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STATIC uint32_t reset_cause;
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void machine_init(void) {
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#if defined(STM32F4)
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if (PWR->CSR & PWR_CSR_SBF) {
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// came out of standby
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reset_cause = PYB_RESET_DEEPSLEEP;
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PWR->CR |= PWR_CR_CSBF;
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} else
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#elif defined(STM32F7)
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if (PWR->CSR1 & PWR_CSR1_SBF) {
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// came out of standby
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reset_cause = PYB_RESET_DEEPSLEEP;
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PWR->CR1 |= PWR_CR1_CSBF;
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} else
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#elif defined(STM32H7)
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if (PWR->CPUCR & PWR_CPUCR_SBF || PWR->CPUCR & PWR_CPUCR_STOPF) {
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// came out of standby or stop mode
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reset_cause = PYB_RESET_DEEPSLEEP;
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PWR->CPUCR |= PWR_CPUCR_CSSF;
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} else
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#elif defined(STM32L4)
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if (PWR->SR1 & PWR_SR1_SBF) {
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// came out of standby
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reset_cause = PYB_RESET_DEEPSLEEP;
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PWR->SCR |= PWR_SCR_CSBF;
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} else
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#endif
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{
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// get reset cause from RCC flags
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uint32_t state = RCC->RCC_SR;
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if (state & RCC_SR_IWDGRSTF || state & RCC_SR_WWDGRSTF) {
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reset_cause = PYB_RESET_WDT;
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} else if (state & RCC_SR_PORRSTF
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#if !defined(STM32F0)
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|| state & RCC_SR_BORRSTF
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#endif
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) {
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reset_cause = PYB_RESET_POWER_ON;
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} else if (state & RCC_SR_PINRSTF) {
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reset_cause = PYB_RESET_HARD;
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} else {
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// default is soft reset
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reset_cause = PYB_RESET_SOFT;
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}
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}
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// clear RCC reset flags
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RCC->RCC_SR |= RCC_SR_RMVF;
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}
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void machine_deinit(void) {
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// we are doing a soft-reset so change the reset_cause
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reset_cause = PYB_RESET_SOFT;
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}
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// machine.info([dump_alloc_table])
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// Print out lots of information about the board.
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STATIC mp_obj_t machine_info(size_t n_args, const mp_obj_t *args) {
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// get and print unique id; 96 bits
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{
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byte *id = (byte*)MP_HAL_UNIQUE_ID_ADDRESS;
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printf("ID=%02x%02x%02x%02x:%02x%02x%02x%02x:%02x%02x%02x%02x\n", id[0], id[1], id[2], id[3], id[4], id[5], id[6], id[7], id[8], id[9], id[10], id[11]);
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}
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// get and print clock speeds
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// SYSCLK=168MHz, HCLK=168MHz, PCLK1=42MHz, PCLK2=84MHz
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{
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#if defined(STM32F0)
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printf("S=%u\nH=%u\nP1=%u\n",
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(unsigned int)HAL_RCC_GetSysClockFreq(),
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(unsigned int)HAL_RCC_GetHCLKFreq(),
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(unsigned int)HAL_RCC_GetPCLK1Freq());
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#else
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printf("S=%u\nH=%u\nP1=%u\nP2=%u\n",
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(unsigned int)HAL_RCC_GetSysClockFreq(),
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(unsigned int)HAL_RCC_GetHCLKFreq(),
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(unsigned int)HAL_RCC_GetPCLK1Freq(),
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(unsigned int)HAL_RCC_GetPCLK2Freq());
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#endif
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}
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// to print info about memory
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{
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printf("_etext=%p\n", &_etext);
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printf("_sidata=%p\n", &_sidata);
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printf("_sdata=%p\n", &_sdata);
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printf("_edata=%p\n", &_edata);
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printf("_sbss=%p\n", &_sbss);
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printf("_ebss=%p\n", &_ebss);
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printf("_sstack=%p\n", &_sstack);
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printf("_estack=%p\n", &_estack);
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printf("_ram_start=%p\n", &_ram_start);
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printf("_heap_start=%p\n", &_heap_start);
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printf("_heap_end=%p\n", &_heap_end);
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printf("_ram_end=%p\n", &_ram_end);
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}
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// qstr info
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{
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size_t n_pool, n_qstr, n_str_data_bytes, n_total_bytes;
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qstr_pool_info(&n_pool, &n_qstr, &n_str_data_bytes, &n_total_bytes);
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printf("qstr:\n n_pool=%u\n n_qstr=%u\n n_str_data_bytes=%u\n n_total_bytes=%u\n", n_pool, n_qstr, n_str_data_bytes, n_total_bytes);
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}
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// GC info
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{
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gc_info_t info;
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gc_info(&info);
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printf("GC:\n");
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printf(" %u total\n", info.total);
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printf(" %u : %u\n", info.used, info.free);
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printf(" 1=%u 2=%u m=%u\n", info.num_1block, info.num_2block, info.max_block);
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}
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// free space on flash
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{
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#if MICROPY_VFS_FAT
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for (mp_vfs_mount_t *vfs = MP_STATE_VM(vfs_mount_table); vfs != NULL; vfs = vfs->next) {
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if (strncmp("/flash", vfs->str, vfs->len) == 0) {
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// assumes that it's a FatFs filesystem
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fs_user_mount_t *vfs_fat = MP_OBJ_TO_PTR(vfs->obj);
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DWORD nclst;
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f_getfree(&vfs_fat->fatfs, &nclst);
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printf("LFS free: %u bytes\n", (uint)(nclst * vfs_fat->fatfs.csize * 512));
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break;
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}
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}
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#endif
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}
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#if MICROPY_PY_THREAD
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pyb_thread_dump();
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#endif
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if (n_args == 1) {
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// arg given means dump gc allocation table
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gc_dump_alloc_table();
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}
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return mp_const_none;
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}
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MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(machine_info_obj, 0, 1, machine_info);
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// Returns a string of 12 bytes (96 bits), which is the unique ID for the MCU.
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STATIC mp_obj_t machine_unique_id(void) {
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byte *id = (byte*)MP_HAL_UNIQUE_ID_ADDRESS;
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return mp_obj_new_bytes(id, 12);
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}
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MP_DEFINE_CONST_FUN_OBJ_0(machine_unique_id_obj, machine_unique_id);
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// Resets the pyboard in a manner similar to pushing the external RESET button.
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STATIC mp_obj_t machine_reset(void) {
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NVIC_SystemReset();
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return mp_const_none;
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}
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MP_DEFINE_CONST_FUN_OBJ_0(machine_reset_obj, machine_reset);
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STATIC mp_obj_t machine_soft_reset(void) {
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pyexec_system_exit = PYEXEC_FORCED_EXIT;
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nlr_raise(mp_obj_new_exception(&mp_type_SystemExit));
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}
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MP_DEFINE_CONST_FUN_OBJ_0(machine_soft_reset_obj, machine_soft_reset);
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__attribute__((naked)) void branch_to_bootloader(uint32_t r0, uint32_t addr) {
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__asm volatile (
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"ldr r2, [r1, #0]\n" // get address of stack pointer
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"msr msp, r2\n" // get stack pointer
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"ldr r2, [r1, #4]\n" // get address of destination
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"bx r2\n" // branch to bootloader
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);
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}
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// Activate the bootloader without BOOT* pins.
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STATIC NORETURN mp_obj_t machine_bootloader(size_t n_args, const mp_obj_t *args) {
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#if MICROPY_HW_ENABLE_USB
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pyb_usb_dev_deinit();
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#endif
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#if MICROPY_HW_ENABLE_STORAGE
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storage_flush();
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#endif
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#if __DCACHE_PRESENT == 1
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// Flush and disable caches before turning off peripherals (eg SDRAM)
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SCB_DisableICache();
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SCB_DisableDCache();
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#endif
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HAL_RCC_DeInit();
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HAL_DeInit();
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#if (__MPU_PRESENT == 1)
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// MPU must be disabled for bootloader to function correctly
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HAL_MPU_Disable();
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#endif
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#if MICROPY_HW_USES_BOOTLOADER
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if (n_args == 0 || !mp_obj_is_true(args[0])) {
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// By default, with no args given, we enter the custom bootloader (mboot)
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branch_to_bootloader(0x70ad0000, 0x08000000);
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}
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if (n_args == 1 && mp_obj_is_str_or_bytes(args[0])) {
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// With a string/bytes given, pass its data to the custom bootloader
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size_t len;
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const char *data = mp_obj_str_get_data(args[0], &len);
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void *mboot_region = (void*)*((volatile uint32_t*)0x08000000);
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memmove(mboot_region, data, len);
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branch_to_bootloader(0x70ad0080, 0x08000000);
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}
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#endif
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#if defined(STM32F7) || defined(STM32H7)
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branch_to_bootloader(0, 0x1ff00000);
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#else
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__HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH();
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branch_to_bootloader(0, 0x00000000);
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#endif
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while (1);
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}
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MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(machine_bootloader_obj, 0, 1, machine_bootloader);
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// get or set the MCU frequencies
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STATIC mp_obj_t machine_freq(size_t n_args, const mp_obj_t *args) {
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if (n_args == 0) {
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// get
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mp_obj_t tuple[] = {
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mp_obj_new_int(HAL_RCC_GetSysClockFreq()),
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mp_obj_new_int(HAL_RCC_GetHCLKFreq()),
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mp_obj_new_int(HAL_RCC_GetPCLK1Freq()),
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#if !defined(STM32F0)
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mp_obj_new_int(HAL_RCC_GetPCLK2Freq()),
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#endif
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};
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return mp_obj_new_tuple(MP_ARRAY_SIZE(tuple), tuple);
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} else {
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// set
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#if defined(STM32F0) || defined(STM32L4)
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mp_raise_NotImplementedError("machine.freq set not supported yet");
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#else
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mp_int_t sysclk = mp_obj_get_int(args[0]);
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mp_int_t ahb = sysclk;
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mp_int_t apb1 = ahb / 4;
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mp_int_t apb2 = ahb / 2;
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if (n_args > 1) {
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ahb = mp_obj_get_int(args[1]);
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if (n_args > 2) {
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apb1 = mp_obj_get_int(args[2]);
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if (n_args > 3) {
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apb2 = mp_obj_get_int(args[3]);
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}
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}
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}
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int ret = powerctrl_set_sysclk(sysclk, ahb, apb1, apb2);
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if (ret == -MP_EINVAL) {
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mp_raise_ValueError("invalid freq");
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} else if (ret < 0) {
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void NORETURN __fatal_error(const char *msg);
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__fatal_error("can't change freq");
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}
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return mp_const_none;
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#endif
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}
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}
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MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(machine_freq_obj, 0, 4, machine_freq);
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STATIC mp_obj_t machine_lightsleep(size_t n_args, const mp_obj_t *args) {
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if (n_args != 0) {
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mp_obj_t args2[2] = {MP_OBJ_NULL, args[0]};
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pyb_rtc_wakeup(2, args2);
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}
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powerctrl_enter_stop_mode();
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return mp_const_none;
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}
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MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(machine_lightsleep_obj, 0, 1, machine_lightsleep);
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STATIC mp_obj_t machine_deepsleep(size_t n_args, const mp_obj_t *args) {
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if (n_args != 0) {
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mp_obj_t args2[2] = {MP_OBJ_NULL, args[0]};
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pyb_rtc_wakeup(2, args2);
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}
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powerctrl_enter_standby_mode();
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return mp_const_none;
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}
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MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(machine_deepsleep_obj, 0, 1, machine_deepsleep);
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STATIC mp_obj_t machine_reset_cause(void) {
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return MP_OBJ_NEW_SMALL_INT(reset_cause);
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}
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STATIC MP_DEFINE_CONST_FUN_OBJ_0(machine_reset_cause_obj, machine_reset_cause);
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STATIC const mp_rom_map_elem_t machine_module_globals_table[] = {
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{ MP_ROM_QSTR(MP_QSTR___name__), MP_ROM_QSTR(MP_QSTR_umachine) },
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{ MP_ROM_QSTR(MP_QSTR_info), MP_ROM_PTR(&machine_info_obj) },
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{ MP_ROM_QSTR(MP_QSTR_unique_id), MP_ROM_PTR(&machine_unique_id_obj) },
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{ MP_ROM_QSTR(MP_QSTR_reset), MP_ROM_PTR(&machine_reset_obj) },
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{ MP_ROM_QSTR(MP_QSTR_soft_reset), MP_ROM_PTR(&machine_soft_reset_obj) },
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{ MP_ROM_QSTR(MP_QSTR_bootloader), MP_ROM_PTR(&machine_bootloader_obj) },
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{ MP_ROM_QSTR(MP_QSTR_freq), MP_ROM_PTR(&machine_freq_obj) },
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#if MICROPY_HW_ENABLE_RNG
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{ MP_ROM_QSTR(MP_QSTR_rng), MP_ROM_PTR(&pyb_rng_get_obj) },
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#endif
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{ MP_ROM_QSTR(MP_QSTR_idle), MP_ROM_PTR(&pyb_wfi_obj) },
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{ MP_ROM_QSTR(MP_QSTR_sleep), MP_ROM_PTR(&machine_lightsleep_obj) },
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{ MP_ROM_QSTR(MP_QSTR_lightsleep), MP_ROM_PTR(&machine_lightsleep_obj) },
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{ MP_ROM_QSTR(MP_QSTR_deepsleep), MP_ROM_PTR(&machine_deepsleep_obj) },
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{ MP_ROM_QSTR(MP_QSTR_reset_cause), MP_ROM_PTR(&machine_reset_cause_obj) },
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#if 0
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{ MP_ROM_QSTR(MP_QSTR_wake_reason), MP_ROM_PTR(&machine_wake_reason_obj) },
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#endif
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{ MP_ROM_QSTR(MP_QSTR_disable_irq), MP_ROM_PTR(&pyb_disable_irq_obj) },
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{ MP_ROM_QSTR(MP_QSTR_enable_irq), MP_ROM_PTR(&pyb_enable_irq_obj) },
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{ MP_ROM_QSTR(MP_QSTR_time_pulse_us), MP_ROM_PTR(&machine_time_pulse_us_obj) },
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{ MP_ROM_QSTR(MP_QSTR_mem8), MP_ROM_PTR(&machine_mem8_obj) },
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{ MP_ROM_QSTR(MP_QSTR_mem16), MP_ROM_PTR(&machine_mem16_obj) },
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{ MP_ROM_QSTR(MP_QSTR_mem32), MP_ROM_PTR(&machine_mem32_obj) },
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{ MP_ROM_QSTR(MP_QSTR_Pin), MP_ROM_PTR(&pin_type) },
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{ MP_ROM_QSTR(MP_QSTR_Signal), MP_ROM_PTR(&machine_signal_type) },
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#if 0
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{ MP_ROM_QSTR(MP_QSTR_RTC), MP_ROM_PTR(&pyb_rtc_type) },
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{ MP_ROM_QSTR(MP_QSTR_ADC), MP_ROM_PTR(&pyb_adc_type) },
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#endif
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#if MICROPY_PY_MACHINE_I2C
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{ MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&machine_i2c_type) },
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#endif
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{ MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&machine_hard_spi_type) },
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{ MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&pyb_uart_type) },
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{ MP_ROM_QSTR(MP_QSTR_WDT), MP_ROM_PTR(&pyb_wdt_type) },
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#if 0
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{ MP_ROM_QSTR(MP_QSTR_Timer), MP_ROM_PTR(&pyb_timer_type) },
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{ MP_ROM_QSTR(MP_QSTR_HeartBeat), MP_ROM_PTR(&pyb_heartbeat_type) },
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{ MP_ROM_QSTR(MP_QSTR_SD), MP_ROM_PTR(&pyb_sd_type) },
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// class constants
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{ MP_ROM_QSTR(MP_QSTR_IDLE), MP_ROM_INT(PYB_PWR_MODE_ACTIVE) },
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{ MP_ROM_QSTR(MP_QSTR_SLEEP), MP_ROM_INT(PYB_PWR_MODE_LPDS) },
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{ MP_ROM_QSTR(MP_QSTR_DEEPSLEEP), MP_ROM_INT(PYB_PWR_MODE_HIBERNATE) },
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#endif
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{ MP_ROM_QSTR(MP_QSTR_PWRON_RESET), MP_ROM_INT(PYB_RESET_POWER_ON) },
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{ MP_ROM_QSTR(MP_QSTR_HARD_RESET), MP_ROM_INT(PYB_RESET_HARD) },
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{ MP_ROM_QSTR(MP_QSTR_WDT_RESET), MP_ROM_INT(PYB_RESET_WDT) },
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{ MP_ROM_QSTR(MP_QSTR_DEEPSLEEP_RESET), MP_ROM_INT(PYB_RESET_DEEPSLEEP) },
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{ MP_ROM_QSTR(MP_QSTR_SOFT_RESET), MP_ROM_INT(PYB_RESET_SOFT) },
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#if 0
|
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{ MP_ROM_QSTR(MP_QSTR_WLAN_WAKE), MP_ROM_INT(PYB_SLP_WAKED_BY_WLAN) },
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{ MP_ROM_QSTR(MP_QSTR_PIN_WAKE), MP_ROM_INT(PYB_SLP_WAKED_BY_GPIO) },
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{ MP_ROM_QSTR(MP_QSTR_RTC_WAKE), MP_ROM_INT(PYB_SLP_WAKED_BY_RTC) },
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#endif
|
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};
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STATIC MP_DEFINE_CONST_DICT(machine_module_globals, machine_module_globals_table);
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const mp_obj_module_t machine_module = {
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.base = { &mp_type_module },
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.globals = (mp_obj_dict_t*)&machine_module_globals,
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};
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