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https://github.com/licsber/micropython.git
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7ee5afe8d1
This changes the signatures of QSPI write_cmd_data, write_cmd_addr_data and read_cmd_qaddr_qdata so they return an error code. The softqspi and stm32 hardware qspi driver are updated to follow this new signature. Also the spiflash driver is updated to use these new return values. Signed-off-by: Damien George <damien@micropython.org>
209 lines
7.3 KiB
C
209 lines
7.3 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2017-2018 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "drivers/bus/qspi.h"
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#define CS_LOW(self) mp_hal_pin_write(self->cs, 0)
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#define CS_HIGH(self) mp_hal_pin_write(self->cs, 1)
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#ifdef MICROPY_HW_SOFTQSPI_SCK_LOW
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// Use externally provided functions for SCK control and IO reading
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#define SCK_LOW(self) MICROPY_HW_SOFTQSPI_SCK_LOW(self)
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#define SCK_HIGH(self) MICROPY_HW_SOFTQSPI_SCK_HIGH(self)
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#define NIBBLE_READ(self) MICROPY_HW_SOFTQSPI_NIBBLE_READ(self)
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#else
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// Use generic pin functions for SCK control and IO reading
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#define SCK_LOW(self) mp_hal_pin_write(self->clk, 0)
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#define SCK_HIGH(self) mp_hal_pin_write(self->clk, 1)
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#define NIBBLE_READ(self) ( \
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mp_hal_pin_read(self->io0) \
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| (mp_hal_pin_read(self->io1) << 1) \
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| (mp_hal_pin_read(self->io2) << 2) \
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| (mp_hal_pin_read(self->io3) << 3))
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#endif
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STATIC void nibble_write(mp_soft_qspi_obj_t *self, uint8_t v) {
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mp_hal_pin_write(self->io0, v & 1);
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mp_hal_pin_write(self->io1, (v >> 1) & 1);
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mp_hal_pin_write(self->io2, (v >> 2) & 1);
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mp_hal_pin_write(self->io3, (v >> 3) & 1);
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}
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STATIC int mp_soft_qspi_ioctl(void *self_in, uint32_t cmd) {
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mp_soft_qspi_obj_t *self = (mp_soft_qspi_obj_t*)self_in;
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switch (cmd) {
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case MP_QSPI_IOCTL_INIT:
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mp_hal_pin_high(self->cs);
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mp_hal_pin_output(self->cs);
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// Configure pins
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mp_hal_pin_write(self->clk, 0);
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mp_hal_pin_output(self->clk);
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//mp_hal_pin_write(self->clk, 1);
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mp_hal_pin_output(self->io0);
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mp_hal_pin_input(self->io1);
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mp_hal_pin_write(self->io2, 1);
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mp_hal_pin_output(self->io2);
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mp_hal_pin_write(self->io3, 1);
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mp_hal_pin_output(self->io3);
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break;
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}
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return 0; // success
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}
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STATIC void mp_soft_qspi_transfer(mp_soft_qspi_obj_t *self, size_t len, const uint8_t *src, uint8_t *dest) {
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// Will run as fast as possible, limited only by CPU speed and GPIO time
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mp_hal_pin_input(self->io1);
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mp_hal_pin_output(self->io0);
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if (self->io3) {
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mp_hal_pin_write(self->io2, 1);
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mp_hal_pin_output(self->io2);
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mp_hal_pin_write(self->io3, 1);
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mp_hal_pin_output(self->io3);
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}
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if (src) {
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for (size_t i = 0; i < len; ++i) {
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uint8_t data_out = src[i];
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uint8_t data_in = 0;
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for (int j = 0; j < 8; ++j, data_out <<= 1) {
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mp_hal_pin_write(self->io0, (data_out >> 7) & 1);
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mp_hal_pin_write(self->clk, 1);
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data_in = (data_in << 1) | mp_hal_pin_read(self->io1);
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mp_hal_pin_write(self->clk, 0);
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}
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if (dest != NULL) {
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dest[i] = data_in;
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}
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}
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} else {
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for (size_t i = 0; i < len; ++i) {
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uint8_t data_in = 0;
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for (int j = 0; j < 8; ++j) {
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mp_hal_pin_write(self->clk, 1);
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data_in = (data_in << 1) | mp_hal_pin_read(self->io1);
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mp_hal_pin_write(self->clk, 0);
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}
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if (dest != NULL) {
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dest[i] = data_in;
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}
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}
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}
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}
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STATIC void mp_soft_qspi_qread(mp_soft_qspi_obj_t *self, size_t len, uint8_t *buf) {
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// Make all IO lines input
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mp_hal_pin_input(self->io2);
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mp_hal_pin_input(self->io3);
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mp_hal_pin_input(self->io0);
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mp_hal_pin_input(self->io1);
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// Will run as fast as possible, limited only by CPU speed and GPIO time
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while (len--) {
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SCK_HIGH(self);
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uint8_t data_in = NIBBLE_READ(self);
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SCK_LOW(self);
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SCK_HIGH(self);
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*buf++ = (data_in << 4) | NIBBLE_READ(self);
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SCK_LOW(self);
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}
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}
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STATIC void mp_soft_qspi_qwrite(mp_soft_qspi_obj_t *self, size_t len, const uint8_t *buf) {
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// Make all IO lines output
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mp_hal_pin_output(self->io2);
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mp_hal_pin_output(self->io3);
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mp_hal_pin_output(self->io0);
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mp_hal_pin_output(self->io1);
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// Will run as fast as possible, limited only by CPU speed and GPIO time
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for (size_t i = 0; i < len; ++i) {
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nibble_write(self, buf[i] >> 4);
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SCK_HIGH(self);
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SCK_LOW(self);
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nibble_write(self, buf[i]);
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SCK_HIGH(self);
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SCK_LOW(self);
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}
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//mp_hal_pin_input(self->io1);
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}
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STATIC int mp_soft_qspi_write_cmd_data(void *self_in, uint8_t cmd, size_t len, uint32_t data) {
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mp_soft_qspi_obj_t *self = (mp_soft_qspi_obj_t*)self_in;
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uint32_t cmd_buf = cmd | data << 8;
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CS_LOW(self);
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mp_soft_qspi_transfer(self, 1 + len, (uint8_t*)&cmd_buf, NULL);
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CS_HIGH(self);
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return 0;
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}
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STATIC int mp_soft_qspi_write_cmd_addr_data(void *self_in, uint8_t cmd, uint32_t addr, size_t len, const uint8_t *src) {
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mp_soft_qspi_obj_t *self = (mp_soft_qspi_obj_t*)self_in;
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uint8_t cmd_buf[5] = {cmd};
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uint8_t addr_len = mp_spi_set_addr_buff(&cmd_buf[1], addr);
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CS_LOW(self);
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mp_soft_qspi_transfer(self, addr_len + 1, cmd_buf, NULL);
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mp_soft_qspi_transfer(self, len, src, NULL);
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CS_HIGH(self);
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return 0;
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}
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STATIC uint32_t mp_soft_qspi_read_cmd(void *self_in, uint8_t cmd, size_t len) {
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mp_soft_qspi_obj_t *self = (mp_soft_qspi_obj_t*)self_in;
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uint32_t cmd_buf = cmd;
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CS_LOW(self);
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mp_soft_qspi_transfer(self, 1 + len, (uint8_t*)&cmd_buf, (uint8_t*)&cmd_buf);
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CS_HIGH(self);
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return cmd_buf >> 8;
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}
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STATIC int mp_soft_qspi_read_cmd_qaddr_qdata(void *self_in, uint8_t cmd, uint32_t addr, size_t len, uint8_t *dest) {
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mp_soft_qspi_obj_t *self = (mp_soft_qspi_obj_t*)self_in;
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uint8_t cmd_buf[7] = {cmd};
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uint8_t addr_len = mp_spi_set_addr_buff(&cmd_buf[1], addr);
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CS_LOW(self);
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mp_soft_qspi_transfer(self, 1, cmd_buf, NULL);
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mp_soft_qspi_qwrite(self, addr_len + 3, &cmd_buf[1]); // 3/4 addr bytes, 1 extra byte (0), 2 dummy bytes (4 dummy cycles)
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mp_soft_qspi_qread(self, len, dest);
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CS_HIGH(self);
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return 0;
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}
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const mp_qspi_proto_t mp_soft_qspi_proto = {
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.ioctl = mp_soft_qspi_ioctl,
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.write_cmd_data = mp_soft_qspi_write_cmd_data,
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.write_cmd_addr_data = mp_soft_qspi_write_cmd_addr_data,
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.read_cmd = mp_soft_qspi_read_cmd,
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.read_cmd_qaddr_qdata = mp_soft_qspi_read_cmd_qaddr_qdata,
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};
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