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7e0b1bc95d
Allowing to increase the clock a little bit to 54Mhz. Not much of a gain, but useful for generating a RNG entropy source from the jitter between DFLL48M and FDPLL96M. |
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.. | ||
clock_config.c | ||
mpconfigmcu.h | ||
mpconfigmcu.mk | ||
pin-af-table.csv |