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76cf98c35b
By using the phase jitter between the DFLL48M clock and the FDPLL96M clock. Even if both use the same reference source, they have a different jitter. SysTick is driven by FDPLL96M, the us counter by DFLL48M. As a random source, the us counter is read out on every SysTick and the value is used to accumulate a simple multiply, add and xor register. According to tests it creates about 30 bit random bit-flips per second. That mechanism will pass quite a few RNG tests, has a suitable frequency distribution and serves better than just the time after boot to seed the PRNG.
59 lines
1.5 KiB
C
59 lines
1.5 KiB
C
// Deinitions common to all SAMD21 boards
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#include "samd21.h"
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#define MICROPY_CONFIG_ROM_LEVEL (MICROPY_CONFIG_ROM_LEVEL_CORE_FEATURES)
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// MicroPython emitters
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#define MICROPY_EMIT_THUMB (0)
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#define MICROPY_EMIT_INLINE_THUMB (0)
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#define MICROPY_MODULE_BUILTIN_INIT (1)
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#define MICROPY_FLOAT_IMPL (MICROPY_FLOAT_IMPL_FLOAT)
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#ifndef MICROPY_PY_BUILTINS_COMPLEX
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#define MICROPY_PY_BUILTINS_COMPLEX (0)
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#endif
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#ifndef MICROPY_PY_MATH
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#define MICROPY_PY_MATH (1)
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#endif
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#ifndef MICROPY_PY_CMATH
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#define MICROPY_PY_CMATH (0)
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#endif
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#define MICROPY_PY_URANDOM_SEED_INIT_FUNC (trng_random_u32())
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unsigned long trng_random_u32(void);
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#define VFS_BLOCK_SIZE_BYTES (1536) // 24x 64B flash pages;
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#ifndef MICROPY_HW_UART_TXBUF
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#define MICROPY_HW_UART_TXBUF (1)
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#endif
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#ifndef MICROPY_PY_MACHINE_RTC
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#if MICROPY_HW_XOSC32K
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#define MICROPY_PY_MACHINE_RTC (1)
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#endif
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#endif
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#ifndef MICROPY_PY_MACHINE_PIN_BOARD_CPU
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#define MICROPY_PY_MACHINE_PIN_BOARD_CPU (1)
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#endif
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#define CPU_FREQ (48000000)
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#define DFLL48M_FREQ (48000000)
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#define MAX_CPU_FREQ (54000000)
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#define FDPLL_REF_FREQ (32768)
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#define IRQ_PRI_PENDSV ((1 << __NVIC_PRIO_BITS) - 1)
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static inline uint32_t raise_irq_pri(uint32_t pri) {
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(void)pri;
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return 0;
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}
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static inline void restore_irq_pri(uint32_t basepri) {
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(void)basepri;
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}
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