mirror of
https://github.com/licsber/micropython.git
synced 2024-09-22 01:50:24 +08:00
5e990cc27f
The RT1176 has two cores, but the actual firmware supports only the CM7. There are currently no good plans on how to use the CM4. The actual MIMXRT1170_EVK board is on par with the existing MIMXRT boards, with the following extensions: - Use 64 MB RAM for the heap. - Support both LAN interfaces as LAN(0) and LAN(1), with LAN(1) being the 1GB interface. The dual LAN port interface can eventually be adapted as well for the RT1062 MCU. This work was done in collaboration with @alphaFred.
131 lines
5.9 KiB
C
131 lines
5.9 KiB
C
#define MICROPY_HW_BOARD_NAME "Teensy 4.1"
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#define MICROPY_HW_MCU_NAME "MIMXRT1062DVJ6A"
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// Teensy 4.1 has 1 board LED
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#define MICROPY_HW_LED1_PIN (pin_GPIO_B0_03)
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#define MICROPY_HW_LED_ON(pin) (mp_hal_pin_high(pin))
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#define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_low(pin))
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#define MICROPY_HW_NUM_PIN_IRQS (4 * 32 + 3)
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// UART config: 8 UARTs at the pins for Teensy 4.1
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#define MICROPY_HW_UART_NUM (sizeof(uart_index_table) / sizeof(uart_index_table)[0])
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#define MICROPY_HW_UART_INDEX { 0, 6, 4, 2, 3, 8, 1, 7, 5 }
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#define IOMUX_TABLE_UART \
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{ IOMUXC_GPIO_AD_B0_12_LPUART1_TX }, { IOMUXC_GPIO_AD_B0_13_LPUART1_RX }, \
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{ IOMUXC_GPIO_AD_B1_02_LPUART2_TX }, { IOMUXC_GPIO_AD_B1_03_LPUART2_RX }, \
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{ IOMUXC_GPIO_AD_B1_06_LPUART3_TX }, { IOMUXC_GPIO_AD_B1_07_LPUART3_RX }, \
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{ IOMUXC_GPIO_B1_00_LPUART4_TX }, { IOMUXC_GPIO_B1_01_LPUART4_RX }, \
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{ IOMUXC_GPIO_B1_12_LPUART5_TX }, { IOMUXC_GPIO_B1_13_LPUART5_RX }, \
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{ IOMUXC_GPIO_AD_B0_02_LPUART6_TX }, { IOMUXC_GPIO_AD_B0_03_LPUART6_RX }, \
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{ IOMUXC_GPIO_EMC_31_LPUART7_TX }, { IOMUXC_GPIO_EMC_32_LPUART7_RX }, \
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{ IOMUXC_GPIO_AD_B1_10_LPUART8_TX }, { IOMUXC_GPIO_AD_B1_11_LPUART8_RX },
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#define MICROPY_HW_SPI_INDEX { 4, 3, 1 }
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#define IOMUX_TABLE_SPI \
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{ IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK }, { IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 }, \
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{ IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO }, { IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI }, \
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{ IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 }, \
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{ 0 }, { 0 }, \
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{ 0 }, { 0 }, \
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{ 0 }, \
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{ IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK }, { IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0 }, \
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{ IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO }, { IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI }, \
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{ 0 }, \
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{ IOMUXC_GPIO_B0_03_LPSPI4_SCK }, { IOMUXC_GPIO_B0_00_LPSPI4_PCS0 }, \
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{ IOMUXC_GPIO_B0_02_LPSPI4_SDO }, { IOMUXC_GPIO_B0_01_LPSPI4_SDI }, \
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{ IOMUXC_GPIO_B1_03_LPSPI4_PCS1 }
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#define DMA_REQ_SRC_RX { 0, kDmaRequestMuxLPSPI1Rx, kDmaRequestMuxLPSPI2Rx, \
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kDmaRequestMuxLPSPI3Rx, kDmaRequestMuxLPSPI4Rx }
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#define DMA_REQ_SRC_TX { 0, kDmaRequestMuxLPSPI1Tx, kDmaRequestMuxLPSPI2Tx, \
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kDmaRequestMuxLPSPI3Tx, kDmaRequestMuxLPSPI4Tx }
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// Define mapping hardware I2C # to logical I2C #
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// SDA/SCL HW-I2C Logical I2C
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// 17/16 LPI2C3 -> 0
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// 18/19 LPI2C1 -> 1
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// 25/24 LPI2C4 -> 2
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#define MICROPY_HW_I2C_INDEX { 1, 3, 4 }
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#define IOMUX_TABLE_I2C \
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{ IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL }, { IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA }, \
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{ 0 }, { 0 }, \
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{ IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL }, { IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA }, \
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{ IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL }, { IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA },
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#define MICROPY_PY_MACHINE_I2S (1)
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#define MICROPY_HW_I2S_NUM (2)
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#define I2S_CLOCK_MUX { 0, kCLOCK_Sai1Mux, kCLOCK_Sai2Mux }
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#define I2S_CLOCK_PRE_DIV { 0, kCLOCK_Sai1PreDiv, kCLOCK_Sai2PreDiv }
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#define I2S_CLOCK_DIV { 0, kCLOCK_Sai1Div, kCLOCK_Sai2Div }
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#define I2S_IOMUXC_GPR_MODE { 0, kIOMUXC_GPR_SAI1MClkOutputDir, kIOMUXC_GPR_SAI2MClkOutputDir }
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#define I2S_DMA_REQ_SRC_RX { 0, kDmaRequestMuxSai1Rx, kDmaRequestMuxSai2Rx }
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#define I2S_DMA_REQ_SRC_TX { 0, kDmaRequestMuxSai1Tx, kDmaRequestMuxSai2Tx }
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#define I2S_AUDIO_PLL_CLOCK (2U)
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#define I2S_GPIO(_hwid, _fn, _mode, _pin, _iomux) \
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{ \
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.hw_id = _hwid, \
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.fn = _fn, \
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.mode = _mode, \
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.name = MP_QSTR_##_pin, \
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.iomux = {_iomux}, \
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}
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#define I2S_GPIO_MAP \
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{ \
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I2S_GPIO(1, SCK, RX, GPIO_AD_B1_11, IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK), /* pin 21 */ \
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I2S_GPIO(1, WS, RX, GPIO_AD_B1_10, IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC), /* pin 20 */ \
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I2S_GPIO(1, SD, RX, GPIO_AD_B1_12, IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00), /* pin 38 */ \
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I2S_GPIO(1, SD, RX, GPIO_B1_00, IOMUXC_GPIO_B1_00_SAI1_RX_DATA00), /* pin 8 */ \
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I2S_GPIO(1, SCK, TX, GPIO_AD_B1_14, IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK), /* pin 26 */ \
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I2S_GPIO(1, SCK, TX, GPIO_B1_02, IOMUXC_GPIO_B1_02_SAI1_TX_BCLK), /* pin 36 */ \
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I2S_GPIO(1, WS, TX, GPIO_AD_B1_15, IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC), /* pin 27 */ \
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I2S_GPIO(1, WS, TX, GPIO_B1_03, IOMUXC_GPIO_B1_03_SAI1_TX_SYNC), /* pin 37 */ \
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I2S_GPIO(1, SD, TX, GPIO_AD_B1_13, IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00), /* pin 39 */ \
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I2S_GPIO(1, SD, TX, GPIO_B1_01, IOMUXC_GPIO_B1_01_SAI1_TX_DATA00), /* pin 7 */ \
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I2S_GPIO(1, MCK, TX, GPIO_AD_B1_09, IOMUXC_GPIO_AD_B1_09_SAI1_MCLK), /* pin 23 */ \
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I2S_GPIO(2, SCK, TX, GPIO_EMC_06, IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK), /* pin 4 */ \
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I2S_GPIO(2, WS, TX, GPIO_EMC_05, IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC), /* pin 3 */ \
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I2S_GPIO(2, SD, TX, GPIO_EMC_04, IOMUXC_GPIO_EMC_04_SAI2_TX_DATA), /* pin 2 */ \
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I2S_GPIO(2, MCK, TX, GPIO_EMC_07, IOMUXC_GPIO_EMC_07_SAI2_MCLK) /* pin 33 */ \
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}
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#define USDHC_DUMMY_PIN NULL, 0
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#define MICROPY_USDHC1 \
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{ \
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.cmd = {GPIO_SD_B0_00_USDHC1_CMD}, \
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.clk = { GPIO_SD_B0_01_USDHC1_CLK }, \
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.cd_b = { USDHC_DUMMY_PIN }, \
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.data0 = { GPIO_SD_B0_02_USDHC1_DATA0 }, \
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.data1 = { GPIO_SD_B0_03_USDHC1_DATA1 }, \
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.data2 = { GPIO_SD_B0_04_USDHC1_DATA2 }, \
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.data3 = { GPIO_SD_B0_05_USDHC1_DATA3 }, \
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}
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// Network definitions
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// Transceiver Phy Address & Type
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#define ENET_PHY_ADDRESS (0)
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#define ENET_PHY_OPS phydp83825_ops
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// Ethernet PIN definitions
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#define ENET_RESET_PIN &pin_GPIO_B0_14
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#define ENET_INT_PIN &pin_GPIO_B0_15
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#define IOMUX_TABLE_ENET \
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{ IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0, 0xB0E9u }, \
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{ IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0, 0xB0E9u }, \
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{ IOMUXC_GPIO_B1_06_ENET_RX_EN, 0, 0xB0E9u }, \
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{ IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0, 0xB0E9u }, \
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{ IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0, 0xB0E9u }, \
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{ IOMUXC_GPIO_B1_09_ENET_TX_EN, 0, 0xB0E9u }, \
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{ IOMUXC_GPIO_B1_10_ENET_REF_CLK, 1, 0x71u }, \
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{ IOMUXC_GPIO_B1_11_ENET_RX_ER, 0, 0xB0E9u }, \
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{ IOMUXC_GPIO_B1_15_ENET_MDIO, 0, 0xB0E9u }, \
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{ IOMUXC_GPIO_B1_14_ENET_MDC, 0, 0xB0E9u },
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