mirror of
https://github.com/licsber/micropython.git
synced 2024-09-22 01:50:24 +08:00
5e990cc27f
The RT1176 has two cores, but the actual firmware supports only the CM7. There are currently no good plans on how to use the CM4. The actual MIMXRT1170_EVK board is on par with the existing MIMXRT boards, with the following extensions: - Use 64 MB RAM for the heap. - Support both LAN interfaces as LAN(0) and LAN(1), with LAN(1) being the 1GB interface. The dual LAN port interface can eventually be adapted as well for the RT1062 MCU. This work was done in collaboration with @alphaFred.
179 lines
7.6 KiB
C
179 lines
7.6 KiB
C
#define MICROPY_HW_BOARD_NAME "Seeed ARCH MIX"
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#define MICROPY_HW_MCU_NAME "MIMXRT1052DVL5B"
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// MIMXRT1050_EVKB has 1 user LED
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#define MICROPY_HW_LED1_PIN (pin_GPIO_AD_B0_09)
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#define MICROPY_HW_LED2_PIN (pin_GPIO_AD_B0_10)
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#define MICROPY_HW_LED3_PIN (pin_GPIO_AD_B0_11)
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#define MICROPY_HW_LED_ON(pin) (mp_hal_pin_low(pin))
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#define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_high(pin))
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#define MICROPY_HW_NUM_PIN_IRQS (4 * 32 + 3)
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// Define mapping logical UART # to hardware UART #
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// LPUART1 on J3_19/J3_20 -> 1
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// LPUART2 on J4_16/J4_17 -> 2
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// LPUART3 on J4_06/J4_07 -> 3
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// LPUART8 on J4_10/J4_11 -> 4
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// LPUART4 on J5_08/J5_12 -> 5
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#define MICROPY_HW_UART_NUM (sizeof(uart_index_table) / sizeof(uart_index_table)[0])
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#define MICROPY_HW_UART_INDEX { 0, 1, 2, 3, 8, 4 }
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#define IOMUX_TABLE_UART \
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{ IOMUXC_GPIO_AD_B0_12_LPUART1_TX }, { IOMUXC_GPIO_AD_B0_13_LPUART1_RX }, \
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{ IOMUXC_GPIO_AD_B1_02_LPUART2_TX }, { IOMUXC_GPIO_AD_B1_03_LPUART2_RX }, \
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{ IOMUXC_GPIO_AD_B1_06_LPUART3_TX }, { IOMUXC_GPIO_AD_B1_07_LPUART3_RX }, \
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{ IOMUXC_GPIO_B1_00_LPUART4_TX }, { IOMUXC_GPIO_B1_01_LPUART4_RX }, \
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{ 0 }, { 0 }, \
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{ 0 }, { 0 }, \
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{ 0 }, { 0 }, \
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{ IOMUXC_GPIO_AD_B1_10_LPUART8_TX }, { IOMUXC_GPIO_AD_B1_11_LPUART8_RX },
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#define MICROPY_HW_SPI_INDEX { 3, 4 }
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#define IOMUX_TABLE_SPI \
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{ 0 }, { 0 }, \
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{ 0 }, { 0 }, \
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{ 0 }, \
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{ 0 }, { 0 }, \
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{ 0 }, { 0 }, \
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{ 0 }, \
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{ IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK }, { IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0 }, \
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{ IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO }, { IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI }, \
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{ 0 }, \
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{ IOMUXC_GPIO_B1_07_LPSPI4_SCK }, { IOMUXC_GPIO_B1_04_LPSPI4_PCS0 }, \
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{ IOMUXC_GPIO_B1_06_LPSPI4_SDO }, { IOMUXC_GPIO_B1_05_LPSPI4_SDI }, \
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{ IOMUXC_GPIO_B1_03_LPSPI4_PCS1 }
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#define DMA_REQ_SRC_RX { 0, kDmaRequestMuxLPSPI1Rx, kDmaRequestMuxLPSPI2Rx, \
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kDmaRequestMuxLPSPI3Rx, kDmaRequestMuxLPSPI4Rx }
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#define DMA_REQ_SRC_TX { 0, kDmaRequestMuxLPSPI1Tx, kDmaRequestMuxLPSPI2Tx, \
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kDmaRequestMuxLPSPI3Tx, kDmaRequestMuxLPSPI4Tx }
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// Define the mapping hardware I2C # to logical I2C #
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// SDA/SCL HW-I2C Logical I2C
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// J3_17/J3_16 LPI2C1 -> 0
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// J4_06/J4_07 LPI2C3 -> 1
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// J5_05/J5_04 LPI2C2 -> 2
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#define MICROPY_HW_I2C_INDEX { 1, 3, 2 }
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#define IOMUX_TABLE_I2C \
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{ IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL }, { IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA }, \
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{ IOMUXC_GPIO_B0_04_LPI2C2_SCL }, { IOMUXC_GPIO_B0_05_LPI2C2_SDA }, \
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{ IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL }, { IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA }
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#define MICROPY_PY_MACHINE_I2S (1)
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#define MICROPY_HW_I2S_NUM (1)
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#define I2S_CLOCK_MUX { 0, kCLOCK_Sai1Mux }
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#define I2S_CLOCK_PRE_DIV { 0, kCLOCK_Sai1PreDiv }
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#define I2S_CLOCK_DIV { 0, kCLOCK_Sai1Div }
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#define I2S_IOMUXC_GPR_MODE { 0, kIOMUXC_GPR_SAI1MClkOutputDir }
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#define I2S_DMA_REQ_SRC_RX { 0, kDmaRequestMuxSai1Rx }
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#define I2S_DMA_REQ_SRC_TX { 0, kDmaRequestMuxSai1Tx }
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#define I2S_AUDIO_PLL_CLOCK (2U)
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#define I2S_GPIO(_hwid, _fn, _mode, _pin, _iomux) \
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{ \
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.hw_id = _hwid, \
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.fn = _fn, \
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.mode = _mode, \
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.name = MP_QSTR_##_pin, \
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.iomux = {_iomux}, \
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}
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#define I2S_GPIO_MAP \
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{ \
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I2S_GPIO(1, MCK, TX, GPIO_AD_B1_09, IOMUXC_GPIO_AD_B1_09_SAI1_MCLK), /* pin J4 09 */ \
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I2S_GPIO(1, SCK, RX, GPIO_AD_B1_11, IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK), /* pin J4 11 */ \
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I2S_GPIO(1, WS, RX, GPIO_AD_B1_10, IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC), /* pin J4 10 */ \
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I2S_GPIO(1, SD, RX, GPIO_AD_B1_12, IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00), /* pin J4 12 */ \
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I2S_GPIO(1, SCK, TX, GPIO_AD_B1_14, IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK), /* pin J4 14 */ \
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I2S_GPIO(1, WS, TX, GPIO_AD_B1_15, IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC), /* pin J4 15 */ \
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I2S_GPIO(1, SD, TX, GPIO_AD_B1_13, IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00) /* pin J4 13 */ \
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}
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#define USDHC_DUMMY_PIN NULL, 0
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#define MICROPY_USDHC1 \
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{ \
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.cmd = {GPIO_SD_B0_00_USDHC1_CMD}, \
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.clk = { GPIO_SD_B0_01_USDHC1_CLK }, \
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.cd_b = { GPIO_B1_12_USDHC1_CD_B }, \
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.data0 = { GPIO_SD_B0_02_USDHC1_DATA0 }, \
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.data1 = { GPIO_SD_B0_03_USDHC1_DATA1 }, \
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.data2 = { GPIO_SD_B0_04_USDHC1_DATA2 }, \
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.data3 = { GPIO_SD_B0_05_USDHC1_DATA3 }, \
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}
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// Network definitions
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// Transceiver Phy Address & Type
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#define ENET_PHY_ADDRESS (1)
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#define ENET_PHY LAN8720
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#define ENET_PHY_OPS phylan8720_ops
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#define ENET_TX_CLK_OUTPUT false
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// Etherner PIN definitions
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// No reset and interrupt pin by intention
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#define ENET_RESET_PIN NULL
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#define ENET_INT_PIN NULL
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#define IOMUX_TABLE_ENET \
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{ IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0, 0xB0E9u }, \
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{ IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0, 0xB0E9u }, \
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{ IOMUXC_GPIO_B1_06_ENET_RX_EN, 0, 0xB0E9u }, \
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{ IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0, 0xB0E9u }, \
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{ IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0, 0xB0E9u }, \
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{ IOMUXC_GPIO_B1_09_ENET_TX_EN, 0, 0xB0E9u }, \
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{ IOMUXC_GPIO_B1_10_ENET_REF_CLK, 1, 0x71u }, \
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{ IOMUXC_GPIO_B1_11_ENET_RX_ER, 0, 0x30E9u }, \
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{ IOMUXC_GPIO_EMC_41_ENET_MDIO, 0, 0xB0E9u }, \
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{ IOMUXC_GPIO_EMC_40_ENET_MDC, 0, 0xB0E9u },
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// --- SEMC --- //
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#define MIMXRT_IOMUXC_SEMC_DATA00 IOMUXC_GPIO_EMC_00_SEMC_DATA00
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#define MIMXRT_IOMUXC_SEMC_DATA01 IOMUXC_GPIO_EMC_01_SEMC_DATA01
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#define MIMXRT_IOMUXC_SEMC_DATA02 IOMUXC_GPIO_EMC_02_SEMC_DATA02
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#define MIMXRT_IOMUXC_SEMC_DATA03 IOMUXC_GPIO_EMC_03_SEMC_DATA03
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#define MIMXRT_IOMUXC_SEMC_DATA04 IOMUXC_GPIO_EMC_04_SEMC_DATA04
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#define MIMXRT_IOMUXC_SEMC_DATA05 IOMUXC_GPIO_EMC_05_SEMC_DATA05
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#define MIMXRT_IOMUXC_SEMC_DATA06 IOMUXC_GPIO_EMC_06_SEMC_DATA06
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#define MIMXRT_IOMUXC_SEMC_DATA07 IOMUXC_GPIO_EMC_07_SEMC_DATA07
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#define MIMXRT_IOMUXC_SEMC_DATA08 IOMUXC_GPIO_EMC_30_SEMC_DATA08
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#define MIMXRT_IOMUXC_SEMC_DATA09 IOMUXC_GPIO_EMC_31_SEMC_DATA09
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#define MIMXRT_IOMUXC_SEMC_DATA10 IOMUXC_GPIO_EMC_32_SEMC_DATA10
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#define MIMXRT_IOMUXC_SEMC_DATA11 IOMUXC_GPIO_EMC_33_SEMC_DATA11
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#define MIMXRT_IOMUXC_SEMC_DATA12 IOMUXC_GPIO_EMC_34_SEMC_DATA12
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#define MIMXRT_IOMUXC_SEMC_DATA13 IOMUXC_GPIO_EMC_35_SEMC_DATA13
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#define MIMXRT_IOMUXC_SEMC_DATA14 IOMUXC_GPIO_EMC_36_SEMC_DATA14
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#define MIMXRT_IOMUXC_SEMC_DATA15 IOMUXC_GPIO_EMC_37_SEMC_DATA15
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#define MIMXRT_IOMUXC_SEMC_ADDR00 IOMUXC_GPIO_EMC_09_SEMC_ADDR00
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#define MIMXRT_IOMUXC_SEMC_ADDR01 IOMUXC_GPIO_EMC_10_SEMC_ADDR01
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#define MIMXRT_IOMUXC_SEMC_ADDR02 IOMUXC_GPIO_EMC_11_SEMC_ADDR02
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#define MIMXRT_IOMUXC_SEMC_ADDR03 IOMUXC_GPIO_EMC_12_SEMC_ADDR03
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#define MIMXRT_IOMUXC_SEMC_ADDR04 IOMUXC_GPIO_EMC_13_SEMC_ADDR04
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#define MIMXRT_IOMUXC_SEMC_ADDR05 IOMUXC_GPIO_EMC_14_SEMC_ADDR05
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#define MIMXRT_IOMUXC_SEMC_ADDR06 IOMUXC_GPIO_EMC_15_SEMC_ADDR06
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#define MIMXRT_IOMUXC_SEMC_ADDR07 IOMUXC_GPIO_EMC_16_SEMC_ADDR07
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#define MIMXRT_IOMUXC_SEMC_ADDR08 IOMUXC_GPIO_EMC_17_SEMC_ADDR08
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#define MIMXRT_IOMUXC_SEMC_ADDR09 IOMUXC_GPIO_EMC_18_SEMC_ADDR09
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#define MIMXRT_IOMUXC_SEMC_ADDR10 IOMUXC_GPIO_EMC_23_SEMC_ADDR10
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#define MIMXRT_IOMUXC_SEMC_ADDR11 IOMUXC_GPIO_EMC_19_SEMC_ADDR11
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#define MIMXRT_IOMUXC_SEMC_ADDR12 IOMUXC_GPIO_EMC_20_SEMC_ADDR12
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#define MIMXRT_IOMUXC_SEMC_BA0 IOMUXC_GPIO_EMC_21_SEMC_BA0
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#define MIMXRT_IOMUXC_SEMC_BA1 IOMUXC_GPIO_EMC_22_SEMC_BA1
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#define MIMXRT_IOMUXC_SEMC_CAS IOMUXC_GPIO_EMC_24_SEMC_CAS
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#define MIMXRT_IOMUXC_SEMC_CKE IOMUXC_GPIO_EMC_27_SEMC_CKE
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#define MIMXRT_IOMUXC_SEMC_CLK IOMUXC_GPIO_EMC_26_SEMC_CLK
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#define MIMXRT_IOMUXC_SEMC_DM00 IOMUXC_GPIO_EMC_08_SEMC_DM00
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#define MIMXRT_IOMUXC_SEMC_DM01 IOMUXC_GPIO_EMC_38_SEMC_DM01
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#define MIMXRT_IOMUXC_SEMC_DQS IOMUXC_GPIO_EMC_39_SEMC_DQS
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#define MIMXRT_IOMUXC_SEMC_RAS IOMUXC_GPIO_EMC_25_SEMC_RAS
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#define MIMXRT_IOMUXC_SEMC_WE IOMUXC_GPIO_EMC_28_SEMC_WE
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#define MIMXRT_IOMUXC_SEMC_CS0 IOMUXC_GPIO_EMC_29_SEMC_CS0
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