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7649f5fbd2
* Make SDRAM test cache-aware for newer MCUs. * Use the defined data bus width (instead of the fixed 8-bits). * Allow optional failure on error with verbose error messages. * Test speed is now inverted (test accepts exhaustive instead fast).
18 lines
462 B
C
18 lines
462 B
C
/*
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* This file is part of the OpenMV project.
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* Copyright (c) 2013/2014 Ibrahim Abdelkader <i.abdalkader@gmail.com>
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* This work is licensed under the MIT license, see the file LICENSE for details.
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*
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* SDRAM Driver.
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*
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*/
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#ifndef __SDRAM_H__
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#define __SDRAM_H__
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bool sdram_init(void);
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void *sdram_start(void);
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void *sdram_end(void);
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void sdram_enter_low_power(void);
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void sdram_leave_low_power(void);
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bool sdram_test(bool exhaustive);
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#endif // __SDRAM_H__
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