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https://github.com/licsber/micropython.git
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f45412793e
This class supports SPI bus controller mode, with blocking transfers. SPI device numbers start at 0, to comply with the pinout of the Teensy boards. With the configured clock frequency the fastest baud rate is 33MHz. For messages longer 16 bytes DMA is used. The class uses the existing framework with extmod/machine_spi.c. Extended driver options: - drive=n with n being between 1 and 6 or PIN.POWER_1 to PIN.POWER_6. Since the pins used by the SPI are fixed, no Pin settings can be made. Thus the drive option is added allowing to control ringing and crosstalk on the connection. - gap_ns=nnnnn is the time between sent data items in a frame given in ns. Default is 2 clock cycles.
45 lines
2.1 KiB
C
45 lines
2.1 KiB
C
#define MICROPY_HW_BOARD_NAME "Teensy 4.1"
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#define MICROPY_HW_MCU_NAME "MIMXRT1062DVJ6A"
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#define BOARD_FLASH_SIZE (8 * 1024 * 1024)
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// Teensy 4.1 has 1 board LED
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#define MICROPY_HW_LED1_PIN (pin_GPIO_B0_03)
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#define MICROPY_HW_LED_ON(pin) (mp_hal_pin_high(pin))
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#define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_low(pin))
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#define BOARD_FLASH_CONFIG_HEADER_H "teensy41_flexspi_nor_config.h"
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#define MICROPY_HW_NUM_PIN_IRQS (4 * 32 + 3)
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// UART config: 8 UARTs at the pins for Teensy 4.1
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#define MICROPY_HW_UART_NUM (sizeof(uart_index_table) / sizeof(uart_index_table)[0])
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#define MICROPY_HW_UART_INDEX { 0, 6, 4, 2, 3, 8, 1, 7, 5 }
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#define IOMUX_TABLE_UART \
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{ IOMUXC_GPIO_AD_B0_12_LPUART1_TX }, { IOMUXC_GPIO_AD_B0_13_LPUART1_RX }, \
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{ IOMUXC_GPIO_AD_B1_02_LPUART2_TX }, { IOMUXC_GPIO_AD_B1_03_LPUART2_RX }, \
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{ IOMUXC_GPIO_AD_B1_06_LPUART3_TX }, { IOMUXC_GPIO_AD_B1_07_LPUART3_RX }, \
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{ IOMUXC_GPIO_B1_00_LPUART4_TX }, { IOMUXC_GPIO_B1_01_LPUART4_RX }, \
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{ IOMUXC_GPIO_B1_12_LPUART5_TX }, { IOMUXC_GPIO_B1_13_LPUART5_RX }, \
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{ IOMUXC_GPIO_AD_B0_02_LPUART6_TX }, { IOMUXC_GPIO_AD_B0_03_LPUART6_RX }, \
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{ IOMUXC_GPIO_EMC_31_LPUART7_TX }, { IOMUXC_GPIO_EMC_32_LPUART7_RX }, \
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{ IOMUXC_GPIO_AD_B1_10_LPUART8_TX }, { IOMUXC_GPIO_AD_B1_11_LPUART8_RX },
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#define MICROPY_HW_SPI_INDEX { 4, 3, 1 }
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#define IOMUX_TABLE_SPI \
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{ IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK }, { IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 }, \
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{ IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO }, { IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI }, \
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{ 0 }, { 0 }, \
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{ 0 }, { 0 }, \
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{ IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK }, { IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0 }, \
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{ IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO }, { IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI }, \
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{ IOMUXC_GPIO_B0_03_LPSPI4_SCK }, { IOMUXC_GPIO_B0_00_LPSPI4_PCS0 }, \
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{ IOMUXC_GPIO_B0_02_LPSPI4_SDO }, { IOMUXC_GPIO_B0_01_LPSPI4_SDI },
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#define DMA_REQ_SRC_RX { 0, kDmaRequestMuxLPSPI1Rx, kDmaRequestMuxLPSPI2Rx, \
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kDmaRequestMuxLPSPI3Rx, kDmaRequestMuxLPSPI4Rx }
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#define DMA_REQ_SRC_TX { 0, kDmaRequestMuxLPSPI1Tx, kDmaRequestMuxLPSPI2Tx, \
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kDmaRequestMuxLPSPI3Tx, kDmaRequestMuxLPSPI4Tx }
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