Commit Graph

6 Commits

Author SHA1 Message Date
Damien George
2c8c2b935e stm32/powerctrl: Improve support for changing system freq on H7 MCUs.
This commit improves pllvalues.py to generate PLL values for H7 MCUs that
are valid (VCO in and out are in range) and extend for the entire range of
SYSCLK values up to 400MHz (up to 480MHz is currently unsupported).
2020-01-31 23:25:18 +11:00
Damien George
89ebb3325b stm32/boards/pllvalues.py: Support HSx_VALUE defined without uint32_t. 2019-06-25 14:18:24 +10:00
Damien George
34cae24e30 stm32/boards/pllvalues.py: Search nested headers for HSx_VALUE defines. 2019-05-31 21:44:53 +10:00
Damien George
3fbf32b947 stm32/powerctrl: Support changing frequency when HSI is clock source.
This patch makes pllvalues.py generate two tables: one for when HSI is used
and one for when HSE is used.  The correct table is then selected at
compile time via the existing MICROPY_HW_CLK_USE_HSI.
2019-05-02 13:00:00 +10:00
Damien George
47550ef2cd stm32: For MCUs that have PLLSAI allow to set SYSCLK at 2MHz increments.
MCUs that have a PLLSAI can use it to generate a 48MHz clock for USB, SDIO
and RNG peripherals.  In such cases the SYSCLK is not restricted to values
that allow the system PLL to generate 48MHz, but can be any frequency.
This patch allows such configurability for F7 MCUs, allowing the SYSCLK to
be set in 2MHz increments via machine.freq().  PLLSAI will only be enabled
if needed, and consumes about 1mA extra.  This fine grained control of
frequency is useful to get accurate SPI baudrates, for example.
2018-09-11 16:42:57 +10:00
Damien George
01dd7804b8 ports: Make new ports/ sub-directory and move all ports there.
This is to keep the top-level directory clean, to make it clear what is
core and what is a port, and to allow the repository to grow with new ports
in a sustainable way.
2017-09-06 13:40:51 +10:00