Commit Graph

9 Commits

Author SHA1 Message Date
Damien George
12413e92a3 stm32/powerctrlboot: Fix config of systick IRQ priority on F0/L0/WB MCU.
Prior to this commit the systick IRQ priority was set at lowest priority on
F0/L0/WB MCUs, because it was left at the default and never configured.
This commit ensures the priority is configured and sets it to the highest
priority.
2019-10-21 12:23:41 +11:00
Damien George
4c1ad1f691 stm32: Add support for USB on L0 MCUs. 2019-07-16 14:45:53 +10:00
iabdalkader
1646eff864 stm32/irq: Fix IRQ_ENABLE_STATS stats config to work on all MCUs.
Only the M4 and M7 MCUs have an FPU and FPU_IRQn, and FPU_IRQn is not
always the last entry/IRQ number.
2019-05-15 16:04:01 +10:00
iabdalkader
07af74daef stm32/spi: Enable SPI IRQs and add IRQHandlers for H7 MCUs.
The H7 HAL uses SPI IRQs when the SPI is running in DMA mode.
2019-05-15 15:59:25 +10:00
Damien George
0941a467e7 stm32: Change flash IRQ priority from 2 to 6 to prevent preemption.
The flash-IRQ handler is used to flush the storage cache, ie write
outstanding block data from RAM to flash.  This is triggered by a timeout,
or by a direct call to flush all storage caches.

Prior to this commit, a timeout could trigger the cache flushing to occur
during the execution of a read/write to external SPI flash storage.  In
such a case the storage subsystem would break down.

SPI storage transfers are already protected against USB IRQs, so by
changing the priority of the flash IRQ to that of the USB IRQ (what is
done in this commit) the SPI transfers can be protected against any
timeouts triggering a cache flush (the cache flush would be postponed until
after the transfer finished, but note that in the case of SPI writes the
timeout is rescheduled after the transfer finishes).

The handling of internal flash sync'ing needs to be changed to directly
call flash_bdev_irq_handler() sync may be called with the IRQ priority
already raised (eg when called from a USB MSC IRQ handler).
2018-09-12 15:46:04 +10:00
Damien George
070937fe93 stm32: Add support for Cortex-M0 CPUs. 2018-05-28 21:46:20 +10:00
Damien George
a03e6c1e05 stm32/irq: Define IRQ priorities directly as encoded hardware values.
For a given IRQn (eg UART) there's no need to carry around both a PRI and
SUBPRI value (eg IRQ_PRI_UART, IRQ_SUBPRI_UART).  Instead, the IRQ_PRI_UART
value has been changed in this patch to be the encoded hardware value,
using NVIC_EncodePriority.  This way the NVIC_SetPriority function can be
used directly, instead of going through HAL_NVIC_SetPriority which must do
extra processing to encode the PRI+SUBPRI.

For a priority grouping of 4 (4 bits for preempt priority, 0 bits for the
sub-priority), which is used in the stm32 port, the IRQ_PRI_xxx constants
remain unchanged in their value.

This patch also "fixes" the use of raise_irq_pri() which should be passed
the encoded value (but as mentioned above the unencoded value is the same
as the encoded value for priority grouping 4, so there was no bug from this
error).
2018-05-02 14:41:02 +10:00
Damien George
d966a33486 stm32: Change header include guards from STMHAL to STM32 to match dir. 2018-02-15 15:47:04 +11:00
Damien George
01dd7804b8 ports: Make new ports/ sub-directory and move all ports there.
This is to keep the top-level directory clean, to make it clear what is
core and what is a port, and to allow the repository to grow with new ports
in a sustainable way.
2017-09-06 13:40:51 +10:00