Frequency range 15Hz/18Hz to > 1 MHz, with decreasing resolution of the
duty cycle. The basic API is supported as documentated, except that
keyword parameters are accepted for both the instatiaton and the
PWM.init() call.
Extensions: support PWM for channel pairs. Channel pairs are declared by
supplying 2-element tuples for the pins. The two channels of a pair must
be the A/B channel of a FLEXPWM module. These form than a complementary
pair.
Additional supported keyword arguments:
- center=value Defines the center position of a pulse within the pulse
cycle. The align keyword is actually shortcut for center.
- sync=True|False: If set to True, the channels will be synchronized to a
submodule 0 channel, which has already to be enabled.
- align=PWM.MIDDLE | PMW.BEGIN | PWM.END. It defines, whether synchronized
channels are Center-Aligned or Edge-aligned. The channels must be either
complementary a channel pair or a group of synchronized channels. It may
as well be applied to a single channel, but withiout any benefit.
- invert= 0..3. Controls ouput inversion of the pins. Bit 0 controls the
first pin, bit 1 the second.
- deadtime=time_ns time of complementary channels for delaying the rising
slope.
- xor=0|1|2 xor causes the output of channel A and B to be xored. If
applied to a X channel, it shows the value oif A ^ B. If applied to an A
or B channel, both channel show the xored signal for xor=1. For xor=2,
the xored signal is split between channels A and B. See also the
Reference Manual, chapter about double pulses. The behavior of xor=2 can
also be achieved using the center method for locating a pulse within a
clock period.
The output is enabled for board pins only.
CPU pins may still be used for FLEXPWM, e.g. as sync source, but the signal
will not be routed to the output. That applies only to FLEXPWM pins. The
use of QTMR pins which are not board pins will be rejected.
As part of this commit, the _WFE() statement is removed from
ticks_delay_us64() to prevent PWM glitching during calls to sleep().
This commit implements 10/100 Mbit Ethernet support in the mimxrt port.
The following boards are configured without ETH network:
- MIMXRT1010_EVK
- Teensy 4.0
The following boards are configured with ETH network:
- MIMXRT1020_EVK
- MIMXRT1050_EVK
- MIMXRT1060_EVK
- MIMXRT1064_EVK
- Teensy 4.1
Ethernet support tested with TEENSY 4.1, MIMRTX1020_EVK and MIMXRT1050_EVK.
Build tested with Teensy 4.0 and MIMXRT1010_EVK to be still working.
Compiles and builds properly for MIMXRT1060_EVK and MIMXRT1064_EVK, but not
tested lacking suitable boards.
Tested functions are:
- ping works bothway
- simple UDP transfer works bothway
- ntptime works
- the ftp server works
- secure socker works
- telnet and webrepl works
The MAC address is 0x02 plus 5 bytes from the manifacturing info field,
which can be considered as unique per device.
Some boards do not wire the RESET and INT pin of the PHY transceiver. For
operation, these are not required. If they are defined, they will be used.
Adds support for SDRAM via `SEMC` peripheral. SDRAM support can be
enabled in the mpconfigboard.mk file by setting `MICROPY_HW_SDRAM_AVAIL`
to `1` and poviding the size of the RAM via `MICROPY_HW_FLASH_SIZE`.
When SDRAM support is enabled the whole SDRAM is currently used used
for MicroPython heap.
Signed-off-by: Philipp Ebensberger
- Moves definition of BOARD_FLASH_SIZE and other header files related to
flash configuration into the Makefile.
- Adds board specific clock_config.h.
- Adds board.h, pin_mux.h, and peripherals.h as they are
required by NXP MCU SDK in order to use our own clock_config.h.
- Renames board specific FlexSPI configuration files.
- Updates flash frequency of MIMXRT1020_EVK
- Creates separated flash_config files for QSPI NOR and
QSPI Hyper flash.
- Unifies VFS start address to be @ 1M for 1010 and 1020 boards.
- Unifies 1050EVK boards
- Adds support to both NOR and HyperFlash on boards with
both capabilities.
- Adds automatic FlexRAM initialization to start-up code based on
linker script and NXP HAL.
- Applies code formatting to all files in mimxrt port.
With this change the flash configuration is restructured and
organized. This simplifies the configuration process and
provides a better overview of each board's settings. With the integration
of clock_config.h, board.h, pin_mux.h, and peripherals.h we gain better
control of the settings and clock configurations. Furthermore the
implementation of an explicit FlexRAM setup improves the system
performance and allows for performance tuning.
Signed-off-by: Philipp Ebensberger
This commit adds full support for a filesystem on all boards, with a block
device object mimxrt.Flash() and uos.VfsLfs2 enabled.
Main changes are:
- Refactoring of linker scripts to accomodate reserved area for VFS. VFS
will take up most of the available flash. 1M is reserved for code. 9K is
reserved for flash configuration, interrupts, etc.
- Addition of _boot.py with filesystem init code, called from main.c.
- Definition of the mimxrt module with a Flash class in modmimxrt.[ch].
- Implementation of a flash driver class in mimxrt_flash.c. All flashing
related functions are stored in ITCM RAM.
- Addition of the uos module with filesystem functions.
- Implementation of uos.urandom() for the sake of completeness of the uos
module.
It uses sample code from CircuitPython supplied under MIT license, which
uses the NXP SDK example code.
Done in collaboration with Philipp Ebensberger aka @alphaFred who
contributed the essential part to enable writing to flash while code is
executing, among other things.
