All board pins that have UART's assigned can be used. Baud rate range is
75 Baud to ~2 MBaud.
No flow control yet, and only RX is buffered. TX buffer and flow control
may be added later for SAMD51 with its larger RAM and Flash.
Its API conforms to the docs. There are 16 IRQ channels available, which
will be used as assignable to the GPIO numbers. In most cases, the irq
channel is GPIO_no % 16.
Changes are:
- Have two separate tables for SAM21 and SAMD51.
- Use a short table for SAMD21.
- Add a comment to each line telling what it's for, making further use
easier.
- Add preliminary handlers/entries for PendSV, EIC and Sercom. These will
be replaced later when the respecitve modules are added.
Features are:
- 3 to 5 different frequency groups.
- Freq range of 1Hz - 24 MHz.
- Duty rate stays stable on freq change.
Keyword options to the PWM constructor:
- device=n Select a specific PWM device. If no device is specified, a free
device is chosen, if available at that pin.
- freq=nnnn
- duty_u16=nnnn
- duty_ns=nnnn
- invert=True/False Allowing two outputs on the same device/channel to have
complementary signals.
If both freq and duty are provided, PWM output will start immediately.
Pins at the same device have the same frequency. If the PWM output number
exceeds the number of channels at the PWM device, the effctive channel_no
is output_no % channel_count. So with a channel count of 4, output 7 is
assigned to channel 3. Pins at a certain channel have the same frequency
and duty rate, but may be seperately inverted.
With the method read_u16(). Keyword arguments of the constructor are:
- bits=n The resolution; default is 12.
- average=n The average of samples, which are taken and cumulated. The
default value is 16. Averaging by hw is faster than averaging
in code.
The ADC runs at a clock freq 1.5 MHz. A single 12 bit conversion takes
8 microseconds.
The pin af table is a representation of the MUX table from the data sheet.
It provides information for each pin about the supported device functions.
That information is needed by pin.irq, machine.ADC, machine.PWM,
machine.UART, machine.SPI and machine.I2C. For each of these, the table
tells for each pin, which device number, af number and pad number is
assigned. Using the table gives a straight, uniform access to the
information, where the benefit outweights the size of the table, which is
not that large.
The tables are MCU-specific. It is not required to tell for each board,
which and where each of the above devices is available. That makes addding
boards easy.
Note: The information for DAC and I2S was not included, since it affects
only a few pins.
Changes in this commit are:
- Use mphal_xx functions whenever possible.
- Remove obsolete includes.
- Clean up traces of a non-functional pin.irq() from earlier builds.
Pin.irq() will be added in further commits in a working manner.
The changes in this commit are:
- Add an interface for pin open-drain mode.
- Improve ticks_us() by using the us-counter.
- Improve ticks_cpu() by using the CPU's SysTick.
Clock settings:
- GCLK0: 48 MHz (SAMD21) or 120 MHz(SAMD51).
- GCLK1: 32768 Hz for driving the PLL.
- GCLK2: 48 MHz for tzhe peripheral clock.
- GCLK3: 1 MHz (SAMD21) or 8 MHz (SAMD51) for the µs ticks timer.
- GCLK8: 1 kHz for WDT (SAMD21 only).
If a 32 kHz crystal is present, it will be used as clock source. Otherwise
the DFLL48M in open-loop mode is used.
GCLK0 for SAM51 can be changed between 48 MHz and 200 MHz. The specified
range is 96 MHz - 120 MHz.
These two boards are used for testing, so it is favorable to have them
added early.
The full test set is:
- ADAFRUIT_FEATHER_M4_EXPRESS: SAMD51 with 32kHz crystal.
- ADAFRUIT_ITSYBITSY_M0_EXPRESS: SAMD21 without crystal.
- ADAFRUIT_ITSYBITSY_M4_EXPRESS: SAMD51 without crystal.
- SEEED_XIAO: SAM21 with 32kHz crystal.
Auto DMA channel is supported in IDF v4.4, and is required to be used on S3
chips, so use this simpler configuration option where possible.
Fixes issue #8634.
Signed-off-by: Damien George <damien@micropython.org>
Updates all README.md and docs, and manifests to `require("mip")`.
Also extend and improve the documentation on freezing and packaging.
This work was funded through GitHub Sponsors.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
This uses the frozentest.mpy that is also used by ports/minimal.
Also fixes two bugs that these new tests picked up:
- File extension matching in manifestfile.py.
- Handling of freeze_mpy results in makemanifest.
This work was funded through GitHub Sponsors.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
frozentest.mpy was previously duplicated in ports/minimal and
ports/powerpc.
This needs to be re-generated on every .mpy version increase, so might as
well just have a single copy of it.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
Instead of being an explicit field, it's now a slot like all the other
methods.
This is a marginal code size improvement because most types have a make_new
(100/138 on PYBV11), however it improves consistency in how types are
declared, removing the special case for make_new.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
The goal here is to remove a slot (making way to turn make_new into a slot)
as well as reduce code size by the ~40 references to mp_identity_getiter
and mp_stream_unbuffered_iter.
This introduces two new type flags:
- MP_TYPE_FLAG_ITER_IS_ITERNEXT: This means that the "iter" slot in the
type is "iternext", and should use the identity getiter.
- MP_TYPE_FLAG_ITER_IS_CUSTOM: This means that the "iter" slot is a pointer
to a mp_getiter_iternext_custom_t instance, which then defines both
getiter and iternext.
And a third flag that is the OR of both, MP_TYPE_FLAG_ITER_IS_STREAM: This
means that the type should use the identity getiter, and
mp_stream_unbuffered_iter as iternext.
Finally, MP_TYPE_FLAG_ITER_IS_GETITER is defined as a no-op flag to give
the default case where "iter" is "getiter".
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
This will always have the maximum/minimum size of a mp_obj_type_t
representation and can be used as a member in other structs.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
The buffer protocol type only has a single member, and this existing layout
creates problems for the upcoming split/slot-index mp_obj_type_t layout
optimisations.
If we need to make the buffer protocol more sophisticated in the future
either we can rely on the mp_obj_type_t optimisations to just add
additional slots to mp_obj_type_t or re-visit the buffer protocol then.
This change is a no-op in terms of generated code.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
