If a board defines a custom bootloader entry function it will be called
first, if not and the ROM API supports RUN bootloader API, then
`machine.bootloader()` will jump to the ROM serial downloader in USB mode.
This commit allows boards to disable Ethernet and keep the networking stack
enabled, to use an alternate networking interface, such as WiFi.
Note that the `network` and `socket` modules are now enabled by default for
a board.
This commit is necessary to make MicroPython work on this eval kit out of
the box, as the eval kit ships with the HyperFlash physically disconnected
from the bus (refer to the schematics or the user guide) and the QSPI
connected instead, but the fuses/board/pins are configured to boot from
internal flash (on FlexSPI2).
Note that enabling the HyperFlash is not trivial, as it requires soldering
and desoldering of many small footprint resistors and changing fuses.
Helps prevent the filesystem from getting formatted by mistake, among other
things. For example, on a Pico board, entering Ctrl+D and Ctrl+C fast many
times will eventually wipe the filesystem (without warning or notice).
Further rationale: Ctrl+C is used a lot by automation scripts (eg mpremote)
and UI's (eg Mu, Thonny) to get the board into a known state. If the board
is not responding for a short time then it's not possible to know if it's
just a slow start up (eg in _boot.py), or an infinite loop in the main
application. The former should not be interrupted, but the latter should.
The only way to distinguish these two cases would be to wait "long enough",
and if there's nothing on the serial after "long enough" then assume it's
running the application and Ctrl+C should break out of it. But defining
"long enough" is impossible for all the different boards and their possible
behaviour. The solution in this commit is to make it so that frozen
start-up code cannot be interrupted by Ctrl+C. That code then effectively
acts like normal C start-up code, which also cannot be interrupted.
Note: on the stm32 port this was never seen as an issue because all
start-up code is in C. But now other ports start to put more things in
_boot.py and so this problem crops up.
Signed-off-by: David Grayson <davidegrayson@gmail.com>
The dispatch active flag is only set once and never reset, so it will
always call the dispatch handler (once enabled), and it's not really
needed because it doesn't make things more efficient.
Also remove unused included headers.
Changes in this commit:
- Move the pwm_seq array to the p_config data structure. That prevents
potential resource collisions between PWM devices.
- Rename the keyword argument 'id' to 'device'. That's consistent with the
SAMD port as the other port allowing to specify it.
This is a best-effort implementation of write polling. It's difficult to
do correctly because if there are multiple output streams (eg UART and USB
CDC) then some may not be writeable while others are. A full solution
should also have a return value from mp_hal_stdout_tx_strn(), returning the
number of bytes written to the stream(s). That's also hard to define.
The renesas-ra and stm32 ports already implement a similar best-effort
mechanism for write polling.
Fixes issue #11026.
Signed-off-by: Damien George <damien@micropython.org>
Prior to this change, setting of UART parameters like parity, stop bits or
data bits did not work correctly. As suggested by @iabdalkader, adding
__DSB() fixes the problem, making sure that changes to the UART LCR_H
register are seen by the peripheral.
Note: the FIFO is already enabled in the call to uart_init(), so the call
to uart_set_fifo_enabled() is not required, but kept for visibility.
Fixes issue #10976.
The following have been tested and are working:
- 550MHz CPU frequency
- UART REPL via ST-Link
- USB REPL and mass storage
- 3x LEDs and 1x user button
- Ethernet
Signed-off-by: Damien George <damien@micropython.org>
For builds with DEBUG=1 and MICROPY_HW_ENABLE_UART_REPL=1, calling
stdio_init_all() in main() detaches the UART input from REPL. This change
suppresses calling stdio_init_all() then.
Previously, setting MICROPY_HW_ENABLE_USBDEV to 0 caused build errors. The
change affects the nrf and samd ports as well, so MICROPY_HW_ENABLE_USBDEV
had to be explicitly enabled there.
The configuration options MICROPY_HW_ENABLE_USBDEV and
MICROPY_HW_ENABLE_UART_REPL are independent, and can be enabled or disabled
by a board.
Signed-off-by: Damien George <damien@micropython.org>
Changes in this commit:
- Add the timeout and timeout_char keyword options.
- Make uart.read() non-blocking.
- Add uart.any().
- Add ioctl MP_STREAM_POLL handling.
- Change uart.write() into non-busy waiting. uart.write() still waits until
all data has been sent, but calls MICROPY_EVENT_POLL_HOOK while waiting.
uart.write() uses DMA for transfer. One option would be to add a small
local buffer, such that transfers up to the size of the buffer could be
done without waiting.
- As a side effect to the change of uart.write(), uart.txdone() and ioctl
flush now report/wait correctly for the end of transmission.
- Change machine_hard_uart_buf_t in machine_hard_uart_obj_t to an instance
of that struct, rather than a pointer to one.
Even if boards do not have a clock crystal. In that case, the clock
quality will be very poor.
Always having machine.RTC means that the date/time can be set in a way that
is consistent with other ports.
This commit also removes the special code in modutime.c for devices without
the RTC class.
Signed-off-by: Damien George <damien@micropython.org>
These have the same frequency, but can have different duty cycle and
polarity.
pwm.deinit() stops all channels of a module, but does not release the
module. pwm.init() without arguments restarts all outputs.
Using extmod/machine_pwm.c for the Python bindings and the existing
softpwm.c driver, by just adding the interface.
Properties:
- Frequency range 1-3906 Hz.
- All PWM outputs run at the same frequency but can have different duty
cycles.
- Limited to the P0.x pins.
Since it uses the existing softpwm.c mechanism, it will be affected by
playing music with the music class.
This is a breaking change, making the hardware PWM on the nrf port
compatible with the other ports providing machine.PWM.
Frequency range 4Hz - ~5.4 MHz. The base clock range is 125kHz to 16 MHz,
and the divider range is 3 - 32767.
The hardware supports up to four outputs per PWM device with different duty
cycles, but only one output is (and was) supported.
Borrowing an idea from the mimxrt port (also stm32 port): in the loader
input file memmap_mp.ld calculate __GcHeapStart and __GcHeapEnd as the
unused RAM. Then in main.c use these addresses as arguments to gc_init().
The benefits of this change are:
1) When libraries are added or removed in the future changing BSS usage,
main.c's sizing of the GC heap does not need to be changed.
2) Currently these changes make the GC area about 30 KBytes larger, eg on
PICO_W the GC heap increases from 166016 to 192448 bytes. Without that
change this RAM would never get used.
3) If someone wants to disable one or more SRAM blocks on the RP2040 to
reduce power consumption it will be easy: just change the MEMORY section
in memmap_mp.ld. For instance to not use SRAM2 and SRAM3 change it to:
MEMORY
{
FLASH(rx) : ORIGIN = 0x10000000, LENGTH = 2048k
RAM(rwx) : ORIGIN = 0x21000000, LENGTH = 128k
SCRATCH_X(rwx) : ORIGIN = 0x20040000, LENGTH = 4k
SCRATCH_Y(rwx) : ORIGIN = 0x20041000, LENGTH = 4k
}
Then to turn off clocks for SRAM2 and SRAM3 from MicroPython, set the
appropriate bits in WAKE_EN0 and SLEEP_EN0.
Tested by running the firmware.uf2 file on PICO_W and displaying
micropython.mem_info(). Confirmed GC total size approximately matched the
size calculated by the loader.
Signed-off-by: cpottle9 <cpottle9@outlook.com>
This function seems to work fine in multi-core applications now.
The delay is now in units of microseconds instead of depending on the clock
speed, and is adjustable by board configuration headers.
Also added documentation.
These changes allow the firmware to support both the REV-1 and REV-2
versions of the board:
- Freeze the new device drivers used in REV-2.
- Add a board-level module that abstracts the IMU chipset.
Changes are:
- Freeze micropython-lib time module to get strftime.
- Reserve the last 1MB of QSPI flash for (optional) WiFi firmware storage.
- Disable SD card mount on boot.
- Enable high-speed BLE firmware download.
This is for boards without networking support so that the default boot.py
continues to work.
Also update boot.py to use network.country and network.hostname instead.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
This removes the previous WiFi driver from drivers/cyw43 (but leaves behind
the BT driver), and makes the stm32 port (i.e. PYBD and Portenta) use the
new "lib/cyw43-driver" open-source driver already in use by the rp2 port.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
Rather than duplicating the implementation of `network`, this allows
ESP8266 to use the shared one in extmod. In particular this gains access
to network.hostname and network.country.
Other than adding these two methods, there is no other user-visible change.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
Rather than duplicating the implementation of `network`, this allows ESP32
to use the shared one in extmod. In particular this gains access to
network.hostname and network.country.
Set default hostnames for various ESP32 boards.
Other than adding these two methods and the change to the default hostname,
there is no other user-visible change.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
This provides a standard interface to setting the global networking config
for all interfaces and interface types.
For ports that already use either a static hostname (mimxrt, rp2) they will
now use the configured value. The default is configured by the port
(or optionally the board).
For interfaces that previously supported .config(hostname), this is still
supported but now implemented using the global network.hostname.
Similarly, pyb.country and rp2.country are now deprecated, but the methods
still exist (and forward to network.hostname).
Because ESP32/ESP8266 do not use extmod/modnetwork.c they are not affected
by this commit.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
Makefile's support "else ifdef", so use it to make the logic clearer.
Also dedent some associated lines for consistency.
Signed-off-by: Damien George <damien@micropython.org>
This matches the behavior of the makefile ports but implemented for CMake,
making it easy to specify custom board definitions.
This work was funded through GitHub Sponsors.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
This matches the behavior of the makefile ports but implemented for CMake,
making it easy to specify custom board definitions.
This work was funded through GitHub Sponsors.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
This allows:
$ make BOARD_DIR=path/to/board
to infer BOARD=board, rather than the previous behavior that required
additionally setting BOARD explicitly.
Also makes the same change for VARIANT_DIR -> VARIANT on Unix.
This work was funded through GitHub Sponsors.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
Signed-off-by: Damien George <damien@micropython.org>
This RNG passes many of the Diehard tests and also the AIS31 test suite.
The RNG is quite slow, delivering 200bytes/s.
Tested on boards with and without a crystal.
It turned out that the result of calling ticks_us() was always either odd
or even, depending on some internal state during boot. So the us-counter
was set to a 2 MHz input and the result shifted by 1. The counting period
is still long enough, since internally a (now) 63 bit value is used for us.
By using the phase jitter between the DFLL48M clock and the FDPLL96M clock.
Even if both use the same reference source, they have a different jitter.
SysTick is driven by FDPLL96M, the us counter by DFLL48M. As a random
source, the us counter is read out on every SysTick and the value is used
to accumulate a simple multiply, add and xor register. According to tests
it creates about 30 bit random bit-flips per second. That mechanism will
pass quite a few RNG tests, has a suitable frequency distribution and
serves better than just the time after boot to seed the PRNG.
Allowing to increase the clock a little bit to 54Mhz. Not much of a gain,
but useful for generating a RNG entropy source from the jitter between
DFLL48M and FDPLL96M.
Remove two SPARKFUN_SAMD51_THINGS_PLUS pin definitions. There were
definitions of TXD and RXD, but these pins do not exist on the board. They
were only shown in the schematics.
Also remove any reference to LED_. This is just a text change, no
functional change.
For compatibility with other ports. Code increase up to ~1250 bytes for
SAMD21. The feature is configurable via MICROPY_PY_MACHINE_PIN_BOARD_CPU
in case flash memory is tight.
This further aligns the features available on Pico and Pico W boards.
os.dupterm is generally useful, but can still be disabled by a board if
needed. hashlib.sha1 requires mbedtls for the implementation, but that's
always available (due to ucryptolib's requirements). The entire hashlib
module can still be disabled by an individual board if needed.
Fixes issue #7881.
Signed-off-by: Damien George <damien@micropython.org>
Before, both uwTick and mp_hal_ticks_ms() were used as clock source. That
assumes, that these two are synchronous and start with the same value,
which may be not the case for all ports. If the lag between uwTick and
mp_hal_ticks_ms() is larger than the timer interval, the timer would either
rush up until the times are synchronous, or not start until uwTick wraps
over.
As suggested by @dpgeorge, MICROPY_SOFT_TIMER_TICKS_MS is now used in
softtimer.c, which has to be defined in a port's mpconfigport.h with
the variable that holds the SysTick counter.
Note that it's not possible to switch everything in softtimer.c to use
mp_hal_ticks_ms() because the logic in SysTick_Handler that schedules
soft_timer_handler() uses (eg on mimxrt) the uwTick variable directly
(named systick_ms there), and mp_hal_ticks_ms() uses a different source
timer. Thus it is made fully configurable.
The default now includes all sub-components (security, l2cap, etc)
and using the kwarg options is no longer supported.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
The default now includes all sub-components (security, l2cap, etc)
and using the kwarg options is no longer supported.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
Prior to this commit, on Pico W (where the CYW43 driver is enabled) the PIO
instruction memory was not released on soft reset, so using PIO after a
soft reset would eventually (after a few soft resets) lead to ENOMEM when
allocating a PIO program.
This commit fixes that by tracking the use of PIO memory by this module and
freeing it on soft reset.
Similarly, use of the state machines themselves are tracked and released on
soft reset.
Fixes issue #9003.
Signed-off-by: Damien George <damien@micropython.org>
