Commit Graph

8 Commits

Author SHA1 Message Date
robert-hh
8f6315a279 mimxrt/machine_pwm: Fix freq change, PWM print, and error checks.
Three bugs have been fixed in this commit:

1. When the duty was set with duty_u16(), changing the freq with pwm.freq()
   would not keep relative duty rate, but the absolute pulse duration.

2. Fix another inconsistency when displaying the PWM pin's properties of a
   QTMR channel.

3. Improve the error checks for the second channel being a PWM pin and pin
   pairs to be a FLEXPWM A/B pair.

Signed-off-by: robert-hh <robert@hammelrath.com>
2023-06-01 12:25:34 +10:00
robert-hh
9c7ad68165 mimxrt/machine_pwm: Start PWM only if freq and duty are set.
And also fix/improve the following:
- Simplify the duty handling a little bit.
- Allow duty_u16(65536), which sets the output high.
- Rename machine_pwm_start() to mp_machine_pwm_start(), in preparation for
  a possible start/stop method pair.
2023-05-04 13:09:39 +10:00
Damien George
b1229efbd1 all: Fix spelling mistakes based on codespell check.
Signed-off-by: Damien George <damien@micropython.org>
2023-04-27 18:03:06 +10:00
robert-hh
5e990cc27f mimxrt: Add support for MIMXRT1176 MCUs, and MIMXRT1170_EVK board.
The RT1176 has two cores, but the actual firmware supports only the CM7.
There are currently no good plans on how to use the CM4.

The actual MIMXRT1170_EVK board is on par with the existing MIMXRT boards,
with the following extensions:
- Use 64 MB RAM for the heap.
- Support both LAN interfaces as LAN(0) and LAN(1), with LAN(1)
  being the 1GB interface.

The dual LAN port interface can eventually be adapted as well for the
RT1062 MCU.

This work was done in collaboration with @alphaFred.
2022-11-17 14:11:50 +11:00
Jim Mussared
0e7bfc88c6 all: Use mp_obj_malloc everywhere it's applicable.
This replaces occurences of

    foo_t *foo = m_new_obj(foo_t);
    foo->base.type = &foo_type;

with

    foo_t *foo = mp_obj_malloc(foo_t, &foo_type);

Excludes any places where base is a sub-field or when new0/memset is used.

Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
2022-05-03 22:28:14 +10:00
Philipp Ebensberger
62cb2069bb mimxrt/machine_pin: Change pin drive constants to DRIVE_x naming.
Updated DRIVE_x constants representing pin drive strength.

Signed-off-by: Philipp Ebensberger
2022-03-08 22:30:33 +11:00
robert-hh
1dc366f901 mimxrt: Replace Pin-config constants by a function call.
The Pin config setting by IOMUXC_SetPinConfig() is supplied by a
bit pattern. That pattern is specific for a MCU family. In preparation
for supporting the MIMXRT117x family, the constant bit pattern is
replaced by a function call, such that the bit pattern is created
at a single place. The code for this functions was taken from
machine_pin.c.

Note: A working port for the MIMXRT1176 exists already.
2022-01-27 16:53:30 +11:00
robert-hh
81f706aee4 mimxrt: Support PWM using the FLEXPWM and QTMR modules.
Frequency range 15Hz/18Hz to > 1 MHz, with decreasing resolution of the
duty cycle.  The basic API is supported as documentated, except that
keyword parameters are accepted for both the instatiaton and the
PWM.init() call.

Extensions: support PWM for channel pairs.  Channel pairs are declared by
supplying 2-element tuples for the pins.  The two channels of a pair must
be the A/B channel of a FLEXPWM module.  These form than a complementary
pair.

Additional supported keyword arguments:

- center=value Defines the center position of a pulse within the pulse
  cycle.  The align keyword is actually shortcut for center.

- sync=True|False: If set to True, the channels will be synchronized to a
  submodule 0 channel, which has already to be enabled.

- align=PWM.MIDDLE | PMW.BEGIN | PWM.END. It defines, whether synchronized
  channels are Center-Aligned or Edge-aligned.  The channels must be either
  complementary a channel pair or a group of synchronized channels.  It may
  as well be applied to a single channel, but withiout any benefit.

- invert= 0..3. Controls ouput inversion of the pins.  Bit 0 controls the
  first pin, bit 1 the second.

- deadtime=time_ns time of complementary channels for delaying the rising
  slope.

- xor=0|1|2 xor causes the output of channel A and B to be xored.  If
  applied to a X channel, it shows the value oif A ^ B.  If applied to an A
  or B channel, both channel show the xored signal for xor=1.  For xor=2,
  the xored signal is split between channels A and B.  See also the
  Reference Manual, chapter about double pulses.  The behavior of xor=2 can
  also be achieved using the center method for locating a pulse within a
  clock period.

The output is enabled for board pins only.

CPU pins may still be used for FLEXPWM, e.g. as sync source, but the signal
will not be routed to the output.  That applies only to FLEXPWM pins.  The
use of QTMR pins which are not board pins will be rejected.

As part of this commit, the _WFE() statement is removed from
ticks_delay_us64() to prevent PWM glitching during calls to sleep().
2021-11-24 13:48:27 +11:00