diff --git a/README.md b/README.md index 3e81a655d..48942daa7 100644 --- a/README.md +++ b/README.md @@ -29,15 +29,13 @@ Major components in this repository: - py/ -- the core Python implementation, including compiler and runtime. - unix/ -- a version of Micro Python that runs on Unix. - stmhal/ -- a version of Micro Python that runs on the Micro Python board - with an STM32F405RG (using ST's new Cube HAL drivers). + with an STM32F405RG (using ST's Cube HAL drivers). - teensy/ -- a version of Micro Python that runs on the Teensy 3.1 (preliminary but functional). Additional components: - bare-arm/ -- a bare minimum version of Micro Python for ARM MCUs. Start with this if you want to port Micro Python to another microcontroller. -- stm/ -- obsolete version of Micro Python for the Micro Python board - that uses ST's old peripheral drivers. - unix-cpy/ -- a version of Micro Python that outputs bytecode (for testing). - tests/ -- test framework and test scripts. - tools/ -- various tools, including the pyboard.py module. diff --git a/stm/.gitignore b/stm/.gitignore deleted file mode 100644 index 378eac25d..000000000 --- a/stm/.gitignore +++ /dev/null @@ -1 +0,0 @@ -build diff --git a/stm/Makefile b/stm/Makefile deleted file mode 100644 index ab4d0ff3f..000000000 --- a/stm/Makefile +++ /dev/null @@ -1,220 +0,0 @@ -include ../py/mkenv.mk - -# qstr definitions (must come before including py.mk) -QSTR_DEFS = qstrdefsport.h - -# include py core make definitions -include ../py/py.mk - -CMSIS_DIR=cmsis -STMPERIPH_DIR=stmperiph -STMUSB_DIR=stmusb -STMUSBD_DIR=stmusbd -STMUSBH_DIR=stmusbh -FATFS_DIR=fatfs -CC3K_DIR=cc3k -DFU=../tools/dfu.py - -CROSS_COMPILE = arm-none-eabi- - -INC = -I. -INC += -I$(PY_SRC) -INC += -I$(BUILD) -INC += -I$(CMSIS_DIR) -INC += -I$(STMPERIPH_DIR) -INC += -I$(STMUSB_DIR) -INC += -I$(STMUSBD_DIR) -INC += -I$(STMUSBH_DIR) -INC += -I$(FATFS_DIR) -#INC += -I$(CC3K_DIR) - -CFLAGS_CORTEX_M4 = -mthumb -mtune=cortex-m4 -mabi=aapcs-linux -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -fsingle-precision-constant -Wdouble-promotion -CFLAGS = $(INC) -Wall -Werror -ansi -std=gnu99 $(CFLAGS_CORTEX_M4) $(COPT) - -BOARD ?= PYBOARD4 -ifeq ($(wildcard boards/$(BOARD)/.),) -$(error Invalid BOARD specified) -endif -CFLAGS += -Iboards/$(BOARD) - -#Debugging/Optimization -ifeq ($(DEBUG), 1) -CFLAGS += -g -DPENDSV_DEBUG -COPT = -O0 -else -COPT += -Os -DNDEBUG -endif - -LDFLAGS = --nostdlib -T stm32f405.ld -Map=$(@:.elf=.map) --cref -LIBS = - -# uncomment this if you want libgcc -#LIBS += $(shell $(CC) -print-libgcc-file-name) - -SRC_C = \ - main.c \ - printf.c \ - math.c \ - system_stm32f4xx.c \ - stm32fxxx_it.c \ - string0.c \ - malloc0.c \ - systick.c \ - pendsv.c \ - gccollect.c \ - lexerfatfs.c \ - import.c \ - pyexec.c \ - led.c \ - gpio.c \ - lcd.c \ - servo.c \ - flash.c \ - storage.c \ - accel.c \ - usart.c \ - usb.c \ - timer.c \ - audio.c \ - sdcard.c \ - i2c.c \ - adc.c \ - rtc.c \ - file.c \ - pin.c \ - pin_named_pins.c \ - pin_map.c \ - exti.c \ - usrsw.c \ - pybmodule.c \ -# pybwlan.c \ - -SRC_S = \ - startup_stm32f40xx.s \ - gchelper.s \ - -SRC_STMPERIPH = $(addprefix $(STMPERIPH_DIR)/,\ - stm_misc.c \ - stm32f4xx_rcc.c \ - stm32f4xx_syscfg.c \ - stm32f4xx_flash.c \ - stm32f4xx_dma.c \ - stm32f4xx_gpio.c \ - stm32f4xx_exti.c \ - stm32f4xx_tim.c \ - stm32f4xx_sdio.c \ - stm32f4xx_pwr.c \ - stm32f4xx_rtc.c \ - stm32f4xx_usart.c \ - stm32f4xx_spi.c \ - stm32f4xx_dac.c \ - stm32f4xx_rng.c \ - stm32f4xx_i2c.c \ - stm32f4xx_adc.c \ - stm324x7i_eval.c \ - stm324x7i_eval_sdio_sd.c \ - ) - -SRC_STMUSB = $(addprefix $(STMUSB_DIR)/,\ - usb_core.c \ - usb_bsp.c \ - usb_dcd.c \ - usb_dcd_int.c \ - usb_hcd.c \ - usb_hcd_int.c \ - ) -# usb_otg.c \ - -SRC_STMUSBD = $(addprefix $(STMUSBD_DIR)/,\ - usbd_core.c \ - usbd_ioreq.c \ - usbd_req.c \ - usbd_usr.c \ - usbd_desc.c \ - usbd_pyb_core.c \ - usbd_pyb_core2.c \ - usbd_cdc_vcp.c \ - usbd_msc_bot.c \ - usbd_msc_data.c \ - usbd_msc_scsi.c \ - usbd_storage_msd.c \ - ) - -SRC_STMUSBH = $(addprefix $(STMUSBH_DIR)/,\ - usbh_core.c \ - usbh_hcs.c \ - usbh_stdreq.c \ - usbh_ioreq.c \ - usbh_usr.c \ - usbh_hid_core.c \ - usbh_hid_mouse.c \ - usbh_hid_keybd.c \ - ) - -SRC_FATFS = $(addprefix $(FATFS_DIR)/,\ - ff.c \ - diskio.c \ - ccsbcs.c \ - ) - -SRC_CC3K = $(addprefix $(CC3K_DIR)/,\ - cc3000_common.c \ - evnt_handler.c \ - hci.c \ - netapp.c \ - nvmem.c \ - security.c \ - socket.c \ - wlan.c \ - ccspi.c \ - pybcc3k.c \ - ) - -OBJ = $(PY_O) $(addprefix $(BUILD)/, $(SRC_C:.c=.o) $(SRC_S:.s=.o) $(SRC_STMPERIPH:.c=.o) $(SRC_STMUSB:.c=.o)) -OBJ += $(addprefix $(BUILD)/, $(SRC_STMUSBD:.c=.o)) -#OBJ += $(addprefix $(BUILD)/, $(SRC_STMUSBH:.c=.o)) -OBJ += $(addprefix $(BUILD)/, $(SRC_FATFS:.c=.o)) -#OBJ += $(addprefix $(BUILD)/, $(SRC_CC3K:.c=.o)) -OBJ += $(BUILD)/pins_$(BOARD).o - -all: $(BUILD)/flash.dfu - -$(BUILD)/flash.dfu: $(BUILD)/flash0.bin $(BUILD)/flash1.bin - $(ECHO) "Create $@" - $(Q)$(PYTHON) $(DFU) -b 0x08000000:$(BUILD)/flash0.bin -b 0x08020000:$(BUILD)/flash1.bin $@ - -$(BUILD)/flash0.bin: $(BUILD)/flash.elf - $(Q)$(OBJCOPY) -O binary -j .isr_vector $^ $@ - -$(BUILD)/flash1.bin: $(BUILD)/flash.elf - $(Q)$(OBJCOPY) -O binary -j .text -j .data $^ $@ - -$(BUILD)/flash.elf: $(OBJ) - $(ECHO) "LINK $@" - $(Q)$(LD) $(LDFLAGS) -o $@ $(OBJ) $(LIBS) - $(Q)$(SIZE) $@ - -MAKE_PINS = boards/make-pins.py -BOARD_PINS = boards/$(BOARD)/pins.csv -AF_FILE = boards/stm32f4xx-af.csv -PREFIX_FILE = boards/stm32f4xx-prefix.c -GEN_PINS_SRC = $(BUILD)/pins_$(BOARD).c -GEN_PINS_HDR = $(BUILD)/pins.h - -# Making OBJ use an order-only depenedency on the generated pins.h file -# has the side effect of making the pins.h file before we actually compile -# any of the objects. The normal dependency generation will deal with the -# case when pins.h is modified. But when it doesn't exist, we don't know -# which source files might need it. -$(OBJ): | $(BUILD)/pins.h - -# Use a pattern rule here so that make will only call make-pins.py once to make -# both pins_$(BOARD).c and pins.h -$(BUILD)/%_$(BOARD).c $(BUILD)/%.h: boards/$(BOARD)/%.csv $(MAKE_PINS) $(AF_FILE) $(PREFIX_FILE) - $(ECHO) "Create $@" - $(Q)$(PYTHON) $(MAKE_PINS) --board $(BOARD_PINS) --af $(AF_FILE) --prefix $(PREFIX_FILE) --hdr $(GEN_PINS_HDR) > $(GEN_PINS_SRC) - -$(BUILD)/pins_$(BOARD).o: $(BUILD)/pins_$(BOARD).c - $(call compile_c) - -include ../py/mkrules.mk diff --git a/stm/accel.c b/stm/accel.c deleted file mode 100644 index 99ce9b063..000000000 --- a/stm/accel.c +++ /dev/null @@ -1,300 +0,0 @@ -#include - -#include -#include -#include - -#include "misc.h" -#include "mpconfig.h" -#include "qstr.h" -#include "systick.h" -#include "obj.h" -#include "runtime.h" -#include "accel.h" - -#define ACCEL_ADDR (0x4c) - -void accel_init(void) { - RCC->APB1ENR |= RCC_APB1ENR_I2C1EN; // enable I2C1 - - //gpio_pin_init(GPIOB, 6 /* B6 is SCL */, 2 /* AF mode */, 1 /* open drain output */, 1 /* 25 MHz */, 0 /* no pull up or pull down */); - //gpio_pin_init(GPIOB, 7 /* B7 is SDA */, 2 /* AF mode */, 1 /* open drain output */, 1 /* 25 MHz */, 0 /* no pull up or pull down */); - //gpio_pin_af(GPIOB, 6, 4 /* AF 4 for I2C1 */); - //gpio_pin_af(GPIOB, 7, 4 /* AF 4 for I2C1 */); - // XXX untested GPIO init! (was above code) - - GPIO_InitTypeDef GPIO_InitStructure; - - // PB5 is connected to AVDD; pull high to enable MMA accel device - GPIOB->BSRRH = GPIO_Pin_5; // PB5 low to start with - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(GPIOB, &GPIO_InitStructure); - - // PB6=SCL, PB7=SDA - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_25MHz; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(GPIOB, &GPIO_InitStructure); - - // alternate functions for SCL and SDA - GPIO_PinAFConfig(GPIOB, GPIO_PinSource6, GPIO_AF_I2C1); - GPIO_PinAFConfig(GPIOB, GPIO_PinSource7, GPIO_AF_I2C1); - - // get clock speeds - RCC_ClocksTypeDef rcc_clocks; - RCC_GetClocksFreq(&rcc_clocks); - - // disable the I2C peripheral before we configure it - I2C1->CR1 &= ~I2C_CR1_PE; - - // program peripheral input clock - I2C1->CR2 = 4; // no interrupts; 4 MHz (hopefully!) (could go up to 42MHz) - - // configure clock control reg - uint32_t freq = rcc_clocks.PCLK1_Frequency / (100000 << 1); // want 100kHz, this is the formula for freq - I2C1->CCR = freq; // standard mode (speed), freq calculated as above - - // configure rise time reg - I2C1->TRISE = (rcc_clocks.PCLK1_Frequency / 1000000) + 1; // formula for trise, gives maximum rise time - - // enable the I2C peripheral - I2C1->CR1 |= I2C_CR1_PE; - - // wait 20ms, then turn on AVDD, then wait 20ms again; this seems to work, but maybe can decrease delays - // doesn't work for soft reboot; 50ms doesn't work either... - sys_tick_delay_ms(20); - GPIOB->BSRRL = GPIO_Pin_5; - sys_tick_delay_ms(20); - - // set START bit in CR1 to generate a start cond! - - // init the chip via I2C commands - accel_start(ACCEL_ADDR, 1); - accel_send_byte(0); - accel_stop(); - - /* - // read and print all 11 registers - accel_start(ACCEL_ADDR, 1); - accel_send_byte(0); - accel_restart(ACCEL_ADDR, 0); - for (int i = 0; i <= 0xa; i++) { - int data; - if (i == 0xa) { - data = accel_read_nack(); - } else { - data = accel_read_ack(); - } - printf(" %02x", data); - } - printf("\n"); - */ - - // put into active mode - accel_start(ACCEL_ADDR, 1); - accel_send_byte(7); // mode - accel_send_byte(1); // active mode - accel_stop(); - - /* - // infinite loop to read values - for (;;) { - sys_tick_delay_ms(500); - - accel_start(ACCEL_ADDR, 1); - accel_send_byte(0); - accel_restart(ACCEL_ADDR, 0); - for (int i = 0; i <= 3; i++) { - int data; - if (i == 3) { - data = accel_read_nack(); - printf(" %02x\n", data); - } else { - data = accel_read_ack() & 0x3f; - if (data & 0x20) { - data |= ~0x1f; - } - printf(" % 2d", data); - } - } - } - */ -} - -static uint32_t i2c_get_sr(void) { - // must read SR1 first, then SR2, as the read can clear some flags - uint32_t sr1 = I2C1->SR1; - uint32_t sr2 = I2C1->SR2; - return (sr2 << 16) | sr1; -} - -void accel_restart(uint8_t addr, int write) { - // send start condition - I2C1->CR1 |= I2C_CR1_START; - - // wait for BUSY, MSL and SB --> Slave has acknowledged start condition - uint32_t timeout = 1000000; - while ((i2c_get_sr() & 0x00030001) != 0x00030001) { - if (--timeout == 0) { - printf("timeout in accel_restart\n"); - return; - } - } - - if (write) { - // send address and write bit - I2C1->DR = (addr << 1) | 0; - // wait for BUSY, MSL, ADDR, TXE and TRA - timeout = 1000000; - while ((i2c_get_sr() & 0x00070082) != 0x00070082) { - if (--timeout == 0) { - printf("timeout in accel_restart write\n"); - return; - } - } - } else { - // send address and read bit - I2C1->DR = (addr << 1) | 1; - // wait for BUSY, MSL and ADDR flags - timeout = 1000000; - while ((i2c_get_sr() & 0x00030002) != 0x00030002) { - if (--timeout == 0) { - printf("timeout in accel_restart read\n"); - return; - } - } - } -} - -void accel_start(uint8_t addr, int write) { - // wait until I2C is not busy - uint32_t timeout = 1000000; - while (I2C1->SR2 & I2C_SR2_BUSY) { - if (--timeout == 0) { - printf("timeout in accel_start\n"); - return; - } - } - - // do rest of start - accel_restart(addr, write); -} - -void accel_send_byte(uint8_t data) { - // send byte - I2C1->DR = data; - // wait for TRA, BUSY, MSL, TXE and BTF (byte transmitted) - uint32_t timeout = 1000000; - while ((i2c_get_sr() & 0x00070084) != 0x00070084) { - if (--timeout == 0) { - printf("timeout in accel_send_byte\n"); - return; - } - } -} - -uint8_t accel_read_ack(void) { - // enable ACK of received byte - I2C1->CR1 |= I2C_CR1_ACK; - // wait for BUSY, MSL and RXNE (byte received) - uint32_t timeout = 1000000; - while ((i2c_get_sr() & 0x00030040) != 0x00030040) { - if (--timeout == 0) { - printf("timeout in accel_read_ack\n"); - break; - } - } - // read and return data - uint8_t data = I2C1->DR; - return data; -} - -uint8_t accel_read_nack(void) { - // disable ACK of received byte (to indicate end of receiving) - I2C1->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ACK); - // last byte should apparently also generate a stop condition - I2C1->CR1 |= I2C_CR1_STOP; - // wait for BUSY, MSL and RXNE (byte received) - uint32_t timeout = 1000000; - while ((i2c_get_sr() & 0x00030040) != 0x00030040) { - if (--timeout == 0) { - printf("timeout in accel_read_nack\n"); - break; - } - } - // read and return data - uint8_t data = I2C1->DR; - return data; -} - -void accel_stop(void) { - // send stop condition - I2C1->CR1 |= I2C_CR1_STOP; -} - -/******************************************************************************/ -/* Micro Python bindings */ - -int accel_buf[12]; - -mp_obj_t pyb_accel_read(void) { - for (int i = 0; i <= 6; i += 3) { - accel_buf[0 + i] = accel_buf[0 + i + 3]; - accel_buf[1 + i] = accel_buf[1 + i + 3]; - accel_buf[2 + i] = accel_buf[2 + i + 3]; - } - - accel_start(ACCEL_ADDR, 1); - accel_send_byte(0); - accel_restart(ACCEL_ADDR, 0); - for (int i = 0; i <= 2; i++) { - int v = accel_read_ack() & 0x3f; - if (v & 0x20) { - v |= ~0x1f; - } - accel_buf[9 + i] = v; - } - int jolt_info = accel_read_nack(); - - mp_obj_t data[4]; - data[0] = mp_obj_new_int(accel_buf[0] + accel_buf[3] + accel_buf[6] + accel_buf[9]); - data[1] = mp_obj_new_int(accel_buf[1] + accel_buf[4] + accel_buf[7] + accel_buf[10]); - data[2] = mp_obj_new_int(accel_buf[2] + accel_buf[5] + accel_buf[8] + accel_buf[11]); - data[3] = mp_obj_new_int(jolt_info); - - return mp_obj_new_tuple(4, data); -} - -MP_DEFINE_CONST_FUN_OBJ_0(pyb_accel_read_obj, pyb_accel_read); - -mp_obj_t pyb_accel_read_all(void) { - mp_obj_t data[11]; - accel_start(ACCEL_ADDR, 1); - accel_send_byte(0); - accel_restart(ACCEL_ADDR, 0); - for (int i = 0; i <= 9; i++) { - data[i] = mp_obj_new_int(accel_read_ack()); - } - data[10] = mp_obj_new_int(accel_read_nack()); - - return mp_obj_new_tuple(11, data); -} - -MP_DEFINE_CONST_FUN_OBJ_0(pyb_accel_read_all_obj, pyb_accel_read_all); - -mp_obj_t pyb_accel_write_mode(mp_obj_t o_int, mp_obj_t o_mode) { - accel_start(ACCEL_ADDR, 1); - accel_send_byte(6); // start at int - accel_send_byte(mp_obj_get_int(o_int)); - accel_send_byte(mp_obj_get_int(o_mode)); - accel_stop(); - return mp_const_none; -} - -MP_DEFINE_CONST_FUN_OBJ_2(pyb_accel_write_mode_obj, pyb_accel_write_mode); diff --git a/stm/accel.h b/stm/accel.h deleted file mode 100644 index c2320f1a4..000000000 --- a/stm/accel.h +++ /dev/null @@ -1,11 +0,0 @@ -void accel_init(void); -void accel_restart(uint8_t addr, int write); -void accel_start(uint8_t addr, int write); -void accel_send_byte(uint8_t data); -uint8_t accel_read_ack(void); -uint8_t accel_read_nack(void); -void accel_stop(void); - -MP_DECLARE_CONST_FUN_OBJ(pyb_accel_read_obj); -MP_DECLARE_CONST_FUN_OBJ(pyb_accel_read_all_obj); -MP_DECLARE_CONST_FUN_OBJ(pyb_accel_write_mode_obj); diff --git a/stm/adc.c b/stm/adc.c deleted file mode 100644 index ad11f8fdd..000000000 --- a/stm/adc.c +++ /dev/null @@ -1,446 +0,0 @@ -#include -#include - -#include "mpconfig.h" -#include "misc.h" -#include "nlr.h" -#include "qstr.h" -#include "obj.h" -#include "adc.h" - -/* ADC defintions */ -#define ADCx (ADC1) -#define ADCx_CLK (RCC_APB2Periph_ADC1) -#define ADC_NUM_CHANNELS (16) - -/* Internally connected ADC channels Temp/VBAT/VREF*/ -#if defined (STM32F40XX) || defined(STM32F41XX) || defined(STM32F40_41xxx) -#define ADC_TEMP_CHANNEL (16) -#define ADC_VBAT_CHANNEL (18) -#define ADC_VREF_CHANNEL (17) -#elif defined (STM32F42XX) || defined(STM32F43XX) -#define ADC_TEMP_CHANNEL (18) -#define ADC_VBAT_CHANNEL (18) /* same channel as TEMP */ -#define ADC_VREF_CHANNEL (17) -#endif - -/* Core temperature sensor definitions */ -#define CORE_TEMP_V25 (943) /* (0.76v/3.3v)*(2^ADC resoultion) */ -#define CORE_TEMP_AVG_SLOPE (3) /* (2.5mv/3.3v)*(2^ADC resoultion) */ - -/* VBAT divider */ -#if defined (STM32F40XX) || defined(STM32F41XX) || defined(STM32F40_41xxx) -#define VBAT_DIV (2) -#elif defined (STM32F42XX) || defined(STM32F43XX) -#define VBAT_DIV (4) -#endif - -/* GPIO struct */ -typedef struct { - GPIO_TypeDef* port; - uint32_t pin; -} gpio_t; - -/* ADC GPIOs */ -static const gpio_t adc_gpio[] = { - {GPIOA, GPIO_Pin_0}, /* ADC123_IN0 */ - {GPIOA, GPIO_Pin_1}, /* ADC123_IN1 */ - {GPIOA, GPIO_Pin_2}, /* ADC123_IN2 */ - {GPIOA, GPIO_Pin_3}, /* ADC123_IN3 */ - {GPIOA, GPIO_Pin_4}, /* ADC12_IN4 */ - {GPIOA, GPIO_Pin_5}, /* ADC12_IN5 */ - {GPIOA, GPIO_Pin_6}, /* ADC12_IN6 */ - {GPIOA, GPIO_Pin_7}, /* ADC12_IN7 */ - {GPIOB, GPIO_Pin_0}, /* ADC12_IN8 */ - {GPIOB, GPIO_Pin_1}, /* ADC12_IN9 */ - {GPIOC, GPIO_Pin_0}, /* ADC123_IN10 */ - {GPIOC, GPIO_Pin_1}, /* ADC123_IN11 */ - {GPIOC, GPIO_Pin_2}, /* ADC123_IN12 */ - {GPIOC, GPIO_Pin_3}, /* ADC123_IN13 */ - {GPIOC, GPIO_Pin_4}, /* ADC12_IN14 */ - {GPIOC, GPIO_Pin_5}, /* ADC12_IN15 */ - -}; - -void adc_init_all(uint32_t resolution) { - ADC_InitTypeDef ADC_InitStructure; - GPIO_InitTypeDef GPIO_InitStructure; - ADC_CommonInitTypeDef ADC_CommonInitStructure; - - /* Enable ADCx, DMA and GPIO clocks */ -#if 0 - /* GPIO clocks enabled in main */ - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | - RCC_AHB1Periph_GPIOB | - RCC_AHB1Periph_GPIOC, ENABLE); -#endif - RCC_APB2PeriphClockCmd(ADCx_CLK, ENABLE); - - /* ADC Common Init */ - ADC_CommonInitStructure.ADC_Mode = ADC_Mode_Independent; - ADC_CommonInitStructure.ADC_Prescaler = ADC_Prescaler_Div2; - ADC_CommonInitStructure.ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled; - ADC_CommonInitStructure.ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles; - ADC_CommonInit(&ADC_CommonInitStructure); - - /* Configure ADC GPIOs */ - for (int i=0; i (ADC_NUM_CHANNELS-1)) { - return 0; - } - - /* ADC regular channel config ADC/Channel/SEQ Rank/Sample time */ - ADC_RegularChannelConfig(ADCx, channel, 1, ADC_SampleTime_15Cycles); - - /* Start ADC single conversion */ - ADC_SoftwareStartConv(ADCx); - - /* Wait for conversion to be complete*/ - while(!ADC_GetFlagStatus(ADCx, ADC_FLAG_EOC) && --timeout >0) { - } - - /* ADC conversion timed out */ - if (timeout == 0) { - return 0; - } - - /* Return converted data */ - return ADC_GetConversionValue(ADCx); -} - -int adc_read_core_temp() -{ - int timeout = 10000; - - /* ADC temperature sensor channel config ADC/Channel/SEQ Rank/Sample time */ - /* Note: sample time must be higher than minimum sample time */ - ADC_RegularChannelConfig(ADCx, ADC_TEMP_CHANNEL, 1, ADC_SampleTime_480Cycles); - - /* Start ADC single conversion */ - ADC_SoftwareStartConv(ADCx); - - /* Wait for conversion to be complete*/ - while(!ADC_GetFlagStatus(ADCx, ADC_FLAG_EOC) && --timeout >0) { - } - - /* ADC conversion timed out */ - if (timeout == 0) { - return 0; - } - - /* Convert ADC reading to temperature */ - /* Temperature formula from datasheet P.411 */ - return ((ADC_GetConversionValue(ADCx) - CORE_TEMP_V25) / CORE_TEMP_AVG_SLOPE) + 25; -} - -float adc_read_core_vbat() -{ - int timeout = 10000; - - /* ADC VBAT channel config ADC/Channel/SEQ Rank/Sample time */ - /* Note: sample time must be higher than minimum sample time */ - ADC_RegularChannelConfig(ADCx, ADC_VBAT_CHANNEL, 1, ADC_SampleTime_144Cycles); - - /* Start ADC single conversion */ - ADC_SoftwareStartConv(ADCx); - - /* Wait for conversion to be complete */ - while(!ADC_GetFlagStatus(ADCx, ADC_FLAG_EOC) && --timeout >0) { - } - - /* ADC conversion timed out */ - if (timeout == 0) { - return 0; - } - - /* Convert ADC reading to voltage, VBAT pin is - internally connected to a bridge divider by VBAT_DIV */ - return ADC_GetConversionValue(ADCx)*VBAT_DIV/4096.0f*3.3f; -} - -float adc_read_core_vref() -{ - int timeout = 10000; - - /* ADC VBAT channel config ADC/Channel/SEQ Rank/Sample time */ - /* Note: sample time must be higher than minimum sample time */ - ADC_RegularChannelConfig(ADCx, ADC_VREF_CHANNEL, 1, ADC_SampleTime_112Cycles); - - /* Start ADC single conversion */ - ADC_SoftwareStartConv(ADCx); - - /* Wait for conversion to be complete*/ - while(!ADC_GetFlagStatus(ADCx, ADC_FLAG_EOC) && --timeout >0) { - } - - /* ADC conversion timed out */ - if (timeout == 0) { - return 0; - } - - /* Convert ADC reading to voltage */ - return ADC_GetConversionValue(ADCx)/4096.0f*3.3f; -} - -/******************************************************************************/ -/* Micro Python bindings : adc_all object */ - -typedef struct _pyb_obj_adc_all_t { - mp_obj_base_t base; - bool is_enabled; -} pyb_obj_adc_all_t; - -static void adc_all_print(void (*print)(void *env, const char *fmt, ...), void *env, mp_obj_t self_in, mp_print_kind_t kind) { - print(env, ""); -} - -static mp_obj_t adc_all_read_channel(mp_obj_t self_in, mp_obj_t channel) { - pyb_obj_adc_all_t *self = self_in; - - if (self->is_enabled) { - uint32_t chan = mp_obj_get_int(channel); - uint32_t data = adc_read_channel(chan); - return mp_obj_new_int(data); - } else { - return mp_const_none; - } -} - -static mp_obj_t adc_all_read_core_temp(mp_obj_t self_in) { - pyb_obj_adc_all_t *self = self_in; - - if (self->is_enabled) { - int data = adc_read_core_temp(); - return mp_obj_new_int(data); - } else { - return mp_const_none; - } -} - -static mp_obj_t adc_all_read_core_vbat(mp_obj_t self_in) { - pyb_obj_adc_all_t *self = self_in; - - if (self->is_enabled) { - float data = adc_read_core_vbat(); - return mp_obj_new_float(data); - } else { - return mp_const_none; - } -} - -static mp_obj_t adc_all_read_core_vref(mp_obj_t self_in) { - pyb_obj_adc_all_t *self = self_in; - - if (self->is_enabled) { - float data = adc_read_core_vref(); - return mp_obj_new_float(data); - } else { - return mp_const_none; - } -} - -static MP_DEFINE_CONST_FUN_OBJ_2(adc_all_read_channel_obj, adc_all_read_channel); -static MP_DEFINE_CONST_FUN_OBJ_1(adc_all_read_core_temp_obj, adc_all_read_core_temp); -static MP_DEFINE_CONST_FUN_OBJ_1(adc_all_read_core_vbat_obj, adc_all_read_core_vbat); -static MP_DEFINE_CONST_FUN_OBJ_1(adc_all_read_core_vref_obj, adc_all_read_core_vref); - -STATIC const mp_map_elem_t adc_all_locals_dict_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR_read_channel), (mp_obj_t) &adc_all_read_channel_obj}, - { MP_OBJ_NEW_QSTR(MP_QSTR_read_core_temp), (mp_obj_t)&adc_all_read_core_temp_obj}, - { MP_OBJ_NEW_QSTR(MP_QSTR_read_core_vbat), (mp_obj_t)&adc_all_read_core_vbat_obj}, - { MP_OBJ_NEW_QSTR(MP_QSTR_read_core_vref), (mp_obj_t)&adc_all_read_core_vref_obj}, -}; - -STATIC MP_DEFINE_CONST_DICT(adc_all_locals_dict, adc_all_locals_dict_table); - -static const mp_obj_type_t adc_all_type = { - { &mp_type_type }, - .name = MP_QSTR_ADC, - .print = adc_all_print, - .locals_dict = (mp_obj_t)&adc_all_locals_dict, -}; - -mp_obj_t pyb_ADC_all(mp_obj_t resolution) { - /* init ADC */ - adc_init_all(mp_obj_get_int(resolution)); - - pyb_obj_adc_all_t *o = m_new_obj(pyb_obj_adc_all_t); - o->base.type = &adc_all_type; - o->is_enabled = true; - return o; -} - -MP_DEFINE_CONST_FUN_OBJ_1(pyb_ADC_all_obj, pyb_ADC_all); - -/******************************************************************************/ -/* Micro Python bindings : adc object (single channel) */ - -typedef struct _pyb_obj_adc_t { - mp_obj_base_t base; - mp_obj_t pin_name; - int channel; - bool is_enabled; -} pyb_obj_adc_t; - -static void adc_print(void (*print)(void *env, const char *fmt, ...), void *env, mp_obj_t self_in, mp_print_kind_t kind) { - pyb_obj_adc_t *self = self_in; - print(env, "pin_name, PRINT_STR); - print(env, " channel=%lu>", self->channel); -} - -static mp_obj_t adc_read(mp_obj_t self_in) { - pyb_obj_adc_t *self = self_in; - - if (self->is_enabled) { - uint32_t data = adc_read_channel(self->channel); - return mp_obj_new_int(data); - } else { - return mp_const_none; - } -} - -static MP_DEFINE_CONST_FUN_OBJ_1(adc_read_obj, adc_read); - -STATIC const mp_map_elem_t adc_locals_dict_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR_read), (mp_obj_t)&adc_read_obj}, -}; - -STATIC MP_DEFINE_CONST_DICT(adc_locals_dict, adc_locals_dict_table); - -static const mp_obj_type_t adc_type = { - { &mp_type_type }, - .name = MP_QSTR_ADC, - .print = adc_print, - .locals_dict = (mp_obj_t)&adc_locals_dict, -}; - -mp_obj_t pyb_ADC(mp_obj_t pin_name_obj) { - - pyb_obj_adc_t *o = m_new_obj(pyb_obj_adc_t); - o->base.type = &adc_type; - o->pin_name = pin_name_obj; - - // work out the channel from the pin name - const char *pin_name = mp_obj_str_get_str(pin_name_obj); - GPIO_TypeDef *port; - switch (pin_name[0]) { - case 'A': case 'a': port = GPIOA; break; - case 'B': case 'b': port = GPIOB; break; - case 'C': case 'c': port = GPIOC; break; - default: goto pin_error; - } - uint pin_num = 0; - for (const char *s = pin_name + 1; *s; s++) { - if (!('0' <= *s && *s <= '9')) { - goto pin_error; - } - pin_num = 10 * pin_num + *s - '0'; - } - if (!(0 <= pin_num && pin_num <= 15)) { - goto pin_error; - } - - int i; - for (i = 0; i < ADC_NUM_CHANNELS; i++) { - if (adc_gpio[i].port == port && adc_gpio[i].pin == (1 << pin_num)) { - o->channel = i; - break; - } - } - - if (i == ADC_NUM_CHANNELS) { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "pin %s does not have ADC capabilities", pin_name)); - } - - // init ADC just for this channel - adc_init_single(o->channel); - - o->is_enabled = true; - - return o; - -pin_error: - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "pin %s does not exist", pin_name)); -} - -MP_DEFINE_CONST_FUN_OBJ_1(pyb_ADC_obj, pyb_ADC); diff --git a/stm/adc.h b/stm/adc.h deleted file mode 100644 index 502da20dd..000000000 --- a/stm/adc.h +++ /dev/null @@ -1,2 +0,0 @@ -MP_DECLARE_CONST_FUN_OBJ(pyb_ADC_all_obj); -MP_DECLARE_CONST_FUN_OBJ(pyb_ADC_obj); diff --git a/stm/audio.c b/stm/audio.c deleted file mode 100644 index 9fa993800..000000000 --- a/stm/audio.c +++ /dev/null @@ -1,256 +0,0 @@ -#include -#include - -#include "stm32f4xx_dac.h" - -#include "mpconfig.h" -#include "nlr.h" -#include "misc.h" -#include "qstr.h" -#include "parse.h" -#include "obj.h" -#include "runtime.h" - -#include "audio.h" - -STATIC void TIM7_Config(uint freq) { - // TIM7 clock enable - RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM7, ENABLE); - - // reset TIM7 - TIM_DeInit(TIM7); - - // Compute the prescaler value so TIM7 triggers at freq-Hz - uint16_t period = (uint16_t) ((SystemCoreClock / 2) / freq) - 1; - - // Time base configuration - TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; - TIM_TimeBaseStructure.TIM_Period = period; // timer triggers with this period - TIM_TimeBaseStructure.TIM_Prescaler = 0; // timer runs at SystemCoreClock / 2 - TIM_TimeBaseStructure.TIM_ClockDivision = 0; // unused for TIM7 - TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; // unused for TIM7 - TIM_TimeBaseInit(TIM7, &TIM_TimeBaseStructure); - - // TIM7 TRGO selection - TIM_SelectOutputTrigger(TIM7, TIM_TRGOSource_Update); - - // TIM7 enable counter - TIM_Cmd(TIM7, ENABLE); -} - -/******************************************************************************/ -// Micro Python bindings - -typedef struct _pyb_audio_t { - mp_obj_base_t base; - uint dac_channel; // DAC_Channel_1 or DAC_Channel_2 - DMA_Stream_TypeDef *dma_stream; // DMA1_Stream6 or DMA1_Stream7 -} pyb_audio_t; - -mp_obj_t pyb_audio_noise(mp_obj_t self_in, mp_obj_t freq) { - pyb_audio_t *self = self_in; - - // set TIM7 to trigger the DAC at the given frequency - TIM7_Config(mp_obj_get_int(freq)); - - DAC_Cmd(self->dac_channel, DISABLE); - - DAC_InitTypeDef DAC_InitStructure; - DAC_InitStructure.DAC_Trigger = DAC_Trigger_T7_TRGO; - DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_Noise; - DAC_InitStructure.DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bits10_0; - DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable; - DAC_Init(self->dac_channel, &DAC_InitStructure); - - DAC_Cmd(self->dac_channel, ENABLE); - - if (self->dac_channel == DAC_Channel_1) { - DAC_SetChannel1Data(DAC_Align_12b_L, 0x7ff0); - } else { - DAC_SetChannel2Data(DAC_Align_12b_L, 0x7ff0); - } - - return mp_const_none; -} - -mp_obj_t pyb_audio_triangle(mp_obj_t self_in, mp_obj_t freq) { - pyb_audio_t *self = self_in; - - // set TIM7 to trigger the DAC at the given frequency - TIM7_Config(mp_obj_get_int(freq)); - - DAC_Cmd(self->dac_channel, DISABLE); - - DAC_InitTypeDef DAC_InitStructure; - DAC_InitStructure.DAC_Trigger = DAC_Trigger_T7_TRGO; - DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_Triangle; - DAC_InitStructure.DAC_LFSRUnmask_TriangleAmplitude = DAC_TriangleAmplitude_1023; - DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable; - DAC_Init(self->dac_channel, &DAC_InitStructure); - - DAC_Cmd(self->dac_channel, ENABLE); - - // set base value of triangle wave - if (self->dac_channel == DAC_Channel_1) { - DAC_SetChannel1Data(DAC_Align_12b_R, 0x100); - } else { - DAC_SetChannel2Data(DAC_Align_12b_R, 0x100); - } - - return mp_const_none; -} - -// direct access to DAC -mp_obj_t pyb_audio_dac(mp_obj_t self_in, mp_obj_t val) { - pyb_audio_t *self = self_in; - if (self->dac_channel == DAC_Channel_1) { - DAC_SetChannel1Data(DAC_Align_8b_R, mp_obj_get_int(val)); - } else { - DAC_SetChannel2Data(DAC_Align_8b_R, mp_obj_get_int(val)); - } - return mp_const_none; -} - -#define DAC_DHR8R1_ADDRESS (DAC_BASE + 0x10) -#define DAC_DHR8R2_ADDRESS (DAC_BASE + 0x1c) - -// initiates a burst of RAM->DAC using DMA -// input data is treated as an array of bytes (8 bit data) -// TIM7 is used to set the frequency of the transfer -mp_obj_t pyb_audio_dma(uint n_args, const mp_obj_t *args, mp_map_t *kw_args) { - pyb_audio_t *self = args[0]; - - // set TIM7 to trigger the DAC at the given frequency - TIM7_Config(mp_obj_get_int(args[2])); - - mp_obj_type_t *type = mp_obj_get_type(args[1]); - if (type->buffer_p.get_buffer == NULL) { - nlr_raise(mp_obj_new_exception_msg(&mp_type_TypeError, "buffer argument must support buffer protocol")); - } - mp_buffer_info_t bufinfo; - type->buffer_p.get_buffer(args[1], &bufinfo, MP_BUFFER_READ); - - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE); - - DMA_Cmd(self->dma_stream, DISABLE); - while (DMA_GetCmdStatus(self->dma_stream) != DISABLE) { - } - - DAC_Cmd(self->dac_channel, DISABLE); - - // DAC channel configuration - DAC_InitTypeDef DAC_InitStructure; - DAC_InitStructure.DAC_Trigger = DAC_Trigger_T7_TRGO; - DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_None; - DAC_InitStructure.DAC_LFSRUnmask_TriangleAmplitude = DAC_TriangleAmplitude_1; // unused, but need to set it to a valid value - DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable; - DAC_Init(self->dac_channel, &DAC_InitStructure); - - // DMA1_Stream[67] channel7 configuration - DMA_DeInit(self->dma_stream); - DMA_InitTypeDef DMA_InitStructure; - DMA_InitStructure.DMA_Channel = DMA_Channel_7; - if (self->dac_channel == DAC_Channel_1) { - DMA_InitStructure.DMA_PeripheralBaseAddr = DAC_DHR8R1_ADDRESS; - } else { - DMA_InitStructure.DMA_PeripheralBaseAddr = DAC_DHR8R2_ADDRESS; - } - DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)bufinfo.buf; - DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; - DMA_InitStructure.DMA_BufferSize = bufinfo.len; - DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; - DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; - DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - mp_map_elem_t *kw_mode = mp_map_lookup(kw_args, MP_OBJ_NEW_QSTR(qstr_from_str("mode")), MP_MAP_LOOKUP); - DMA_InitStructure.DMA_Mode = kw_mode == NULL ? DMA_Mode_Normal : mp_obj_get_int(kw_mode->value); // normal = 0, circular = 0x100 - DMA_InitStructure.DMA_Priority = DMA_Priority_High; - DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; - DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull; - DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; - DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; - DMA_Init(self->dma_stream, &DMA_InitStructure); - - // enable DMA stream - DMA_Cmd(self->dma_stream, ENABLE); - while (DMA_GetCmdStatus(self->dma_stream) == DISABLE) { - } - - // enable DAC channel - DAC_Cmd(self->dac_channel, ENABLE); - - // enable DMA for DAC channel - DAC_DMACmd(self->dac_channel, ENABLE); - - //printf("DMA: %p %lu\n", bufinfo.buf, bufinfo.len); - - return mp_const_none; -} - -STATIC MP_DEFINE_CONST_FUN_OBJ_2(pyb_audio_noise_obj, pyb_audio_noise); -STATIC MP_DEFINE_CONST_FUN_OBJ_2(pyb_audio_triangle_obj, pyb_audio_triangle); -STATIC MP_DEFINE_CONST_FUN_OBJ_2(pyb_audio_dac_obj, pyb_audio_dac); -STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pyb_audio_dma_obj, 3, pyb_audio_dma); - -STATIC const mp_map_elem_t pyb_audio_locals_dict_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR_noise), (mp_obj_t)&pyb_audio_noise_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_triangle), (mp_obj_t)&pyb_audio_triangle_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_dac), (mp_obj_t)&pyb_audio_dac_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_dma), (mp_obj_t)&pyb_audio_dma_obj }, -}; - -STATIC MP_DEFINE_CONST_DICT(pyb_audio_locals_dict, pyb_audio_locals_dict_table); - -STATIC const mp_obj_type_t pyb_audio_type = { - { &mp_type_type }, - .name = MP_QSTR_, - .locals_dict = (mp_obj_t)&pyb_audio_locals_dict, -}; - -STATIC const pyb_audio_t pyb_audio_channel_1 = {{&pyb_audio_type}, DAC_Channel_1, DMA1_Stream5}; -STATIC const pyb_audio_t pyb_audio_channel_2 = {{&pyb_audio_type}, DAC_Channel_2, DMA1_Stream6}; - -// create the audio object -// currently support either DAC1 on X5 (id = 1) or DAC2 on X6 (id = 2) - -STATIC mp_obj_t pyb_Audio(mp_obj_t id) { - // DAC peripheral clock - RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE); - - int dac_id = mp_obj_get_int(id); - uint pin; - const pyb_audio_t *dac_obj; - - if (dac_id == 1) { - pin = GPIO_Pin_4; - dac_obj = &pyb_audio_channel_1; - } else { - pin = GPIO_Pin_5; - dac_obj = &pyb_audio_channel_2; - } - - // DAC channel configuration - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = pin; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(GPIOA, &GPIO_InitStructure); - - // DAC channel Configuration - DAC_InitTypeDef DAC_InitStructure; - DAC_InitStructure.DAC_Trigger = DAC_Trigger_None; - DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_None; - DAC_InitStructure.DAC_LFSRUnmask_TriangleAmplitude = DAC_TriangleAmplitude_1023; - DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable; - DAC_Init(dac_obj->dac_channel, &DAC_InitStructure); - - // Enable DAC Channel - DAC_Cmd(dac_obj->dac_channel, ENABLE); - - // from now on use DAC_SetChannel[12]Data to trigger a conversion - - // return static object - return (mp_obj_t)dac_obj; -} - -MP_DEFINE_CONST_FUN_OBJ_1(pyb_Audio_obj, pyb_Audio); diff --git a/stm/audio.h b/stm/audio.h deleted file mode 100644 index 9b1f124a3..000000000 --- a/stm/audio.h +++ /dev/null @@ -1 +0,0 @@ -MP_DECLARE_CONST_FUN_OBJ(pyb_Audio_obj); diff --git a/stm/boards/NETDUINO_PLUS_2/mpconfigboard.h b/stm/boards/NETDUINO_PLUS_2/mpconfigboard.h deleted file mode 100644 index 9bc5149ec..000000000 --- a/stm/boards/NETDUINO_PLUS_2/mpconfigboard.h +++ /dev/null @@ -1,38 +0,0 @@ -#define NETDUINO_PLUS_2 - -#define MICROPY_HW_BOARD_NAME "NetduinoPlus2" - -#define MICROPY_HW_HAS_SWITCH (1) - -// On the netuino, the sdcard appears to be wired up as a 1-bit -// SPI, so the driver needs to be converted to support that before -// we can turn this on. -#define MICROPY_HW_HAS_SDCARD (0) -#define MICROPY_HW_HAS_MMA7660 (0) -#define MICROPY_HW_HAS_LIS3DSH (0) -#define MICROPY_HW_HAS_LCD (0) -#define MICROPY_HW_HAS_WLAN (0) -#define MICROPY_HW_ENABLE_RNG (1) -#define MICROPY_HW_ENABLE_RTC (0) -#define MICROPY_HW_ENABLE_TIMER (1) -#define MICROPY_HW_ENABLE_SERVO (1) -#define MICROPY_HW_ENABLE_AUDIO (0) - -// USRSW is pulled low. Pressing the button makes the input go high. -#define USRSW_PIN (pin_B11) -#define USRSW_PUPD (GPIO_PuPd_NOPULL) -#define USRSW_EXTI_EDGE (EXTI_Trigger_Rising) -#define USRSW_PRESSED (1) - -/* LED */ -#define PYB_LED1 (pin_A10) // Blue LED -#define PYB_LED2 (pin_C13) // White LED (aka Power) -#define PYB_LED3 (pin_A10) // Same as Led(1) -#define PYB_LED4 (pin_C13) // Same as Led(2) - -#define PYB_OTYPE (GPIO_OType_PP) - -#define PYB_LED_ON(pin) (pin->gpio->BSRRL = pin->pin_mask) -#define PYB_LED_OFF(pin) (pin->gpio->BSRRH = pin->pin_mask) - -#define HSE_VALUE (25000000) diff --git a/stm/boards/NETDUINO_PLUS_2/pins.csv b/stm/boards/NETDUINO_PLUS_2/pins.csv deleted file mode 100644 index f9b94a6c8..000000000 --- a/stm/boards/NETDUINO_PLUS_2/pins.csv +++ /dev/null @@ -1,28 +0,0 @@ -D0,PC7 -D1,PC6 -D2,PA3 -D3,PA2 -D4,PB12 -D5,PB8 -D6,PB9 -D7,PA1 -D8,PA0 -D9,PA6 -D10,PB10 -D11,PB15 -D12,PB14 -D13,PB13 -A0,PC0 -A1,PC1 -A2,PC2 -A3,PC3 -A4,PC4 -A5,PC5 -LED,PA10 -SW,PB11 -PWR_LED,PC13 -PWR_SD,PB1 -PWR_HDR,PB2 -PWR_ETH,PC15 -RST_ETH,PD2 - diff --git a/stm/boards/PYBOARD3/mpconfigboard.h b/stm/boards/PYBOARD3/mpconfigboard.h deleted file mode 100644 index 29e23eaab..000000000 --- a/stm/boards/PYBOARD3/mpconfigboard.h +++ /dev/null @@ -1,32 +0,0 @@ -#define PYBOARD3 - -#define MICROPY_HW_BOARD_NAME "PYBv3" - -#define MICROPY_HW_HAS_SWITCH (1) -#define MICROPY_HW_HAS_SDCARD (1) -#define MICROPY_HW_HAS_MMA7660 (1) -#define MICROPY_HW_HAS_LIS3DSH (0) -#define MICROPY_HW_HAS_LCD (0) -#define MICROPY_HW_HAS_WLAN (0) -#define MICROPY_HW_ENABLE_RNG (1) -#define MICROPY_HW_ENABLE_RTC (1) -#define MICROPY_HW_ENABLE_TIMER (1) -#define MICROPY_HW_ENABLE_SERVO (1) -#define MICROPY_HW_ENABLE_AUDIO (0) - -// USRSW has no pullup or pulldown, and pressing the switch makes the input go low -#define USRSW_PIN (pin_A13) -#define USRSW_PUPD (GPIO_PuPd_UP) -#define USRSW_EXTI_EDGE (EXTI_Trigger_Falling) -#define USRSW_PRESSED (0) - -/* LED */ -#define PYB_LED1 (pin_A8) // R1 - red -#define PYB_LED2 (pin_A10) // R2 - red -#define PYB_LED3 (pin_C4) // G1 - green -#define PYB_LED4 (pin_C5) // G2 - green - -#define PYB_OTYPE (GPIO_OType_PP) - -#define PYB_LED_ON(pin) (pin->gpio->BSRRH = pin->pin_mask) -#define PYB_LED_OFF(pin) (pin->gpio->BSRRL = pin->pin_mask) diff --git a/stm/boards/PYBOARD3/pins.csv b/stm/boards/PYBOARD3/pins.csv deleted file mode 100644 index cc07b1544..000000000 --- a/stm/boards/PYBOARD3/pins.csv +++ /dev/null @@ -1,37 +0,0 @@ -B13,PB13 -B14,PB14 -B15,PB15 -C6,PC6 -C7,PC7 -A13,PA13 -A14,PA14 -A15,PA15 -B3,PB3 -B4,PB4 -B6,PB6 -B7,PB7 -B8,PB8 -B9,PB9 -C0,PC0 -C1,PC1 -C2,PC2 -C3,PC3 -A0,PA0 -A1,PA1 -A2,PA2 -A3,PA3 -A4,PA4 -A5,PA5 -A6,PA6 -A7,PA7 -B0,PB0 -B1,PB1 -B10,PB10 -B11,PB11 -B12,PB12 -LED_R1,PA8 -LED_R2,PA10 -LED_G1,PC4 -LED_G2,PC5 -SW,PA13 - diff --git a/stm/boards/PYBOARD4/mpconfigboard.h b/stm/boards/PYBOARD4/mpconfigboard.h deleted file mode 100644 index 155901da1..000000000 --- a/stm/boards/PYBOARD4/mpconfigboard.h +++ /dev/null @@ -1,33 +0,0 @@ -#define PYBOARD4 - -#define MICROPY_HW_BOARD_NAME "PYBv4" - -#define MICROPY_HW_HAS_SWITCH (1) -#define MICROPY_HW_HAS_SDCARD (1) -#define MICROPY_HW_HAS_MMA7660 (1) -#define MICROPY_HW_HAS_LIS3DSH (0) -#define MICROPY_HW_HAS_LCD (1) -#define MICROPY_HW_HAS_WLAN (0) -#define MICROPY_HW_ENABLE_RNG (1) -#define MICROPY_HW_ENABLE_RTC (1) -#define MICROPY_HW_ENABLE_TIMER (1) -#define MICROPY_HW_ENABLE_SERVO (1) -#define MICROPY_HW_ENABLE_AUDIO (1) - -// USRSW has no pullup or pulldown, and pressing the switch makes the input go low -#define USRSW_PIN (pin_B3) -#define USRSW_PUPD (GPIO_PuPd_UP) -#define USRSW_EXTI_EDGE (EXTI_Trigger_Falling) -#define USRSW_PRESSED (0) - -/* LED */ -#define PYB_LED1 (pin_A13) // red -#define PYB_LED2 (pin_A14) // green -#define PYB_LED3 (pin_A15) // yellow -#define PYB_LED4 (pin_B4) // blue - -#define PYB_OTYPE (GPIO_OType_PP) - -#define PYB_LED_ON(pin) (pin->gpio->BSRRL = pin->pin_mask) -#define PYB_LED_OFF(pin) (pin->gpio->BSRRH = pin->pin_mask) - diff --git a/stm/boards/PYBOARD4/pins.csv b/stm/boards/PYBOARD4/pins.csv deleted file mode 100644 index 2ca7fef18..000000000 --- a/stm/boards/PYBOARD4/pins.csv +++ /dev/null @@ -1,45 +0,0 @@ -X1,PA0 -X2,PA1 -X3,PA2 -X4,PA3 -X5,PA4 -X6,PA5 -X7,PA6 -X8,PA7 -X9,PB6 -X10,PB7 -X11,PC4 -X12,PC5 -X13,Reset -X14,GND -X15,3.3V -X16,VIN -X17,PB3 -X18,PC13 -X19,PC0 -X20,PC1 -X21,PC2 -X22,PC3 -X23,A3.3V -X24,AGND -Y1,PC6 -Y2,PC7 -Y3,PB8 -Y4,PB9 -Y5,PB12 -Y6,PB13 -Y7,PB14 -Y8,PB15 -Y9,PB10 -Y10,PB11 -Y11,PB0 -Y12,PB1 -Y13,Reset -Y14,GND -Y15,3.3V -Y16,VIN -LED_BLUE,PB4 -LED_RED,PA13 -LED_GREEN,PA14 -LED_YELLOW,PA15 -SW,PB3 diff --git a/stm/boards/STM32F4DISC/mpconfigboard.h b/stm/boards/STM32F4DISC/mpconfigboard.h deleted file mode 100644 index b463c90ad..000000000 --- a/stm/boards/STM32F4DISC/mpconfigboard.h +++ /dev/null @@ -1,33 +0,0 @@ -#define STM32F4DISC - -#define MICROPY_HW_BOARD_NAME "F4DISC" - -#define MICROPY_HW_HAS_SWITCH (1) -#define MICROPY_HW_HAS_SDCARD (0) -#define MICROPY_HW_HAS_MMA7660 (0) -#define MICROPY_HW_HAS_LIS3DSH (1) -#define MICROPY_HW_HAS_LCD (0) -#define MICROPY_HW_HAS_WLAN (0) -#define MICROPY_HW_ENABLE_RNG (1) -#define MICROPY_HW_ENABLE_RTC (1) -#define MICROPY_HW_ENABLE_TIMER (1) -#define MICROPY_HW_ENABLE_SERVO (0) -#define MICROPY_HW_ENABLE_AUDIO (0) - -// USRSW is pulled low. Pressing the button makes the input go high. -#define USRSW_PIN (pin_A0) -#define USRSW_PUPD (GPIO_PuPd_NOPULL) -#define USRSW_EXTI_EDGE (EXTI_Trigger_Rising) -#define USRSW_PRESSED (1) - -/* LED */ -#define PYB_LED1 (pin_D14) // red -#define PYB_LED2 (pin_D12) // green -#define PYB_LED3 (pin_D13) // orange -#define PYB_LED4 (pin_D15) // blue - -#define PYB_OTYPE (GPIO_OType_PP) - -#define PYB_LED_ON(pin) (pin->gpio->BSRRL = pin->pin_mask) -#define PYB_LED_OFF(pin) (pin->gpio->BSRRH = pin->pin_mask) - diff --git a/stm/boards/STM32F4DISC/pins.csv b/stm/boards/STM32F4DISC/pins.csv deleted file mode 100644 index 4049fef7d..000000000 --- a/stm/boards/STM32F4DISC/pins.csv +++ /dev/null @@ -1,85 +0,0 @@ -PC0,PC0 -PC1,PC1 -PC2,PC2 -PC3,PC3 -PA0,PA0 -PA1,PA1 -PA2,PA2 -PA3,PA3 -PA4,PA4 -PA5,PA5 -PA6,PA6 -PA7,PA7 -PC4,PC4 -PC5,PC5 -PB0,PB0 -PB1,PB1 -PB2,PB2 -PE7,PE7 -PE8,PE8 -PE9,PE9 -PE10,PE10 -PE11,PE11 -PE12,PE12 -PE13,PE13 -PE14,PE14 -PE15,PE15 -PB10,PB10 -PB11,PB11 -PB12,PB12 -PB13,PB13 -PB14,PB14 -PB15,PB15 -PD8,PD8 -PD9,PD9 -PD10,PD10 -PD11,PD11 -PD12,PD12 -PD13,PD13 -PD14,PD14 -PD15,PD15 -PC6,PC6 -PC7,PC7 -PC8,PC8 -PC9,PC9 -PA8,PA8 -PA9,PA9 -PA10,PA10 -PA13,PA13 -PA14,PA14 -PA15,PA15 -PC10,PC10 -PC11,PC11 -PC12,PC12 -PD0,PD0 -PD1,PD1 -PD2,PD2 -PD3,PD3 -PD4,PD4 -PD5,PD5 -PD6,PD6 -PD7,PD7 -PB4,PB4 -PB5,PB5 -PB6,PB6 -PB7,PB7 -PB8,PB8 -PB9,PB9 -PE0,PE0 -PE1,PE1 -PE2,PE2 -PE3,PE3 -PE4,PE4 -PE5,PE5 -PE6,PE6 -PC13,PC13 -PC14,PC14 -PC15,PC15 -PH0,PH0 -PH1,PH1 -LED_GREEN,PD12 -LED_ORANGE,PD13 -LED_RED,PD14 -LED_BLUE,PD15 -SW,PA0 - diff --git a/stm/boards/make-pins.py b/stm/boards/make-pins.py deleted file mode 100755 index 8c1bedbf0..000000000 --- a/stm/boards/make-pins.py +++ /dev/null @@ -1,261 +0,0 @@ -#!/usr/bin/env python -"""Creates the pin file for the STM32F4xx.""" - -from __future__ import print_function - -import argparse -import sys -import csv - -SUPPORTED_FN = { - 'TIM' : ['CH1', 'CH2', 'CH3', 'CH4', - 'CH1N', 'CH2N', 'CH3N', 'CH1_ETR', 'ETR', 'BKIN'], - 'I2C' : ['SDA', 'SCL'], - 'USART' : ['RX', 'TX', 'CTS', 'RTS', 'CK'], - 'UART' : ['RX', 'TX', 'CTS', 'RTS'], - 'SPI' : ['NSS', 'SCK', 'MISO', 'MOSI'] -} - -def parse_port_pin(name_str): - """Parses a string and returns a (port-num, pin-num) tuple.""" - if len(name_str) < 3: - raise ValueError("Expecting pin name to be at least 3 charcters.") - if name_str[0] != 'P': - raise ValueError("Expecting pin name to start with P") - if name_str[1] < 'A' or name_str[1] > 'J': - raise ValueError("Expecting pin port to be between A and J") - port = ord(name_str[1]) - ord('A') - pin_str = name_str[2:] - if not pin_str.isdigit(): - raise ValueError("Expecting numeric pin number.") - return (port, int(pin_str)) - -def split_name_num(name_num): - num = None - for num_idx in range(len(name_num) - 1, -1, -1): - if not name_num[num_idx].isdigit(): - name = name_num[0:num_idx + 1] - num_str = name_num[num_idx + 1:] - if len(num_str) > 0: - num = int(num_str) - break - return name, num - - -class AlternateFunction(object): - """Holds the information associated with a pins alternate function.""" - - def __init__(self, idx, af_str): - self.idx = idx - self.af_str = af_str - - self.func = '' - self.fn_num = None - self.pin_type = '' - self.supported = False - - af_words = af_str.split('_', 1) - self.func, self.fn_num = split_name_num(af_words[0]) - if len(af_words) > 1: - self.pin_type = af_words[1] - if self.func in SUPPORTED_FN: - pin_types = SUPPORTED_FN[self.func] - if self.pin_type in pin_types: - self.supported = True - - def is_supported(self): - return self.supported - - def ptr(self): - """Returns the numbered function (i.e. USART6) for this AF.""" - if self.fn_num is None: - return self.func - return '{:s}{:d}'.format(self.func, self.fn_num) - - def print(self): - """Prints the C representation of this AF.""" - if self.supported: - print(' AF', end='') - else: - print(' //', end='') - fn_num = self.fn_num - if fn_num is None: - fn_num = 0 - print('({:2d}, {:8s}, {:2d}, {:10s}, {:8s}), // {:s}'.format(self.idx, - self.func, fn_num, self.pin_type, self.ptr(), self.af_str)) - - -class Pin(object): - """Holds the information associated with a pin.""" - - def __init__(self, port, pin): - self.port = port - self.pin = pin - self.alt_fn = [] - self.board_name = None - self.alt_fn_count = 0 - - def port_letter(self): - return chr(self.port + ord('A')) - - def pin_name(self): - return '{:s}{:d}'.format(self.port_letter(), self.pin) - - def parse_af(self, af_idx, af_strs_in): - if len(af_strs_in) == 0: - return - # If there is a slash, then the slash separates 2 aliases for the - # same alternate function. - af_strs = af_strs_in.split('/') - for af_str in af_strs: - alt_fn = AlternateFunction(af_idx, af_str) - self.alt_fn.append(alt_fn) - if alt_fn.is_supported(): - self.alt_fn_count += 1 - - def alt_fn_name(self): - if self.alt_fn_count > 0: - return 'pin_{:s}_af'.format(self.pin_name()) - return 'NULL' - - def print(self): - if self.alt_fn_count == 0: - print("// ", end='') - print('const pin_af_obj_t {:s}[] = {{'.format(self.alt_fn_name())) - for alt_fn in self.alt_fn: - alt_fn.print() - if self.alt_fn_count == 0: - print("// ", end='') - print('};') - print('') - print('const pin_obj_t pin_{:s} = PIN({:s}, {:d}, {:d}, {:s});'.format( - self.pin_name(), self.port_letter(), self.pin, - self.alt_fn_count, self.alt_fn_name())) - print('') - - def print_header(self, hdr_file): - hdr_file.write('extern const pin_obj_t pin_{:s};\n'. - format(self.pin_name())) - if self.alt_fn_count > 0: - hdr_file.write('extern const pin_af_obj_t pin_{:s}_af[];\n'. - format(self.pin_name())) - - -class Pins(object): - - def __init__(self): - self.pins = [] - self.board_pins = [] - - def find_pin(self, port_num, pin_num): - for pin in self.pins: - if pin.port == port_num and pin.pin == pin_num: - return pin - - def parse_af_file(self, filename, pinname_col, af_col): - with open(filename, 'r') as csvfile: - rows = csv.reader(csvfile) - for row in rows: - try: - (port_num, pin_num) = parse_port_pin(row[pinname_col]) - except: - continue - pin = Pin(port_num, pin_num) - for af_idx in range(af_col, len(row)): - pin.parse_af(af_idx - af_col, row[af_idx]) - self.pins.append(pin) - - def parse_board_file(self, filename): - with open(filename, 'r') as csvfile: - rows = csv.reader(csvfile) - for row in rows: - try: - (port_num, pin_num) = parse_port_pin(row[1]) - except: - continue - pin = self.find_pin(port_num, pin_num) - if pin: - pin.board_name = row[0] - self.board_pins.append(pin) - - def print_named(self, label, pins): - print('const pin_named_pin_t pin_{:s}_pins[] = {{'.format(label)) - for pin in pins: - if pin.board_name: - if label == 'board': - pin_name = pin.board_name - else: - pin_name = pin.pin_name() - print(' {{ "{:s}", &pin_{:s} }},'.format(pin_name, pin.pin_name())) - print(' { NULL, NULL }') - print('};') - - def print(self): - for pin in self.pins: - if pin.board_name: - pin.print() - self.print_named('cpu', self.pins) - print('') - self.print_named('board', self.board_pins) - - def print_header(self, hdr_filename): - with open(hdr_filename, 'wt') as hdr_file: - for pin in self.pins: - if pin.board_name: - pin.print_header(hdr_file) - - -def main(): - parser = argparse.ArgumentParser( - prog="make-pins.py", - usage="%(prog)s [options] [command]", - description="Generate board specific pin file" - ) - parser.add_argument( - "-a", "--af", - dest="af_filename", - help="Specifies the alternate function file for the chip", - default="stm32f4xx-af.csv" - ) - parser.add_argument( - "-b", "--board", - dest="board_filename", - help="Specifies the board file", - ) - parser.add_argument( - "-p", "--prefix", - dest="prefix_filename", - help="Specifies beginning portion of generated pins file", - default="stm32f4xx-prefix.c" - ) - parser.add_argument( - "-r", "--hdr", - dest="hdr_filename", - help="Specifies name of generated pin header file", - default="build/pins.h" - ) - args = parser.parse_args(sys.argv[1:]) - - pins = Pins() - - print('// This file was automatically generated by make-pins.py') - print('//') - if args.af_filename: - print('// --af {:s}'.format(args.af_filename)) - pins.parse_af_file(args.af_filename, 1, 2) - - if args.board_filename: - print('// --board {:s}'.format(args.board_filename)) - pins.parse_board_file(args.board_filename) - - if args.prefix_filename: - print('// --prefix {:s}'.format(args.prefix_filename)) - print('') - with open(args.prefix_filename, 'r') as prefix_file: - print(prefix_file.read()) - pins.print() - pins.print_header(args.hdr_filename) - - -if __name__ == "__main__": - main() diff --git a/stm/boards/stm32f4xx-af.csv b/stm/boards/stm32f4xx-af.csv deleted file mode 100644 index fde7fcfc1..000000000 --- a/stm/boards/stm32f4xx-af.csv +++ /dev/null @@ -1,142 +0,0 @@ -Port,,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15 -,,SYS,TIM1/2,TIM3/4/5,TIM8/9/10/11,I2C1/2/3,SPI1/SPI2/I2S2/I2S2ext,SPI3/I2Sext/I2S3,USART1/2/3/I2S3ext,UART4/5/USART6,CAN1/CAN2/TIM12/13/14,OTG_FS/OTG_HS,ETH,FSMC/SDIO/OTG_FS,DCMI,, -PortA,PA0,,TIM2_CH1_ETR,TIM5_CH1,TIM8_ETR,,,,USART2_CTS,UART4_TX,,,ETH_MII_CRS,,,,EVENTOUT -PortA,PA1,,TIM2_CH2,TIM5_CH2,,,,,USART2_RTS,UART4_RX,,,ETH_MII_RX_CLK/ETH_RMII__REF_CLK,,,,EVENTOUT -PortA,PA2,,TIM2_CH3,TIM5_CH3,TIM9_CH1,,,,USART2_TX,,,,ETH_MDIO,,,,EVENTOUT -PortA,PA3,,TIM2_CH4,TIM5_CH4,TIM9_CH2,,,,USART2_RX,,,OTG_HS_ULPI_D0,ETH_MII_COL,,,,EVENTOUT -PortA,PA4,,,,,,SPI1_NSS,SPI3_NSS/I2S3_WS,USART2_CK,,,,,OTG_HS_SOF,DCMI_HSYNC,,EVENTOUT -PortA,PA5,,TIM2_CH1_ETR,,TIM8_CH1N,,SPI1_SCK,,,,,OTG_HS_ULPI_CK,,,,,EVENTOUT -PortA,PA6,,TIM1_BKIN,TIM3_CH1,TIM8_BKIN,,SPI1_MISO,,,,TIM13_CH1,,,,DCMI_PIXCK,,EVENTOUT -PortA,PA7,,TIM1_CH1N,TIM3_CH2,TIM8_CH1N,,SPI1_MOSI,,,,TIM14_CH1,,ETH_MII_RX_DV/ETH_RMII_CRS_DV,,,,EVENTOUT -PortA,PA8,MCO1,TIM1_CH1,,,I2C3_SCL,,,USART1_CK,,,OTG_FS_SOF,,,,,EVENTOUT -PortA,PA9,,TIM1_CH2,,,I2C3_SMBA,,,USART1_TX,,,,,,DCMI_D0,,EVENTOUT -PortA,PA10,,TIM1_CH3,,,,,,USART1_RX,,,OTG_FS_ID,,,DCMI_D1,,EVENTOUT -PortA,PA11,,TIM1_CH4,,,,,,USART1_CTS,,CAN1_RX,OTG_FS_DM,,,,,EVENTOUT -PortA,PA12,,TIM1_ETR,,,,,,USART1_RTS,,CAN1_TX,OTG_FS_DP,,,,,EVENTOUT -PortA,PA13,JTMS-SWDIO,,,,,,,,,,,,,,,EVENTOUT -PortA,PA14,JTCK-SWCLK,,,,,,,,,,,,,,,EVENTOUT -PortA,PA15,JTDI,TIM2_CH1/TIM2_ETR,,,,SPI1_NSS,SPI3_NSS/I2S3_WS,,,,,,,,,EVENTOUT -PortB,PB0,,TIM1_CH2N,TIM3_CH3,TIM8_CH2N,,,,,,,OTG_HS_ULPI_D1,ETH_MII_RXD2,,,,EVENTOUT -PortB,PB1,,TIM1_CH3N,TIM3_CH4,TIM8_CH3N,,,,,,,OTG_HS_ULPI_D2,ETH_MII_RXD3,,,,EVENTOUT -PortB,PB2,,,,,,,,,,,,,,,,EVENTOUT -PortB,PB3,JTDO/TRACESWO,TIM2_CH2,,,,SPI1_SCK,SPI3_SCKI2S3_CK,,,,,,,,,EVENTOUT -PortB,PB4,NJTRST,,TIM3_CH1,,,SPI1_MISO,SPI3_MISO,I2S3ext_SD,,,,,,,,EVENTOUT -PortB,PB5,,,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI,SPI3_MOSI/I2S3_SD,,,CAN2_RX,OTG_HS_ULPI_D7,ETH_PPS_OUT,,DCMI_D10,,EVENTOUT -PortB,PB6,,,TIM4_CH1,,I2C1_SCL,,,USART1_TX,,CAN2_TX,,,,DCMI_D5,,EVENTOUT -PortB,PB7,,,TIM4_CH2,,I2C1_SDA,,,USART1_RX,,,,,FSMC_NL,DCMI_VSYNC,,EVENTOUT -PortB,PB8,,,TIM4_CH3,TIM10_CH1,I2C1_SCL,,,,,CAN1_RX,,ETH_MII_TXD3,SDIO_D4,DCMI_D6,,EVENTOUT -PortB,PB9,,,TIM4_CH4,TIM11_CH1,I2C1_SDA,SPI2_NSS/I2S2_WS,,,,CAN1_TX,,,SDIO_D5,DCMI_D7,,EVENTOUT -PortB,PB10,,TIM2_CH3,,,I2C2_SCL,SPI2_SCKI2S2_CK,,USART3_TX,,,OTG_HS_ULPI_D3,ETH_MII_RX_ER,,,,EVENTOUT -PortB,PB11,,TIM2_CH4,,,I2C2_SDA,,,USART3_RX,,,OTG_HS_ULPI_D4,ETH_MII_TX_EN/ETH_RMII_TX_EN,,,,EVENTOUT -PortB,PB12,,TIM1_BKIN,,,I2C2_SMBA,SPI2_NSS/I2S2_WS,,USART3_CK,,CAN2_RX,OTG_HS_ULPI_D5,ETH_MII_TXD0/ETH_RMII_TXD0,OTG_HS_ID,,,EVENTOUT -PortB,PB13,,TIM1_CH1N,,,,SPI2_SCKI2S2_CK,,USART3_CTS,,CAN2_TX,OTG_HS_ULPI_D6,ETH_MII_TXD1/ETH_RMII_TXD1,,,,EVENTOUT -PortB,PB14,,TIM1_CH2N,,TIM8_CH2N,,SPI2_MISO,I2S2ext_SD,USART3_RTS,,TIM12_CH1,,,OTG_HS_DM,,,EVENTOUT -PortB,PB15,RTC_REFIN,TIM1_CH3N,,TIM8_CH3N,,SPI2_MOSI/I2S2_SD,,,,TIM12_CH2,,,OTG_HS_DP,,,EVENTOUT -PortC,PC0,,,,,,,,,,,OTG_HS_ULPI_STP,,,,,EVENTOUT -PortC,PC1,,,,,,,,,,,,ETH_MDC,,,,EVENTOUT -PortC,PC2,,,,,,SPI2_MISO,I2S2ext_SD,,,,OTG_HS_ULPI_DIR,ETH_MII_TXD2,,,,EVENTOUT -PortC,PC3,,,,,,SPI2_MOSI/I2S2_SD,,,,,OTG_HS_ULPI_NXT,ETH_MII_TX_CLK,,,,EVENTOUT -PortC,PC4,,,,,,,,,,,,ETH_MII_RXD0/ETH_RMII_RXD0,,,,EVENTOUT -PortC,PC5,,,,,,,,,,,,ETH_MII_RXD1/ETH_RMII_RXD1,,,,EVENTOUT -PortC,PC6,,,TIM3_CH1,TIM8_CH1,,I2S2_MCK,,,USART6_TX,,,,SDIO_D6,DCMI_D0,,EVENTOUT -PortC,PC7,,,TIM3_CH2,TIM8_CH2,,,I2S3_MCK,,USART6_RX,,,,SDIO_D7,DCMI_D1,,EVENTOUT -PortC,PC8,,,TIM3_CH3,TIM8_CH3,,,,,USART6_CK,,,,SDIO_D0,DCMI_D2,,EVENTOUT -PortC,PC9,MCO2,,TIM3_CH4,TIM8_CH4,I2C3_SDA,I2S_CKIN,,,,,,,SDIO_D1,DCMI_D3,,EVENTOUT -PortC,PC10,,,,,,,SPI3_SCK/I2S3_CK,USART3_TX,UART4_TX,,,,SDIO_D2,DCMI_D8,,EVENTOUT -PortC,PC11,,,,,,I2S3ext_SD,SPI3_MISO,USART3_RX,UART4_RX,,,,SDIO_D3,DCMI_D4,,EVENTOUT -PortC,PC12,,,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,UART5_TX,,,,SDIO_CK,DCMI_D9,,EVENTOUT -PortC,PC13,,,,,,,,,,,,,,,,EVENTOUT -PortC,PC14,,,,,,,,,,,,,,,,EVENTOUT -PortC,PC15,,,,,,,,,,,,,,,,EVENTOUT -PortD,PD0,,,,,,,,,,CAN1_RX,,,FSMC_D2,,,EVENTOUT -PortD,PD1,,,,,,,,,,CAN1_TX,,,FSMC_D3,,,EVENTOUT -PortD,PD2,,,TIM3_ETR,,,,,,UART5_RX,,,,SDIO_CMD,DCMI_D11,,EVENTOUT -PortD,PD3,,,,,,,,USART2_CTS,,,,,FSMC_CLK,,,EVENTOUT -PortD,PD4,,,,,,,,USART2_RTS,,,,,FSMC_NOE,,,EVENTOUT -PortD,PD5,,,,,,,,USART2_TX,,,,,FSMC_NWE,,,EVENTOUT -PortD,PD6,,,,,,,,USART2_RX,,,,,FSMC_NWAIT,,,EVENTOUT -PortD,PD7,,,,,,,,USART2_CK,,,,,FSMC_NE1/FSMC_NCE2,,,EVENTOUT -PortD,PD8,,,,,,,,USART3_TX,,,,,FSMC_D13,,,EVENTOUT -PortD,PD9,,,,,,,,USART3_RX,,,,,FSMC_D14,,,EVENTOUT -PortD,PD10,,,,,,,,USART3_CK,,,,,FSMC_D15,,,EVENTOUT -PortD,PD11,,,,,,,,USART3_CTS,,,,,FSMC_A16,,,EVENTOUT -PortD,PD12,,,TIM4_CH1,,,,,USART3_RTS,,,,,FSMC_A17,,,EVENTOUT -PortD,PD13,,,TIM4_CH2,,,,,,,,,,FSMC_A18,,,EVENTOUT -PortD,PD14,,,TIM4_CH3,,,,,,,,,,FSMC_D0,,,EVENTOUT -PortD,PD15,,,TIM4_CH4,,,,,,,,,,FSMC_D1,,,EVENTOUT -PortE,PE0,,,TIM4_ETR,,,,,,,,,,FSMC_NBL0,DCMI_D2,,EVENTOUT -PortE,PE1,,,,,,,,,,,,,FSMC_NBL1,DCMI_D3,,EVENTOUT -PortE,PE2,TRACECLK,,,,,,,,,,,ETH_MII_TXD3,FSMC_A23,,,EVENTOUT -PortE,PE3,TRACED0,,,,,,,,,,,,FSMC_A19,,,EVENTOUT -PortE,PE4,TRACED1,,,,,,,,,,,,FSMC_A20,DCMI_D4,,EVENTOUT -PortE,PE5,TRACED2,,,TIM9_CH1,,,,,,,,,FSMC_A21,DCMI_D6,,EVENTOUT -PortE,PE6,TRACED3,,,TIM9_CH2,,,,,,,,,FSMC_A22,DCMI_D7,,EVENTOUT -PortE,PE7,,TIM1_ETR,,,,,,,,,,,FSMC_D4,,,EVENTOUT -PortE,PE8,,TIM1_CH1N,,,,,,,,,,,FSMC_D5,,,EVENTOUT -PortE,PE9,,TIM1_CH1,,,,,,,,,,,FSMC_D6,,,EVENTOUT -PortE,PE10,,TIM1_CH2N,,,,,,,,,,,FSMC_D7,,,EVENTOUT -PortE,PE11,,TIM1_CH2,,,,,,,,,,,FSMC_D8,,,EVENTOUT -PortE,PE12,,TIM1_CH3N,,,,,,,,,,,FSMC_D9,,,EVENTOUT -PortE,PE13,,TIM1_CH3,,,,,,,,,,,FSMC_D10,,,EVENTOUT -PortE,PE14,,TIM1_CH4,,,,,,,,,,,FSMC_D11,,,EVENTOUT -PortE,PE15,,TIM1_BKIN,,,,,,,,,,,FSMC_D12,,,EVENTOUT -PortF,PF0,,,,,I2C2_SDA,,,,,,,,FSMC_A0,,,EVENTOUT -PortF,PF1,,,,,I2C2_SCL,,,,,,,,FSMC_A1,,,EVENTOUT -PortF,PF2,,,,,I2C2_SMBA,,,,,,,,FSMC_A2,,,EVENTOUT -PortF,PF3,,,,,,,,,,,,,FSMC_A3,,,EVENTOUT -PortF,PF4,,,,,,,,,,,,,FSMC_A4,,,EVENTOUT -PortF,PF5,,,,,,,,,,,,,FSMC_A5,,,EVENTOUT -PortF,PF6,,,,TIM10_CH1,,,,,,,,,FSMC_NIORD,,,EVENTOUT -PortF,PF7,,,,TIM11_CH1,,,,,,,,,FSMC_NREG,,,EVENTOUT -PortF,PF8,,,,,,,,,,TIM13_CH1,,,FSMC_NIOWR,,,EVENTOUT -PortF,PF9,,,,,,,,,,TIM14_CH1,,,FSMC_CD,,,EVENTOUT -PortF,PF10,,,,,,,,,,,,,FSMC_INTR,,,EVENTOUT -PortF,PF11,,,,,,,,,,,,,,DCMI_D12,,EVENTOUT -PortF,PF12,,,,,,,,,,,,,FSMC_A6,,,EVENTOUT -PortF,PF13,,,,,,,,,,,,,FSMC_A7,,,EVENTOUT -PortF,PF14,,,,,,,,,,,,,FSMC_A8,,,EVENTOUT -PortF,PF15,,,,,,,,,,,,,FSMC_A9,,,EVENTOUT -PortG,PG0,,,,,,,,,,,,,FSMC_A10,,,EVENTOUT -PortG,PG1,,,,,,,,,,,,,FSMC_A11,,,EVENTOUT -PortG,PG2,,,,,,,,,,,,,FSMC_A12,,,EVENTOUT -PortG,PG3,,,,,,,,,,,,,FSMC_A13,,,EVENTOUT -PortG,PG4,,,,,,,,,,,,,FSMC_A14,,,EVENTOUT -PortG,PG5,,,,,,,,,,,,,FSMC_A15,,,EVENTOUT -PortG,PG6,,,,,,,,,,,,,FSMC_INT2,,,EVENTOUT -PortG,PG7,,,,,,,,,USART6_CK,,,,FSMC_INT3,,,EVENTOUT -PortG,PG8,,,,,,,,,USART6_RTS,,,ETH_PPS_OUT,,,,EVENTOUT -PortG,PG9,,,,,,,,,USART6_RX,,,,FSMC_NE2/FSMC_NCE3,,,EVENTOUT -PortG,PG10,,,,,,,,,,,,,FSMC_NCE4_1/FSMC_NE3,,,EVENTOUT -PortG,PG11,,,,,,,,,,,,ETH_MII_TX_EN/ETH_RMII_TX_EN,FSMC_NCE4_2,,,EVENTOUT -PortG,PG12,,,,,,,,,USART6_RTS,,,,FSMC_NE4,,,EVENTOUT -PortG,PG13,,,,,,,,,USART6_CTS,,,ETH_MII_TXD0/ETH_RMII_TXD0,FSMC_A24,,,EVENTOUT -PortG,PG14,,,,,,,,,USART6_TX,,,ETH_MII_TXD1/ETH_RMII_TXD1,FSMC_A25,,,EVENTOUT -PortG,PG15,,,,,,,,,USART6_CTS,,,,,DCMI_D13,,EVENTOUT -PortH,PH0,,,,,,,,,,,,,,,,EVENTOUT -PortH,PH1,,,,,,,,,,,,,,,,EVENTOUT -PortH,PH2,,,,,,,,,,,,ETH_MII_CRS,,,,EVENTOUT -PortH,PH3,,,,,,,,,,,,ETH_MII_COL,,,,EVENTOUT -PortH,PH4,,,,,I2C2_SCL,,,,,,OTG_HS_ULPI_NXT,,,,,EVENTOUT -PortH,PH5,,,,,I2C2_SDA,,,,,,,,,,,EVENTOUT -PortH,PH6,,,,,I2C2_SMBA,,,,,TIM12_CH1,,ETH_MII_RXD2,,,,EVENTOUT -PortH,PH7,,,,,I2C3_SCL,,,,,,,ETH_MII_RXD3,,,,EVENTOUT -PortH,PH8,,,,,I2C3_SDA,,,,,,,,,DCMI_HSYNC,,EVENTOUT -PortH,PH9,,,,,I2C3_SMBA,,,,,TIM12_CH2,,,,DCMI_D0,,EVENTOUT -PortH,PH10,,,TIM5_CH1,,,,,,,,,,,DCMI_D1,,EVENTOUT -PortH,PH11,,,TIM5_CH2,,,,,,,,,,,DCMI_D2,,EVENTOUT -PortH,PH12,,,TIM5_CH3,,,,,,,,,,,DCMI_D3,,EVENTOUT -PortH,PH13,,,,TIM8_CH1N,,,,,,CAN1_TX,,,,,,EVENTOUT -PortH,PH14,,,,TIM8_CH2N,,,,,,,,,,DCMI_D4,,EVENTOUT -PortH,PH15,,,,TIM8_CH3N,,,,,,,,,,DCMI_D11,,EVENTOUT -PortI,PI0,,,TIM5_CH4,,,SPI2_NSS/I2S2_WS,,,,,,,,DCMI_D13,,EVENTOUT -PortI,PI1,,,,,,SPI2_SCKI2S2_CK,,,,,,,,DCMI_D8,,EVENTOUT -PortI,PI2,,,,TIM8_CH4,,SPI2_MISO,I2S2ext_SD,,,,,,,DCMI_D9,,EVENTOUT -PortI,PI3,,,,TIM8_ETR,,SPI2_MOSI/I2S2_SD,,,,,,,,DCMI_D10,,EVENTOUT -PortI,PI4,,,,TIM8_BKIN,,,,,,,,,,DCMI_D5,,EVENTOUT -PortI,PI5,,,,TIM8_CH1,,,,,,,,,,DCMI_VSYNC,,EVENTOUT -PortI,PI6,,,,TIM8_CH2,,,,,,,,,,DCMI_D6,,EVENTOUT -PortI,PI7,,,,TIM8_CH3,,,,,,,,,,DCMI_D7,,EVENTOUT -PortI,PI8,,,,,,,,,,,,,,,,EVENTOUT -PortI,PI9,,,,,,,,,,CAN1_RX,,,,,,EVENTOUT -PortI,PI10,,,,,,,,,,,,ETH_MII_RX_ER,,,,EVENTOUT -PortI,PI11,,,,,,,,,,,OTG_HS_ULPI_DIR,,,,,EVENTOUT diff --git a/stm/boards/stm32f4xx-prefix.c b/stm/boards/stm32f4xx-prefix.c deleted file mode 100644 index e68de4cf4..000000000 --- a/stm/boards/stm32f4xx-prefix.c +++ /dev/null @@ -1,34 +0,0 @@ -// stm32fxx-prefix.c becomes the initial portion of the generated pins file. - -#include -#include -#include - -#include "misc.h" -#include "mpconfig.h" -#include "qstr.h" -#include "obj.h" - -#include "pin.h" - -#define AF(af_idx, af_fn, af_unit, af_type, af_ptr) \ -{ \ - { &pin_af_obj_type }, \ - .idx = (af_idx), \ - .fn = AF_FN_ ## af_fn, \ - .unit = (af_unit), \ - .type = AF_PIN_TYPE_ ## af_fn ## _ ## af_type, \ - .af_fn = (af_ptr) \ -} - -#define PIN(p_port, p_pin, p_num_af, p_af) \ -{ \ - { &pin_obj_type }, \ - .name = #p_port #p_pin, \ - .port = PORT_ ## p_port, \ - .pin = (p_pin), \ - .num_af = (p_num_af), \ - .pin_mask = (1 << ((p_pin) & 0x0f)), \ - .gpio = GPIO ## p_port, \ - .af = p_af, \ -} diff --git a/stm/cc3k/cc3000_common.c b/stm/cc3k/cc3000_common.c deleted file mode 100644 index 48eda2676..000000000 --- a/stm/cc3k/cc3000_common.c +++ /dev/null @@ -1,196 +0,0 @@ -/***************************************************************************** -* -* cc3000_common.c.c - CC3000 Host Driver Implementation. -* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ -* -* Adapted for use with the Arduino/AVR by KTOWN (Kevin Townsend) -* & Limor Fried for Adafruit Industries -* This library works with the Adafruit CC3000 breakout -* ----> https://www.adafruit.com/products/1469 -* Adafruit invests time and resources providing this open source code, -* please support Adafruit and open-source hardware by purchasing -* products from Adafruit! -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*****************************************************************************/ -//***************************************************************************** -// -//! \addtogroup common_api -//! @{ -// -//***************************************************************************** -/****************************************************************************** - * - * Include files - * - *****************************************************************************/ -#include - -#include "cc3000_common.h" -#include "socket.h" -#include "wlan.h" -#include "evnt_handler.h" -#include "ccdebug.h" - -//***************************************************************************** -// -//! __error__ -//! -//! @param pcFilename - file name, where error occurred -//! @param ulLine - line number, where error occurred -//! -//! @return none -//! -//! @brief stub function for ASSERT macro -// -//***************************************************************************** -void -__error__(char *pcFilename, unsigned long ulLine) -{ - //TODO full up function -} - - - -//***************************************************************************** -// -//! UINT32_TO_STREAM_f -//! -//! @param p pointer to the new stream -//! @param u32 pointer to the 32 bit -//! -//! @return pointer to the new stream -//! -//! @brief This function is used for copying 32 bit to stream -//! while converting to little endian format. -// -//***************************************************************************** - -uint8_t* UINT32_TO_STREAM_f (uint8_t *p, uint32_t u32) -{ - *(p)++ = (uint8_t)(u32); - *(p)++ = (uint8_t)((u32) >> 8); - *(p)++ = (uint8_t)((u32) >> 16); - *(p)++ = (uint8_t)((u32) >> 24); - return p; -} - -//***************************************************************************** -// -//! UINT16_TO_STREAM_f -//! -//! @param p pointer to the new stream -//! @param u32 pointer to the 16 bit -//! -//! @return pointer to the new stream -//! -//! @brief This function is used for copying 16 bit to stream -//! while converting to little endian format. -// -//***************************************************************************** - -uint8_t* UINT16_TO_STREAM_f (uint8_t *p, uint16_t u16) -{ - *(p)++ = (uint8_t)(u16); - *(p)++ = (uint8_t)((u16) >> 8); - return p; -} - -//***************************************************************************** -// -//! STREAM_TO_UINT16_f -//! -//! @param p pointer to the stream -//! @param offset offset in the stream -//! -//! @return pointer to the new 16 bit -//! -//! @brief This function is used for copying received stream to -//! 16 bit in little endian format. -// -//***************************************************************************** - -uint16_t STREAM_TO_UINT16_f(char* cp, uint16_t offset) -{ - uint8_t *p = (uint8_t *)cp; - /* - DEBUGPRINT_F("Stream2u16: "); - DEBUGPRINT_HEX(cp[offset+1]); - DEBUGPRINT_F(" + "); - DEBUGPRINT_HEX(cp[offset]); - DEBUGPRINT_F("\n\r"); - */ - - return (uint16_t)((uint16_t) - ((uint16_t)(*(p + offset + 1)) << 8) + - (uint16_t)(*(p + offset))); -} - -//***************************************************************************** -// -//! STREAM_TO_UINT32_f -//! -//! @param p pointer to the stream -//! @param offset offset in the stream -//! -//! @return pointer to the new 32 bit -//! -//! @brief This function is used for copying received stream to -//! 32 bit in little endian format. -// -//***************************************************************************** - -uint32_t STREAM_TO_UINT32_f(char * cp, uint16_t offset) -{ - uint8_t *p = (uint8_t *)cp; - - /* - DEBUGPRINT_F("\tStream2u32: "); - DEBUGPRINT_HEX(cp[offset+3]); DEBUGPRINT_F(" + "); - DEBUGPRINT_HEX(cp[offset+2]); DEBUGPRINT_F(" + "); - DEBUGPRINT_HEX(cp[offset+1]); DEBUGPRINT_F(" + "); - DEBUGPRINT_HEX(cp[offset]); - DEBUGPRINT_F("\n\r"); - */ - - return (uint32_t)((uint32_t)((uint32_t) - (*(p + offset + 3)) << 24) + (uint32_t)((uint32_t) - (*(p + offset + 2)) << 16) + (uint32_t)((uint32_t) - (*(p + offset + 1)) << 8) + (uint32_t)(*(p + offset))); -} - - - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/stm/cc3k/cc3000_common.h b/stm/cc3k/cc3000_common.h deleted file mode 100644 index 4297d249b..000000000 --- a/stm/cc3k/cc3000_common.h +++ /dev/null @@ -1,385 +0,0 @@ -/***************************************************************************** -* -* cc3000_common.h - CC3000 Host Driver Implementation. -* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ -* -* Adapted for use with the Arduino/AVR by KTOWN (Kevin Townsend) -* & Limor Fried for Adafruit Industries -* This library works with the Adafruit CC3000 breakout -* ----> https://www.adafruit.com/products/1469 -* Adafruit invests time and resources providing this open source code, -* please support Adafruit and open-source hardware by purchasing -* products from Adafruit! -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*****************************************************************************/ -#ifndef __COMMON_H__ -#define __COMMON_H__ - -//****************************************************************************** -// Include files -//****************************************************************************** -//#include -//#include -//#include - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" { -#endif - -//***************************************************************************** -// ERROR CODES -//***************************************************************************** -#define ESUCCESS 0 -#define EFAIL -1 -#define EERROR EFAIL - -//***************************************************************************** -// COMMON DEFINES -//***************************************************************************** -#define ERROR_SOCKET_INACTIVE -57 - -#define WLAN_ENABLE (1) -#define WLAN_DISABLE (0) - -#define MAC_ADDR_LEN (6) - -#define SP_PORTION_SIZE (32) - -// #define CC3000_TINY_DRIVER - -/*Defines for minimal and maximal RX buffer size. This size includes the spi - header and hci header. - The maximal buffer size derives from: - MTU + HCI header + SPI header + sendto() agrs size - The minimum buffer size derives from: - HCI header + SPI header + max args size - - This buffer is used for receiving events and data. - The packet can not be longer than MTU size and CC3000 does not support - fragmentation. Note that the same buffer is used for reception of the data - and events from CC3000. That is why the minimum is defined. - The calculation for the actual size of buffer for reception is: - Given the maximal data size MAX_DATA that is expected to be received by - application, the required buffer is: - Using recv() or recvfrom(): - - max(CC3000_MINIMAL_RX_SIZE, MAX_DATA + HEADERS_SIZE_DATA + fromlen - + ucArgsize + 1) - - Using gethostbyname() with minimal buffer size will limit the host name - returned to 99 bytes only. - The 1 is used for the overrun detection - - Buffer size increased to 130 following the add_profile() with WEP security - which requires TX buffer size of 130 bytes: - HEADERS_SIZE_EVNT + WLAN_ADD_PROFILE_WEP_PARAM_LEN + MAX SSID LEN + 4 * MAX KEY LEN = 130 - MAX SSID LEN = 32 - MAX SSID LEN = 13 (with add_profile only ascii key setting is supported, - therfore maximum key size is 13) -*/ - -#define CC3000_MINIMAL_RX_SIZE (130 + 1) -#define CC3000_MAXIMAL_RX_SIZE (1519 + 1) - -/*Defines for minimal and maximal TX buffer size. - This buffer is used for sending events and data. - The packet can not be longer than MTU size and CC3000 does not support - fragmentation. Note that the same buffer is used for transmission of the data - and commands. That is why the minimum is defined. - The calculation for the actual size of buffer for transmission is: - Given the maximal data size MAX_DATA, the required buffer is: - Using Sendto(): - - max(CC3000_MINIMAL_TX_SIZE, MAX_DATA + SPI_HEADER_SIZE - + SOCKET_SENDTO_PARAMS_LEN + SIMPLE_LINK_HCI_DATA_HEADER_SIZE + 1) - - Using Send(): - - max(CC3000_MINIMAL_TX_SIZE, MAX_DATA + SPI_HEADER_SIZE - + HCI_CMND_SEND_ARG_LENGTH + SIMPLE_LINK_HCI_DATA_HEADER_SIZE + 1) - - The 1 is used for the overrun detection */ - -#define CC3000_MINIMAL_TX_SIZE (130 + 1) -#define CC3000_MAXIMAL_TX_SIZE (1519 + 1) - -//TX and RX buffer sizes, allow to receive and transmit maximum data at length 8. -#ifdef CC3000_TINY_DRIVER -#define TINY_CC3000_MAXIMAL_RX_SIZE 44 -#define TINY_CC3000_MAXIMAL_TX_SIZE 59 -#endif - -/*In order to determine your preferred buffer size, - change CC3000_MAXIMAL_RX_SIZE and CC3000_MAXIMAL_TX_SIZE to a value between - the minimal and maximal specified above. - Note that the buffers are allocated by SPI. - In case you change the size of those buffers, you might need also to change - the linker file, since for example on MSP430 FRAM devices the buffers are - allocated in the FRAM section that is allocated manually and not by IDE. -*/ - -#ifndef CC3000_TINY_DRIVER - - #define CC3000_RX_BUFFER_SIZE (CC3000_MINIMAL_RX_SIZE) - #define CC3000_TX_BUFFER_SIZE (CC3000_MINIMAL_TX_SIZE) - -//if defined TINY DRIVER we use smaller RX and TX buffer in order to minimize RAM consumption -#else - #define CC3000_RX_BUFFER_SIZE (TINY_CC3000_MAXIMAL_RX_SIZE) - #define CC3000_TX_BUFFER_SIZE (TINY_CC3000_MAXIMAL_TX_SIZE) - -#endif - -//***************************************************************************** -// Compound Types -//***************************************************************************** -#ifdef __AVR__ -typedef unsigned long time_t; /* KTown: Updated to be compatible with Arduino Time.h */ -#else -typedef long time_t; -#endif -typedef unsigned long clock_t; -typedef long suseconds_t; - -typedef struct timeval timeval; - -struct timeval -{ - time_t tv_sec; /* seconds */ - suseconds_t tv_usec; /* microseconds */ -}; - -typedef char *(*tFWPatches)(unsigned long *usLength); - -typedef char *(*tDriverPatches)(unsigned long *usLength); - -typedef char *(*tBootLoaderPatches)(unsigned long *usLength); - -typedef void (*tWlanCB)(long event_type, char * data, unsigned char length ); - -typedef long (*tWlanReadInteruptPin)(void); - -typedef void (*tWlanInterruptEnable)(void); - -typedef void (*tWlanInterruptDisable)(void); - -typedef void (*tWriteWlanPin)(unsigned char val); - -typedef struct -{ - unsigned short usRxEventOpcode; - unsigned short usEventOrDataReceived; - unsigned char *pucReceivedData; - unsigned char *pucTxCommandBuffer; - - tFWPatches sFWPatches; - tDriverPatches sDriverPatches; - tBootLoaderPatches sBootLoaderPatches; - tWlanCB sWlanCB; - tWlanReadInteruptPin ReadWlanInterruptPin; - tWlanInterruptEnable WlanInterruptEnable; - tWlanInterruptDisable WlanInterruptDisable; - tWriteWlanPin WriteWlanPin; - - signed long slTransmitDataError; - unsigned short usNumberOfFreeBuffers; - unsigned short usSlBufferLength; - unsigned short usBufferSize; - unsigned short usRxDataPending; - - unsigned long NumberOfSentPackets; - unsigned long NumberOfReleasedPackets; - - unsigned char InformHostOnTxComplete; -}sSimplLinkInformation; - -extern volatile sSimplLinkInformation tSLInformation; - - -//***************************************************************************** -// Prototypes for the APIs. -//***************************************************************************** - - - -//***************************************************************************** -// -//! SimpleLinkWaitEvent -//! -//! @param usOpcode command operation code -//! @param pRetParams command return parameters -//! -//! @return none -//! -//! @brief Wait for event, pass it to the hci_event_handler and -//! update the event opcode in a global variable. -// -//***************************************************************************** - -extern void SimpleLinkWaitEvent(unsigned short usOpcode, void *pRetParams); - -//***************************************************************************** -// -//! SimpleLinkWaitData -//! -//! @param pBuf data buffer -//! @param from from information -//! @param fromlen from information length -//! -//! @return none -//! -//! @brief Wait for data, pass it to the hci_event_handler -//! and update in a global variable that there is -//! data to read. -// -//***************************************************************************** - -extern void SimpleLinkWaitData(uint8_t *pBuf, uint8_t *from, uint8_t *fromlen); - -//***************************************************************************** -// -//! UINT32_TO_STREAM_f -//! -//! \param p pointer to the new stream -//! \param u32 pointer to the 32 bit -//! -//! \return pointer to the new stream -//! -//! \brief This function is used for copying 32 bit to stream -//! while converting to little endian format. -// -//***************************************************************************** - -extern uint8_t* UINT32_TO_STREAM_f (uint8_t *p, uint32_t u32); - -//***************************************************************************** -// -//! UINT16_TO_STREAM_f -//! -//! \param p pointer to the new stream -//! \param u32 pointer to the 16 bit -//! -//! \return pointer to the new stream -//! -//! \brief This function is used for copying 16 bit to stream -//! while converting to little endian format. -// -//***************************************************************************** - -extern uint8_t* UINT16_TO_STREAM_f (uint8_t *p, uint16_t u16); - -//***************************************************************************** -// -//! STREAM_TO_UINT16_f -//! -//! \param p pointer to the stream -//! \param offset offset in the stream -//! -//! \return pointer to the new 16 bit -//! -//! \brief This function is used for copying received stream to -//! 16 bit in little endian format. -// -//***************************************************************************** - -extern uint16_t STREAM_TO_UINT16_f(char* p, uint16_t offset); - -//***************************************************************************** -// -//! STREAM_TO_UINT32_f -//! -//! \param p pointer to the stream -//! \param offset offset in the stream -//! -//! \return pointer to the new 32 bit -//! -//! \brief This function is used for copying received stream to -//! 32 bit in little endian format. -// -//***************************************************************************** - -extern uint32_t STREAM_TO_UINT32_f(char* p, uint16_t offset); - - -//***************************************************************************** -// -//! cc3k_int_poll -//! -//! \brief checks if the interrupt pin is low -//! just in case the hardware missed a falling edge -//! function is in ccspi.cpp -// -//***************************************************************************** - -extern void cc3k_int_poll(); - - - -//***************************************************************************** -// COMMON MACROs -//***************************************************************************** - - -//This macro is used for copying 8 bit to stream while converting to little endian format. -#define UINT8_TO_STREAM(_p, _val) {*(_p)++ = (_val);} -//This macro is used for copying 16 bit to stream while converting to little endian format. -#define UINT16_TO_STREAM(_p, _u16) (UINT16_TO_STREAM_f(_p, _u16)) -//This macro is used for copying 32 bit to stream while converting to little endian format. -#define UINT32_TO_STREAM(_p, _u32) (UINT32_TO_STREAM_f(_p, _u32)) -//This macro is used for copying a specified value length bits (l) to stream while converting to little endian format. -#define ARRAY_TO_STREAM(p, a, l) {register short _i; for (_i = 0; _i < l; _i++) *(p)++ = ((uint8_t *) a)[_i];} -//This macro is used for copying received stream to 8 bit in little endian format. -#define STREAM_TO_UINT8(_p, _offset, _u8) {_u8 = (uint8_t)(*(_p + _offset));} -//This macro is used for copying received stream to 16 bit in little endian format. -#define STREAM_TO_UINT16(_p, _offset, _u16) {_u16 = STREAM_TO_UINT16_f(_p, _offset);} -//This macro is used for copying received stream to 32 bit in little endian format. -#define STREAM_TO_UINT32(_p, _offset, _u32) {_u32 = STREAM_TO_UINT32_f(_p, _offset);} -#define STREAM_TO_STREAM(p, a, l) {register short _i; for (_i = 0; _i < l; _i++) *(a)++= ((uint8_t *) p)[_i];} - - - - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif // __cplusplus - -#endif // __COMMON_H__ diff --git a/stm/cc3k/ccdebug.h b/stm/cc3k/ccdebug.h deleted file mode 100644 index 6237e1dbe..000000000 --- a/stm/cc3k/ccdebug.h +++ /dev/null @@ -1,56 +0,0 @@ -/**************************************************************************/ -/*! - @file Adafruit_CC3000.cpp - @author KTOWN (Kevin Townsend for Adafruit Industries) - @license BSD (see license.txt) - - This is a library for the Adafruit CC3000 WiFi breakout board - This library works with the Adafruit CC3000 breakout - ----> https://www.adafruit.com/products/1469 - - Check out the links above for our tutorials and wiring diagrams - These chips use SPI to communicate. - - Adafruit invests time and resources providing this open source code, - please support Adafruit and open-source hardware by purchasing - products from Adafruit! - - @section HISTORY - - v1.0 - Initial release -*/ -/**************************************************************************/ - -//#include - -#ifndef _CC3000_DEBUG -#define _CC3000_DEBUG - -#define DEBUG_MODE (0) - -#define PRINT_F(__s) DEBUGPRINT(FLASHIFY(__s)) - -#if (DEBUG_MODE != 0) -#define DEBUGPRINT_F(__s) DEBUGPRINT(FLASHIFY(__s)) -#define DEBUGPRINT_DEC(x) printDec(x) -#define DEBUGPRINT_DEC16(x) printDec16(x) -#define DEBUGPRINT_HEX(x) printHex(x) -#define DEBUGPRINT_HEX16(x) printHex16(x) -#else -#define DEBUGPRINT_F(__s) /* do nothing! */ -#define DEBUGPRINT_DEC(x) -#define DEBUGPRINT_DEC16(x) -#define DEBUGPRINT_HEX(x) -#define DEBUGPRINT_HEX16(x) -#endif - -#if 0 // print debugging info -#define DEBUG_PRINT (1) -#define DEBUG_printf(args...) printf(args) -#else // don't print debugging info -#define DEBUG_printf(args...) (void)0 -#endif - -int printf(const char *fmt, ...); - -#endif diff --git a/stm/cc3k/ccspi.c b/stm/cc3k/ccspi.c deleted file mode 100644 index 5024953b0..000000000 --- a/stm/cc3k/ccspi.c +++ /dev/null @@ -1,737 +0,0 @@ -/***************************************************************************** -* -* spi.c - CC3000 Host Driver Implementation. -* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ -* -* Adapted for use with the Arduino/AVR by KTOWN (Kevin Townsend) -* & Limor Fried for Adafruit Industries -* This library works with the Adafruit CC3000 breakout -* ----> https://www.adafruit.com/products/1469 -* Adafruit invests time and resources providing this open source code, -* please support Adafruit and open-source hardware by purchasing -* products from Adafruit! -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*****************************************************************************/ -#include -#include // for memset - -#include "ccspi.h" -#include "hci.h" -#include "netapp.h" -#include "evnt_handler.h" -#include "cc3000_common.h" -#include "ccdebug.h" -#include "pybcc3k.h" - -extern uint8_t g_csPin, g_irqPin, g_vbatPin, g_IRQnum, g_SPIspeed; - -#define READ (3) -#define WRITE (1) -#define HI(value) (((value) & 0xFF00) >> 8) -#define LO(value) ((value) & 0x00FF) -#define HEADERS_SIZE_EVNT (SPI_HEADER_SIZE + 5) -#define SPI_HEADER_SIZE (5) - -#define eSPI_STATE_POWERUP (0) -#define eSPI_STATE_INITIALIZED (1) -#define eSPI_STATE_IDLE (2) -#define eSPI_STATE_WRITE_IRQ (3) -#define eSPI_STATE_WRITE_FIRST_PORTION (4) -#define eSPI_STATE_WRITE_EOT (5) -#define eSPI_STATE_READ_IRQ (6) -#define eSPI_STATE_READ_FIRST_PORTION (7) -#define eSPI_STATE_READ_EOT (8) - -// CC3000 chip select -#define CC3000_ASSERT_CS() pyb_cc3000_set_cs(0) -// CC3000 chip deselect -#define CC3000_DEASSERT_CS() pyb_cc3000_set_cs(1) - -/* smartconfig flags (defined in Adafruit_CC3000.cpp) */ -// extern unsigned long ulSmartConfigFinished, ulCC3000DHCP; - -typedef struct -{ - gcSpiHandleRx SPIRxHandler; - - unsigned short usTxPacketLength; - unsigned short usRxPacketLength; - unsigned long ulSpiState; - unsigned char *pTxPacket; - unsigned char *pRxPacket; - -} tSpiInformation; - -tSpiInformation sSpiInformation; - -/* Static buffer for 5 bytes of SPI HEADER */ -unsigned char tSpiReadHeader[] = {READ, 0, 0, 0, 0}; - -void SpiWriteDataSynchronous(unsigned char *data, unsigned short size); -void SpiWriteAsync(const unsigned char *data, unsigned short size); -void SpiPauseSpi(void); -void SpiResumeSpi(void); -void SSIContReadOperation(void); -void cc3k_int_poll(void); - -// The magic number that resides at the end of the TX/RX buffer (1 byte after the allocated size) -// for the purpose of detection of the overrun. The location of the memory where the magic number -// resides shall never be written. In case it is written - the overrun occured and either recevie function -// or send function will stuck forever. -#define CC3000_BUFFER_MAGIC_NUMBER (0xDE) - -char spi_buffer[CC3000_RX_BUFFER_SIZE]; -unsigned char wlan_tx_buffer[CC3000_TX_BUFFER_SIZE]; - -static volatile char ccspi_is_in_irq = 0; -static volatile char ccspi_int_enabled = 0; - -/* Mandatory functions are: - - SpiOpen - - SpiWrite - - SpiRead - - SpiClose - - SpiResumeSpi - - ReadWlanInterruptPin - - WlanInterruptEnable - - WlanInterruptDisable - - WriteWlanPin - */ - -void SpiInit(void) -{ - pyb_cc3000_spi_init(); -} - - -/**************************************************************************/ -/*! - - */ -/**************************************************************************/ -void SpiClose(void) -{ - DEBUGPRINT_F("\tCC3000: SpiClose"); - - if (sSpiInformation.pRxPacket) - { - sSpiInformation.pRxPacket = 0; - } - - /* Disable Interrupt in GPIOA module... */ - tSLInformation.WlanInterruptDisable(); -} - -/**************************************************************************/ -/*! - - */ -/**************************************************************************/ -void SpiOpen(gcSpiHandleRx pfRxHandler) -{ - DEBUGPRINT_F("\tCC3000: SpiOpen"); - - sSpiInformation.ulSpiState = eSPI_STATE_POWERUP; - - memset(spi_buffer, 0, sizeof(spi_buffer)); - memset(wlan_tx_buffer, 0, sizeof(spi_buffer)); - - sSpiInformation.SPIRxHandler = pfRxHandler; - sSpiInformation.usTxPacketLength = 0; - sSpiInformation.pTxPacket = NULL; - sSpiInformation.pRxPacket = (unsigned char *)spi_buffer; - sSpiInformation.usRxPacketLength = 0; - - spi_buffer[CC3000_RX_BUFFER_SIZE - 1] = CC3000_BUFFER_MAGIC_NUMBER; - wlan_tx_buffer[CC3000_TX_BUFFER_SIZE - 1] = CC3000_BUFFER_MAGIC_NUMBER; - - /* Enable interrupt on the GPIO pin of WLAN IRQ */ - tSLInformation.WlanInterruptEnable(); - - DEBUGPRINT_F("\tCC3000: Finished SpiOpen\n\r"); -} - -/**************************************************************************/ -/*! - - */ -/**************************************************************************/ -#if 0 -int init_spi(void) -{ - - DEBUGPRINT_F("\tCC3000: init_spi\n\r"); - - /* Set POWER_EN pin to output and disable the CC3000 by default */ - pinMode(g_vbatPin, OUTPUT); - digitalWrite(g_vbatPin, 0); - delay(500); - - /* Set CS pin to output (don't de-assert yet) */ - pinMode(g_csPin, OUTPUT); - - /* Set interrupt/gpio pin to input */ -#if defined(INPUT_PULLUP) - pinMode(g_irqPin, INPUT_PULLUP); -#else - pinMode(g_irqPin, INPUT); - digitalWrite(g_irqPin, HIGH); // w/weak pullup -#endif - - /* Initialise SPI (Mode 1) */ - SPI.begin(); - SPI.setDataMode(SPI_MODE1); - SPI.setBitOrder(MSBFIRST); - SPI.setClockDivider(g_SPIspeed); - - // Newly-initialized SPI is in the same state that ASSERT_CS will set it - // to. Invoke DEASSERT (which also restores SPI registers) so the next - // ASSERT call won't clobber the ccspi_old* values -- we need those! - CC3000_DEASSERT_CS(); - - /* ToDo: Configure IRQ interrupt! */ - - DEBUGPRINT_F("\tCC3000: Finished init_spi\n\r"); - - return(ESUCCESS); -} -#endif - -/**************************************************************************/ -/*! - - */ -/**************************************************************************/ -long SpiFirstWrite(unsigned char *ucBuf, unsigned short usLength) -{ - DEBUGPRINT_F("\tCC3000: SpiWriteFirst\n\r"); - - /* Workaround for the first transaction */ - CC3000_ASSERT_CS(); - - /* delay (stay low) for ~50us */ - pyb_delay_us(50); - - /* SPI writes first 4 bytes of data */ - SpiWriteDataSynchronous(ucBuf, 4); - - pyb_delay_us(50); - - SpiWriteDataSynchronous(ucBuf + 4, usLength - 4); - - /* From this point on - operate in a regular manner */ - sSpiInformation.ulSpiState = eSPI_STATE_IDLE; - - CC3000_DEASSERT_CS(); - - return(0); -} - -/**************************************************************************/ -/*! - - */ -/**************************************************************************/ -long SpiWrite(unsigned char *pUserBuffer, unsigned short usLength) -{ - unsigned char ucPad = 0; - - DEBUGPRINT_F("\tCC3000: SpiWrite\n\r"); - - /* Figure out the total length of the packet in order to figure out if there is padding or not */ - if(!(usLength & 0x0001)) - { - ucPad++; - } - - pUserBuffer[0] = WRITE; - pUserBuffer[1] = HI(usLength + ucPad); - pUserBuffer[2] = LO(usLength + ucPad); - pUserBuffer[3] = 0; - pUserBuffer[4] = 0; - - usLength += (SPI_HEADER_SIZE + ucPad); - - /* The magic number that resides at the end of the TX/RX buffer (1 byte after the allocated size) - * for the purpose of overrun detection. If the magic number is overwritten - buffer overrun - * occurred - and we will be stuck here forever! */ - if (wlan_tx_buffer[CC3000_TX_BUFFER_SIZE - 1] != CC3000_BUFFER_MAGIC_NUMBER) - { - DEBUGPRINT_F("\tCC3000: Error - No magic number found in SpiWrite\n\r"); - while (1); - } - - if (sSpiInformation.ulSpiState == eSPI_STATE_POWERUP) - { - while (sSpiInformation.ulSpiState != eSPI_STATE_INITIALIZED); - } - - if (sSpiInformation.ulSpiState == eSPI_STATE_INITIALIZED) - { - /* This is time for first TX/RX transactions over SPI: the IRQ is down - so need to send read buffer size command */ - SpiFirstWrite(pUserBuffer, usLength); - } - else - { - /* We need to prevent here race that can occur in case two back to back packets are sent to the - * device, so the state will move to IDLE and once again to not IDLE due to IRQ */ - tSLInformation.WlanInterruptDisable(); - - while (sSpiInformation.ulSpiState != eSPI_STATE_IDLE); - - sSpiInformation.ulSpiState = eSPI_STATE_WRITE_IRQ; - sSpiInformation.pTxPacket = pUserBuffer; - sSpiInformation.usTxPacketLength = usLength; - - /* Assert the CS line and wait till SSI IRQ line is active and then initialize write operation */ - CC3000_ASSERT_CS(); - - /* Re-enable IRQ - if it was not disabled - this is not a problem... */ - tSLInformation.WlanInterruptEnable(); - - /* Check for a missing interrupt between the CS assertion and enabling back the interrupts */ - if (tSLInformation.ReadWlanInterruptPin() == 0) - { - SpiWriteDataSynchronous(sSpiInformation.pTxPacket, sSpiInformation.usTxPacketLength); - - sSpiInformation.ulSpiState = eSPI_STATE_IDLE; - - CC3000_DEASSERT_CS(); - } - } - - /* Due to the fact that we are currently implementing a blocking situation - * here we will wait till end of transaction */ - while (eSPI_STATE_IDLE != sSpiInformation.ulSpiState); - - return(0); -} - -/**************************************************************************/ -/*! - - */ -/**************************************************************************/ -void SpiWriteDataSynchronous(unsigned char *data, unsigned short size) -{ - int bSend = 0, bRecv = 0; - while (bSend0 && r>=0) bRecv++; - } - - pyb_delay_us(10); // because of final clock pulse - - DEBUG_printf("SpiWriteDataSynchronous: data=%p size=%u bSend=%d bRecv=%d [%x %x %x %x]\n", data, size, bSend, bRecv, data[0], data[1], data[2], data[3]); -} - -/**************************************************************************/ -/*! - - */ -/**************************************************************************/ -void SpiReadDataSynchronous(unsigned char *data, unsigned short size) -{ - int bSend = 0, bRecv = 0; - while (bSend0 && r>=0) data[bRecv++] = r; - } - - pyb_delay_us(10); // because of final clock pulse - - DEBUG_printf("SpiReadDataSynchronous: data=%p size=%u bSend=%d bRecv=%d [%x %x %x %x]\n", data, size, bSend, bRecv, data[0], data[1], data[2], data[3]); -} - -/**************************************************************************/ -/*! - - */ -/**************************************************************************/ -void SpiReadHeader(void) -{ - DEBUGPRINT_F("\tCC3000: SpiReadHeader\n\r"); - - SpiReadDataSynchronous(sSpiInformation.pRxPacket, HEADERS_SIZE_EVNT); -} - -/**************************************************************************/ -/*! - - */ -/**************************************************************************/ -long SpiReadDataCont(void) -{ - long data_to_recv; - unsigned char *evnt_buff, type; - - DEBUGPRINT_F("\tCC3000: SpiReadDataCont\n\r"); - - /* Determine what type of packet we have */ - evnt_buff = sSpiInformation.pRxPacket; - data_to_recv = 0; - STREAM_TO_UINT8((uint8_t *)(evnt_buff + SPI_HEADER_SIZE), HCI_PACKET_TYPE_OFFSET, type); - - switch(type) - { - case HCI_TYPE_DATA: - { - /* We need to read the rest of data.. */ - STREAM_TO_UINT16((char *)(evnt_buff + SPI_HEADER_SIZE), HCI_DATA_LENGTH_OFFSET, data_to_recv); - if (!((HEADERS_SIZE_EVNT + data_to_recv) & 1)) - { - data_to_recv++; - } - - if (data_to_recv) - { - SpiReadDataSynchronous(evnt_buff + HEADERS_SIZE_EVNT, data_to_recv); - } - break; - } - case HCI_TYPE_EVNT: - { - /* Calculate the rest length of the data */ - STREAM_TO_UINT8((char *)(evnt_buff + SPI_HEADER_SIZE), HCI_EVENT_LENGTH_OFFSET, data_to_recv); - data_to_recv -= 1; - - /* Add padding byte if needed */ - if ((HEADERS_SIZE_EVNT + data_to_recv) & 1) - { - data_to_recv++; - } - - if (data_to_recv) - { - SpiReadDataSynchronous(evnt_buff + HEADERS_SIZE_EVNT, data_to_recv); - } - - sSpiInformation.ulSpiState = eSPI_STATE_READ_EOT; - break; - } - } - - return (0); -} - -/**************************************************************************/ -/*! - - */ -/**************************************************************************/ -void SpiPauseSpi(void) -{ - DEBUGPRINT_F("\tCC3000: SpiPauseSpi\n\r"); - - ccspi_int_enabled = 0; - pyb_cc3000_pause_spi(); -} - -/**************************************************************************/ -/*! - - */ -/**************************************************************************/ -void SpiResumeSpi(void) -{ - DEBUGPRINT_F("\tCC3000: SpiResumeSpi\n\r"); - - ccspi_int_enabled = 1; - pyb_cc3000_resume_spi(); -} - -/**************************************************************************/ -/*! - - */ -/**************************************************************************/ -void SpiTriggerRxProcessing(void) -{ - DEBUGPRINT_F("\tCC3000: SpiTriggerRxProcessing\n\r"); - - /* Trigger Rx processing */ - SpiPauseSpi(); - CC3000_DEASSERT_CS(); - - //DEBUGPRINT_F("Magic?\n\r"); - /* The magic number that resides at the end of the TX/RX buffer (1 byte after the allocated size) - * for the purpose of detection of the overrun. If the magic number is overriten - buffer overrun - * occurred - and we will stuck here forever! */ - if (sSpiInformation.pRxPacket[CC3000_RX_BUFFER_SIZE - 1] != CC3000_BUFFER_MAGIC_NUMBER) - { - /* You've got problems if you're here! */ - DEBUGPRINT_F("\tCC3000: ERROR - magic number missing!\n\r"); - while (1); - } - - //DEBUGPRINT_F("OK!\n\r"); - sSpiInformation.ulSpiState = eSPI_STATE_IDLE; - sSpiInformation.SPIRxHandler(sSpiInformation.pRxPacket + SPI_HEADER_SIZE); -} - -/**************************************************************************/ -/*! - - */ -/**************************************************************************/ -void SSIContReadOperation(void) -{ - DEBUGPRINT_F("\tCC3000: SpiContReadOperation\n\r"); - - /* The header was read - continue with the payload read */ - if (!SpiReadDataCont()) - { - /* All the data was read - finalize handling by switching to teh task - * and calling from task Event Handler */ - //DEBUGPRINT_F("SPItrig\n\r"); - SpiTriggerRxProcessing(); - } -} - -/**************************************************************************/ -/*! - - */ -/**************************************************************************/ -void WriteWlanPin( unsigned char val ) -{ -#if 0 - if (DEBUG_MODE) - { - DEBUGPRINT_F("\tCC3000: WriteWlanPin - "); - DEBUGPRINT_DEC(val); - DEBUGPRINT_F("\n\r"); - delay(1); - } - if (val) - { - digitalWrite(g_vbatPin, HIGH); - } - else - { - digitalWrite(g_vbatPin, LOW); - } -#endif - pyb_cc3000_set_en(val == WLAN_ENABLE); -} - -/**************************************************************************/ -/*! - - */ -/**************************************************************************/ -long ReadWlanInterruptPin(void) -{ - DEBUGPRINT_F("\tCC3000: ReadWlanInterruptPin - "); - DEBUGPRINT_DEC(digitalRead(g_irqPin)); - DEBUGPRINT_F("\n\r"); - - return pyb_cc3000_get_irq(); -} - -/**************************************************************************/ -/*! - - */ -/**************************************************************************/ -void WlanInterruptEnable() -{ - DEBUGPRINT_F("\tCC3000: WlanInterruptEnable.\n\r"); - // delay(100); - ccspi_int_enabled = 1; - pyb_cc3000_enable_irq(); -} - -/**************************************************************************/ -/*! - - */ -/**************************************************************************/ -void WlanInterruptDisable() -{ - DEBUGPRINT_F("\tCC3000: WlanInterruptDisable\n\r"); - ccspi_int_enabled = 0; - pyb_cc3000_disable_irq(); -} - -//***************************************************************************** -// -//! sendDriverPatch -//! -//! @param pointer to the length -//! -//! @return none -//! -//! @brief The function returns a pointer to the driver patch: -//! since there is no patch in the host - it returns 0 -// -//***************************************************************************** -char *sendDriverPatch(unsigned long *Length) { - *Length = 0; - return NULL; -} - -//***************************************************************************** -// -//! sendBootLoaderPatch -//! -//! @param pointer to the length -//! -//! @return none -//! -//! @brief The function returns a pointer to the boot loader patch: -//! since there is no patch in the host - it returns 0 -// -//***************************************************************************** -char *sendBootLoaderPatch(unsigned long *Length) { - *Length = 0; - return NULL; -} - -//***************************************************************************** -// -//! sendWLFWPatch -//! -//! @param pointer to the length -//! -//! @return none -//! -//! @brief The function returns a pointer to the FW patch: -//! since there is no patch in the host - it returns 0 -// -//***************************************************************************** -char *sendWLFWPatch(unsigned long *Length) { - *Length = 0; - return NULL; -} - - -/**************************************************************************/ -/*! - - */ -/**************************************************************************/ - -void SpiIntGPIOHandler(void) -{ - DEBUG_printf("SpiIntGPIOHandler\n"); - - ccspi_is_in_irq = 1; - - if (sSpiInformation.ulSpiState == eSPI_STATE_POWERUP) - { - //This means IRQ line was low call a callback of HCI Layer to inform - //on event - sSpiInformation.ulSpiState = eSPI_STATE_INITIALIZED; - } - else if (sSpiInformation.ulSpiState == eSPI_STATE_IDLE) - { - sSpiInformation.ulSpiState = eSPI_STATE_READ_IRQ; - - /* IRQ line goes down - we are start reception */ - CC3000_ASSERT_CS(); - - // Wait for TX/RX Compete which will come as DMA interrupt - SpiReadHeader(); - - sSpiInformation.ulSpiState = eSPI_STATE_READ_EOT; - - SSIContReadOperation(); - } - else if (sSpiInformation.ulSpiState == eSPI_STATE_WRITE_IRQ) - { - SpiWriteDataSynchronous(sSpiInformation.pTxPacket, sSpiInformation.usTxPacketLength); - - sSpiInformation.ulSpiState = eSPI_STATE_IDLE; - - CC3000_DEASSERT_CS(); - } - ccspi_is_in_irq = 0; -} - -#if 0 -void SPI_IRQ(void) -{ - ccspi_is_in_irq = 1; - - DEBUGPRINT_F("\tCC3000: Entering SPI_IRQ\n\r"); - - if (sSpiInformation.ulSpiState == eSPI_STATE_POWERUP) - { - /* IRQ line was low ... perform a callback on the HCI Layer */ - sSpiInformation.ulSpiState = eSPI_STATE_INITIALIZED; - } - else if (sSpiInformation.ulSpiState == eSPI_STATE_IDLE) - { - //DEBUGPRINT_F("IDLE\n\r"); - sSpiInformation.ulSpiState = eSPI_STATE_READ_IRQ; - /* IRQ line goes down - start reception */ - - CC3000_ASSERT_CS(); - - // Wait for TX/RX Compete which will come as DMA interrupt - SpiReadHeader(); - sSpiInformation.ulSpiState = eSPI_STATE_READ_EOT; - //DEBUGPRINT_F("SSICont\n\r"); - SSIContReadOperation(); - } - else if (sSpiInformation.ulSpiState == eSPI_STATE_WRITE_IRQ) - { - SpiWriteDataSynchronous(sSpiInformation.pTxPacket, sSpiInformation.usTxPacketLength); - sSpiInformation.ulSpiState = eSPI_STATE_IDLE; - CC3000_DEASSERT_CS(); - } - - DEBUGPRINT_F("\tCC3000: Leaving SPI_IRQ\n\r"); - - ccspi_is_in_irq = 0; - return; -} -#endif - -//***************************************************************************** -// -//! cc3k_int_poll -//! -//! \brief checks if the interrupt pin is low -//! just in case the hardware missed a falling edge -//! function is in ccspi.cpp -// -//***************************************************************************** - -void cc3k_int_poll() -{ - if (pyb_cc3000_get_irq() == 0 && ccspi_is_in_irq == 0 && ccspi_int_enabled != 0) { - SpiIntGPIOHandler(); - } -} diff --git a/stm/cc3k/ccspi.h b/stm/cc3k/ccspi.h deleted file mode 100644 index 70805ec38..000000000 --- a/stm/cc3k/ccspi.h +++ /dev/null @@ -1,83 +0,0 @@ -/***************************************************************************** -* -* spi.h - CC3000 Host Driver Implementation. -* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ -* -* Adapted for use with the Arduino/AVR by KTOWN (Kevin Townsend) -* & Limor Fried for Adafruit Industries -* This library works with the Adafruit CC3000 breakout -* ----> https://www.adafruit.com/products/1469 -* Adafruit invests time and resources providing this open source code, -* please support Adafruit and open-source hardware by purchasing -* products from Adafruit! -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*****************************************************************************/ - - -#ifndef __SPI_H__ -#define __SPI_H__ - -//#include -//#include -//#include - -//#include "wlan.h" - -typedef void (*gcSpiHandleRx)(void *p); -typedef void (*gcSpiHandleTx)(void); - -extern unsigned char wlan_tx_buffer[]; - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void SpiInit(void); -extern void SpiOpen(gcSpiHandleRx pfRxHandler); -extern void SpiClose(void); -extern long SpiWrite(unsigned char *pUserBuffer, unsigned short usLength); -extern void SpiResumeSpi(void); -extern void SpiCleanGPIOISR(void); -extern long TXBufferIsEmpty(void); -extern long RXBufferIsEmpty(void); -extern void CC3000_UsynchCallback(long lEventType, char * data, unsigned char length); -extern void WriteWlanPin( unsigned char val ); -extern long ReadWlanInterruptPin(void); -extern void WlanInterruptEnable(); -extern void WlanInterruptDisable(); -extern char *sendDriverPatch(unsigned long *Length); -extern char *sendBootLoaderPatch(unsigned long *Length); -extern char *sendWLFWPatch(unsigned long *Length); -extern void SpiIntGPIOHandler(void); - -#endif - diff --git a/stm/cc3k/evnt_handler.c b/stm/cc3k/evnt_handler.c deleted file mode 100644 index 5a75fadcc..000000000 --- a/stm/cc3k/evnt_handler.c +++ /dev/null @@ -1,873 +0,0 @@ -/***************************************************************************** -* -* evnt_handler.c - CC3000 Host Driver Implementation. -* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ -* -* Adapted for use with the Arduino/AVR by KTOWN (Kevin Townsend) -* & Limor Fried for Adafruit Industries -* This library works with the Adafruit CC3000 breakout -* ----> https://www.adafruit.com/products/1469 -* Adafruit invests time and resources providing this open source code, -* please support Adafruit and open-source hardware by purchasing -* products from Adafruit! -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*****************************************************************************/ -//***************************************************************************** -// -//! \addtogroup evnt_handler_api -//! @{ -// -//****************************************************************************** - -//****************************************************************************** -// INCLUDE FILES -//****************************************************************************** - -#include - -#include "cc3000_common.h" -#include "string.h" -#include "hci.h" -#include "evnt_handler.h" -#include "wlan.h" -#include "socket.h" -#include "netapp.h" -#include "ccspi.h" -#include "ccdebug.h" - - - -//***************************************************************************** -// COMMON DEFINES -//***************************************************************************** - -#define FLOW_CONTROL_EVENT_HANDLE_OFFSET (0) -#define FLOW_CONTROL_EVENT_BLOCK_MODE_OFFSET (1) -#define FLOW_CONTROL_EVENT_FREE_BUFFS_OFFSET (2) -#define FLOW_CONTROL_EVENT_SIZE (4) - -#define BSD_RSP_PARAMS_SOCKET_OFFSET (0) -#define BSD_RSP_PARAMS_STATUS_OFFSET (4) - -#define GET_HOST_BY_NAME_RETVAL_OFFSET (0) -#define GET_HOST_BY_NAME_ADDR_OFFSET (4) - -#define ACCEPT_SD_OFFSET (0) -#define ACCEPT_RETURN_STATUS_OFFSET (4) -#define ACCEPT_ADDRESS__OFFSET (8) - -#define SL_RECEIVE_SD_OFFSET (0) -#define SL_RECEIVE_NUM_BYTES_OFFSET (4) -#define SL_RECEIVE__FLAGS__OFFSET (8) - - -#define SELECT_STATUS_OFFSET (0) -#define SELECT_READFD_OFFSET (4) -#define SELECT_WRITEFD_OFFSET (8) -#define SELECT_EXFD_OFFSET (12) - - -#define NETAPP_IPCONFIG_IP_OFFSET (0) -#define NETAPP_IPCONFIG_SUBNET_OFFSET (4) -#define NETAPP_IPCONFIG_GW_OFFSET (8) -#define NETAPP_IPCONFIG_DHCP_OFFSET (12) -#define NETAPP_IPCONFIG_DNS_OFFSET (16) -#define NETAPP_IPCONFIG_MAC_OFFSET (20) -#define NETAPP_IPCONFIG_SSID_OFFSET (26) - -#define NETAPP_IPCONFIG_IP_LENGTH (4) -#define NETAPP_IPCONFIG_MAC_LENGTH (6) -#define NETAPP_IPCONFIG_SSID_LENGTH (32) - - -#define NETAPP_PING_PACKETS_SENT_OFFSET (0) -#define NETAPP_PING_PACKETS_RCVD_OFFSET (4) -#define NETAPP_PING_MIN_RTT_OFFSET (8) -#define NETAPP_PING_MAX_RTT_OFFSET (12) -#define NETAPP_PING_AVG_RTT_OFFSET (16) - -#define GET_SCAN_RESULTS_TABlE_COUNT_OFFSET (0) -#define GET_SCAN_RESULTS_SCANRESULT_STATUS_OFFSET (4) -#define GET_SCAN_RESULTS_ISVALID_TO_SSIDLEN_OFFSET (8) -#define GET_SCAN_RESULTS_FRAME_TIME_OFFSET (10) -#define GET_SCAN_RESULTS_SSID_MAC_LENGTH (38) - - - -//***************************************************************************** -// GLOBAL VARAIABLES -//***************************************************************************** - -unsigned long socket_active_status = SOCKET_STATUS_INIT_VAL; - - -//***************************************************************************** -// Prototypes for the static functions -//***************************************************************************** - -static long hci_event_unsol_flowcontrol_handler(char *pEvent); - -static void update_socket_active_status(char *resp_params); - - -//***************************************************************************** -// -//! hci_unsol_handle_patch_request -//! -//! @param event_hdr event header -//! -//! @return none -//! -//! @brief Handle unsolicited event from type patch request -// -//***************************************************************************** -void hci_unsol_handle_patch_request(char *event_hdr) -{ - char *params = (char *)(event_hdr) + HCI_EVENT_HEADER_SIZE; - unsigned long ucLength = 0; - char *patch; - - switch (*params) - { - case HCI_EVENT_PATCHES_DRV_REQ: - - if (tSLInformation.sDriverPatches) - { - patch = tSLInformation.sDriverPatches(&ucLength); - - if (patch) - { - hci_patch_send(HCI_EVENT_PATCHES_DRV_REQ, - tSLInformation.pucTxCommandBuffer, patch, ucLength); - return; - } - } - - // Send 0 length Patches response event - hci_patch_send(HCI_EVENT_PATCHES_DRV_REQ, - tSLInformation.pucTxCommandBuffer, 0, 0); - break; - - case HCI_EVENT_PATCHES_FW_REQ: - - if (tSLInformation.sFWPatches) - { - patch = tSLInformation.sFWPatches(&ucLength); - - // Build and send a patch - if (patch) - { - hci_patch_send(HCI_EVENT_PATCHES_FW_REQ, - tSLInformation.pucTxCommandBuffer, patch, ucLength); - return; - } - } - - // Send 0 length Patches response event - hci_patch_send(HCI_EVENT_PATCHES_FW_REQ, - tSLInformation.pucTxCommandBuffer, 0, 0); - break; - - case HCI_EVENT_PATCHES_BOOTLOAD_REQ: - - if (tSLInformation.sBootLoaderPatches) - { - patch = tSLInformation.sBootLoaderPatches(&ucLength); - - if (patch) - { - hci_patch_send(HCI_EVENT_PATCHES_BOOTLOAD_REQ, - tSLInformation.pucTxCommandBuffer, patch, ucLength); - return; - } - } - - // Send 0 length Patches response event - hci_patch_send(HCI_EVENT_PATCHES_BOOTLOAD_REQ, - tSLInformation.pucTxCommandBuffer, 0, 0); - break; - } -} - - - -//***************************************************************************** -// -//! hci_event_handler -//! -//! @param pRetParams incoming data buffer -//! @param from from information (in case of data received) -//! @param fromlen from information length (in case of data received) -//! -//! @return none -//! -//! @brief Parse the incoming events packets and issues corresponding -//! event handler from global array of handlers pointers -// -//***************************************************************************** - - -unsigned char * -hci_event_handler(void *pRetParams, unsigned char *from, unsigned char *fromlen) -{ - unsigned char *pucReceivedData, ucArgsize; - unsigned short usLength; - unsigned char *pucReceivedParams; - unsigned short usReceivedEventOpcode = 0; - unsigned long retValue32; - unsigned char * RecvParams; - unsigned char *RetParams; - - while (1) - { - cc3k_int_poll(); - - if (tSLInformation.usEventOrDataReceived != 0) - { - - pucReceivedData = (tSLInformation.pucReceivedData); - - if (*pucReceivedData == HCI_TYPE_EVNT) - { - // Event Received - STREAM_TO_UINT16((char *)pucReceivedData, - HCI_EVENT_OPCODE_OFFSET, - usReceivedEventOpcode); - pucReceivedParams = pucReceivedData + HCI_EVENT_HEADER_SIZE; - RecvParams = pucReceivedParams; - RetParams = (unsigned char *)pRetParams; - - // In case unsolicited event received - here the handling finished - if (hci_unsol_event_handler((char *)pucReceivedData) == 0) - { - STREAM_TO_UINT8(pucReceivedData, HCI_DATA_LENGTH_OFFSET, usLength); - - switch(usReceivedEventOpcode) - { - case HCI_CMND_READ_BUFFER_SIZE: - { - STREAM_TO_UINT8((char *)pucReceivedParams, 0, - tSLInformation.usNumberOfFreeBuffers); - STREAM_TO_UINT16((char *)pucReceivedParams, 1, - tSLInformation.usSlBufferLength); - } - break; - - case HCI_CMND_WLAN_CONFIGURE_PATCH: - case HCI_NETAPP_DHCP: - case HCI_NETAPP_PING_SEND: - case HCI_NETAPP_PING_STOP: - case HCI_NETAPP_ARP_FLUSH: - case HCI_NETAPP_SET_DEBUG_LEVEL: - case HCI_NETAPP_SET_TIMERS: - case HCI_EVNT_NVMEM_READ: - case HCI_EVNT_NVMEM_CREATE_ENTRY: - case HCI_CMND_NVMEM_WRITE_PATCH: - case HCI_NETAPP_PING_REPORT: - case HCI_EVNT_MDNS_ADVERTISE: - - STREAM_TO_UINT8(pucReceivedData, HCI_EVENT_STATUS_OFFSET - ,*(unsigned char *)pRetParams); - break; - - case HCI_CMND_SETSOCKOPT: - case HCI_CMND_WLAN_CONNECT: - case HCI_CMND_WLAN_IOCTL_STATUSGET: - case HCI_EVNT_WLAN_IOCTL_ADD_PROFILE: - case HCI_CMND_WLAN_IOCTL_DEL_PROFILE: - case HCI_CMND_WLAN_IOCTL_SET_CONNECTION_POLICY: - case HCI_CMND_WLAN_IOCTL_SET_SCANPARAM: - case HCI_CMND_WLAN_IOCTL_SIMPLE_CONFIG_START: - case HCI_CMND_WLAN_IOCTL_SIMPLE_CONFIG_STOP: - case HCI_CMND_WLAN_IOCTL_SIMPLE_CONFIG_SET_PREFIX: - case HCI_CMND_EVENT_MASK: - case HCI_EVNT_WLAN_DISCONNECT: - case HCI_EVNT_SOCKET: - case HCI_EVNT_BIND: - case HCI_CMND_LISTEN: - case HCI_EVNT_CLOSE_SOCKET: - case HCI_EVNT_CONNECT: - case HCI_EVNT_NVMEM_WRITE: - - STREAM_TO_UINT32((char *)pucReceivedParams,0 - ,*(unsigned long *)pRetParams); - break; - - case HCI_EVNT_READ_SP_VERSION: - - STREAM_TO_UINT8(pucReceivedData, HCI_EVENT_STATUS_OFFSET - ,*(unsigned char *)pRetParams); - pRetParams = ((char *)pRetParams) + 1; - STREAM_TO_UINT32((char *)pucReceivedParams, 0, retValue32); - UINT32_TO_STREAM((unsigned char *)pRetParams, retValue32); - break; - - case HCI_EVNT_BSD_GETHOSTBYNAME: - - STREAM_TO_UINT32((char *)pucReceivedParams - ,GET_HOST_BY_NAME_RETVAL_OFFSET,*(unsigned long *)pRetParams); - pRetParams = ((char *)pRetParams) + 4; - STREAM_TO_UINT32((char *)pucReceivedParams - ,GET_HOST_BY_NAME_ADDR_OFFSET,*(unsigned long *)pRetParams); - break; - - case HCI_EVNT_ACCEPT: - { - STREAM_TO_UINT32((char *)pucReceivedParams,ACCEPT_SD_OFFSET - ,*(unsigned long *)pRetParams); - pRetParams = ((char *)pRetParams) + 4; - STREAM_TO_UINT32((char *)pucReceivedParams - ,ACCEPT_RETURN_STATUS_OFFSET,*(unsigned long *)pRetParams); - pRetParams = ((char *)pRetParams) + 4; - - //This argument returns in network order - memcpy((unsigned char *)pRetParams, - pucReceivedParams + ACCEPT_ADDRESS__OFFSET, sizeof(sockaddr)); - break; - } - - case HCI_EVNT_RECV: - case HCI_EVNT_RECVFROM: - { - STREAM_TO_UINT32((char *)pucReceivedParams,SL_RECEIVE_SD_OFFSET ,*(unsigned long *)pRetParams); - pRetParams = ((char *)pRetParams) + 4; - STREAM_TO_UINT32((char *)pucReceivedParams,SL_RECEIVE_NUM_BYTES_OFFSET,*(unsigned long *)pRetParams); - pRetParams = ((char *)pRetParams) + 4; - STREAM_TO_UINT32((char *)pucReceivedParams,SL_RECEIVE__FLAGS__OFFSET,*(unsigned long *)pRetParams); - //tBsdReadReturnParams *tread = (tBsdReadReturnParams *)pRetParams; // unused - if(((tBsdReadReturnParams *)pRetParams)->iNumberOfBytes == ERROR_SOCKET_INACTIVE) - { - set_socket_active_status(((tBsdReadReturnParams *)pRetParams)->iSocketDescriptor,SOCKET_STATUS_INACTIVE); - } - break; - } - - case HCI_EVNT_SEND: - case HCI_EVNT_SENDTO: - { - STREAM_TO_UINT32((char *)pucReceivedParams,SL_RECEIVE_SD_OFFSET ,*(unsigned long *)pRetParams); - pRetParams = ((char *)pRetParams) + 4; - STREAM_TO_UINT32((char *)pucReceivedParams,SL_RECEIVE_NUM_BYTES_OFFSET,*(unsigned long *)pRetParams); - pRetParams = ((char *)pRetParams) + 4; - - break; - } - - case HCI_EVNT_SELECT: - { - STREAM_TO_UINT32((char *)pucReceivedParams,SELECT_STATUS_OFFSET,*(unsigned long *)pRetParams); - pRetParams = ((char *)pRetParams) + 4; - STREAM_TO_UINT32((char *)pucReceivedParams,SELECT_READFD_OFFSET,*(unsigned long *)pRetParams); - pRetParams = ((char *)pRetParams) + 4; - STREAM_TO_UINT32((char *)pucReceivedParams,SELECT_WRITEFD_OFFSET,*(unsigned long *)pRetParams); - pRetParams = ((char *)pRetParams) + 4; - STREAM_TO_UINT32((char *)pucReceivedParams,SELECT_EXFD_OFFSET,*(unsigned long *)pRetParams); - break; - } - - case HCI_CMND_GETSOCKOPT: - - STREAM_TO_UINT8(pucReceivedData, HCI_EVENT_STATUS_OFFSET,((tBsdGetSockOptReturnParams *)pRetParams)->iStatus); - //This argument returns in network order - memcpy((unsigned char *)pRetParams, pucReceivedParams, 4); - break; - - case HCI_CMND_WLAN_IOCTL_GET_SCAN_RESULTS: - - STREAM_TO_UINT32((char *)pucReceivedParams,GET_SCAN_RESULTS_TABlE_COUNT_OFFSET,*(unsigned long *)pRetParams); - pRetParams = ((char *)pRetParams) + 4; - STREAM_TO_UINT32((char *)pucReceivedParams,GET_SCAN_RESULTS_SCANRESULT_STATUS_OFFSET,*(unsigned long *)pRetParams); - pRetParams = ((char *)pRetParams) + 4; - STREAM_TO_UINT16((char *)pucReceivedParams,GET_SCAN_RESULTS_ISVALID_TO_SSIDLEN_OFFSET,*(unsigned long *)pRetParams); - pRetParams = ((char *)pRetParams) + 2; - STREAM_TO_UINT16((char *)pucReceivedParams,GET_SCAN_RESULTS_FRAME_TIME_OFFSET,*(unsigned long *)pRetParams); - pRetParams = ((char *)pRetParams) + 2; - memcpy((unsigned char *)pRetParams, (char *)(pucReceivedParams + GET_SCAN_RESULTS_FRAME_TIME_OFFSET + 2), GET_SCAN_RESULTS_SSID_MAC_LENGTH); - break; - - case HCI_CMND_SIMPLE_LINK_START: - break; - - case HCI_NETAPP_IPCONFIG: - - //Read IP address - STREAM_TO_STREAM(RecvParams,RetParams,NETAPP_IPCONFIG_IP_LENGTH); - RecvParams += 4; - - //Read subnet - STREAM_TO_STREAM(RecvParams,RetParams,NETAPP_IPCONFIG_IP_LENGTH); - RecvParams += 4; - - //Read default GW - STREAM_TO_STREAM(RecvParams,RetParams,NETAPP_IPCONFIG_IP_LENGTH); - RecvParams += 4; - - //Read DHCP server - STREAM_TO_STREAM(RecvParams,RetParams,NETAPP_IPCONFIG_IP_LENGTH); - RecvParams += 4; - - //Read DNS server - STREAM_TO_STREAM(RecvParams,RetParams,NETAPP_IPCONFIG_IP_LENGTH); - RecvParams += 4; - - //Read Mac address - STREAM_TO_STREAM(RecvParams,RetParams,NETAPP_IPCONFIG_MAC_LENGTH); - RecvParams += 6; - - //Read SSID - STREAM_TO_STREAM(RecvParams,RetParams,NETAPP_IPCONFIG_SSID_LENGTH); - - } - } - - if (usReceivedEventOpcode == tSLInformation.usRxEventOpcode) - { - tSLInformation.usRxEventOpcode = 0; - } - } - else - { - pucReceivedParams = pucReceivedData; - STREAM_TO_UINT8((char *)pucReceivedData, HCI_PACKET_ARGSIZE_OFFSET, ucArgsize); - - STREAM_TO_UINT16((char *)pucReceivedData, HCI_PACKET_LENGTH_OFFSET, usLength); - - // Data received: note that the only case where from and from length - // are not null is in recv from, so fill the args accordingly - if (from) - { - STREAM_TO_UINT32((char *)(pucReceivedData + HCI_DATA_HEADER_SIZE), BSD_RECV_FROM_FROMLEN_OFFSET, *(unsigned long *)fromlen); - memcpy(from, (pucReceivedData + HCI_DATA_HEADER_SIZE + BSD_RECV_FROM_FROM_OFFSET) ,*fromlen); - } - - memcpy(pRetParams, pucReceivedParams + HCI_DATA_HEADER_SIZE + ucArgsize, - usLength - ucArgsize); - - tSLInformation.usRxDataPending = 0; - } - - tSLInformation.usEventOrDataReceived = 0; - - SpiResumeSpi(); - - // Since we are going to TX - we need to handle this event after the - // ResumeSPi since we need interrupts - if ((*pucReceivedData == HCI_TYPE_EVNT) && - (usReceivedEventOpcode == HCI_EVNT_PATCHES_REQ)) - { - hci_unsol_handle_patch_request((char *)pucReceivedData); - } - - if ((tSLInformation.usRxEventOpcode == 0) && (tSLInformation.usRxDataPending == 0)) - { - return NULL; - } - } - } - -} - -//***************************************************************************** -// -//! hci_unsol_event_handler -//! -//! @param event_hdr event header -//! -//! @return 1 if event supported and handled -//! 0 if event is not supported -//! -//! @brief Handle unsolicited events -// -//***************************************************************************** -long -hci_unsol_event_handler(char *event_hdr) -{ - char * data = NULL; - long event_type; - unsigned long NumberOfReleasedPackets; - unsigned long NumberOfSentPackets; - - STREAM_TO_UINT16(event_hdr, HCI_EVENT_OPCODE_OFFSET,event_type); - - DEBUGPRINT_F("\tHCI_UNSOL_EVT: "); - DEBUGPRINT_HEX16(event_type); - - if (event_type & HCI_EVNT_UNSOL_BASE) - { - switch(event_type) - { - - case HCI_EVNT_DATA_UNSOL_FREE_BUFF: - { - hci_event_unsol_flowcontrol_handler(event_hdr); - - NumberOfReleasedPackets = tSLInformation.NumberOfReleasedPackets; - NumberOfSentPackets = tSLInformation.NumberOfSentPackets; - - if (NumberOfReleasedPackets == NumberOfSentPackets) - { - if (tSLInformation.InformHostOnTxComplete) - { - tSLInformation.sWlanCB(HCI_EVENT_CC3000_CAN_SHUT_DOWN, NULL, 0); - } - } - return 1; - - } - } - } - - if(event_type & HCI_EVNT_WLAN_UNSOL_BASE) - { - switch(event_type) - { - case HCI_EVNT_WLAN_KEEPALIVE: - case HCI_EVNT_WLAN_UNSOL_CONNECT: - case HCI_EVNT_WLAN_UNSOL_DISCONNECT: - case HCI_EVNT_WLAN_UNSOL_INIT: - case HCI_EVNT_WLAN_ASYNC_SIMPLE_CONFIG_DONE: - - if( tSLInformation.sWlanCB ) - { - tSLInformation.sWlanCB(event_type, 0, 0); - } - break; - - case HCI_EVNT_WLAN_UNSOL_DHCP: - { - unsigned char params[NETAPP_IPCONFIG_MAC_OFFSET + 1]; // extra byte is for the status - unsigned char *recParams = params; - - data = (char*)(event_hdr) + HCI_EVENT_HEADER_SIZE; - - //Read IP address - STREAM_TO_STREAM(data,recParams,NETAPP_IPCONFIG_IP_LENGTH); - data += 4; - //Read subnet - STREAM_TO_STREAM(data,recParams,NETAPP_IPCONFIG_IP_LENGTH); - data += 4; - //Read default GW - STREAM_TO_STREAM(data,recParams,NETAPP_IPCONFIG_IP_LENGTH); - data += 4; - //Read DHCP server - STREAM_TO_STREAM(data,recParams,NETAPP_IPCONFIG_IP_LENGTH); - data += 4; - //Read DNS server - STREAM_TO_STREAM(data,recParams,NETAPP_IPCONFIG_IP_LENGTH); - // read the status - STREAM_TO_UINT8(event_hdr, HCI_EVENT_STATUS_OFFSET, *recParams); - - - if( tSLInformation.sWlanCB ) - { - tSLInformation.sWlanCB(event_type, (char *)params, sizeof(params)); - } - } - break; - - case HCI_EVNT_WLAN_ASYNC_PING_REPORT: - { - netapp_pingreport_args_t params; - data = (char*)(event_hdr) + HCI_EVENT_HEADER_SIZE; - STREAM_TO_UINT32(data, NETAPP_PING_PACKETS_SENT_OFFSET, params.packets_sent); - STREAM_TO_UINT32(data, NETAPP_PING_PACKETS_RCVD_OFFSET, params.packets_received); - STREAM_TO_UINT32(data, NETAPP_PING_MIN_RTT_OFFSET, params.min_round_time); - STREAM_TO_UINT32(data, NETAPP_PING_MAX_RTT_OFFSET, params.max_round_time); - STREAM_TO_UINT32(data, NETAPP_PING_AVG_RTT_OFFSET, params.avg_round_time); - - if( tSLInformation.sWlanCB ) - { - tSLInformation.sWlanCB(event_type, (char *)¶ms, sizeof(params)); - } - } - break; - case HCI_EVNT_BSD_TCP_CLOSE_WAIT: - { - DEBUGPRINT_F("\tTCP Close Wait\n\r"); - uint8_t socketnum; - data = (char*)(event_hdr) + HCI_EVENT_HEADER_SIZE; - /* - printHex(data[0]); PRINT_F("\t"); - printHex(data[1]); PRINT_F("\t"); - printHex(data[2]); PRINT_F("\t"); - printHex(data[3]); PRINT_F("\t"); - printHex(data[4]); PRINT_F("\t"); - printHex(data[5]); PRINT_F("\t"); - */ - socketnum = data[0]; - //STREAM_TO_UINT16(data, 0, socketnum); - if( tSLInformation.sWlanCB ) - { - tSLInformation.sWlanCB(event_type, (char *)&socketnum, 1); - } - } - break; - - //'default' case which means "event not supported" - default: - return (0); - } - return(1); - } - - if ((event_type == HCI_EVNT_SEND) || (event_type == HCI_EVNT_SENDTO) - || (event_type == HCI_EVNT_WRITE)) - { - char *pArg; - long status; - - DEBUGPRINT_F("\tSEND event response\n\r"); - - pArg = M_BSD_RESP_PARAMS_OFFSET(event_hdr); - STREAM_TO_UINT32(pArg, BSD_RSP_PARAMS_STATUS_OFFSET,status); - - if (ERROR_SOCKET_INACTIVE == status) - { - // The only synchronous event that can come from SL device in form of - // command complete is "Command Complete" on data sent, in case SL device - // was unable to transmit - STREAM_TO_UINT8(event_hdr, HCI_EVENT_STATUS_OFFSET, tSLInformation.slTransmitDataError); - update_socket_active_status(M_BSD_RESP_PARAMS_OFFSET(event_hdr)); - - return (1); - } - else - return (0); - } - - return(0); -} - -//***************************************************************************** -// -//! hci_unsolicited_event_handler -//! -//! @param None -//! -//! @return ESUCCESS if successful, EFAIL if an error occurred -//! -//! @brief Parse the incoming unsolicited event packets and issues -//! corresponding event handler. -// -//***************************************************************************** -long -hci_unsolicited_event_handler(void) -{ - unsigned long res = 0; - unsigned char *pucReceivedData; - - if (tSLInformation.usEventOrDataReceived != 0) - { - pucReceivedData = (tSLInformation.pucReceivedData); - - if (*pucReceivedData == HCI_TYPE_EVNT) - { - - // In case unsolicited event received - here the handling finished - if (hci_unsol_event_handler((char *)pucReceivedData) == 1) - { - - // There was an unsolicited event received - we can release the buffer - // and clean the event received - tSLInformation.usEventOrDataReceived = 0; - - res = 1; - SpiResumeSpi(); - } - } - } - - return res; -} - -//***************************************************************************** -// -//! set_socket_active_status -//! -//! @param Sd -//! @param Status -//! @return none -//! -//! @brief Check if the socket ID and status are valid and set -//! accordingly the global socket status -// -//***************************************************************************** -void set_socket_active_status(long Sd, long Status) -{ - if(M_IS_VALID_SD(Sd) && M_IS_VALID_STATUS(Status)) - { - socket_active_status &= ~(1 << Sd); /* clean socket's mask */ - socket_active_status |= (Status << Sd); /* set new socket's mask */ - } -} - - -//***************************************************************************** -// -//! hci_event_unsol_flowcontrol_handler -//! -//! @param pEvent pointer to the string contains parameters for IPERF -//! @return ESUCCESS if successful, EFAIL if an error occurred -//! -//! @brief Called in case unsolicited event from type -//! HCI_EVNT_DATA_UNSOL_FREE_BUFF has received. -//! Keep track on the number of packets transmitted and update the -//! number of free buffer in the SL device. -// -//***************************************************************************** -long -hci_event_unsol_flowcontrol_handler(char *pEvent) -{ - - long temp, value; - unsigned short i; - unsigned short pusNumberOfHandles=0; - char *pReadPayload; - - STREAM_TO_UINT16((char *)pEvent,HCI_EVENT_HEADER_SIZE,pusNumberOfHandles); - pReadPayload = ((char *)pEvent + - HCI_EVENT_HEADER_SIZE + sizeof(pusNumberOfHandles)); - temp = 0; - - for(i = 0; i < pusNumberOfHandles ; i++) - { - STREAM_TO_UINT16(pReadPayload, FLOW_CONTROL_EVENT_FREE_BUFFS_OFFSET, value); - temp += value; - pReadPayload += FLOW_CONTROL_EVENT_SIZE; - } - - tSLInformation.usNumberOfFreeBuffers += temp; - tSLInformation.NumberOfReleasedPackets += temp; - - return(ESUCCESS); -} - -//***************************************************************************** -// -//! get_socket_active_status -//! -//! @param Sd Socket IS -//! @return Current status of the socket. -//! -//! @brief Retrieve socket status -// -//***************************************************************************** - -long -get_socket_active_status(long Sd) -{ - if(M_IS_VALID_SD(Sd)) - { - return (socket_active_status & (1 << Sd)) ? SOCKET_STATUS_INACTIVE : SOCKET_STATUS_ACTIVE; - } - return SOCKET_STATUS_INACTIVE; -} - -//***************************************************************************** -// -//! update_socket_active_status -//! -//! @param resp_params Socket IS -//! @return Current status of the socket. -//! -//! @brief Retrieve socket status -// -//***************************************************************************** -void -update_socket_active_status(char *resp_params) -{ - long status, sd; - - STREAM_TO_UINT32(resp_params, BSD_RSP_PARAMS_SOCKET_OFFSET,sd); - STREAM_TO_UINT32(resp_params, BSD_RSP_PARAMS_STATUS_OFFSET,status); - - if(ERROR_SOCKET_INACTIVE == status) - { - set_socket_active_status(sd, SOCKET_STATUS_INACTIVE); - } -} - - -//***************************************************************************** -// -//! SimpleLinkWaitEvent -//! -//! @param usOpcode command operation code -//! @param pRetParams command return parameters -//! -//! @return none -//! -//! @brief Wait for event, pass it to the hci_event_handler and -//! update the event opcode in a global variable. -// -//***************************************************************************** - -void -SimpleLinkWaitEvent(unsigned short usOpcode, void *pRetParams) -{ - // In the blocking implementation the control to caller will be returned only - // after the end of current transaction - tSLInformation.usRxEventOpcode = usOpcode; - hci_event_handler(pRetParams, 0, 0); -} - -//***************************************************************************** -// -//! SimpleLinkWaitData -//! -//! @param pBuf data buffer -//! @param from from information -//! @param fromlen from information length -//! -//! @return none -//! -//! @brief Wait for data, pass it to the hci_event_handler -//! and update in a global variable that there is -//! data to read. -// -//***************************************************************************** - -void -SimpleLinkWaitData(unsigned char *pBuf, unsigned char *from, - unsigned char *fromlen) -{ - // In the blocking implementation the control to caller will be returned only - // after the end of current transaction, i.e. only after data will be received - tSLInformation.usRxDataPending = 1; - hci_event_handler(pBuf, from, fromlen); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/stm/cc3k/evnt_handler.h b/stm/cc3k/evnt_handler.h deleted file mode 100644 index 1391752bd..000000000 --- a/stm/cc3k/evnt_handler.h +++ /dev/null @@ -1,175 +0,0 @@ -/***************************************************************************** -* -* evnt_handler.h - CC3000 Host Driver Implementation. -* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ -* -* Adapted for use with the Arduino/AVR by KTOWN (Kevin Townsend) -* & Limor Fried for Adafruit Industries -* This library works with the Adafruit CC3000 breakout -* ----> https://www.adafruit.com/products/1469 -* Adafruit invests time and resources providing this open source code, -* please support Adafruit and open-source hardware by purchasing -* products from Adafruit! -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*****************************************************************************/ -#ifndef __EVENT_HANDLER_H__ -#define __EVENT_HANDLER_H__ - -#include "hci.h" -#include "socket.h" - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" { -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** - -//***************************************************************************** -// -//! hci_event_handler -//! -//! @param pRetParams incoming data buffer -//! @param from from information (in case of data received) -//! @param fromlen from information length (in case of data received) -//! -//! @return none -//! -//! @brief Parse the incoming events packets and issues corresponding -//! event handler from global array of handlers pointers -// -//***************************************************************************** -extern unsigned char *hci_event_handler(void *pRetParams, unsigned char *from, unsigned char *fromlen); - -//***************************************************************************** -// -//! hci_unsol_event_handler -//! -//! @param event_hdr event header -//! -//! @return 1 if event supported and handled -//! 0 if event is not supported -//! -//! @brief Handle unsolicited events -// -//***************************************************************************** -extern long hci_unsol_event_handler(char *event_hdr); - -//***************************************************************************** -// -//! hci_unsolicited_event_handler -//! -//! @param None -//! -//! @return ESUCCESS if successful, EFAIL if an error occurred -//! -//! @brief Parse the incoming unsolicited event packets and issues -//! corresponding event handler. -// -//***************************************************************************** -extern long hci_unsolicited_event_handler(void); - -#define M_BSD_RESP_PARAMS_OFFSET(hci_event_hdr)((char *)(hci_event_hdr) + HCI_EVENT_HEADER_SIZE) - -#define SOCKET_STATUS_ACTIVE 0 -#define SOCKET_STATUS_INACTIVE 1 -/* Init socket_active_status = 'all ones': init all sockets with SOCKET_STATUS_INACTIVE. - Will be changed by 'set_socket_active_status' upon 'connect' and 'accept' calls */ -#define SOCKET_STATUS_INIT_VAL 0xFFFF -#define M_IS_VALID_SD(sd) ((0 <= (sd)) && ((sd) <= 7)) -#define M_IS_VALID_STATUS(status) (((status) == SOCKET_STATUS_ACTIVE)||((status) == SOCKET_STATUS_INACTIVE)) - -extern unsigned long socket_active_status; - -extern void set_socket_active_status(long Sd, long Status); -extern long get_socket_active_status(long Sd); - -typedef struct _bsd_accept_return_t -{ - long iSocketDescriptor; - long iStatus; - sockaddr tSocketAddress; - -} tBsdReturnParams; - - -typedef struct _bsd_read_return_t -{ - long iSocketDescriptor; - long iNumberOfBytes; - unsigned long uiFlags; -} tBsdReadReturnParams; - -#define BSD_RECV_FROM_FROMLEN_OFFSET (4) -#define BSD_RECV_FROM_FROM_OFFSET (16) - - -typedef struct _bsd_select_return_t -{ - long iStatus; - unsigned long uiRdfd; - unsigned long uiWrfd; - unsigned long uiExfd; -} tBsdSelectRecvParams; - - -typedef struct _bsd_getsockopt_return_t -{ - unsigned char ucOptValue[4]; - char iStatus; -} tBsdGetSockOptReturnParams; - -typedef struct _bsd_gethostbyname_return_t -{ - long retVal; - long outputAddress; -} tBsdGethostbynameParams; - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif // __cplusplus - -#endif // __EVENT_HANDLER_H__ - diff --git a/stm/cc3k/hci.c b/stm/cc3k/hci.c deleted file mode 100644 index ef77db95f..000000000 --- a/stm/cc3k/hci.c +++ /dev/null @@ -1,242 +0,0 @@ -/***************************************************************************** -* -* hci.c - CC3000 Host Driver Implementation. -* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ -* -* Adapted for use with the Arduino/AVR by KTOWN (Kevin Townsend) -* & Limor Fried for Adafruit Industries -* This library works with the Adafruit CC3000 breakout -* ----> https://www.adafruit.com/products/1469 -* Adafruit invests time and resources providing this open source code, -* please support Adafruit and open-source hardware by purchasing -* products from Adafruit! -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*****************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup hci_app -//! @{ -// -//***************************************************************************** - -#include -#include // for memcpy - -#include "cc3000_common.h" -#include "hci.h" -#include "ccspi.h" -#include "evnt_handler.h" -#include "wlan.h" - -#define SL_PATCH_PORTION_SIZE (1000) - - -//***************************************************************************** -// -//! hci_command_send -//! -//! @param usOpcode command operation code -//! @param pucBuff pointer to the command's arguments buffer -//! @param ucArgsLength length of the arguments -//! -//! @return none -//! -//! @brief Initiate an HCI command. -// -//***************************************************************************** -unsigned short -hci_command_send(unsigned short usOpcode, unsigned char *pucBuff, - unsigned char ucArgsLength) -{ - unsigned char *stream; - - stream = (pucBuff + SPI_HEADER_SIZE); - - UINT8_TO_STREAM(stream, HCI_TYPE_CMND); - stream = UINT16_TO_STREAM(stream, usOpcode); - UINT8_TO_STREAM(stream, ucArgsLength); - - //Update the opcode of the event we will be waiting for - SpiWrite(pucBuff, ucArgsLength + SIMPLE_LINK_HCI_CMND_HEADER_SIZE); - - return(0); -} - -//***************************************************************************** -// -//! hci_data_send -//! -//! @param usOpcode command operation code -//! @param ucArgs pointer to the command's arguments buffer -//! @param usArgsLength length of the arguments -//! @param ucTail pointer to the data buffer -//! @param usTailLength buffer length -//! -//! @return none -//! -//! @brief Initiate an HCI data write operation -// -//***************************************************************************** -long -hci_data_send(unsigned char ucOpcode, - unsigned char *ucArgs, - unsigned short usArgsLength, - unsigned short usDataLength, - const unsigned char *ucTail, - unsigned short usTailLength) -{ - unsigned char *stream; - - stream = ((ucArgs) + SPI_HEADER_SIZE); - - UINT8_TO_STREAM(stream, HCI_TYPE_DATA); - UINT8_TO_STREAM(stream, ucOpcode); - UINT8_TO_STREAM(stream, usArgsLength); - stream = UINT16_TO_STREAM(stream, usArgsLength + usDataLength + usTailLength); - - // Send the packet over the SPI - SpiWrite(ucArgs, SIMPLE_LINK_HCI_DATA_HEADER_SIZE + usArgsLength + usDataLength + usTailLength); - - return(ESUCCESS); -} - - -//***************************************************************************** -// -//! hci_data_command_send -//! -//! @param usOpcode command operation code -//! @param pucBuff pointer to the data buffer -//! @param ucArgsLength arguments length -//! @param ucDataLength data length -//! -//! @return none -//! -//! @brief Prepeare HCI header and initiate an HCI data write operation -// -//***************************************************************************** -void hci_data_command_send(unsigned short usOpcode, unsigned char *pucBuff, - unsigned char ucArgsLength,unsigned short ucDataLength) -{ - unsigned char *stream = (pucBuff + SPI_HEADER_SIZE); - - UINT8_TO_STREAM(stream, HCI_TYPE_DATA); - UINT8_TO_STREAM(stream, usOpcode); - UINT8_TO_STREAM(stream, ucArgsLength); - stream = UINT16_TO_STREAM(stream, ucArgsLength + ucDataLength); - - // Send the command over SPI on data channel - SpiWrite(pucBuff, ucArgsLength + ucDataLength + SIMPLE_LINK_HCI_DATA_CMND_HEADER_SIZE); - - return; -} - -//***************************************************************************** -// -//! hci_patch_send -//! -//! @param usOpcode command operation code -//! @param pucBuff pointer to the command's arguments buffer -//! @param patch pointer to patch content buffer -//! @param usDataLength data length -//! -//! @return none -//! -//! @brief Prepeare HCI header and initiate an HCI patch write operation -// -//***************************************************************************** -void -hci_patch_send(unsigned char ucOpcode, unsigned char *pucBuff, char *patch, unsigned short usDataLength) -{ - unsigned char *data_ptr = (pucBuff + SPI_HEADER_SIZE); - unsigned short usTransLength; - unsigned char *stream = (pucBuff + SPI_HEADER_SIZE); - - UINT8_TO_STREAM(stream, HCI_TYPE_PATCH); - UINT8_TO_STREAM(stream, ucOpcode); - stream = UINT16_TO_STREAM(stream, usDataLength + SIMPLE_LINK_HCI_PATCH_HEADER_SIZE); - - if (usDataLength <= SL_PATCH_PORTION_SIZE) - { - UINT16_TO_STREAM(stream, usDataLength); - stream = UINT16_TO_STREAM(stream, usDataLength); - memcpy((pucBuff + SPI_HEADER_SIZE) + HCI_PATCH_HEADER_SIZE, patch, usDataLength); - - // Update the opcode of the event we will be waiting for - SpiWrite(pucBuff, usDataLength + HCI_PATCH_HEADER_SIZE); - } - else - { - - usTransLength = (usDataLength/SL_PATCH_PORTION_SIZE); - UINT16_TO_STREAM(stream, usDataLength + SIMPLE_LINK_HCI_PATCH_HEADER_SIZE + usTransLength*SIMPLE_LINK_HCI_PATCH_HEADER_SIZE); - stream = UINT16_TO_STREAM(stream, SL_PATCH_PORTION_SIZE); - memcpy(pucBuff + SPI_HEADER_SIZE + HCI_PATCH_HEADER_SIZE, patch, SL_PATCH_PORTION_SIZE); - usDataLength -= SL_PATCH_PORTION_SIZE; - patch += SL_PATCH_PORTION_SIZE; - - // Update the opcode of the event we will be waiting for - SpiWrite(pucBuff, SL_PATCH_PORTION_SIZE + HCI_PATCH_HEADER_SIZE); - - while (usDataLength) - { - cc3k_int_poll(); - - if (usDataLength <= SL_PATCH_PORTION_SIZE) - { - usTransLength = usDataLength; - usDataLength = 0; - - } - else - { - usTransLength = SL_PATCH_PORTION_SIZE; - usDataLength -= usTransLength; - } - - *(unsigned short *)data_ptr = usTransLength; - memcpy(data_ptr + SIMPLE_LINK_HCI_PATCH_HEADER_SIZE, patch, usTransLength); - patch += usTransLength; - - // Update the opcode of the event we will be waiting for - SpiWrite((unsigned char *)data_ptr, usTransLength + sizeof(usTransLength)); - } - } -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -// -//***************************************************************************** diff --git a/stm/cc3k/hci.h b/stm/cc3k/hci.h deleted file mode 100644 index 3466a9cfe..000000000 --- a/stm/cc3k/hci.h +++ /dev/null @@ -1,336 +0,0 @@ -/***************************************************************************** -* -* hci.h - CC3000 Host Driver Implementation. -* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ -* -* Adapted for use with the Arduino/AVR by KTOWN (Kevin Townsend) -* & Limor Fried for Adafruit Industries -* This library works with the Adafruit CC3000 breakout -* ----> https://www.adafruit.com/products/1469 -* Adafruit invests time and resources providing this open source code, -* please support Adafruit and open-source hardware by purchasing -* products from Adafruit! -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*****************************************************************************/ -#ifndef __HCI_H__ -#define __HCI_H__ - -#include "cc3000_common.h" - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" { -#endif - - -#define SPI_HEADER_SIZE (5) -#define SIMPLE_LINK_HCI_CMND_HEADER_SIZE (4) -#define HEADERS_SIZE_CMD (SPI_HEADER_SIZE + SIMPLE_LINK_HCI_CMND_HEADER_SIZE) -#define SIMPLE_LINK_HCI_DATA_CMND_HEADER_SIZE (5) -#define SIMPLE_LINK_HCI_DATA_HEADER_SIZE (5) -#define SIMPLE_LINK_HCI_PATCH_HEADER_SIZE (2) - - -//***************************************************************************** -// -// Values that can be used as HCI Commands and HCI Packet header defines -// -//***************************************************************************** -#define HCI_TYPE_CMND 0x1 -#define HCI_TYPE_DATA 0x2 -#define HCI_TYPE_PATCH 0x3 -#define HCI_TYPE_EVNT 0x4 - - -#define HCI_EVENT_PATCHES_DRV_REQ (1) -#define HCI_EVENT_PATCHES_FW_REQ (2) -#define HCI_EVENT_PATCHES_BOOTLOAD_REQ (3) - - -#define HCI_CMND_WLAN_BASE (0x0000) -#define HCI_CMND_WLAN_CONNECT 0x0001 -#define HCI_CMND_WLAN_DISCONNECT 0x0002 -#define HCI_CMND_WLAN_IOCTL_SET_SCANPARAM 0x0003 -#define HCI_CMND_WLAN_IOCTL_SET_CONNECTION_POLICY 0x0004 -#define HCI_CMND_WLAN_IOCTL_ADD_PROFILE 0x0005 -#define HCI_CMND_WLAN_IOCTL_DEL_PROFILE 0x0006 -#define HCI_CMND_WLAN_IOCTL_GET_SCAN_RESULTS 0x0007 -#define HCI_CMND_EVENT_MASK 0x0008 -#define HCI_CMND_WLAN_IOCTL_STATUSGET 0x0009 -#define HCI_CMND_WLAN_IOCTL_SIMPLE_CONFIG_START 0x000A -#define HCI_CMND_WLAN_IOCTL_SIMPLE_CONFIG_STOP 0x000B -#define HCI_CMND_WLAN_IOCTL_SIMPLE_CONFIG_SET_PREFIX 0x000C -#define HCI_CMND_WLAN_CONFIGURE_PATCH 0x000D - - -#define HCI_CMND_SOCKET_BASE 0x1000 -#define HCI_CMND_SOCKET 0x1001 -#define HCI_CMND_BIND 0x1002 -#define HCI_CMND_RECV 0x1004 -#define HCI_CMND_ACCEPT 0x1005 -#define HCI_CMND_LISTEN 0x1006 -#define HCI_CMND_CONNECT 0x1007 -#define HCI_CMND_BSD_SELECT 0x1008 -#define HCI_CMND_SETSOCKOPT 0x1009 -#define HCI_CMND_GETSOCKOPT 0x100A -#define HCI_CMND_CLOSE_SOCKET 0x100B -#define HCI_CMND_RECVFROM 0x100D -#define HCI_CMND_GETHOSTNAME 0x1010 -#define HCI_CMND_MDNS_ADVERTISE 0x1011 - - -#define HCI_DATA_BASE 0x80 - -#define HCI_CMND_SEND (0x01 + HCI_DATA_BASE) -#define HCI_CMND_SENDTO (0x03 + HCI_DATA_BASE) -#define HCI_DATA_BSD_RECVFROM (0x04 + HCI_DATA_BASE) -#define HCI_DATA_BSD_RECV (0x05 + HCI_DATA_BASE) - - -#define HCI_CMND_NVMEM_CBASE (0x0200) - - -#define HCI_CMND_NVMEM_CREATE_ENTRY (0x0203) -#define HCI_CMND_NVMEM_SWAP_ENTRY (0x0205) -#define HCI_CMND_NVMEM_READ (0x0201) -#define HCI_CMND_NVMEM_WRITE (0x0090) -#define HCI_CMND_NVMEM_WRITE_PATCH (0x0204) -#define HCI_CMND_READ_SP_VERSION (0x0207) - -#define HCI_CMND_READ_BUFFER_SIZE 0x400B -#define HCI_CMND_SIMPLE_LINK_START 0x4000 - -#define HCI_CMND_NETAPP_BASE 0x2000 - -#define HCI_NETAPP_DHCP (0x0001 + HCI_CMND_NETAPP_BASE) -#define HCI_NETAPP_PING_SEND (0x0002 + HCI_CMND_NETAPP_BASE) -#define HCI_NETAPP_PING_REPORT (0x0003 + HCI_CMND_NETAPP_BASE) -#define HCI_NETAPP_PING_STOP (0x0004 + HCI_CMND_NETAPP_BASE) -#define HCI_NETAPP_IPCONFIG (0x0005 + HCI_CMND_NETAPP_BASE) -#define HCI_NETAPP_ARP_FLUSH (0x0006 + HCI_CMND_NETAPP_BASE) -#define HCI_NETAPP_SET_DEBUG_LEVEL (0x0008 + HCI_CMND_NETAPP_BASE) -#define HCI_NETAPP_SET_TIMERS (0x0009 + HCI_CMND_NETAPP_BASE) - - - - - - -//***************************************************************************** -// -// Values that can be used as HCI Events defines -// -//***************************************************************************** -#define HCI_EVNT_WLAN_BASE 0x0000 -#define HCI_EVNT_WLAN_CONNECT 0x0001 -#define HCI_EVNT_WLAN_DISCONNECT \ - 0x0002 -#define HCI_EVNT_WLAN_IOCTL_ADD_PROFILE \ - 0x0005 - - -#define HCI_EVNT_SOCKET HCI_CMND_SOCKET -#define HCI_EVNT_BIND HCI_CMND_BIND -#define HCI_EVNT_RECV HCI_CMND_RECV -#define HCI_EVNT_ACCEPT HCI_CMND_ACCEPT -#define HCI_EVNT_LISTEN HCI_CMND_LISTEN -#define HCI_EVNT_CONNECT HCI_CMND_CONNECT -#define HCI_EVNT_SELECT HCI_CMND_BSD_SELECT -#define HCI_EVNT_CLOSE_SOCKET HCI_CMND_CLOSE_SOCKET -#define HCI_EVNT_RECVFROM HCI_CMND_RECVFROM -#define HCI_EVNT_SETSOCKOPT HCI_CMND_SETSOCKOPT -#define HCI_EVNT_GETSOCKOPT HCI_CMND_GETSOCKOPT -#define HCI_EVNT_BSD_GETHOSTBYNAME HCI_CMND_GETHOSTNAME -#define HCI_EVNT_MDNS_ADVERTISE HCI_CMND_MDNS_ADVERTISE - -#define HCI_EVNT_SEND 0x1003 -#define HCI_EVNT_WRITE 0x100E -#define HCI_EVNT_SENDTO 0x100F - -#define HCI_EVNT_PATCHES_REQ 0x1000 - -#define HCI_EVNT_UNSOL_BASE 0x4000 - -#define HCI_EVNT_WLAN_UNSOL_BASE (0x8000) - -#define HCI_EVNT_WLAN_UNSOL_CONNECT (0x0001 + HCI_EVNT_WLAN_UNSOL_BASE) -#define HCI_EVNT_WLAN_UNSOL_DISCONNECT (0x0002 + HCI_EVNT_WLAN_UNSOL_BASE) -#define HCI_EVNT_WLAN_UNSOL_INIT (0x0004 + HCI_EVNT_WLAN_UNSOL_BASE) -#define HCI_EVNT_WLAN_TX_COMPLETE (0x0008 + HCI_EVNT_WLAN_UNSOL_BASE) -#define HCI_EVNT_WLAN_UNSOL_DHCP (0x0010 + HCI_EVNT_WLAN_UNSOL_BASE) -#define HCI_EVNT_WLAN_ASYNC_PING_REPORT (0x0040 + HCI_EVNT_WLAN_UNSOL_BASE) -#define HCI_EVNT_WLAN_ASYNC_SIMPLE_CONFIG_DONE (0x0080 + HCI_EVNT_WLAN_UNSOL_BASE) -#define HCI_EVNT_WLAN_KEEPALIVE (0x0200 + HCI_EVNT_WLAN_UNSOL_BASE) -#define HCI_EVNT_BSD_TCP_CLOSE_WAIT (0x0800 + HCI_EVNT_WLAN_UNSOL_BASE) - -#define HCI_EVNT_DATA_UNSOL_FREE_BUFF \ - 0x4100 - -#define HCI_EVNT_NVMEM_CREATE_ENTRY \ - HCI_CMND_NVMEM_CREATE_ENTRY -#define HCI_EVNT_NVMEM_SWAP_ENTRY HCI_CMND_NVMEM_SWAP_ENTRY - -#define HCI_EVNT_NVMEM_READ HCI_CMND_NVMEM_READ -#define HCI_EVNT_NVMEM_WRITE (0x0202) - -#define HCI_EVNT_READ_SP_VERSION \ - HCI_CMND_READ_SP_VERSION - -#define HCI_EVNT_INPROGRESS 0xFFFF - - -#define HCI_DATA_RECVFROM 0x84 -#define HCI_DATA_RECV 0x85 -#define HCI_DATA_NVMEM 0x91 - -#define HCI_EVENT_CC3000_CAN_SHUT_DOWN 0x99 - -//***************************************************************************** -// -// Prototypes for the structures for APIs. -// -//***************************************************************************** - -#define HCI_DATA_HEADER_SIZE (5) -#define HCI_EVENT_HEADER_SIZE (5) -#define HCI_DATA_CMD_HEADER_SIZE (5) -#define HCI_PATCH_HEADER_SIZE (6) - -#define HCI_PACKET_TYPE_OFFSET (0) -#define HCI_PACKET_ARGSIZE_OFFSET (2) -#define HCI_PACKET_LENGTH_OFFSET (3) - - -#define HCI_EVENT_OPCODE_OFFSET (1) -#define HCI_EVENT_LENGTH_OFFSET (3) -#define HCI_EVENT_STATUS_OFFSET (4) -#define HCI_DATA_LENGTH_OFFSET (3) - - - - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** - -//***************************************************************************** -// -//! hci_command_send -//! -//! @param usOpcode command operation code -//! @param pucBuff pointer to the command's arguments buffer -//! @param ucArgsLength length of the arguments -//! -//! @return none -//! -//! @brief Initiate an HCI command. -// -//***************************************************************************** -extern unsigned short hci_command_send(unsigned short usOpcode, - unsigned char *ucArgs, - unsigned char ucArgsLength); - - -//***************************************************************************** -// -//! hci_data_send -//! -//! @param usOpcode command operation code -//! @param ucArgs pointer to the command's arguments buffer -//! @param usArgsLength length of the arguments -//! @param ucTail pointer to the data buffer -//! @param usTailLength buffer length -//! -//! @return none -//! -//! @brief Initiate an HCI data write operation -// -//***************************************************************************** -extern long hci_data_send(unsigned char ucOpcode, - unsigned char *ucArgs, - unsigned short usArgsLength, - unsigned short usDataLength, - const unsigned char *ucTail, - unsigned short usTailLength); - - -//***************************************************************************** -// -//! hci_data_command_send -//! -//! @param usOpcode command operation code -//! @param pucBuff pointer to the data buffer -//! @param ucArgsLength arguments length -//! @param ucDataLength data length -//! -//! @return none -//! -//! @brief Prepare HCI header and initiate an HCI data write operation -// -//***************************************************************************** -extern void hci_data_command_send(unsigned short usOpcode, unsigned char *pucBuff, - unsigned char ucArgsLength, unsigned short ucDataLength); - -//***************************************************************************** -// -//! hci_patch_send -//! -//! @param usOpcode command operation code -//! @param pucBuff pointer to the command's arguments buffer -//! @param patch pointer to patch content buffer -//! @param usDataLength data length -//! -//! @return none -//! -//! @brief Prepare HCI header and initiate an HCI patch write operation -// -//***************************************************************************** -extern void hci_patch_send(unsigned char ucOpcode, unsigned char *pucBuff, char *patch, unsigned short usDataLength); - - - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif // __cplusplus - -#endif // __HCI_H__ diff --git a/stm/cc3k/host_driver_version.h b/stm/cc3k/host_driver_version.h deleted file mode 100644 index c218704a2..000000000 --- a/stm/cc3k/host_driver_version.h +++ /dev/null @@ -1,55 +0,0 @@ -/***************************************************************************** -* -* host_driver_version.h - CC3000 Host Driver Implementation. -* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*****************************************************************************/ -#ifndef __HOST_DRIVER_VERSION_H__ -#define __HOST_DRIVER_VERSION_H__ - -#define DRIVER_VERSION_NUMBER 13 - - - -#endif // __VERSION_H__ - - - - - - - - - - - - - diff --git a/stm/cc3k/netapp.c b/stm/cc3k/netapp.c deleted file mode 100644 index 4b3efb24d..000000000 --- a/stm/cc3k/netapp.c +++ /dev/null @@ -1,477 +0,0 @@ -/***************************************************************************** -* -* netapp.c - CC3000 Host Driver Implementation. -* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ -* -* Adapted for use with the Arduino/AVR by KTOWN (Kevin Townsend) -* & Limor Fried for Adafruit Industries -* This library works with the Adafruit CC3000 breakout -* ----> https://www.adafruit.com/products/1469 -* Adafruit invests time and resources providing this open source code, -* please support Adafruit and open-source hardware by purchasing -* products from Adafruit! -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*****************************************************************************/ -#include - -#include "netapp.h" -#include "hci.h" -#include "socket.h" -#include "evnt_handler.h" -#include "nvmem.h" - -#define MIN_TIMER_VAL_SECONDS 20 -#define MIN_TIMER_SET(t) if ((0 != t) && (t < MIN_TIMER_VAL_SECONDS)) \ - { \ - t = MIN_TIMER_VAL_SECONDS; \ - } - - -#define NETAPP_DHCP_PARAMS_LEN (20) -#define NETAPP_SET_TIMER_PARAMS_LEN (20) -#define NETAPP_SET_DEBUG_LEVEL_PARAMS_LEN (4) -#define NETAPP_PING_SEND_PARAMS_LEN (16) - - -//***************************************************************************** -// -//! netapp_config_mac_adrress -//! -//! @param mac device mac address, 6 bytes. Saved: yes -//! -//! @return return on success 0, otherwise error. -//! -//! @brief Configure device MAC address and store it in NVMEM. -//! The value of the MAC address configured through the API will -//! be stored in CC3000 non volatile memory, thus preserved -//! over resets. -// -//***************************************************************************** -long netapp_config_mac_adrress(unsigned char * mac) -{ - return nvmem_set_mac_address(mac); -} - -//***************************************************************************** -// -//! netapp_dhcp -//! -//! @param aucIP device mac address, 6 bytes. Saved: yes -//! @param aucSubnetMask device mac address, 6 bytes. Saved: yes -//! @param aucDefaultGateway device mac address, 6 bytes. Saved: yes -//! @param aucDNSServer device mac address, 6 bytes. Saved: yes -//! -//! @return return on success 0, otherwise error. -//! -//! @brief netapp_dhcp is used to configure the network interface, -//! static or dynamic (DHCP).\n In order to activate DHCP mode, -//! aucIP, aucSubnetMask, aucDefaultGateway must be 0. -//! The default mode of CC3000 is DHCP mode. -//! Note that the configuration is saved in non volatile memory -//! and thus preserved over resets. -//! -//! @note If the mode is altered a reset of CC3000 device is required -//! in order to apply changes.\nAlso note that asynchronous event -//! of DHCP_EVENT, which is generated when an IP address is -//! allocated either by the DHCP server or due to static -//! allocation is generated only upon a connection to the -//! AP was established. -//! -//***************************************************************************** -long netapp_dhcp(unsigned long *aucIP, unsigned long *aucSubnetMask,unsigned long *aucDefaultGateway, unsigned long *aucDNSServer) -{ - signed char scRet; - unsigned char *ptr; - unsigned char *args; - - scRet = EFAIL; - ptr = tSLInformation.pucTxCommandBuffer; - args = (ptr + HEADERS_SIZE_CMD); - - // Fill in temporary command buffer - ARRAY_TO_STREAM(args,aucIP,4); - ARRAY_TO_STREAM(args,aucSubnetMask,4); - ARRAY_TO_STREAM(args,aucDefaultGateway,4); - args = UINT32_TO_STREAM(args, 0); - ARRAY_TO_STREAM(args,aucDNSServer,4); - - // Initiate a HCI command - hci_command_send(HCI_NETAPP_DHCP, ptr, NETAPP_DHCP_PARAMS_LEN); - - // Wait for command complete event - SimpleLinkWaitEvent(HCI_NETAPP_DHCP, &scRet); - - return(scRet); -} - - -//***************************************************************************** -// -//! netapp_timeout_values -//! -//! @param aucDHCP DHCP lease time request, also impact -//! the DHCP renew timeout. Range: [0-0xffffffff] seconds, -//! 0 or 0xffffffff == infinity lease timeout. -//! Resolution:10 seconds. Influence: only after -//! reconnecting to the AP. -//! Minimal bound value: MIN_TIMER_VAL_SECONDS - 20 seconds. -//! The parameter is saved into the CC3000 NVMEM. -//! The default value on CC3000 is 14400 seconds. -//! -//! @param aucARP ARP refresh timeout, if ARP entry is not updated by -//! incoming packet, the ARP entry will be deleted by -//! the end of the timeout. -//! Range: [0-0xffffffff] seconds, 0 == infinity ARP timeout -//! Resolution: 10 seconds. Influence: on runtime. -//! Minimal bound value: MIN_TIMER_VAL_SECONDS - 20 seconds -//! The parameter is saved into the CC3000 NVMEM. -//! The default value on CC3000 is 3600 seconds. -//! -//! @param aucKeepalive Keepalive event sent by the end of keepalive timeout -//! Range: [0-0xffffffff] seconds, 0 == infinity timeout -//! Resolution: 10 seconds. -//! Influence: on runtime. -//! Minimal bound value: MIN_TIMER_VAL_SECONDS - 20 sec -//! The parameter is saved into the CC3000 NVMEM. -//! The default value on CC3000 is 10 seconds. -//! -//! @param aucInactivity Socket inactivity timeout, socket timeout is -//! refreshed by incoming or outgoing packet, by the -//! end of the socket timeout the socket will be closed -//! Range: [0-0xffffffff] sec, 0 == infinity timeout. -//! Resolution: 10 seconds. Influence: on runtime. -//! Minimal bound value: MIN_TIMER_VAL_SECONDS - 20 sec -//! The parameter is saved into the CC3000 NVMEM. -//! The default value on CC3000 is 60 seconds. -//! -//! @return return on success 0, otherwise error. -//! -//! @brief Set new timeout values. Function set new timeout values for: -//! DHCP lease timeout, ARP refresh timeout, keepalive event -//! timeout and socket inactivity timeout -//! -//! @note If a parameter set to non zero value which is less than 20s, -//! it will be set automatically to 20s. -//! -//***************************************************************************** - -#ifndef CC3000_TINY_DRIVER -long -netapp_timeout_values(unsigned long *aucDHCP, unsigned long *aucARP,unsigned long *aucKeepalive, unsigned long *aucInactivity) -{ - signed char scRet; - unsigned char *ptr; - unsigned char *args; - - scRet = EFAIL; - ptr = tSLInformation.pucTxCommandBuffer; - args = (ptr + HEADERS_SIZE_CMD); - - // Set minimal values of timers - MIN_TIMER_SET(*aucDHCP) - MIN_TIMER_SET(*aucARP) - MIN_TIMER_SET(*aucKeepalive) - MIN_TIMER_SET(*aucInactivity) - - // Fill in temporary command buffer - args = UINT32_TO_STREAM(args, *aucDHCP); - args = UINT32_TO_STREAM(args, *aucARP); - args = UINT32_TO_STREAM(args, *aucKeepalive); - args = UINT32_TO_STREAM(args, *aucInactivity); - - // Initiate a HCI command - hci_command_send(HCI_NETAPP_SET_TIMERS, ptr, NETAPP_SET_TIMER_PARAMS_LEN); - - // Wait for command complete event - SimpleLinkWaitEvent(HCI_NETAPP_SET_TIMERS, &scRet); - - return(scRet); -} -#endif - - -//***************************************************************************** -// -//! netapp_ping_send -//! -//! @param ip destination IP address -//! @param pingAttempts number of echo requests to send -//! @param pingSize send buffer size which may be up to 1400 bytes -//! @param pingTimeout Time to wait for a response,in milliseconds. -//! -//! @return return on success 0, otherwise error. -//! -//! @brief send ICMP ECHO_REQUEST to network hosts -//! -//! @note If an operation finished successfully asynchronous ping report -//! event will be generated. The report structure is as defined -//! by structure netapp_pingreport_args_t. -//! -//! @warning Calling this function while a previous Ping Requests are in -//! progress will stop the previous ping request. -//***************************************************************************** - -#ifndef CC3000_TINY_DRIVER -long -netapp_ping_send(uint32_t *ip, uint32_t ulPingAttempts, uint32_t ulPingSize, uint32_t ulPingTimeout) -{ - signed char scRet; - unsigned char *ptr, *args; - - scRet = EFAIL; - ptr = tSLInformation.pucTxCommandBuffer; - args = (ptr + HEADERS_SIZE_CMD); - - // Fill in temporary command buffer - args = UINT32_TO_STREAM(args, *ip); - args = UINT32_TO_STREAM(args, ulPingAttempts); - args = UINT32_TO_STREAM(args, ulPingSize); - args = UINT32_TO_STREAM(args, ulPingTimeout); - - /* - if (CC3KPrinter != 0) - { - for(uint8_t i=0; i<4+4+4+4; i++) { - CC3KPrinter->print(" 0x"); CC3KPrinter->( (ptr + HEADERS_SIZE_CMD)[i], HEX); - } - } - */ - - // Initiate a HCI command - hci_command_send(HCI_NETAPP_PING_SEND, ptr, NETAPP_PING_SEND_PARAMS_LEN); - - // Wait for command complete event - SimpleLinkWaitEvent(HCI_NETAPP_PING_SEND, &scRet); - - return(scRet); -} -#endif - -//***************************************************************************** -// -//! netapp_ping_report -//! -//! @param none -//! -//! @return none -//! -//! @brief Request for ping status. This API triggers the CC3000 to send -//! asynchronous events: HCI_EVNT_WLAN_ASYNC_PING_REPORT. -//! This event will carry the report structure: -//! netapp_pingreport_args_t. This structure is filled in with ping -//! results up till point of triggering API. -//! netapp_pingreport_args_t:\n packets_sent - echo sent, -//! packets_received - echo reply, min_round_time - minimum -//! round time, max_round_time - max round time, -//! avg_round_time - average round time -//! -//! @note When a ping operation is not active, the returned structure -//! fields are 0. -//! -//***************************************************************************** - - -#ifndef CC3000_TINY_DRIVER -void netapp_ping_report() -{ - unsigned char *ptr; - ptr = tSLInformation.pucTxCommandBuffer; - signed char scRet; - - scRet = EFAIL; - - // Initiate a HCI command - hci_command_send(HCI_NETAPP_PING_REPORT, ptr, 0); - - // Wait for command complete event - SimpleLinkWaitEvent(HCI_NETAPP_PING_REPORT, &scRet); -} -#endif - -//***************************************************************************** -// -//! netapp_ping_stop -//! -//! @param none -//! -//! @return On success, zero is returned. On error, -1 is returned. -//! -//! @brief Stop any ping request. -//! -//! -//***************************************************************************** - -#ifndef CC3000_TINY_DRIVER -long netapp_ping_stop() -{ - signed char scRet; - unsigned char *ptr; - - scRet = EFAIL; - ptr = tSLInformation.pucTxCommandBuffer; - - // Initiate a HCI command - hci_command_send(HCI_NETAPP_PING_STOP, ptr, 0); - - // Wait for command complete event - SimpleLinkWaitEvent(HCI_NETAPP_PING_STOP, &scRet); - - return(scRet); -} -#endif - -//***************************************************************************** -// -//! netapp_ipconfig -//! -//! @param[out] ipconfig This argument is a pointer to a -//! tNetappIpconfigRetArgs structure. This structure is -//! filled in with the network interface configuration. -//! tNetappIpconfigRetArgs:\n aucIP - ip address, -//! aucSubnetMask - mask, aucDefaultGateway - default -//! gateway address, aucDHCPServer - dhcp server address -//! aucDNSServer - dns server address, uaMacAddr - mac -//! address, uaSSID - connected AP ssid -//! -//! @return none -//! -//! @brief Obtain the CC3000 Network interface information. -//! Note that the information is available only after the WLAN -//! connection was established. Calling this function before -//! associated, will cause non-defined values to be returned. -//! -//! @note The function is useful for figuring out the IP Configuration of -//! the device when DHCP is used and for figuring out the SSID of -//! the Wireless network the device is associated with. -//! -//***************************************************************************** - -#ifndef CC3000_TINY_DRIVER -void netapp_ipconfig( tNetappIpconfigRetArgs * ipconfig ) -{ - unsigned char *ptr; - - ptr = tSLInformation.pucTxCommandBuffer; - - // Initiate a HCI command - hci_command_send(HCI_NETAPP_IPCONFIG, ptr, 0); - - // Wait for command complete event - SimpleLinkWaitEvent(HCI_NETAPP_IPCONFIG, ipconfig ); - -} -#else -void netapp_ipconfig( tNetappIpconfigRetArgs * ipconfig ) -{ - -} -#endif - -//***************************************************************************** -// -//! netapp_arp_flush -//! -//! @param none -//! -//! @return none -//! -//! @brief Flushes ARP table -//! -//***************************************************************************** - -#ifndef CC3000_TINY_DRIVER -long netapp_arp_flush(void) -{ - signed char scRet; - unsigned char *ptr; - - scRet = EFAIL; - ptr = tSLInformation.pucTxCommandBuffer; - - // Initiate a HCI command - hci_command_send(HCI_NETAPP_ARP_FLUSH, ptr, 0); - - // Wait for command complete event - SimpleLinkWaitEvent(HCI_NETAPP_ARP_FLUSH, &scRet); - - return(scRet); -} -#endif - -//***************************************************************************** -// -//! netapp_set_debug_level -//! -//! @param[in] level debug level. Bitwise [0-8], -//! 0(disable)or 1(enable).\n Bitwise map: 0 - Critical -//! message, 1 information message, 2 - core messages, 3 - -//! HCI messages, 4 - Network stack messages, 5 - wlan -//! messages, 6 - wlan driver messages, 7 - epprom messages, -//! 8 - general messages. Default: 0x13f. Saved: no -//! -//! @return On success, zero is returned. On error, -1 is returned -//! -//! @brief Debug messages sent via the UART debug channel, this function -//! enable/disable the debug level -//! -//***************************************************************************** - - -#ifndef CC3000_TINY_DRIVER -long netapp_set_debug_level(unsigned long ulLevel) -{ - signed char scRet; - unsigned char *ptr, *args; - - scRet = EFAIL; - ptr = tSLInformation.pucTxCommandBuffer; - args = (ptr + HEADERS_SIZE_CMD); - - // - // Fill in temporary command buffer - // - args = UINT32_TO_STREAM(args, ulLevel); - - - // - // Initiate a HCI command - // - hci_command_send(HCI_NETAPP_SET_DEBUG_LEVEL, ptr, NETAPP_SET_DEBUG_LEVEL_PARAMS_LEN); - - // - // Wait for command complete event - // - SimpleLinkWaitEvent(HCI_NETAPP_SET_DEBUG_LEVEL, &scRet); - - return(scRet); - -} -#endif diff --git a/stm/cc3k/netapp.h b/stm/cc3k/netapp.h deleted file mode 100644 index 747ae64ed..000000000 --- a/stm/cc3k/netapp.h +++ /dev/null @@ -1,349 +0,0 @@ -/***************************************************************************** -* -* netapp.h - CC3000 Host Driver Implementation. -* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ -* -* Adapted for use with the Arduino/AVR by KTOWN (Kevin Townsend) -* & Limor Fried for Adafruit Industries -* This library works with the Adafruit CC3000 breakout -* ----> https://www.adafruit.com/products/1469 -* Adafruit invests time and resources providing this open source code, -* please support Adafruit and open-source hardware by purchasing -* products from Adafruit! -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*****************************************************************************/ -#ifndef __NETAPP_H__ -#define __NETAPP_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" { -#endif - -//***************************************************************************** -// -//! \addtogroup netapp_api -//! @{ -// -//***************************************************************************** - -typedef struct _netapp_dhcp_ret_args_t -{ - unsigned char aucIP[4]; - unsigned char aucSubnetMask[4]; - unsigned char aucDefaultGateway[4]; - unsigned char aucDHCPServer[4]; - unsigned char aucDNSServer[4]; -}tNetappDhcpParams; - -typedef struct _netapp_ipconfig_ret_args_t -{ - unsigned char aucIP[4]; - unsigned char aucSubnetMask[4]; - unsigned char aucDefaultGateway[4]; - unsigned char aucDHCPServer[4]; - unsigned char aucDNSServer[4]; - unsigned char uaMacAddr[6]; - unsigned char uaSSID[32]; -}tNetappIpconfigRetArgs; - - -/*Ping send report parameters*/ -typedef struct _netapp_pingreport_args -{ - unsigned long packets_sent; - unsigned long packets_received; - unsigned long min_round_time; - unsigned long max_round_time; - unsigned long avg_round_time; -} netapp_pingreport_args_t; - - -//***************************************************************************** -// -//! netapp_config_mac_adrress -//! -//! @param mac device mac address, 6 bytes. Saved: yes -//! -//! @return return on success 0, otherwise error. -//! -//! @brief Configure device MAC address and store it in NVMEM. -//! The value of the MAC address configured through the API will -//! be stored in CC3000 non volatile memory, thus preserved -//! over resets. -// -//***************************************************************************** -extern long netapp_config_mac_adrress( unsigned char *mac ); - -//***************************************************************************** -// -//! netapp_dhcp -//! -//! @param aucIP device mac address, 6 bytes. Saved: yes -//! @param aucSubnetMask device mac address, 6 bytes. Saved: yes -//! @param aucDefaultGateway device mac address, 6 bytes. Saved: yes -//! @param aucDNSServer device mac address, 6 bytes. Saved: yes -//! -//! @return return on success 0, otherwise error. -//! -//! @brief netapp_dhcp is used to configure the network interface, -//! static or dynamic (DHCP).\n In order to activate DHCP mode, -//! aucIP, aucSubnetMask, aucDefaultGateway must be 0. -//! The default mode of CC3000 is DHCP mode. -//! Note that the configuration is saved in non volatile memory -//! and thus preserved over resets. -//! -//! @note If the mode is altered a reset of CC3000 device is required -//! in order to apply changes.\nAlso note that asynchronous event -//! of DHCP_EVENT, which is generated when an IP address is -//! allocated either by the DHCP server or due to static -//! allocation is generated only upon a connection to the -//! AP was established. -//! -//***************************************************************************** -extern long netapp_dhcp(unsigned long *aucIP, unsigned long *aucSubnetMask,unsigned long *aucDefaultGateway, unsigned long *aucDNSServer); - - - -//***************************************************************************** -// -//! netapp_timeout_values -//! -//! @param aucDHCP DHCP lease time request, also impact -//! the DHCP renew timeout. Range: [0-0xffffffff] seconds, -//! 0 or 0xffffffff == infinity lease timeout. -//! Resolution:10 seconds. Influence: only after -//! reconnecting to the AP. -//! Minimal bound value: MIN_TIMER_VAL_SECONDS - 20 seconds. -//! The parameter is saved into the CC3000 NVMEM. -//! The default value on CC3000 is 14400 seconds. -//! -//! @param aucARP ARP refresh timeout, if ARP entry is not updated by -//! incoming packet, the ARP entry will be deleted by -//! the end of the timeout. -//! Range: [0-0xffffffff] seconds, 0 == infinity ARP timeout -//! Resolution: 10 seconds. Influence: on runtime. -//! Minimal bound value: MIN_TIMER_VAL_SECONDS - 20 seconds -//! The parameter is saved into the CC3000 NVMEM. -//! The default value on CC3000 is 3600 seconds. -//! -//! @param aucKeepalive Keepalive event sent by the end of keepalive timeout -//! Range: [0-0xffffffff] seconds, 0 == infinity timeout -//! Resolution: 10 seconds. -//! Influence: on runtime. -//! Minimal bound value: MIN_TIMER_VAL_SECONDS - 20 sec -//! The parameter is saved into the CC3000 NVMEM. -//! The default value on CC3000 is 10 seconds. -//! -//! @param aucInactivity Socket inactivity timeout, socket timeout is -//! refreshed by incoming or outgoing packet, by the -//! end of the socket timeout the socket will be closed -//! Range: [0-0xffffffff] sec, 0 == infinity timeout. -//! Resolution: 10 seconds. Influence: on runtime. -//! Minimal bound value: MIN_TIMER_VAL_SECONDS - 20 sec -//! The parameter is saved into the CC3000 NVMEM. -//! The default value on CC3000 is 60 seconds. -//! -//! @return return on success 0, otherwise error. -//! -//! @brief Set new timeout values. Function set new timeout values for: -//! DHCP lease timeout, ARP refresh timeout, keepalive event -//! timeout and socket inactivity timeout -//! -//! @note If a parameter set to non zero value which is less than 20s, -//! it will be set automatically to 20s. -//! -//***************************************************************************** - #ifndef CC3000_TINY_DRIVER -extern long netapp_timeout_values(unsigned long *aucDHCP, unsigned long *aucARP,unsigned long *aucKeepalive, unsigned long *aucInactivity); -#endif - -//***************************************************************************** -// -//! netapp_ping_send -//! -//! @param ip destination IP address -//! @param pingAttempts number of echo requests to send -//! @param pingSize send buffer size which may be up to 1400 bytes -//! @param pingTimeout Time to wait for a response,in milliseconds. -//! -//! @return return on success 0, otherwise error. -//! -//! @brief send ICMP ECHO_REQUEST to network hosts -//! -//! @note If an operation finished successfully asynchronous ping report -//! event will be generated. The report structure is as defined -//! by structure netapp_pingreport_args_t. -//! -//! @warning Calling this function while a previous Ping Requests are in -//! progress will stop the previous ping request. -//***************************************************************************** - - #ifndef CC3000_TINY_DRIVER -extern long netapp_ping_send(uint32_t *ip, uint32_t ulPingAttempts, uint32_t ulPingSize, uint32_t ulPingTimeout); -#endif - -//***************************************************************************** -// -//! netapp_ping_stop -//! -//! @param none -//! -//! @return On success, zero is returned. On error, -1 is returned. -//! -//! @brief Stop any ping request. -//! -//! -//***************************************************************************** - -#ifndef CC3000_TINY_DRIVER -extern long netapp_ping_stop(); -#endif -//***************************************************************************** -// -//! netapp_ping_report -//! -//! @param none -//! -//! @return none -//! -//! @brief Request for ping status. This API triggers the CC3000 to send -//! asynchronous events: HCI_EVNT_WLAN_ASYNC_PING_REPORT. -//! This event will carry the report structure: -//! netapp_pingreport_args_t. This structure is filled in with ping -//! results up till point of triggering API. -//! netapp_pingreport_args_t:\n packets_sent - echo sent, -//! packets_received - echo reply, min_round_time - minimum -//! round time, max_round_time - max round time, -//! avg_round_time - average round time -//! -//! @note When a ping operation is not active, the returned structure -//! fields are 0. -//! -//***************************************************************************** -#ifndef CC3000_TINY_DRIVER -extern void netapp_ping_report(); -#endif - - -//***************************************************************************** -// -//! netapp_ipconfig -//! -//! @param[out] ipconfig This argument is a pointer to a -//! tNetappIpconfigRetArgs structure. This structure is -//! filled in with the network interface configuration. -//! tNetappIpconfigRetArgs:\n aucIP - ip address, -//! aucSubnetMask - mask, aucDefaultGateway - default -//! gateway address, aucDHCPServer - dhcp server address -//! aucDNSServer - dns server address, uaMacAddr - mac -//! address, uaSSID - connected AP ssid -//! -//! @return none -//! -//! @brief Obtain the CC3000 Network interface information. -//! Note that the information is available only after the WLAN -//! connection was established. Calling this function before -//! associated, will cause non-defined values to be returned. -//! -//! @note The function is useful for figuring out the IP Configuration of -//! the device when DHCP is used and for figuring out the SSID of -//! the Wireless network the device is associated with. -//! -//***************************************************************************** - -extern void netapp_ipconfig( tNetappIpconfigRetArgs * ipconfig ); - - -//***************************************************************************** -// -//! netapp_arp_flush -//! -//! @param none -//! -//! @return none -//! -//! @brief Flushes ARP table -//! -//***************************************************************************** - -#ifndef CC3000_TINY_DRIVER -extern long netapp_arp_flush(); -#endif - - -//***************************************************************************** -// -//! netapp_set_debug_level -//! -//! @param[in] level debug level. Bitwise [0-8], -//! 0(disable)or 1(enable).\n Bitwise map: 0 - Critical -//! message, 1 information message, 2 - core messages, 3 - -//! HCI messages, 4 - Network stack messages, 5 - wlan -//! messages, 6 - wlan driver messages, 7 - epprom messages, -//! 8 - general messages. Default: 0x13f. Saved: no -//! -//! @return On success, zero is returned. On error, -1 is returned -//! -//! @brief Debug messages sent via the UART debug channel, this function -//! enable/disable the debug level -//! -//***************************************************************************** - - -#ifndef CC3000_TINY_DRIVER -long netapp_set_debug_level(unsigned long ulLevel); -#endif -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - - - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif // __cplusplus - -#endif // __NETAPP_H__ - diff --git a/stm/cc3k/nvmem.c b/stm/cc3k/nvmem.c deleted file mode 100644 index 411362008..000000000 --- a/stm/cc3k/nvmem.c +++ /dev/null @@ -1,366 +0,0 @@ -/***************************************************************************** -* -* nvmem.c - CC3000 Host Driver Implementation. -* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ -* -* Adapted for use with the Arduino/AVR by KTOWN (Kevin Townsend) -* & Limor Fried for Adafruit Industries -* This library works with the Adafruit CC3000 breakout -* ----> https://www.adafruit.com/products/1469 -* Adafruit invests time and resources providing this open source code, -* please support Adafruit and open-source hardware by purchasing -* products from Adafruit! -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*****************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup nvmem_api -//! @{ -// -//***************************************************************************** - -#include -#include - -#include "nvmem.h" -#include "hci.h" -#include "socket.h" -#include "evnt_handler.h" -#include "ccdebug.h" - -//***************************************************************************** -// -// Prototypes for the structures for APIs. -// -//***************************************************************************** - -#define NVMEM_READ_PARAMS_LEN (12) -#define NVMEM_CREATE_PARAMS_LEN (8) -#define NVMEM_WRITE_PARAMS_LEN (16) - -//***************************************************************************** -// -//! nvmem_read -//! -//! @param ulFileId nvmem file id:\n -//! NVMEM_NVS_FILEID, NVMEM_NVS_SHADOW_FILEID, -//! NVMEM_WLAN_CONFIG_FILEID, NVMEM_WLAN_CONFIG_SHADOW_FILEID, -//! NVMEM_WLAN_DRIVER_SP_FILEID, NVMEM_WLAN_FW_SP_FILEID, -//! NVMEM_MAC_FILEID, NVMEM_FRONTEND_VARS_FILEID, -//! NVMEM_IP_CONFIG_FILEID, NVMEM_IP_CONFIG_SHADOW_FILEID, -//! NVMEM_BOOTLOADER_SP_FILEID, NVMEM_RM_FILEID, -//! and user files 12-15. -//! @param ulLength number of bytes to read -//! @param ulOffset ulOffset in file from where to read -//! @param buff output buffer pointer -//! -//! @return number of bytes read, otherwise error. -//! -//! @brief Reads data from the file referred by the ulFileId parameter. -//! Reads data from file ulOffset till length. Err if the file can't -//! be used, is invalid, or if the read is out of bounds. -//! -//***************************************************************************** - -signed long -nvmem_read(unsigned long ulFileId, unsigned long ulLength, unsigned long ulOffset, unsigned char *buff) -{ - unsigned char ucStatus = 0xFF; - unsigned char *ptr; - unsigned char *args; - - ptr = tSLInformation.pucTxCommandBuffer; - args = (ptr + HEADERS_SIZE_CMD); - - // Fill in HCI packet structure - args = UINT32_TO_STREAM(args, ulFileId); - args = UINT32_TO_STREAM(args, ulLength); - args = UINT32_TO_STREAM(args, ulOffset); - - // Initiate a HCI command - hci_command_send(HCI_CMND_NVMEM_READ, ptr, NVMEM_READ_PARAMS_LEN); - SimpleLinkWaitEvent(HCI_CMND_NVMEM_READ, &ucStatus); - - // In case there is data - read it - even if an error code is returned - // Note: It is the user responsibility to ignore the data in case of an error code - - // Wait for the data in a synchronous way. Here we assume that the buffer is - // big enough to store also parameters of nvmem - - SimpleLinkWaitData(buff, 0, 0); - - return(ucStatus); -} - -//***************************************************************************** -// -//! nvmem_write -//! -//! @param ulFileId nvmem file id:\n -//! NVMEM_WLAN_DRIVER_SP_FILEID, NVMEM_WLAN_FW_SP_FILEID, -//! NVMEM_MAC_FILEID, NVMEM_BOOTLOADER_SP_FILEID, -//! and user files 12-15. -//! @param ulLength number of bytes to write -//! @param ulEntryOffset offset in file to start write operation from -//! @param buff data to write -//! -//! @return on success 0, error otherwise. -//! -//! @brief Write data to nvmem. -//! writes data to file referred by the ulFileId parameter. -//! Writes data to file ulOffset till ulLength.The file id will be -//! marked invalid till the write is done. The file entry doesn't -//! need to be valid - only allocated. -//! -//***************************************************************************** - -signed long -nvmem_write(unsigned long ulFileId, unsigned long ulLength, unsigned long - ulEntryOffset, unsigned char *buff) -{ - long iRes; - unsigned char *ptr; - unsigned char *args; - - iRes = EFAIL; - - ptr = tSLInformation.pucTxCommandBuffer; - args = (ptr + SPI_HEADER_SIZE + HCI_DATA_CMD_HEADER_SIZE); - - // Fill in HCI packet structure - args = UINT32_TO_STREAM(args, ulFileId); - args = UINT32_TO_STREAM(args, 12); - args = UINT32_TO_STREAM(args, ulLength); - args = UINT32_TO_STREAM(args, ulEntryOffset); - - memcpy((ptr + SPI_HEADER_SIZE + HCI_DATA_CMD_HEADER_SIZE + - NVMEM_WRITE_PARAMS_LEN),buff,ulLength); -#if (DEBUG_MODE == 1) - PRINT_F("Writing:\t"); - for (uint8_t i=0; i= SP_PORTION_SIZE)) - { -#if (DEBUG_MODE == 1) - PRINT_F("Writing: "); printDec16(offset); PRINT_F("\t"); - for (uint8_t i=0; i https://www.adafruit.com/products/1469 -* Adafruit invests time and resources providing this open source code, -* please support Adafruit and open-source hardware by purchasing -* products from Adafruit! -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*****************************************************************************/ -#ifndef __NVRAM_H__ -#define __NVRAM_H__ - -#include "cc3000_common.h" - - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" { -#endif - - -//***************************************************************************** -// -//! \addtogroup nvmem_api -//! @{ -// -//***************************************************************************** - -/**************************************************************************** -** -** Definitions for File IDs -** -****************************************************************************/ -/* NVMEM file ID - system files*/ -#define NVMEM_NVS_FILEID (0) -#define NVMEM_NVS_SHADOW_FILEID (1) -#define NVMEM_WLAN_CONFIG_FILEID (2) -#define NVMEM_WLAN_CONFIG_SHADOW_FILEID (3) -#define NVMEM_WLAN_DRIVER_SP_FILEID (4) -#define NVMEM_WLAN_FW_SP_FILEID (5) -#define NVMEM_MAC_FILEID (6) -#define NVMEM_FRONTEND_VARS_FILEID (7) -#define NVMEM_IP_CONFIG_FILEID (8) -#define NVMEM_IP_CONFIG_SHADOW_FILEID (9) -#define NVMEM_BOOTLOADER_SP_FILEID (10) -#define NVMEM_RM_FILEID (11) - -/* NVMEM file ID - user files*/ -#define NVMEM_AES128_KEY_FILEID (12) -#define NVMEM_SHARED_MEM_FILEID (13) - -/* max entry in order to invalid nvmem */ -#define NVMEM_MAX_ENTRY (16) - - -//***************************************************************************** -// -//! nvmem_read -//! -//! @param ulFileId nvmem file id:\n -//! NVMEM_NVS_FILEID, NVMEM_NVS_SHADOW_FILEID, -//! NVMEM_WLAN_CONFIG_FILEID, NVMEM_WLAN_CONFIG_SHADOW_FILEID, -//! NVMEM_WLAN_DRIVER_SP_FILEID, NVMEM_WLAN_FW_SP_FILEID, -//! NVMEM_MAC_FILEID, NVMEM_FRONTEND_VARS_FILEID, -//! NVMEM_IP_CONFIG_FILEID, NVMEM_IP_CONFIG_SHADOW_FILEID, -//! NVMEM_BOOTLOADER_SP_FILEID, NVMEM_RM_FILEID, -//! and user files 12-15. -//! @param ulLength number of bytes to read -//! @param ulOffset ulOffset in file from where to read -//! @param buff output buffer pointer -//! -//! @return number of bytes read, otherwise error. -//! -//! @brief Reads data from the file referred by the ulFileId parameter. -//! Reads data from file ulOffset till length. Err if the file can't -//! be used, is invalid, or if the read is out of bounds. -//! -//***************************************************************************** - -extern signed long nvmem_read(unsigned long file_id, unsigned long length, unsigned long offset, unsigned char *buff); - -//***************************************************************************** -// -//! nvmem_write -//! -//! @param ulFileId nvmem file id:\n -//! NVMEM_WLAN_DRIVER_SP_FILEID, NVMEM_WLAN_FW_SP_FILEID, -//! NVMEM_MAC_FILEID, NVMEM_BOOTLOADER_SP_FILEID, -//! and user files 12-15. -//! @param ulLength number of bytes to write -//! @param ulEntryOffset offset in file to start write operation from -//! @param buff data to write -//! -//! @return on success 0, error otherwise. -//! -//! @brief Write data to nvmem. -//! writes data to file referred by the ulFileId parameter. -//! Writes data to file ulOffset till ulLength.The file id will be -//! marked invalid till the write is done. The file entry doesn't -//! need to be valid - only allocated. -//! -//***************************************************************************** - -extern signed long nvmem_write(unsigned long ulFileId, unsigned long ulLength, unsigned long ulEntryOffset, unsigned char *buff); - - -//***************************************************************************** -// -//! nvmem_set_mac_address -//! -//! @param mac mac address to be set -//! -//! @return on success 0, error otherwise. -//! -//! @brief Write MAC address to EEPROM. -//! mac address as appears over the air (OUI first) -//! -//***************************************************************************** -extern unsigned char nvmem_set_mac_address(unsigned char *mac); - - -//***************************************************************************** -// -//! nvmem_get_mac_address -//! -//! @param[out] mac mac address -//! -//! @return on success 0, error otherwise. -//! -//! @brief Read MAC address from EEPROM. -//! mac address as appears over the air (OUI first) -//! -//***************************************************************************** -extern unsigned char nvmem_get_mac_address(unsigned char *mac); - - -//***************************************************************************** -// -//! nvmem_write_patch -//! -//! @param ulFileId nvmem file id:\n -//! NVMEM_WLAN_DRIVER_SP_FILEID, NVMEM_WLAN_FW_SP_FILEID, -//! @param spLength number of bytes to write -//! @param spData SP data to write -//! -//! @return on success 0, error otherwise. -//! -//! @brief program a patch to a specific file ID. -//! The SP data is assumed to be organized in 2-dimensional. -//! Each line is SP_PORTION_SIZE bytes long. Actual programming is -//! applied in SP_PORTION_SIZE bytes portions. -//! -//***************************************************************************** -extern unsigned char nvmem_write_patch(unsigned long ulFileId, unsigned long spLength, const unsigned char *spData); - - -//***************************************************************************** -// -//! nvmem_read_sp_version -//! -//! @param[out] patchVer first number indicates package ID and the second -//! number indicates package build number -//! -//! @return on success 0, error otherwise. -//! -//! @brief Read patch version. read package version (WiFi FW patch, -//! driver-supplicant-NS patch, bootloader patch) -//! -//***************************************************************************** -#ifndef CC3000_TINY_DRIVER -extern unsigned char nvmem_read_sp_version(unsigned char* patchVer); -#endif - -//***************************************************************************** -// -//! nvmem_create_entry -//! -//! @param ulFileId nvmem file Id:\n -//! * NVMEM_AES128_KEY_FILEID: 12 -//! * NVMEM_SHARED_MEM_FILEID: 13 -//! * and fileIDs 14 and 15 -//! @param ulNewLen entry ulLength -//! -//! @return on success 0, error otherwise. -//! -//! @brief Create new file entry and allocate space on the NVMEM. -//! Applies only to user files. -//! Modify the size of file. -//! If the entry is unallocated - allocate it to size -//! ulNewLen (marked invalid). -//! If it is allocated then deallocate it first. -//! To just mark the file as invalid without resizing - -//! set ulNewLen=0. -//! -//***************************************************************************** -extern int8_t nvmem_create_entry(unsigned long file_id, unsigned long newlen); - - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** - - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - - -#ifdef __cplusplus -} -#endif // __cplusplus - -#endif // __NVRAM_H__ diff --git a/stm/cc3k/pybcc3k.c b/stm/cc3k/pybcc3k.c deleted file mode 100644 index 9b7113869..000000000 --- a/stm/cc3k/pybcc3k.c +++ /dev/null @@ -1,204 +0,0 @@ -#include - -#include "stm32f4xx_rcc.h" -#include -#include "stm32f4xx_gpio.h" -#include -#include -#include "stm32f4xx_spi.h" - -#include "misc.h" -#include "systick.h" - -#include "ccdebug.h" -#include "pybcc3k.h" - -// IRQ on PA14, input, pulled up, active low -// EN on PC7, output, active high -// CS on PC6, output, active low -// SPI2 on PB15=MOSI, PB14=MISO, PB13=SCK -// SCK for CC3000: max 16MHz, low when idle, data sampled on falling edge - -// TODO this could be really wrong wrt calibration -void pyb_delay_us(uint32_t usec) { - volatile uint32_t count = 0; - const uint32_t utime = (160 * usec / 5); - do { - if (++count > utime) { - return; - } - } while (1); -} - -void pyb_cc3000_set_en(int val) { - DEBUG_printf("pyb_cc3000_set_en val=%d\n", val); - if (val) { - GPIOC->BSRRL = GPIO_Pin_7; // set pin high - } else { - GPIOC->BSRRH = GPIO_Pin_7; // set pin low - } -} - -void pyb_cc3000_set_cs(int val) { - DEBUG_printf("pyb_cc3000_set_cs val=%d\n", val); - if (val) { - GPIOC->BSRRL = GPIO_Pin_6; // set pin high - } else { - GPIOC->BSRRH = GPIO_Pin_6; // set pin low - } -} - -int pyb_cc3000_get_irq(void) { - if ((GPIOA->IDR & GPIO_Pin_14) == 0) { - return 0; - } else { - return 1; - } -} - -uint32_t exti14_enabled = 0; // TODO hack; do it properly! -uint32_t exti14_missed = 0; // TODO hack; do it properly! - -void pyb_cc3000_enable_irq(void) { - DEBUG_printf("pyb_cc3000_enable_irq: en=%lu miss=%lu\n", exti14_enabled, exti14_missed); - if (exti14_missed) { - /* doesn't look like this is needed - DEBUG_printf("pyb_cc3000_enable_irq: handling missed IRQ\n"); - // TODO hack if we have a pending IRQ - extern void SpiIntGPIOHandler(void); - SpiIntGPIOHandler(); - */ - exti14_missed = 0; - } - exti14_enabled = 1; -} - -void pyb_cc3000_disable_irq(void) { - DEBUG_printf("pyb_cc3000_disable_irq: en=%lu miss=%lu\n", exti14_enabled, exti14_missed); - exti14_enabled = 0; -} - -void pyb_cc3000_pause_spi(void) { - DEBUG_printf("pyb_cc3000_pause_spi\n"); - exti14_enabled = 0; -} - -void pyb_cc3000_resume_spi(void) { - DEBUG_printf("pyb_cc3000_resume_spi\n"); - exti14_enabled = 1; -} - -static void EXTILine14_Config(void) { - /* Enable SYSCFG clock */ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); - - /* Configure PA14 pin as pulled-up input */ - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_14; - GPIO_Init(GPIOA, &GPIO_InitStructure); - - /* Connect EXTI Line14 to PA14 pin */ - SYSCFG_EXTILineConfig(EXTI_PortSourceGPIOA, EXTI_PinSource14); - - /* Configure EXTI Line14, falling edge */ - EXTI_InitTypeDef EXTI_InitStructure; - EXTI_InitStructure.EXTI_Line = EXTI_Line14; - EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; - EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling; - EXTI_InitStructure.EXTI_LineCmd = ENABLE; - EXTI_Init(&EXTI_InitStructure); - - /* Enable and set EXTI15_10 Interrupt to the lowest priority */ - NVIC_InitTypeDef NVIC_InitStructure; - NVIC_InitStructure.NVIC_IRQChannel = EXTI15_10_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); -} - -void pyb_cc3000_spi_init(void) { - DEBUG_printf("pyb_cc3000_spi_init\n"); - - // enable SPI clock - RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE); - - // GPIO clocks should already be enabled - - /*!< SPI pins configuration *************************************************/ - - /*!< Connect SPI pins to AF5 */ - GPIO_PinAFConfig(GPIOB, GPIO_PinSource13, GPIO_AF_SPI2); - GPIO_PinAFConfig(GPIOB, GPIO_PinSource14, GPIO_AF_SPI2); - GPIO_PinAFConfig(GPIOB, GPIO_PinSource15, GPIO_AF_SPI2); - - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN; - GPIO_Init(GPIOB, &GPIO_InitStructure); - - /* - inf.baudRate = 100000; // FIXME - just slow for debug - inf.spiMode = SPIF_SPI_MODE_1; // Mode 1 CPOL= 0 CPHA= 1 - */ - - /*!< SPI configuration */ - SPI_InitTypeDef SPI_InitStructure; - SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; - SPI_InitStructure.SPI_Mode = SPI_Mode_Master; - SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; // should be correct - SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; // clock is low when idle - SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge; // data latched on second edge, which is falling edge for low-idle - SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; // software control - SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_8; // clock freq = f_PCLK / this_prescale_value - SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; // should be correct - SPI_InitStructure.SPI_CRCPolynomial = 7; // ? - SPI_Init(SPI2, &SPI_InitStructure); - - /*!< Enable the SPI */ - SPI_Cmd(SPI2, ENABLE); - - /* - // WLAN CS, EN and WALN IRQ Configuration - jshSetPinStateIsManual(WLAN_CS_PIN, false); - jshPinOutput(WLAN_CS_PIN, 1); // de-assert CS - jshSetPinStateIsManual(WLAN_EN_PIN, false); - jshPinOutput(WLAN_EN_PIN, 0); // disable WLAN - jshSetPinStateIsManual(WLAN_IRQ_PIN, true); - jshPinSetState(WLAN_IRQ_PIN, JSHPINSTATE_GPIO_IN_PULLUP); // flip into read mode with pullup - */ - // configure wlan CS and EN pins - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_25MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(GPIOC, &GPIO_InitStructure); - pyb_cc3000_set_cs(1); // de-assert CS - pyb_cc3000_set_en(0); // disable wlan - - // configure EXTI on A14 - EXTILine14_Config(); - - // wait a little (ensure that WLAN takes effect) - sys_tick_delay_ms(500); // force a 500ms delay! FIXME -} - -uint8_t pyb_cc3000_spi_send(uint8_t val) { - /*!< Loop while DR register in not emplty */ - while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_TXE) == RESET); - - /*!< Send byte through the SPI1 peripheral */ - SPI_I2S_SendData(SPI2, val); - - /*!< Wait to receive a byte */ - while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_RXNE) == RESET); - - /*!< Return the byte read from the SPI bus */ - return SPI_I2S_ReceiveData(SPI2); -} diff --git a/stm/cc3k/pybcc3k.h b/stm/cc3k/pybcc3k.h deleted file mode 100644 index 5e6c644d4..000000000 --- a/stm/cc3k/pybcc3k.h +++ /dev/null @@ -1,12 +0,0 @@ -void pyb_delay_us(uint32_t us); - -void pyb_cc3000_set_en(int val); -void pyb_cc3000_set_cs(int val); -int pyb_cc3000_get_irq(void); -void pyb_cc3000_enable_irq(void); -void pyb_cc3000_disable_irq(void); -void pyb_cc3000_pause_spi(void); -void pyb_cc3000_resume_spi(void); - -void pyb_cc3000_spi_init(void); -uint8_t pyb_cc3000_spi_send(uint8_t val); diff --git a/stm/cc3k/security.c b/stm/cc3k/security.c deleted file mode 100644 index c12aee370..000000000 --- a/stm/cc3k/security.c +++ /dev/null @@ -1,535 +0,0 @@ -/***************************************************************************** -* -* security.c - CC3000 Host Driver Implementation. -* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*****************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup security_api -//! @{ -// -//***************************************************************************** - -#include - -#include "security.h" - -#ifndef CC3000_UNENCRYPTED_SMART_CONFIG -// foreward sbox -const unsigned char sbox[256] = { -//0 1 2 3 4 5 6 7 8 9 A B C D E F -0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76, //0 -0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0, //1 -0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc, 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15, //2 -0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75, //3 -0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84, //4 -0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf, //5 -0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8, //6 -0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5, 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2, //7 -0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73, //8 -0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb, //9 -0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79, //A -0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9, 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08, //B -0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a, //C -0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e, //D -0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf, //E -0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16 }; //F -// inverse sbox -const unsigned char rsbox[256] = -{ 0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38, 0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb -, 0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87, 0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb -, 0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d, 0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e -, 0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2, 0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25 -, 0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16, 0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92 -, 0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda, 0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84 -, 0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a, 0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06 -, 0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02, 0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b -, 0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea, 0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73 -, 0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85, 0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e -, 0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89, 0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b -, 0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20, 0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4 -, 0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31, 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f -, 0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d, 0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef -, 0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0, 0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61 -, 0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26, 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d }; -// round constant -const unsigned char Rcon[11] = { - 0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36}; - - -unsigned char expandedKey[176]; - -//***************************************************************************** -// -//! expandKey -//! -//! @param key AES128 key - 16 bytes -//! @param expandedKey expanded AES128 key -//! -//! @return none -//! -//! @brief expend a 16 bytes key for AES128 implementation -//! -//***************************************************************************** - -void expandKey(unsigned char *expandedKey, - unsigned char *key) -{ - unsigned short ii, buf1; - for (ii=0;ii<16;ii++) - expandedKey[ii] = key[ii]; - for (ii=1;ii<11;ii++){ - buf1 = expandedKey[ii*16 - 4]; - expandedKey[ii*16 + 0] = sbox[expandedKey[ii*16 - 3]]^expandedKey[(ii-1)*16 + 0]^Rcon[ii]; - expandedKey[ii*16 + 1] = sbox[expandedKey[ii*16 - 2]]^expandedKey[(ii-1)*16 + 1]; - expandedKey[ii*16 + 2] = sbox[expandedKey[ii*16 - 1]]^expandedKey[(ii-1)*16 + 2]; - expandedKey[ii*16 + 3] = sbox[buf1 ]^expandedKey[(ii-1)*16 + 3]; - expandedKey[ii*16 + 4] = expandedKey[(ii-1)*16 + 4]^expandedKey[ii*16 + 0]; - expandedKey[ii*16 + 5] = expandedKey[(ii-1)*16 + 5]^expandedKey[ii*16 + 1]; - expandedKey[ii*16 + 6] = expandedKey[(ii-1)*16 + 6]^expandedKey[ii*16 + 2]; - expandedKey[ii*16 + 7] = expandedKey[(ii-1)*16 + 7]^expandedKey[ii*16 + 3]; - expandedKey[ii*16 + 8] = expandedKey[(ii-1)*16 + 8]^expandedKey[ii*16 + 4]; - expandedKey[ii*16 + 9] = expandedKey[(ii-1)*16 + 9]^expandedKey[ii*16 + 5]; - expandedKey[ii*16 +10] = expandedKey[(ii-1)*16 +10]^expandedKey[ii*16 + 6]; - expandedKey[ii*16 +11] = expandedKey[(ii-1)*16 +11]^expandedKey[ii*16 + 7]; - expandedKey[ii*16 +12] = expandedKey[(ii-1)*16 +12]^expandedKey[ii*16 + 8]; - expandedKey[ii*16 +13] = expandedKey[(ii-1)*16 +13]^expandedKey[ii*16 + 9]; - expandedKey[ii*16 +14] = expandedKey[(ii-1)*16 +14]^expandedKey[ii*16 +10]; - expandedKey[ii*16 +15] = expandedKey[(ii-1)*16 +15]^expandedKey[ii*16 +11]; - } - -} - -//***************************************************************************** -// -//! galois_mul2 -//! -//! @param value argument to multiply -//! -//! @return multiplied argument -//! -//! @brief multiply by 2 in the galois field -//! -//***************************************************************************** - -unsigned char galois_mul2(unsigned char value) -{ - if (value>>7) - { - value = value << 1; - return (value^0x1b); - } else - return value<<1; -} - -//***************************************************************************** -// -//! aes_encr -//! -//! @param[in] expandedKey expanded AES128 key -//! @param[in/out] state 16 bytes of plain text and cipher text -//! -//! @return none -//! -//! @brief internal implementation of AES128 encryption. -//! straight forward aes encryption implementation -//! first the group of operations -//! - addRoundKey -//! - subbytes -//! - shiftrows -//! - mixcolums -//! is executed 9 times, after this addroundkey to finish the 9th -//! round, after that the 10th round without mixcolums -//! no further subfunctions to save cycles for function calls -//! no structuring with "for (....)" to save cycles. -//! -//! -//***************************************************************************** - -void aes_encr(unsigned char *state, unsigned char *expandedKey) -{ - unsigned char buf1, buf2, buf3, round; - - for (round = 0; round < 9; round ++){ - // addroundkey, sbox and shiftrows - // row 0 - state[ 0] = sbox[(state[ 0] ^ expandedKey[(round*16) ])]; - state[ 4] = sbox[(state[ 4] ^ expandedKey[(round*16) + 4])]; - state[ 8] = sbox[(state[ 8] ^ expandedKey[(round*16) + 8])]; - state[12] = sbox[(state[12] ^ expandedKey[(round*16) + 12])]; - // row 1 - buf1 = state[1] ^ expandedKey[(round*16) + 1]; - state[ 1] = sbox[(state[ 5] ^ expandedKey[(round*16) + 5])]; - state[ 5] = sbox[(state[ 9] ^ expandedKey[(round*16) + 9])]; - state[ 9] = sbox[(state[13] ^ expandedKey[(round*16) + 13])]; - state[13] = sbox[buf1]; - // row 2 - buf1 = state[2] ^ expandedKey[(round*16) + 2]; - buf2 = state[6] ^ expandedKey[(round*16) + 6]; - state[ 2] = sbox[(state[10] ^ expandedKey[(round*16) + 10])]; - state[ 6] = sbox[(state[14] ^ expandedKey[(round*16) + 14])]; - state[10] = sbox[buf1]; - state[14] = sbox[buf2]; - // row 3 - buf1 = state[15] ^ expandedKey[(round*16) + 15]; - state[15] = sbox[(state[11] ^ expandedKey[(round*16) + 11])]; - state[11] = sbox[(state[ 7] ^ expandedKey[(round*16) + 7])]; - state[ 7] = sbox[(state[ 3] ^ expandedKey[(round*16) + 3])]; - state[ 3] = sbox[buf1]; - - // mixcolums ////////// - // col1 - buf1 = state[0] ^ state[1] ^ state[2] ^ state[3]; - buf2 = state[0]; - buf3 = state[0]^state[1]; buf3=galois_mul2(buf3); state[0] = state[0] ^ buf3 ^ buf1; - buf3 = state[1]^state[2]; buf3=galois_mul2(buf3); state[1] = state[1] ^ buf3 ^ buf1; - buf3 = state[2]^state[3]; buf3=galois_mul2(buf3); state[2] = state[2] ^ buf3 ^ buf1; - buf3 = state[3]^buf2; buf3=galois_mul2(buf3); state[3] = state[3] ^ buf3 ^ buf1; - // col2 - buf1 = state[4] ^ state[5] ^ state[6] ^ state[7]; - buf2 = state[4]; - buf3 = state[4]^state[5]; buf3=galois_mul2(buf3); state[4] = state[4] ^ buf3 ^ buf1; - buf3 = state[5]^state[6]; buf3=galois_mul2(buf3); state[5] = state[5] ^ buf3 ^ buf1; - buf3 = state[6]^state[7]; buf3=galois_mul2(buf3); state[6] = state[6] ^ buf3 ^ buf1; - buf3 = state[7]^buf2; buf3=galois_mul2(buf3); state[7] = state[7] ^ buf3 ^ buf1; - // col3 - buf1 = state[8] ^ state[9] ^ state[10] ^ state[11]; - buf2 = state[8]; - buf3 = state[8]^state[9]; buf3=galois_mul2(buf3); state[8] = state[8] ^ buf3 ^ buf1; - buf3 = state[9]^state[10]; buf3=galois_mul2(buf3); state[9] = state[9] ^ buf3 ^ buf1; - buf3 = state[10]^state[11]; buf3=galois_mul2(buf3); state[10] = state[10] ^ buf3 ^ buf1; - buf3 = state[11]^buf2; buf3=galois_mul2(buf3); state[11] = state[11] ^ buf3 ^ buf1; - // col4 - buf1 = state[12] ^ state[13] ^ state[14] ^ state[15]; - buf2 = state[12]; - buf3 = state[12]^state[13]; buf3=galois_mul2(buf3); state[12] = state[12] ^ buf3 ^ buf1; - buf3 = state[13]^state[14]; buf3=galois_mul2(buf3); state[13] = state[13] ^ buf3 ^ buf1; - buf3 = state[14]^state[15]; buf3=galois_mul2(buf3); state[14] = state[14] ^ buf3 ^ buf1; - buf3 = state[15]^buf2; buf3=galois_mul2(buf3); state[15] = state[15] ^ buf3 ^ buf1; - - } - // 10th round without mixcols - state[ 0] = sbox[(state[ 0] ^ expandedKey[(round*16) ])]; - state[ 4] = sbox[(state[ 4] ^ expandedKey[(round*16) + 4])]; - state[ 8] = sbox[(state[ 8] ^ expandedKey[(round*16) + 8])]; - state[12] = sbox[(state[12] ^ expandedKey[(round*16) + 12])]; - // row 1 - buf1 = state[1] ^ expandedKey[(round*16) + 1]; - state[ 1] = sbox[(state[ 5] ^ expandedKey[(round*16) + 5])]; - state[ 5] = sbox[(state[ 9] ^ expandedKey[(round*16) + 9])]; - state[ 9] = sbox[(state[13] ^ expandedKey[(round*16) + 13])]; - state[13] = sbox[buf1]; - // row 2 - buf1 = state[2] ^ expandedKey[(round*16) + 2]; - buf2 = state[6] ^ expandedKey[(round*16) + 6]; - state[ 2] = sbox[(state[10] ^ expandedKey[(round*16) + 10])]; - state[ 6] = sbox[(state[14] ^ expandedKey[(round*16) + 14])]; - state[10] = sbox[buf1]; - state[14] = sbox[buf2]; - // row 3 - buf1 = state[15] ^ expandedKey[(round*16) + 15]; - state[15] = sbox[(state[11] ^ expandedKey[(round*16) + 11])]; - state[11] = sbox[(state[ 7] ^ expandedKey[(round*16) + 7])]; - state[ 7] = sbox[(state[ 3] ^ expandedKey[(round*16) + 3])]; - state[ 3] = sbox[buf1]; - // last addroundkey - state[ 0]^=expandedKey[160]; - state[ 1]^=expandedKey[161]; - state[ 2]^=expandedKey[162]; - state[ 3]^=expandedKey[163]; - state[ 4]^=expandedKey[164]; - state[ 5]^=expandedKey[165]; - state[ 6]^=expandedKey[166]; - state[ 7]^=expandedKey[167]; - state[ 8]^=expandedKey[168]; - state[ 9]^=expandedKey[169]; - state[10]^=expandedKey[170]; - state[11]^=expandedKey[171]; - state[12]^=expandedKey[172]; - state[13]^=expandedKey[173]; - state[14]^=expandedKey[174]; - state[15]^=expandedKey[175]; -} - -//***************************************************************************** -// -//! aes_decr -//! -//! @param[in] expandedKey expanded AES128 key -//! @param[in\out] state 16 bytes of cipher text and plain text -//! -//! @return none -//! -//! @brief internal implementation of AES128 decryption. -//! straight forward aes decryption implementation -//! the order of substeps is the exact reverse of decryption -//! inverse functions: -//! - addRoundKey is its own inverse -//! - rsbox is inverse of sbox -//! - rightshift instead of leftshift -//! - invMixColumns = barreto + mixColumns -//! no further subfunctions to save cycles for function calls -//! no structuring with "for (....)" to save cycles -//! -//***************************************************************************** - -void aes_decr(unsigned char *state, unsigned char *expandedKey) -{ - unsigned char buf1, buf2, buf3; - signed char round; - round = 9; - - // initial addroundkey - state[ 0]^=expandedKey[160]; - state[ 1]^=expandedKey[161]; - state[ 2]^=expandedKey[162]; - state[ 3]^=expandedKey[163]; - state[ 4]^=expandedKey[164]; - state[ 5]^=expandedKey[165]; - state[ 6]^=expandedKey[166]; - state[ 7]^=expandedKey[167]; - state[ 8]^=expandedKey[168]; - state[ 9]^=expandedKey[169]; - state[10]^=expandedKey[170]; - state[11]^=expandedKey[171]; - state[12]^=expandedKey[172]; - state[13]^=expandedKey[173]; - state[14]^=expandedKey[174]; - state[15]^=expandedKey[175]; - - // 10th round without mixcols - state[ 0] = rsbox[state[ 0]] ^ expandedKey[(round*16) ]; - state[ 4] = rsbox[state[ 4]] ^ expandedKey[(round*16) + 4]; - state[ 8] = rsbox[state[ 8]] ^ expandedKey[(round*16) + 8]; - state[12] = rsbox[state[12]] ^ expandedKey[(round*16) + 12]; - // row 1 - buf1 = rsbox[state[13]] ^ expandedKey[(round*16) + 1]; - state[13] = rsbox[state[ 9]] ^ expandedKey[(round*16) + 13]; - state[ 9] = rsbox[state[ 5]] ^ expandedKey[(round*16) + 9]; - state[ 5] = rsbox[state[ 1]] ^ expandedKey[(round*16) + 5]; - state[ 1] = buf1; - // row 2 - buf1 = rsbox[state[ 2]] ^ expandedKey[(round*16) + 10]; - buf2 = rsbox[state[ 6]] ^ expandedKey[(round*16) + 14]; - state[ 2] = rsbox[state[10]] ^ expandedKey[(round*16) + 2]; - state[ 6] = rsbox[state[14]] ^ expandedKey[(round*16) + 6]; - state[10] = buf1; - state[14] = buf2; - // row 3 - buf1 = rsbox[state[ 3]] ^ expandedKey[(round*16) + 15]; - state[ 3] = rsbox[state[ 7]] ^ expandedKey[(round*16) + 3]; - state[ 7] = rsbox[state[11]] ^ expandedKey[(round*16) + 7]; - state[11] = rsbox[state[15]] ^ expandedKey[(round*16) + 11]; - state[15] = buf1; - - for (round = 8; round >= 0; round--){ - // barreto - //col1 - buf1 = galois_mul2(galois_mul2(state[0]^state[2])); - buf2 = galois_mul2(galois_mul2(state[1]^state[3])); - state[0] ^= buf1; state[1] ^= buf2; state[2] ^= buf1; state[3] ^= buf2; - //col2 - buf1 = galois_mul2(galois_mul2(state[4]^state[6])); - buf2 = galois_mul2(galois_mul2(state[5]^state[7])); - state[4] ^= buf1; state[5] ^= buf2; state[6] ^= buf1; state[7] ^= buf2; - //col3 - buf1 = galois_mul2(galois_mul2(state[8]^state[10])); - buf2 = galois_mul2(galois_mul2(state[9]^state[11])); - state[8] ^= buf1; state[9] ^= buf2; state[10] ^= buf1; state[11] ^= buf2; - //col4 - buf1 = galois_mul2(galois_mul2(state[12]^state[14])); - buf2 = galois_mul2(galois_mul2(state[13]^state[15])); - state[12] ^= buf1; state[13] ^= buf2; state[14] ^= buf1; state[15] ^= buf2; - // mixcolums ////////// - // col1 - buf1 = state[0] ^ state[1] ^ state[2] ^ state[3]; - buf2 = state[0]; - buf3 = state[0]^state[1]; buf3=galois_mul2(buf3); state[0] = state[0] ^ buf3 ^ buf1; - buf3 = state[1]^state[2]; buf3=galois_mul2(buf3); state[1] = state[1] ^ buf3 ^ buf1; - buf3 = state[2]^state[3]; buf3=galois_mul2(buf3); state[2] = state[2] ^ buf3 ^ buf1; - buf3 = state[3]^buf2; buf3=galois_mul2(buf3); state[3] = state[3] ^ buf3 ^ buf1; - // col2 - buf1 = state[4] ^ state[5] ^ state[6] ^ state[7]; - buf2 = state[4]; - buf3 = state[4]^state[5]; buf3=galois_mul2(buf3); state[4] = state[4] ^ buf3 ^ buf1; - buf3 = state[5]^state[6]; buf3=galois_mul2(buf3); state[5] = state[5] ^ buf3 ^ buf1; - buf3 = state[6]^state[7]; buf3=galois_mul2(buf3); state[6] = state[6] ^ buf3 ^ buf1; - buf3 = state[7]^buf2; buf3=galois_mul2(buf3); state[7] = state[7] ^ buf3 ^ buf1; - // col3 - buf1 = state[8] ^ state[9] ^ state[10] ^ state[11]; - buf2 = state[8]; - buf3 = state[8]^state[9]; buf3=galois_mul2(buf3); state[8] = state[8] ^ buf3 ^ buf1; - buf3 = state[9]^state[10]; buf3=galois_mul2(buf3); state[9] = state[9] ^ buf3 ^ buf1; - buf3 = state[10]^state[11]; buf3=galois_mul2(buf3); state[10] = state[10] ^ buf3 ^ buf1; - buf3 = state[11]^buf2; buf3=galois_mul2(buf3); state[11] = state[11] ^ buf3 ^ buf1; - // col4 - buf1 = state[12] ^ state[13] ^ state[14] ^ state[15]; - buf2 = state[12]; - buf3 = state[12]^state[13]; buf3=galois_mul2(buf3); state[12] = state[12] ^ buf3 ^ buf1; - buf3 = state[13]^state[14]; buf3=galois_mul2(buf3); state[13] = state[13] ^ buf3 ^ buf1; - buf3 = state[14]^state[15]; buf3=galois_mul2(buf3); state[14] = state[14] ^ buf3 ^ buf1; - buf3 = state[15]^buf2; buf3=galois_mul2(buf3); state[15] = state[15] ^ buf3 ^ buf1; - - // addroundkey, rsbox and shiftrows - // row 0 - state[ 0] = rsbox[state[ 0]] ^ expandedKey[(round*16) ]; - state[ 4] = rsbox[state[ 4]] ^ expandedKey[(round*16) + 4]; - state[ 8] = rsbox[state[ 8]] ^ expandedKey[(round*16) + 8]; - state[12] = rsbox[state[12]] ^ expandedKey[(round*16) + 12]; - // row 1 - buf1 = rsbox[state[13]] ^ expandedKey[(round*16) + 1]; - state[13] = rsbox[state[ 9]] ^ expandedKey[(round*16) + 13]; - state[ 9] = rsbox[state[ 5]] ^ expandedKey[(round*16) + 9]; - state[ 5] = rsbox[state[ 1]] ^ expandedKey[(round*16) + 5]; - state[ 1] = buf1; - // row 2 - buf1 = rsbox[state[ 2]] ^ expandedKey[(round*16) + 10]; - buf2 = rsbox[state[ 6]] ^ expandedKey[(round*16) + 14]; - state[ 2] = rsbox[state[10]] ^ expandedKey[(round*16) + 2]; - state[ 6] = rsbox[state[14]] ^ expandedKey[(round*16) + 6]; - state[10] = buf1; - state[14] = buf2; - // row 3 - buf1 = rsbox[state[ 3]] ^ expandedKey[(round*16) + 15]; - state[ 3] = rsbox[state[ 7]] ^ expandedKey[(round*16) + 3]; - state[ 7] = rsbox[state[11]] ^ expandedKey[(round*16) + 7]; - state[11] = rsbox[state[15]] ^ expandedKey[(round*16) + 11]; - state[15] = buf1; - } - -} - -//***************************************************************************** -// -//! aes_encrypt -//! -//! @param[in] key AES128 key of size 16 bytes -//! @param[in\out] state 16 bytes of plain text and cipher text -//! -//! @return none -//! -//! @brief AES128 encryption: -//! Given AES128 key and 16 bytes plain text, cipher text of 16 bytes -//! is computed. The AES implementation is in mode ECB (Electronic -//! Code Book). -//! -//! -//***************************************************************************** - -void aes_encrypt(unsigned char *state, - unsigned char *key) -{ - // expand the key into 176 bytes - expandKey(expandedKey, key); - aes_encr(state, expandedKey); -} - -//***************************************************************************** -// -//! aes_decrypt -//! -//! @param[in] key AES128 key of size 16 bytes -//! @param[in\out] state 16 bytes of cipher text and plain text -//! -//! @return none -//! -//! @brief AES128 decryption: -//! Given AES128 key and 16 bytes cipher text, plain text of 16 bytes -//! is computed The AES implementation is in mode ECB -//! (Electronic Code Book). -//! -//! -//***************************************************************************** - -void aes_decrypt(unsigned char *state, - unsigned char *key) -{ - expandKey(expandedKey, key); // expand the key into 176 bytes - aes_decr(state, expandedKey); -} - -//***************************************************************************** -// -//! aes_read_key -//! -//! @param[out] key AES128 key of size 16 bytes -//! -//! @return on success 0, error otherwise. -//! -//! @brief Reads AES128 key from EEPROM -//! Reads the AES128 key from fileID #12 in EEPROM -//! returns an error if the key does not exist. -//! -//! -//***************************************************************************** - -signed long aes_read_key(unsigned char *key) -{ - signed long returnValue; - - returnValue = nvmem_read(NVMEM_AES128_KEY_FILEID, AES128_KEY_SIZE, 0, key); - - return returnValue; -} - -//***************************************************************************** -// -//! aes_write_key -//! -//! @param[out] key AES128 key of size 16 bytes -//! -//! @return on success 0, error otherwise. -//! -//! @brief writes AES128 key from EEPROM -//! Writes the AES128 key to fileID #12 in EEPROM -//! -//! -//***************************************************************************** - -signed long aes_write_key(unsigned char *key) -{ - signed long returnValue; - - returnValue = nvmem_write(NVMEM_AES128_KEY_FILEID, AES128_KEY_SIZE, 0, key); - - return returnValue; -} - -#endif //CC3000_UNENCRYPTED_SMART_CONFIG - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/stm/cc3k/security.h b/stm/cc3k/security.h deleted file mode 100644 index 02214272e..000000000 --- a/stm/cc3k/security.h +++ /dev/null @@ -1,135 +0,0 @@ -/***************************************************************************** -* -* security.h - CC3000 Host Driver Implementation. -* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*****************************************************************************/ -#ifndef __SECURITY__ -#define __SECURITY__ - -#include "nvmem.h" - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" { -#endif - - -#define AES128_KEY_SIZE 16 - -#ifndef CC3000_UNENCRYPTED_SMART_CONFIG - - -//***************************************************************************** -// -//! aes_encrypt -//! -//! @param[in] key AES128 key of size 16 bytes -//! @param[in\out] state 16 bytes of plain text and cipher text -//! -//! @return none -//! -//! @brief AES128 encryption: -//! Given AES128 key and 16 bytes plain text, cipher text of 16 bytes -//! is computed. The AES implementation is in mode ECB (Electronic -//! Code Book). -//! -//! -//***************************************************************************** -extern void aes_encrypt(unsigned char *state, unsigned char *key); - -//***************************************************************************** -// -//! aes_decrypt -//! -//! @param[in] key AES128 key of size 16 bytes -//! @param[in\out] state 16 bytes of cipher text and plain text -//! -//! @return none -//! -//! @brief AES128 decryption: -//! Given AES128 key and 16 bytes cipher text, plain text of 16 bytes -//! is computed The AES implementation is in mode ECB -//! (Electronic Code Book). -//! -//! -//***************************************************************************** -extern void aes_decrypt(unsigned char *state, unsigned char *key); - - -//***************************************************************************** -// -//! aes_read_key -//! -//! @param[out] key AES128 key of size 16 bytes -//! -//! @return on success 0, error otherwise. -//! -//! @brief Reads AES128 key from EEPROM -//! Reads the AES128 key from fileID #12 in EEPROM -//! returns an error if the key does not exist. -//! -//! -//***************************************************************************** -extern signed long aes_read_key(unsigned char *key); - -//***************************************************************************** -// -//! aes_write_key -//! -//! @param[out] key AES128 key of size 16 bytes -//! -//! @return on success 0, error otherwise. -//! -//! @brief writes AES128 key from EEPROM -//! Writes the AES128 key to fileID #12 in EEPROM -//! -//! -//***************************************************************************** -extern signed long aes_write_key(unsigned char *key); - -#endif //CC3000_UNENCRYPTED_SMART_CONFIG - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif // __cplusplus - -#endif diff --git a/stm/cc3k/socket.c b/stm/cc3k/socket.c deleted file mode 100644 index cfccbd783..000000000 --- a/stm/cc3k/socket.c +++ /dev/null @@ -1,1190 +0,0 @@ -/***************************************************************************** -* -* socket.c - CC3000 Host Driver Implementation. -* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ -* -* Adapted for use with the Arduino/AVR by KTOWN (Kevin Townsend) -* & Limor Fried for Adafruit Industries -* This library works with the Adafruit CC3000 breakout -* ----> https://www.adafruit.com/products/1469 -* Adafruit invests time and resources providing this open source code, -* please support Adafruit and open-source hardware by purchasing -* products from Adafruit! -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*****************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup socket_api -//! @{ -// -//***************************************************************************** - -#include -#include // for memcpy - -#include "hci.h" -#include "socket.h" -#include "evnt_handler.h" -#include "netapp.h" -#include "ccdebug.h" - -extern int errno; - -//Enable this flag if and only if you must comply with BSD socket -//close() function -#ifdef _API_USE_BSD_CLOSE - #define close(sd) closesocket(sd) -#endif - -//Enable this flag if and only if you must comply with BSD socket read() and -//write() functions -#ifdef _API_USE_BSD_READ_WRITE - #define read(sd, buf, len, flags) recv(sd, buf, len, flags) - #define write(sd, buf, len, flags) send(sd, buf, len, flags) -#endif - -#define SOCKET_OPEN_PARAMS_LEN (12) -#define SOCKET_CLOSE_PARAMS_LEN (4) -#define SOCKET_ACCEPT_PARAMS_LEN (4) -#define SOCKET_BIND_PARAMS_LEN (20) -#define SOCKET_LISTEN_PARAMS_LEN (8) -#define SOCKET_GET_HOST_BY_NAME_PARAMS_LEN (9) -#define SOCKET_CONNECT_PARAMS_LEN (20) -#define SOCKET_SELECT_PARAMS_LEN (44) -#define SOCKET_SET_SOCK_OPT_PARAMS_LEN (20) -#define SOCKET_GET_SOCK_OPT_PARAMS_LEN (12) -#define SOCKET_RECV_FROM_PARAMS_LEN (12) -#define SOCKET_SENDTO_PARAMS_LEN (24) -#define SOCKET_MDNS_ADVERTISE_PARAMS_LEN (12) - - -// The legnth of arguments for the SEND command: sd + buff_offset + len + flags, -// while size of each parameter is 32 bit - so the total length is 16 bytes; - -#define HCI_CMND_SEND_ARG_LENGTH (16) - - -#define SELECT_TIMEOUT_MIN_MICRO_SECONDS 5000 - -#define HEADERS_SIZE_DATA (SPI_HEADER_SIZE + 5) - -#define SIMPLE_LINK_HCI_CMND_TRANSPORT_HEADER_SIZE (SPI_HEADER_SIZE + SIMPLE_LINK_HCI_CMND_HEADER_SIZE) - -#define MDNS_DEVICE_SERVICE_MAX_LENGTH (32) - - -//***************************************************************************** -// -//! HostFlowControlConsumeBuff -//! -//! @param sd socket descriptor -//! -//! @return 0 in case there are buffers available, -//! -1 in case of bad socket -//! -2 if there are no free buffers present (only when -//! SEND_NON_BLOCKING is enabled) -//! -//! @brief if SEND_NON_BLOCKING not define - block until have free buffer -//! becomes available, else return immediately with correct status -//! regarding the buffers available. -// -//***************************************************************************** -int -HostFlowControlConsumeBuff(int sd) -{ -#ifndef SEND_NON_BLOCKING - /* wait in busy loop */ - do - { - // In case last transmission failed then we will return the last failure - // reason here. - // Note that the buffer will not be allocated in this case - if (tSLInformation.slTransmitDataError != 0) - { - errno = tSLInformation.slTransmitDataError; - tSLInformation.slTransmitDataError = 0; - return errno; - } - - if(SOCKET_STATUS_ACTIVE != get_socket_active_status(sd)) - return -1; - } while(0 == tSLInformation.usNumberOfFreeBuffers); - - tSLInformation.usNumberOfFreeBuffers--; - - return 0; -#else - - // In case last transmission failed then we will return the last failure - // reason here. - // Note that the buffer will not be allocated in this case - if (tSLInformation.slTransmitDataError != 0) - { - errno = tSLInformation.slTransmitDataError; - tSLInformation.slTransmitDataError = 0; - return errno; - } - if(SOCKET_STATUS_ACTIVE != get_socket_active_status(sd)) - return -1; - - //If there are no available buffers, return -2. It is recommended to use - // select or receive to see if there is any buffer occupied with received data - // If so, call receive() to release the buffer. - if(0 == tSLInformation.usNumberOfFreeBuffers) - { - return -2; - } - else - { - tSLInformation.usNumberOfFreeBuffers--; - return 0; - } -#endif -} - -//***************************************************************************** -// -//! socket -//! -//! @param domain selects the protocol family which will be used for -//! communication. On this version only AF_INET is supported -//! @param type specifies the communication semantics. On this version -//! only SOCK_STREAM, SOCK_DGRAM, SOCK_RAW are supported -//! @param protocol specifies a particular protocol to be used with the -//! socket IPPROTO_TCP, IPPROTO_UDP or IPPROTO_RAW are -//! supported. -//! -//! @return On success, socket handle that is used for consequent socket -//! operations. On error, -1 is returned. -//! -//! @brief create an endpoint for communication -//! The socket function creates a socket that is bound to a specific -//! transport service provider. This function is called by the -//! application layer to obtain a socket handle. -// -//***************************************************************************** - -int -socket(long domain, long type, long protocol) -{ - long ret; - unsigned char *ptr, *args; - - ret = EFAIL; - ptr = tSLInformation.pucTxCommandBuffer; - args = (ptr + HEADERS_SIZE_CMD); - - // Fill in HCI packet structure - args = UINT32_TO_STREAM(args, domain); - args = UINT32_TO_STREAM(args, type); - args = UINT32_TO_STREAM(args, protocol); - - // Initiate a HCI command - hci_command_send(HCI_CMND_SOCKET, ptr, SOCKET_OPEN_PARAMS_LEN); - - // Since we are in blocking state - wait for event complete - SimpleLinkWaitEvent(HCI_CMND_SOCKET, &ret); - - // Process the event - errno = ret; - - set_socket_active_status(ret, SOCKET_STATUS_ACTIVE); - - return(ret); -} - -//***************************************************************************** -// -//! closesocket -//! -//! @param sd socket handle. -//! -//! @return On success, zero is returned. On error, -1 is returned. -//! -//! @brief The socket function closes a created socket. -// -//***************************************************************************** - -long -closesocket(long sd) -{ - long ret; - unsigned char *ptr, *args; - - ret = EFAIL; - ptr = tSLInformation.pucTxCommandBuffer; - args = (ptr + HEADERS_SIZE_CMD); - - // Fill in HCI packet structure - args = UINT32_TO_STREAM(args, sd); - - // Initiate a HCI command - hci_command_send(HCI_CMND_CLOSE_SOCKET, ptr, SOCKET_CLOSE_PARAMS_LEN); - - // Since we are in blocking state - wait for event complete - SimpleLinkWaitEvent(HCI_CMND_CLOSE_SOCKET, &ret); - errno = ret; - - // since 'close' call may result in either OK (and then it closed) or error - // mark this socket as invalid - set_socket_active_status(sd, SOCKET_STATUS_INACTIVE); - - return(ret); -} - -//***************************************************************************** -// -//! accept -//! -//! @param[in] sd socket descriptor (handle) -//! @param[out] addr the argument addr is a pointer to a sockaddr structure -//! This structure is filled in with the address of the -//! peer socket, as known to the communications layer. -//! determined. The exact format of the address returned -//! addr is by the socket's address sockaddr. -//! On this version only AF_INET is supported. -//! This argument returns in network order. -//! @param[out] addrlen the addrlen argument is a value-result argument: -//! it should initially contain the size of the structure -//! pointed to by addr. -//! -//! @return For socket in blocking mode: -//! On success, socket handle. on failure negative -//! For socket in non-blocking mode: -//! - On connection establishment, socket handle -//! - On connection pending, SOC_IN_PROGRESS (-2) -//! - On failure, SOC_ERROR (-1) -//! -//! @brief accept a connection on a socket: -//! This function is used with connection-based socket types -//! (SOCK_STREAM). It extracts the first connection request on the -//! queue of pending connections, creates a new connected socket, and -//! returns a new file descriptor referring to that socket. -//! The newly created socket is not in the listening state. -//! The original socket sd is unaffected by this call. -//! The argument sd is a socket that has been created with socket(), -//! bound to a local address with bind(), and is listening for -//! connections after a listen(). The argument addr is a pointer -//! to a sockaddr structure. This structure is filled in with the -//! address of the peer socket, as known to the communications layer. -//! The exact format of the address returned addr is determined by the -//! socket's address family. The addrlen argument is a value-result -//! argument: it should initially contain the size of the structure -//! pointed to by addr, on return it will contain the actual -//! length (in bytes) of the address returned. -//! -//! @sa socket ; bind ; listen -// -//***************************************************************************** - -long -accept(long sd, sockaddr *addr, socklen_t *addrlen) -{ - long ret; - unsigned char *ptr, *args; - tBsdReturnParams tAcceptReturnArguments; - - ret = EFAIL; - ptr = tSLInformation.pucTxCommandBuffer; - args = (ptr + HEADERS_SIZE_CMD); - - // Fill in temporary command buffer - args = UINT32_TO_STREAM(args, sd); - - // Initiate a HCI command - hci_command_send(HCI_CMND_ACCEPT, - ptr, SOCKET_ACCEPT_PARAMS_LEN); - - // Since we are in blocking state - wait for event complete - SimpleLinkWaitEvent(HCI_CMND_ACCEPT, &tAcceptReturnArguments); - - - // need specify return parameters!!! - memcpy(addr, &tAcceptReturnArguments.tSocketAddress, ASIC_ADDR_LEN); - *addrlen = ASIC_ADDR_LEN; - errno = tAcceptReturnArguments.iStatus; - ret = errno; - - // if succeeded, iStatus = new socket descriptor. otherwise - error number - if(M_IS_VALID_SD(ret)) - { - set_socket_active_status(ret, SOCKET_STATUS_ACTIVE); - } - else - { - set_socket_active_status(sd, SOCKET_STATUS_INACTIVE); - } - - return(ret); -} - -//***************************************************************************** -// -//! bind -//! -//! @param[in] sd socket descriptor (handle) -//! @param[out] addr specifies the destination address. On this version -//! only AF_INET is supported. -//! @param[out] addrlen contains the size of the structure pointed to by addr. -//! -//! @return On success, zero is returned. On error, -1 is returned. -//! -//! @brief assign a name to a socket -//! This function gives the socket the local address addr. -//! addr is addrlen bytes long. Traditionally, this is called when a -//! socket is created with socket, it exists in a name space (address -//! family) but has no name assigned. -//! It is necessary to assign a local address before a SOCK_STREAM -//! socket may receive connections. -//! -//! @sa socket ; accept ; listen -// -//***************************************************************************** - -long -bind(long sd, const sockaddr *addr, long addrlen) -{ - long ret; - unsigned char *ptr, *args; - - ret = EFAIL; - ptr = tSLInformation.pucTxCommandBuffer; - args = (ptr + HEADERS_SIZE_CMD); - - addrlen = ASIC_ADDR_LEN; - - // Fill in temporary command buffer - args = UINT32_TO_STREAM(args, sd); - args = UINT32_TO_STREAM(args, 0x00000008); - args = UINT32_TO_STREAM(args, addrlen); - ARRAY_TO_STREAM(args, ((unsigned char *)addr), addrlen); - - // Initiate a HCI command - hci_command_send(HCI_CMND_BIND, - ptr, SOCKET_BIND_PARAMS_LEN); - - // Since we are in blocking state - wait for event complete - SimpleLinkWaitEvent(HCI_CMND_BIND, &ret); - - errno = ret; - - return(ret); -} - -//***************************************************************************** -// -//! listen -//! -//! @param[in] sd socket descriptor (handle) -//! @param[in] backlog specifies the listen queue depth. On this version -//! backlog is not supported. -//! @return On success, zero is returned. On error, -1 is returned. -//! -//! @brief listen for connections on a socket -//! The willingness to accept incoming connections and a queue -//! limit for incoming connections are specified with listen(), -//! and then the connections are accepted with accept. -//! The listen() call applies only to sockets of type SOCK_STREAM -//! The backlog parameter defines the maximum length the queue of -//! pending connections may grow to. -//! -//! @sa socket ; accept ; bind -//! -//! @note On this version, backlog is not supported -// -//***************************************************************************** - -long -listen(long sd, long backlog) -{ - long ret; - unsigned char *ptr, *args; - - ret = EFAIL; - ptr = tSLInformation.pucTxCommandBuffer; - args = (ptr + HEADERS_SIZE_CMD); - - // Fill in temporary command buffer - args = UINT32_TO_STREAM(args, sd); - args = UINT32_TO_STREAM(args, backlog); - - // Initiate a HCI command - hci_command_send(HCI_CMND_LISTEN, - ptr, SOCKET_LISTEN_PARAMS_LEN); - - // Since we are in blocking state - wait for event complete - SimpleLinkWaitEvent(HCI_CMND_LISTEN, &ret); - errno = ret; - - return(ret); -} - -//***************************************************************************** -// -//! gethostbyname -//! -//! @param[in] hostname host name -//! @param[in] usNameLen name length -//! @param[out] out_ip_addr This parameter is filled in with host IP address. -//! In case that host name is not resolved, -//! out_ip_addr is zero. -//! @return On success, positive is returned. On error, negative is returned -//! -//! @brief Get host IP by name. Obtain the IP Address of machine on network, -//! by its name. -//! -//! @note On this version, only blocking mode is supported. Also note that -//! the function requires DNS server to be configured prior to its usage. -// -//***************************************************************************** - -#ifndef CC3000_TINY_DRIVER -int -gethostbyname(const char * hostname, uint8_t usNameLen, uint32_t * out_ip_addr) -{ - tBsdGethostbynameParams ret; - unsigned char *ptr, *args; - - errno = EFAIL; - - if (usNameLen > HOSTNAME_MAX_LENGTH) - { - return errno; - } - - ptr = tSLInformation.pucTxCommandBuffer; - args = (ptr + SIMPLE_LINK_HCI_CMND_TRANSPORT_HEADER_SIZE); - - // Fill in HCI packet structure - args = UINT32_TO_STREAM(args, 8); - args = UINT32_TO_STREAM(args, usNameLen); - ARRAY_TO_STREAM(args, hostname, usNameLen); - - // Initiate a HCI command - hci_command_send(HCI_CMND_GETHOSTNAME, ptr, SOCKET_GET_HOST_BY_NAME_PARAMS_LEN - + usNameLen - 1); - - // Since we are in blocking state - wait for event complete - SimpleLinkWaitEvent(HCI_EVNT_BSD_GETHOSTBYNAME, &ret); - - errno = ret.retVal; - //Dprinter->print("errno: "); Dprinter->println(errno); - (*((uint32_t *)out_ip_addr)) = ret.outputAddress; - - return (errno); - -} -#endif - -//***************************************************************************** -// -//! connect -//! -//! @param[in] sd socket descriptor (handle) -//! @param[in] addr specifies the destination addr. On this version -//! only AF_INET is supported. -//! @param[out] addrlen contains the size of the structure pointed to by addr -//! @return On success, zero is returned. On error, -1 is returned -//! -//! @brief initiate a connection on a socket -//! Function connects the socket referred to by the socket descriptor -//! sd, to the address specified by addr. The addrlen argument -//! specifies the size of addr. The format of the address in addr is -//! determined by the address space of the socket. If it is of type -//! SOCK_DGRAM, this call specifies the peer with which the socket is -//! to be associated; this address is that to which datagrams are to be -//! sent, and the only address from which datagrams are to be received. -//! If the socket is of type SOCK_STREAM, this call attempts to make a -//! connection to another socket. The other socket is specified by -//! address, which is an address in the communications space of the -//! socket. Note that the function implements only blocking behavior -//! thus the caller will be waiting either for the connection -//! establishment or for the connection establishment failure. -//! -//! @sa socket -// -//***************************************************************************** - -long -connect(long sd, const sockaddr *addr, long addrlen) -{ - long int ret; - unsigned char *ptr, *args; - - ret = EFAIL; - ptr = tSLInformation.pucTxCommandBuffer; - args = (ptr + SIMPLE_LINK_HCI_CMND_TRANSPORT_HEADER_SIZE); - addrlen = 8; - - // Fill in temporary command buffer - args = UINT32_TO_STREAM(args, sd); - args = UINT32_TO_STREAM(args, 0x00000008); - args = UINT32_TO_STREAM(args, addrlen); - ARRAY_TO_STREAM(args, ((unsigned char *)addr), addrlen); - - // Initiate a HCI command - hci_command_send(HCI_CMND_CONNECT, - ptr, SOCKET_CONNECT_PARAMS_LEN); - - // Since we are in blocking state - wait for event complete - SimpleLinkWaitEvent(HCI_CMND_CONNECT, &ret); - - errno = ret; - - return((long)ret); -} - - -//***************************************************************************** -// -//! select -//! -//! @param[in] nfds the highest-numbered file descriptor in any of the -//! three sets, plus 1. -//! @param[out] writesds socket descriptors list for write monitoring -//! @param[out] readsds socket descriptors list for read monitoring -//! @param[out] exceptsds socket descriptors list for exception monitoring -//! @param[in] timeout is an upper bound on the amount of time elapsed -//! before select() returns. Null means infinity -//! timeout. The minimum timeout is 5 milliseconds, -//! less than 5 milliseconds will be set -//! automatically to 5 milliseconds. -//! @return On success, select() returns the number of file descriptors -//! contained in the three returned descriptor sets (that is, the -//! total number of bits that are set in readfds, writefds, -//! exceptfds) which may be zero if the timeout expires before -//! anything interesting happens. -//! On error, -1 is returned. -//! *readsds - return the sockets on which Read request will -//! return without delay with valid data. -//! *writesds - return the sockets on which Write request -//! will return without delay. -//! *exceptsds - return the sockets which closed recently. -//! -//! @brief Monitor socket activity -//! Select allow a program to monitor multiple file descriptors, -//! waiting until one or more of the file descriptors become -//! "ready" for some class of I/O operation -//! -//! @Note If the timeout value set to less than 5ms it will automatically set -//! to 5ms to prevent overload of the system -//! -//! @sa socket -// -//***************************************************************************** - -int -select(long nfds, fd_set *readsds, fd_set *writesds, fd_set *exceptsds, - struct timeval *timeout) -{ - unsigned char *ptr, *args; - tBsdSelectRecvParams tParams; - unsigned long is_blocking; - - if( timeout == NULL) - { - is_blocking = 1; /* blocking , infinity timeout */ - } - else - { - is_blocking = 0; /* no blocking, timeout */ - } - - // Fill in HCI packet structure - ptr = tSLInformation.pucTxCommandBuffer; - args = (ptr + HEADERS_SIZE_CMD); - - // Fill in temporary command buffer - args = UINT32_TO_STREAM(args, nfds); - args = UINT32_TO_STREAM(args, 0x00000014); - args = UINT32_TO_STREAM(args, 0x00000014); - args = UINT32_TO_STREAM(args, 0x00000014); - args = UINT32_TO_STREAM(args, 0x00000014); - args = UINT32_TO_STREAM(args, is_blocking); - args = UINT32_TO_STREAM(args, ((readsds) ? *(unsigned long*)readsds : 0)); - args = UINT32_TO_STREAM(args, ((writesds) ? *(unsigned long*)writesds : 0)); - args = UINT32_TO_STREAM(args, ((exceptsds) ? *(unsigned long*)exceptsds : 0)); - - if (timeout) - { - if ( 0 == timeout->tv_sec && timeout->tv_usec < - SELECT_TIMEOUT_MIN_MICRO_SECONDS) - { - timeout->tv_usec = SELECT_TIMEOUT_MIN_MICRO_SECONDS; - } - args = UINT32_TO_STREAM(args, timeout->tv_sec); - args = UINT32_TO_STREAM(args, timeout->tv_usec); - } - - // Initiate a HCI command - hci_command_send(HCI_CMND_BSD_SELECT, ptr, SOCKET_SELECT_PARAMS_LEN); - - // Since we are in blocking state - wait for event complete - SimpleLinkWaitEvent(HCI_EVNT_SELECT, &tParams); - - // Update actually read FD - if (tParams.iStatus >= 0) - { - if (readsds) - { - memcpy(readsds, &tParams.uiRdfd, sizeof(tParams.uiRdfd)); - } - - if (writesds) - { - memcpy(writesds, &tParams.uiWrfd, sizeof(tParams.uiWrfd)); - } - - if (exceptsds) - { - memcpy(exceptsds, &tParams.uiExfd, sizeof(tParams.uiExfd)); - } - - return(tParams.iStatus); - - } - else - { - errno = tParams.iStatus; - return(-1); - } -} - -//***************************************************************************** -// -//! setsockopt -//! -//! @param[in] sd socket handle -//! @param[in] level defines the protocol level for this option -//! @param[in] optname defines the option name to Interrogate -//! @param[in] optval specifies a value for the option -//! @param[in] optlen specifies the length of the option value -//! @return On success, zero is returned. On error, -1 is returned -//! -//! @brief set socket options -//! This function manipulate the options associated with a socket. -//! Options may exist at multiple protocol levels; they are always -//! present at the uppermost socket level. -//! When manipulating socket options the level at which the option -//! resides and the name of the option must be specified. -//! To manipulate options at the socket level, level is specified as -//! SOL_SOCKET. To manipulate options at any other level the protocol -//! number of the appropriate protocol controlling the option is -//! supplied. For example, to indicate that an option is to be -//! interpreted by the TCP protocol, level should be set to the -//! protocol number of TCP; -//! The parameters optval and optlen are used to access optval - -//! use for setsockopt(). For getsockopt() they identify a buffer -//! in which the value for the requested option(s) are to -//! be returned. For getsockopt(), optlen is a value-result -//! parameter, initially containing the size of the buffer -//! pointed to by option_value, and modified on return to -//! indicate the actual size of the value returned. If no option -//! value is to be supplied or returned, option_value may be NULL. -//! -//! @Note On this version the following two socket options are enabled: -//! The only protocol level supported in this version -//! is SOL_SOCKET (level). -//! 1. SOCKOPT_RECV_TIMEOUT (optname) -//! SOCKOPT_RECV_TIMEOUT configures recv and recvfrom timeout -//! in milliseconds. -//! In that case optval should be pointer to unsigned long. -//! 2. SOCKOPT_NONBLOCK (optname). sets the socket non-blocking mode on -//! or off. -//! In that case optval should be SOCK_ON or SOCK_OFF (optval). -//! -//! @sa getsockopt -// -//***************************************************************************** - -#ifndef CC3000_TINY_DRIVER -int -setsockopt(long sd, long level, long optname, const void *optval, - socklen_t optlen) -{ - long ret; - unsigned char *ptr, *args; - - ptr = tSLInformation.pucTxCommandBuffer; - args = (ptr + HEADERS_SIZE_CMD); - - // Fill in temporary command buffer - args = UINT32_TO_STREAM(args, sd); - args = UINT32_TO_STREAM(args, level); - args = UINT32_TO_STREAM(args, optname); - args = UINT32_TO_STREAM(args, 0x00000008); - args = UINT32_TO_STREAM(args, optlen); - ARRAY_TO_STREAM(args, ((unsigned char *)optval), optlen); - - // Initiate a HCI command - hci_command_send(HCI_CMND_SETSOCKOPT, - ptr, SOCKET_SET_SOCK_OPT_PARAMS_LEN + optlen); - - // Since we are in blocking state - wait for event complete - SimpleLinkWaitEvent(HCI_CMND_SETSOCKOPT, &ret); - - if (ret >= 0) - { - return (0); - } - else - { - errno = ret; - return (-1); - } -} -#endif - -//***************************************************************************** -// -//! getsockopt -//! -//! @param[in] sd socket handle -//! @param[in] level defines the protocol level for this option -//! @param[in] optname defines the option name to Interrogate -//! @param[out] optval specifies a value for the option -//! @param[out] optlen specifies the length of the option value -//! @return On success, zero is returned. On error, -1 is returned -//! -//! @brief set socket options -//! This function manipulate the options associated with a socket. -//! Options may exist at multiple protocol levels; they are always -//! present at the uppermost socket level. -//! When manipulating socket options the level at which the option -//! resides and the name of the option must be specified. -//! To manipulate options at the socket level, level is specified as -//! SOL_SOCKET. To manipulate options at any other level the protocol -//! number of the appropriate protocol controlling the option is -//! supplied. For example, to indicate that an option is to be -//! interpreted by the TCP protocol, level should be set to the -//! protocol number of TCP; -//! The parameters optval and optlen are used to access optval - -//! use for setsockopt(). For getsockopt() they identify a buffer -//! in which the value for the requested option(s) are to -//! be returned. For getsockopt(), optlen is a value-result -//! parameter, initially containing the size of the buffer -//! pointed to by option_value, and modified on return to -//! indicate the actual size of the value returned. If no option -//! value is to be supplied or returned, option_value may be NULL. -//! -//! @Note On this version the following two socket options are enabled: -//! The only protocol level supported in this version -//! is SOL_SOCKET (level). -//! 1. SOCKOPT_RECV_TIMEOUT (optname) -//! SOCKOPT_RECV_TIMEOUT configures recv and recvfrom timeout -//! in milliseconds. -//! In that case optval should be pointer to unsigned long. -//! 2. SOCKOPT_NONBLOCK (optname). sets the socket non-blocking mode on -//! or off. -//! In that case optval should be SOCK_ON or SOCK_OFF (optval). -//! -//! @sa setsockopt -// -//***************************************************************************** - -int -getsockopt (long sd, long level, long optname, void *optval, socklen_t *optlen) -{ - unsigned char *ptr, *args; - tBsdGetSockOptReturnParams tRetParams; - - ptr = tSLInformation.pucTxCommandBuffer; - args = (ptr + HEADERS_SIZE_CMD); - - // Fill in temporary command buffer - args = UINT32_TO_STREAM(args, sd); - args = UINT32_TO_STREAM(args, level); - args = UINT32_TO_STREAM(args, optname); - - // Initiate a HCI command - hci_command_send(HCI_CMND_GETSOCKOPT, - ptr, SOCKET_GET_SOCK_OPT_PARAMS_LEN); - - // Since we are in blocking state - wait for event complete - SimpleLinkWaitEvent(HCI_CMND_GETSOCKOPT, &tRetParams); - - if (((signed char)tRetParams.iStatus) >= 0) - { - *optlen = 4; - memcpy(optval, tRetParams.ucOptValue, 4); - return (0); - } - else - { - errno = tRetParams.iStatus; - return (-1); - } -} - -//***************************************************************************** -// -//! simple_link_recv -//! -//! @param sd socket handle -//! @param buf read buffer -//! @param len buffer length -//! @param flags indicates blocking or non-blocking operation -//! @param from pointer to an address structure indicating source address -//! @param fromlen source address structure size -//! -//! @return Return the number of bytes received, or -1 if an error -//! occurred -//! -//! @brief Read data from socket -//! Return the length of the message on successful completion. -//! If a message is too long to fit in the supplied buffer, -//! excess bytes may be discarded depending on the type of -//! socket the message is received from -// -//***************************************************************************** -int -simple_link_recv(long sd, void *buf, long len, long flags, sockaddr *from, - socklen_t *fromlen, long opcode) -{ - unsigned char *ptr, *args; - tBsdReadReturnParams tSocketReadEvent; - - ptr = tSLInformation.pucTxCommandBuffer; - args = (ptr + HEADERS_SIZE_CMD); - - // Fill in HCI packet structure - args = UINT32_TO_STREAM(args, sd); - args = UINT32_TO_STREAM(args, len); - args = UINT32_TO_STREAM(args, flags); - - // Generate the read command, and wait for the - hci_command_send(opcode, ptr, SOCKET_RECV_FROM_PARAMS_LEN); - - // Since we are in blocking state - wait for event complete - SimpleLinkWaitEvent(opcode, &tSocketReadEvent); - - DEBUGPRINT_F("\n\r\tRecv'd data... Socket #"); - DEBUGPRINT_DEC(tSocketReadEvent.iSocketDescriptor); - DEBUGPRINT_F(" Bytes: 0x"); - DEBUGPRINT_HEX(tSocketReadEvent.iNumberOfBytes); - DEBUGPRINT_F(" Flags: 0x"); - DEBUGPRINT_HEX(tSocketReadEvent.uiFlags); - DEBUGPRINT_F("\n\r"); - - // In case the number of bytes is more then zero - read data - if (tSocketReadEvent.iNumberOfBytes > 0) - { - // Wait for the data in a synchronous way. Here we assume that the bug is - // big enough to store also parameters of receive from too.... - SimpleLinkWaitData((unsigned char *)buf, (unsigned char *)from, (unsigned char *)fromlen); - } - - errno = tSocketReadEvent.iNumberOfBytes; - -#if (DEBUG_MODE == 1) - for (uint8_t i=0; i MDNS_DEVICE_SERVICE_MAX_LENGTH) - { - return EFAIL; - } - - pTxBuffer = tSLInformation.pucTxCommandBuffer; - pArgs = (pTxBuffer + SIMPLE_LINK_HCI_CMND_TRANSPORT_HEADER_SIZE); - - // Fill in HCI packet structure - pArgs = UINT32_TO_STREAM(pArgs, mdnsEnabled); - pArgs = UINT32_TO_STREAM(pArgs, 8); - pArgs = UINT32_TO_STREAM(pArgs, deviceServiceNameLength); - ARRAY_TO_STREAM(pArgs, deviceServiceName, deviceServiceNameLength); - - // Initiate a HCI command - hci_command_send(HCI_CMND_MDNS_ADVERTISE, pTxBuffer, SOCKET_MDNS_ADVERTISE_PARAMS_LEN + deviceServiceNameLength); - - // Since we are in blocking state - wait for event complete - SimpleLinkWaitEvent(HCI_EVNT_MDNS_ADVERTISE, &ret); - - return ret; - -} diff --git a/stm/cc3k/socket.h b/stm/cc3k/socket.h deleted file mode 100644 index 58e7ef13b..000000000 --- a/stm/cc3k/socket.h +++ /dev/null @@ -1,691 +0,0 @@ -/***************************************************************************** -* -* socket.h - CC3000 Host Driver Implementation. -* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ -* -* Adapted for use with the Arduino/AVR by KTOWN (Kevin Townsend) -* & Limor Fried for Adafruit Industries -* This library works with the Adafruit CC3000 breakout -* ----> https://www.adafruit.com/products/1469 -* Adafruit invests time and resources providing this open source code, -* please support Adafruit and open-source hardware by purchasing -* products from Adafruit! -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*****************************************************************************/ -#ifndef __SOCKET_H__ -#define __SOCKET_H__ - - -//***************************************************************************** -// -//! \addtogroup socket_api -//! @{ -// -//***************************************************************************** - - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" { -#endif - -#define HOSTNAME_MAX_LENGTH (230) // 230 bytes + header shouldn't exceed 8 bit value - -//--------- Address Families -------- - -#define AF_INET 2 -#define AF_INET6 23 - -//------------ Socket Types ------------ - -#define SOCK_STREAM 1 -#define SOCK_DGRAM 2 -#define SOCK_RAW 3 // Raw sockets allow new IPv4 protocols to be implemented in user space. A raw socket receives or sends the raw datagram not including link level headers -#define SOCK_RDM 4 -#define SOCK_SEQPACKET 5 - -//----------- Socket Protocol ---------- - -#define IPPROTO_IP 0 // dummy for IP -#define IPPROTO_ICMP 1 // control message protocol -#define IPPROTO_IPV4 IPPROTO_IP // IP inside IP -#define IPPROTO_TCP 6 // tcp -#define IPPROTO_UDP 17 // user datagram protocol -#define IPPROTO_IPV6 41 // IPv6 in IPv6 -#define IPPROTO_NONE 59 // No next header -#define IPPROTO_RAW 255 // raw IP packet -#define IPPROTO_MAX 256 - -//----------- Socket retunr codes ----------- - -#define SOC_ERROR (-1) // error -#define SOC_IN_PROGRESS (-2) // socket in progress - -//----------- Socket Options ----------- -#define SOL_SOCKET 0xffff // socket level -#define SOCKOPT_RECV_NONBLOCK 0 // recv non block mode, set SOCK_ON or SOCK_OFF (default block mode) -#define SOCKOPT_RECV_TIMEOUT 1 // optname to configure recv and recvfromtimeout -#define SOCKOPT_ACCEPT_NONBLOCK 2 // accept non block mode, set SOCK_ON or SOCK_OFF (default block mode) -#define SOCK_ON 0 // socket non-blocking mode is enabled -#define SOCK_OFF 1 // socket blocking mode is enabled - -#define TCP_NODELAY 0x0001 -#define TCP_BSDURGENT 0x7000 - -#define MAX_PACKET_SIZE 1500 -#define MAX_LISTEN_QUEUE 4 - -#define IOCTL_SOCKET_EVENTMASK - -#ifdef ENOBUFS -#undef ENOBUFS -#endif -#define ENOBUFS 55 // No buffer space available - -#define __FD_SETSIZE 32 - -#define ASIC_ADDR_LEN 8 - -#define NO_QUERY_RECIVED -3 - - -typedef struct _in_addr_t -{ - unsigned long s_addr; // load with inet_aton() -} in_addr; - -typedef struct _sockaddr_t -{ - unsigned short int sa_family; - unsigned char sa_data[14]; -} sockaddr; - -typedef struct _sockaddr_in_t -{ - short sin_family; // e.g. AF_INET - unsigned short sin_port; // e.g. htons(3490) - in_addr sin_addr; // see struct in_addr, below - char sin_zero[8]; // zero this if you want to -} sockaddr_in; - -typedef unsigned long socklen_t; - -// The fd_set member is required to be an array of longs. -typedef long int __fd_mask; - -// It's easier to assume 8-bit bytes than to get CHAR_BIT. -#define __NFDBITS (8 * sizeof (__fd_mask)) -#define __FDELT(d) ((d) / __NFDBITS) -#define __FDMASK(d) ((__fd_mask) 1 << ((d) % __NFDBITS)) - -#ifdef fd_set -#undef fd_set // for compatibility with newlib, which defines fd_set -#endif - -// fd_set for select and pselect. -typedef struct -{ - __fd_mask fds_bits[__FD_SETSIZE / __NFDBITS]; -#define __FDS_BITS(set) ((set)->fds_bits) -} fd_set; - -// We don't use `memset' because this would require a prototype and -// the array isn't too big. -#define __FD_ZERO(set) \ - do { \ - unsigned int __i; \ - fd_set *__arr = (set); \ - for (__i = 0; __i < sizeof (fd_set) / sizeof (__fd_mask); ++__i) \ - __FDS_BITS (__arr)[__i] = 0; \ - } while (0) -#define __FD_SET(d, set) (__FDS_BITS (set)[__FDELT (d)] |= __FDMASK (d)) -#define __FD_CLR(d, set) (__FDS_BITS (set)[__FDELT (d)] &= ~__FDMASK (d)) -#define __FD_ISSET(d, set) (__FDS_BITS (set)[__FDELT (d)] & __FDMASK (d)) - -// Access macros for 'fd_set'. -#ifdef FD_SET -#undef FD_SET -#endif -#ifdef FD_CLR -#undef FD_CLR -#endif -#ifdef FD_ISSET -#undef FD_ISSET -#endif -#ifdef FD_ZERO -#undef FD_ZERO -#endif -#define FD_SET(fd, fdsetp) __FD_SET (fd, fdsetp) -#define FD_CLR(fd, fdsetp) __FD_CLR (fd, fdsetp) -#define FD_ISSET(fd, fdsetp) __FD_ISSET (fd, fdsetp) -#define FD_ZERO(fdsetp) __FD_ZERO (fdsetp) - -//Use in case of Big Endian only - -#define htonl(A) ((((unsigned long)(A) & 0xff000000) >> 24) | \ - (((unsigned long)(A) & 0x00ff0000) >> 8) | \ - (((unsigned long)(A) & 0x0000ff00) << 8) | \ - (((unsigned long)(A) & 0x000000ff) << 24)) - -#define ntohl htonl - -//Use in case of Big Endian only -#define htons(A) ((((unsigned long)(A) & 0xff00) >> 8) | \ - (((unsigned long)(A) & 0x00ff) << 8)) - - -#define ntohs htons - -// mDNS port - 5353 mDNS multicast address - 224.0.0.251 -#define SET_mDNS_ADD(sockaddr) sockaddr.sa_data[0] = 0x14; \ - sockaddr.sa_data[1] = 0xe9; \ - sockaddr.sa_data[2] = 0xe0; \ - sockaddr.sa_data[3] = 0x0; \ - sockaddr.sa_data[4] = 0x0; \ - sockaddr.sa_data[5] = 0xfb; - - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** - -//***************************************************************************** -// -//! socket -//! -//! @param domain selects the protocol family which will be used for -//! communication. On this version only AF_INET is supported -//! @param type specifies the communication semantics. On this version -//! only SOCK_STREAM, SOCK_DGRAM, SOCK_RAW are supported -//! @param protocol specifies a particular protocol to be used with the -//! socket IPPROTO_TCP, IPPROTO_UDP or IPPROTO_RAW are -//! supported. -//! -//! @return On success, socket handle that is used for consequent socket -//! operations. On error, -1 is returned. -//! -//! @brief create an endpoint for communication -//! The socket function creates a socket that is bound to a specific -//! transport service provider. This function is called by the -//! application layer to obtain a socket handle. -// -//***************************************************************************** -extern int socket(long domain, long type, long protocol); - -//***************************************************************************** -// -//! closesocket -//! -//! @param sd socket handle. -//! -//! @return On success, zero is returned. On error, -1 is returned. -//! -//! @brief The socket function closes a created socket. -// -//***************************************************************************** -extern long closesocket(long sd); - -//***************************************************************************** -// -//! accept -//! -//! @param[in] sd socket descriptor (handle) -//! @param[out] addr the argument addr is a pointer to a sockaddr structure -//! This structure is filled in with the address of the -//! peer socket, as known to the communications layer. -//! determined. The exact format of the address returned -//! addr is by the socket's address sockaddr. -//! On this version only AF_INET is supported. -//! This argument returns in network order. -//! @param[out] addrlen the addrlen argument is a value-result argument: -//! it should initially contain the size of the structure -//! pointed to by addr. -//! -//! @return For socket in blocking mode: -//! On success, socket handle. on failure negative -//! For socket in non-blocking mode: -//! - On connection establishment, socket handle -//! - On connection pending, SOC_IN_PROGRESS (-2) -//! - On failure, SOC_ERROR (-1) -//! -//! @brief accept a connection on a socket: -//! This function is used with connection-based socket types -//! (SOCK_STREAM). It extracts the first connection request on the -//! queue of pending connections, creates a new connected socket, and -//! returns a new file descriptor referring to that socket. -//! The newly created socket is not in the listening state. -//! The original socket sd is unaffected by this call. -//! The argument sd is a socket that has been created with socket(), -//! bound to a local address with bind(), and is listening for -//! connections after a listen(). The argument addr is a pointer -//! to a sockaddr structure. This structure is filled in with the -//! address of the peer socket, as known to the communications layer. -//! The exact format of the address returned addr is determined by the -//! socket's address family. The addrlen argument is a value-result -//! argument: it should initially contain the size of the structure -//! pointed to by addr, on return it will contain the actual -//! length (in bytes) of the address returned. -//! -//! @sa socket ; bind ; listen -// -//***************************************************************************** -extern long accept(long sd, sockaddr *addr, socklen_t *addrlen); - -//***************************************************************************** -// -//! bind -//! -//! @param[in] sd socket descriptor (handle) -//! @param[out] addr specifies the destination address. On this version -//! only AF_INET is supported. -//! @param[out] addrlen contains the size of the structure pointed to by addr. -//! -//! @return On success, zero is returned. On error, -1 is returned. -//! -//! @brief assign a name to a socket -//! This function gives the socket the local address addr. -//! addr is addrlen bytes long. Traditionally, this is called when a -//! socket is created with socket, it exists in a name space (address -//! family) but has no name assigned. -//! It is necessary to assign a local address before a SOCK_STREAM -//! socket may receive connections. -//! -//! @sa socket ; accept ; listen -// -//***************************************************************************** -extern long bind(long sd, const sockaddr *addr, long addrlen); - -//***************************************************************************** -// -//! listen -//! -//! @param[in] sd socket descriptor (handle) -//! @param[in] backlog specifies the listen queue depth. On this version -//! backlog is not supported. -//! @return On success, zero is returned. On error, -1 is returned. -//! -//! @brief listen for connections on a socket -//! The willingness to accept incoming connections and a queue -//! limit for incoming connections are specified with listen(), -//! and then the connections are accepted with accept. -//! The listen() call applies only to sockets of type SOCK_STREAM -//! The backlog parameter defines the maximum length the queue of -//! pending connections may grow to. -//! -//! @sa socket ; accept ; bind -//! -//! @note On this version, backlog is not supported -// -//***************************************************************************** -extern long listen(long sd, long backlog); - -//***************************************************************************** -// -//! gethostbyname -//! -//! @param[in] hostname host name -//! @param[in] usNameLen name length -//! @param[out] out_ip_addr This parameter is filled in with host IP address. -//! In case that host name is not resolved, -//! out_ip_addr is zero. -//! @return On success, positive is returned. On error, negative is returned -//! -//! @brief Get host IP by name. Obtain the IP Address of machine on network, -//! by its name. -//! -//! @note On this version, only blocking mode is supported. Also note that -//! the function requires DNS server to be configured prior to its usage. -// -//***************************************************************************** -#ifndef CC3000_TINY_DRIVER -extern int gethostbyname(const char * hostname, uint8_t usNameLen, uint32_t* out_ip_addr); -#endif - - -//***************************************************************************** -// -//! connect -//! -//! @param[in] sd socket descriptor (handle) -//! @param[in] addr specifies the destination addr. On this version -//! only AF_INET is supported. -//! @param[out] addrlen contains the size of the structure pointed to by addr -//! @return On success, zero is returned. On error, -1 is returned -//! -//! @brief initiate a connection on a socket -//! Function connects the socket referred to by the socket descriptor -//! sd, to the address specified by addr. The addrlen argument -//! specifies the size of addr. The format of the address in addr is -//! determined by the address space of the socket. If it is of type -//! SOCK_DGRAM, this call specifies the peer with which the socket is -//! to be associated; this address is that to which datagrams are to be -//! sent, and the only address from which datagrams are to be received. -//! If the socket is of type SOCK_STREAM, this call attempts to make a -//! connection to another socket. The other socket is specified by -//! address, which is an address in the communications space of the -//! socket. Note that the function implements only blocking behavior -//! thus the caller will be waiting either for the connection -//! establishment or for the connection establishment failure. -//! -//! @sa socket -// -//***************************************************************************** -extern long connect(long sd, const sockaddr *addr, long addrlen); - -//***************************************************************************** -// -//! select -//! -//! @param[in] nfds the highest-numbered file descriptor in any of the -//! three sets, plus 1. -//! @param[out] writesds socket descriptors list for write monitoring -//! @param[out] readsds socket descriptors list for read monitoring -//! @param[out] exceptsds socket descriptors list for exception monitoring -//! @param[in] timeout is an upper bound on the amount of time elapsed -//! before select() returns. Null means infinity -//! timeout. The minimum timeout is 5 milliseconds, -//! less than 5 milliseconds will be set -//! automatically to 5 milliseconds. -//! @return On success, select() returns the number of file descriptors -//! contained in the three returned descriptor sets (that is, the -//! total number of bits that are set in readfds, writefds, -//! exceptfds) which may be zero if the timeout expires before -//! anything interesting happens. -//! On error, -1 is returned. -//! *readsds - return the sockets on which Read request will -//! return without delay with valid data. -//! *writesds - return the sockets on which Write request -//! will return without delay. -//! *exceptsds - return the sockets which closed recently. -//! -//! @brief Monitor socket activity -//! Select allow a program to monitor multiple file descriptors, -//! waiting until one or more of the file descriptors become -//! "ready" for some class of I/O operation -//! -//! @Note If the timeout value set to less than 5ms it will automatically set -//! to 5ms to prevent overload of the system -//! -//! @sa socket -// -//***************************************************************************** -extern int select(long nfds, fd_set *readsds, fd_set *writesds, - fd_set *exceptsds, struct timeval *timeout); - -//***************************************************************************** -// -//! setsockopt -//! -//! @param[in] sd socket handle -//! @param[in] level defines the protocol level for this option -//! @param[in] optname defines the option name to Interrogate -//! @param[in] optval specifies a value for the option -//! @param[in] optlen specifies the length of the option value -//! @return On success, zero is returned. On error, -1 is returned -//! -//! @brief set socket options -//! This function manipulate the options associated with a socket. -//! Options may exist at multiple protocol levels; they are always -//! present at the uppermost socket level. -//! When manipulating socket options the level at which the option -//! resides and the name of the option must be specified. -//! To manipulate options at the socket level, level is specified as -//! SOL_SOCKET. To manipulate options at any other level the protocol -//! number of the appropriate protocol controlling the option is -//! supplied. For example, to indicate that an option is to be -//! interpreted by the TCP protocol, level should be set to the -//! protocol number of TCP; -//! The parameters optval and optlen are used to access optval - -//! use for setsockopt(). For getsockopt() they identify a buffer -//! in which the value for the requested option(s) are to -//! be returned. For getsockopt(), optlen is a value-result -//! parameter, initially containing the size of the buffer -//! pointed to by option_value, and modified on return to -//! indicate the actual size of the value returned. If no option -//! value is to be supplied or returned, option_value may be NULL. -//! -//! @Note On this version the following two socket options are enabled: -//! The only protocol level supported in this version -//! is SOL_SOCKET (level). -//! 1. SOCKOPT_RECV_TIMEOUT (optname) -//! SOCKOPT_RECV_TIMEOUT configures recv and recvfrom timeout -//! in milliseconds. -//! In that case optval should be pointer to unsigned long. -//! 2. SOCKOPT_NONBLOCK (optname). sets the socket non-blocking mode on -//! or off. -//! In that case optval should be SOCK_ON or SOCK_OFF (optval). -//! -//! @sa getsockopt -// -//***************************************************************************** -#ifndef CC3000_TINY_DRIVER -extern int setsockopt(long sd, long level, long optname, const void *optval, - socklen_t optlen); -#endif -//***************************************************************************** -// -//! getsockopt -//! -//! @param[in] sd socket handle -//! @param[in] level defines the protocol level for this option -//! @param[in] optname defines the option name to Interrogate -//! @param[out] optval specifies a value for the option -//! @param[out] optlen specifies the length of the option value -//! @return On success, zero is returned. On error, -1 is returned -//! -//! @brief set socket options -//! This function manipulate the options associated with a socket. -//! Options may exist at multiple protocol levels; they are always -//! present at the uppermost socket level. -//! When manipulating socket options the level at which the option -//! resides and the name of the option must be specified. -//! To manipulate options at the socket level, level is specified as -//! SOL_SOCKET. To manipulate options at any other level the protocol -//! number of the appropriate protocol controlling the option is -//! supplied. For example, to indicate that an option is to be -//! interpreted by the TCP protocol, level should be set to the -//! protocol number of TCP; -//! The parameters optval and optlen are used to access optval - -//! use for setsockopt(). For getsockopt() they identify a buffer -//! in which the value for the requested option(s) are to -//! be returned. For getsockopt(), optlen is a value-result -//! parameter, initially containing the size of the buffer -//! pointed to by option_value, and modified on return to -//! indicate the actual size of the value returned. If no option -//! value is to be supplied or returned, option_value may be NULL. -//! -//! @Note On this version the following two socket options are enabled: -//! The only protocol level supported in this version -//! is SOL_SOCKET (level). -//! 1. SOCKOPT_RECV_TIMEOUT (optname) -//! SOCKOPT_RECV_TIMEOUT configures recv and recvfrom timeout -//! in milliseconds. -//! In that case optval should be pointer to unsigned long. -//! 2. SOCKOPT_NONBLOCK (optname). sets the socket non-blocking mode on -//! or off. -//! In that case optval should be SOCK_ON or SOCK_OFF (optval). -//! -//! @sa setsockopt -// -//***************************************************************************** -extern int getsockopt(long sd, long level, long optname, void *optval, - socklen_t *optlen); - -//***************************************************************************** -// -//! recv -//! -//! @param[in] sd socket handle -//! @param[out] buf Points to the buffer where the message should be stored -//! @param[in] len Specifies the length in bytes of the buffer pointed to -//! by the buffer argument. -//! @param[in] flags Specifies the type of message reception. -//! On this version, this parameter is not supported. -//! -//! @return Return the number of bytes received, or -1 if an error -//! occurred -//! -//! @brief function receives a message from a connection-mode socket -//! -//! @sa recvfrom -//! -//! @Note On this version, only blocking mode is supported. -// -//***************************************************************************** -extern int recv(long sd, void *buf, long len, long flags); - -//***************************************************************************** -// -//! recvfrom -//! -//! @param[in] sd socket handle -//! @param[out] buf Points to the buffer where the message should be stored -//! @param[in] len Specifies the length in bytes of the buffer pointed to -//! by the buffer argument. -//! @param[in] flags Specifies the type of message reception. -//! On this version, this parameter is not supported. -//! @param[in] from pointer to an address structure indicating the source -//! address: sockaddr. On this version only AF_INET is -//! supported. -//! @param[in] fromlen source address structure size -//! -//! @return Return the number of bytes received, or -1 if an error -//! occurred -//! -//! @brief read data from socket -//! function receives a message from a connection-mode or -//! connectionless-mode socket. Note that raw sockets are not -//! supported. -//! -//! @sa recv -//! -//! @Note On this version, only blocking mode is supported. -// -//***************************************************************************** -extern int recvfrom(long sd, void *buf, long len, long flags, sockaddr *from, - socklen_t *fromlen); - -//***************************************************************************** -// -//! send -//! -//! @param sd socket handle -//! @param buf Points to a buffer containing the message to be sent -//! @param len message size in bytes -//! @param flags On this version, this parameter is not supported -//! -//! @return Return the number of bytes transmitted, or -1 if an -//! error occurred -//! -//! @brief Write data to TCP socket -//! This function is used to transmit a message to another -//! socket. -//! -//! @Note On this version, only blocking mode is supported. -//! -//! @sa sendto -// -//***************************************************************************** - -extern int send(long sd, const void *buf, long len, long flags); - -//***************************************************************************** -// -//! sendto -//! -//! @param sd socket handle -//! @param buf Points to a buffer containing the message to be sent -//! @param len message size in bytes -//! @param flags On this version, this parameter is not supported -//! @param to pointer to an address structure indicating the destination -//! address: sockaddr. On this version only AF_INET is -//! supported. -//! @param tolen destination address structure size -//! -//! @return Return the number of bytes transmitted, or -1 if an -//! error occurred -//! -//! @brief Write data to TCP socket -//! This function is used to transmit a message to another -//! socket. -//! -//! @Note On this version, only blocking mode is supported. -//! -//! @sa send -// -//***************************************************************************** - -extern int sendto(long sd, const void *buf, long len, long flags, - const sockaddr *to, socklen_t tolen); - -//***************************************************************************** -// -//! mdnsAdvertiser -//! -//! @param[in] mdnsEnabled flag to enable/disable the mDNS feature -//! @param[in] deviceServiceName Service name as part of the published -//! canonical domain name -//! @param[in] deviceServiceNameLength Length of the service name -//! -//! -//! @return On success, zero is returned, return SOC_ERROR if socket was not -//! opened successfully, or if an error occurred. -//! -//! @brief Set CC3000 in mDNS advertiser mode in order to advertise itself. -// -//***************************************************************************** -extern int mdnsAdvertiser(unsigned short mdnsEnabled, char * deviceServiceName, unsigned short deviceServiceNameLength); - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif // __cplusplus - -#endif // __SOCKET_H__ diff --git a/stm/cc3k/wlan.c b/stm/cc3k/wlan.c deleted file mode 100644 index be6b3242c..000000000 --- a/stm/cc3k/wlan.c +++ /dev/null @@ -1,1264 +0,0 @@ -/***************************************************************************** -* -* wlan.c - CC3000 Host Driver Implementation. -* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ -* -* Adapted for use with the Arduino/AVR by KTOWN (Kevin Townsend) -* & Limor Fried for Adafruit Industries -* This library works with the Adafruit CC3000 breakout -* ----> https://www.adafruit.com/products/1469 -* Adafruit invests time and resources providing this open source code, -* please support Adafruit and open-source hardware by purchasing -* products from Adafruit! - -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*****************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup wlan_api -//! @{ -// -//***************************************************************************** -#include -#include - -#include "wlan.h" -#include "hci.h" -#include "ccspi.h" -#include "socket.h" -#include "nvmem.h" -#include "security.h" -#include "evnt_handler.h" -#include "ccdebug.h" - -extern int errno; - -volatile sSimplLinkInformation tSLInformation; - -#define SMART_CONFIG_PROFILE_SIZE 67 // 67 = 32 (max ssid) + 32 (max key) + 1 (SSID length) + 1 (security type) + 1 (key length) - -#ifndef CC3000_UNENCRYPTED_SMART_CONFIG -unsigned char key[AES128_KEY_SIZE]; -unsigned char profileArray[SMART_CONFIG_PROFILE_SIZE]; -#endif //CC3000_UNENCRYPTED_SMART_CONFIG - -/* patches type */ -#define PATCHES_HOST_TYPE_WLAN_DRIVER 0x01 -#define PATCHES_HOST_TYPE_WLAN_FW 0x02 -#define PATCHES_HOST_TYPE_BOOTLOADER 0x03 - -#define SL_SET_SCAN_PARAMS_INTERVAL_LIST_SIZE (16) -#define SL_SIMPLE_CONFIG_PREFIX_LENGTH (3) -#define ETH_ALEN (6) -#define MAXIMAL_SSID_LENGTH (32) - -#define SL_PATCHES_REQUEST_DEFAULT (0) -#define SL_PATCHES_REQUEST_FORCE_HOST (1) -#define SL_PATCHES_REQUEST_FORCE_NONE (2) - - -#define WLAN_SEC_UNSEC (0) -#define WLAN_SEC_WEP (1) -#define WLAN_SEC_WPA (2) -#define WLAN_SEC_WPA2 (3) - - -#define WLAN_SL_INIT_START_PARAMS_LEN (1) -#define WLAN_PATCH_PARAMS_LENGTH (8) -#define WLAN_SET_CONNECTION_POLICY_PARAMS_LEN (12) -#define WLAN_DEL_PROFILE_PARAMS_LEN (4) -#define WLAN_SET_MASK_PARAMS_LEN (4) -#define WLAN_SET_SCAN_PARAMS_LEN (100) -#define WLAN_GET_SCAN_RESULTS_PARAMS_LEN (4) -#define WLAN_ADD_PROFILE_NOSEC_PARAM_LEN (24) -#define WLAN_ADD_PROFILE_WEP_PARAM_LEN (36) -#define WLAN_ADD_PROFILE_WPA_PARAM_LEN (44) -#define WLAN_CONNECT_PARAM_LEN (29) -#define WLAN_SMART_CONFIG_START_PARAMS_LEN (4) - - - - -//***************************************************************************** -// -//! SimpleLink_Init_Start -//! -//! @param usPatchesAvailableAtHost flag to indicate if patches available -//! from host or from EEPROM. Due to the -//! fact the patches are burn to the EEPROM -//! using the patch programmer utility, the -//! patches will be available from the EEPROM -//! and not from the host. -//! -//! @return none -//! -//! @brief Send HCI_CMND_SIMPLE_LINK_START to CC3000 -// -//***************************************************************************** -static void SimpleLink_Init_Start(unsigned short usPatchesAvailableAtHost) -{ - unsigned char *ptr; - unsigned char *args; - - ptr = tSLInformation.pucTxCommandBuffer; - args = (unsigned char *)(ptr + HEADERS_SIZE_CMD); - if (usPatchesAvailableAtHost > 2) - usPatchesAvailableAtHost = 2; - - UINT8_TO_STREAM(args, usPatchesAvailableAtHost); - - // IRQ Line asserted - send HCI_CMND_SIMPLE_LINK_START to CC3000 - hci_command_send(HCI_CMND_SIMPLE_LINK_START, ptr, WLAN_SL_INIT_START_PARAMS_LEN); - SimpleLinkWaitEvent(HCI_CMND_SIMPLE_LINK_START, 0); -} - - - -//***************************************************************************** -// -//! wlan_init -//! -//! @param sWlanCB Asynchronous events callback. -//! 0 no event call back. -//! -call back parameters: -//! 1) event_type: HCI_EVNT_WLAN_UNSOL_CONNECT connect event, -//! HCI_EVNT_WLAN_UNSOL_DISCONNECT disconnect event, -//! HCI_EVNT_WLAN_ASYNC_SIMPLE_CONFIG_DONE config done, -//! HCI_EVNT_WLAN_UNSOL_DHCP dhcp report, -//! HCI_EVNT_WLAN_ASYNC_PING_REPORT ping report OR -//! HCI_EVNT_WLAN_KEEPALIVE keepalive. -//! 2) data: pointer to extra data that received by the event -//! (NULL no data). -//! 3) length: data length. -//! -Events with extra data: -//! HCI_EVNT_WLAN_UNSOL_DHCP: 4 bytes IP, 4 bytes Mask, -//! 4 bytes default gateway, 4 bytes DHCP server and 4 bytes -//! for DNS server. -//! HCI_EVNT_WLAN_ASYNC_PING_REPORT: 4 bytes Packets sent, -//! 4 bytes Packets received, 4 bytes Min round time, -//! 4 bytes Max round time and 4 bytes for Avg round time. -//! -//! @param sFWPatches 0 no patch or pointer to FW patches -//! @param sDriverPatches 0 no patch or pointer to driver patches -//! @param sBootLoaderPatches 0 no patch or pointer to bootloader patches -//! @param sReadWlanInterruptPin init callback. the callback read wlan -//! interrupt status. -//! @param sWlanInterruptEnable init callback. the callback enable wlan -//! interrupt. -//! @param sWlanInterruptDisable init callback. the callback disable wlan -//! interrupt. -//! @param sWriteWlanPin init callback. the callback write value -//! to device pin. -//! -//! @return none -//! -//! @sa wlan_set_event_mask , wlan_start , wlan_stop -//! -//! @brief Initialize wlan driver -//! -//! @warning This function must be called before ANY other wlan driver function -// -//***************************************************************************** - -void wlan_init( tWlanCB sWlanCB, - tFWPatches sFWPatches, - tDriverPatches sDriverPatches, - tBootLoaderPatches sBootLoaderPatches, - tWlanReadInteruptPin sReadWlanInterruptPin, - tWlanInterruptEnable sWlanInterruptEnable, - tWlanInterruptDisable sWlanInterruptDisable, - tWriteWlanPin sWriteWlanPin) -{ - - tSLInformation.sFWPatches = sFWPatches; - tSLInformation.sDriverPatches = sDriverPatches; - tSLInformation.sBootLoaderPatches = sBootLoaderPatches; - - // init io callback - tSLInformation.ReadWlanInterruptPin = sReadWlanInterruptPin; - tSLInformation.WlanInterruptEnable = sWlanInterruptEnable; - tSLInformation.WlanInterruptDisable = sWlanInterruptDisable; - tSLInformation.WriteWlanPin = sWriteWlanPin; - - //init asynchronous events callback - tSLInformation.sWlanCB= sWlanCB; - - // By default TX Complete events are routed to host too - tSLInformation.InformHostOnTxComplete = 1; -} - -//***************************************************************************** -// -//! SpiReceiveHandler -//! -//! @param pvBuffer - pointer to the received data buffer -//! The function triggers Received event/data processing -//! -//! @param Pointer to the received data -//! @return none -//! -//! @brief The function triggers Received event/data processing. It is -//! called from the SPI library to receive the data -// -//***************************************************************************** -void SpiReceiveHandler(void *pvBuffer) -{ - tSLInformation.usEventOrDataReceived = 1; - tSLInformation.pucReceivedData = (unsigned char *)pvBuffer; - - hci_unsolicited_event_handler(); -} - - -//***************************************************************************** -// -//! wlan_start -//! -//! @param usPatchesAvailableAtHost - flag to indicate if patches available -//! from host or from EEPROM. Due to the -//! fact the patches are burn to the EEPROM -//! using the patch programmer utility, the -//! patches will be available from the EEPROM -//! and not from the host. -//! -//! @return none -//! -//! @brief Start WLAN device. This function asserts the enable pin of -//! the device (WLAN_EN), starting the HW initialization process. -//! The function blocked until device Initialization is completed. -//! Function also configure patches (FW, driver or bootloader) -//! and calls appropriate device callbacks. -//! -//! @Note Prior calling the function wlan_init shall be called. -//! @Warning This function must be called after wlan_init and before any -//! other wlan API -//! @sa wlan_init , wlan_stop -//! -// -//***************************************************************************** - -void -wlan_start(unsigned short usPatchesAvailableAtHost) -{ - - unsigned long ulSpiIRQState; - - tSLInformation.NumberOfSentPackets = 0; - tSLInformation.NumberOfReleasedPackets = 0; - tSLInformation.usRxEventOpcode = 0; - tSLInformation.usNumberOfFreeBuffers = 0; - tSLInformation.usSlBufferLength = 0; - tSLInformation.usBufferSize = 0; - tSLInformation.usRxDataPending = 0; - tSLInformation.slTransmitDataError = 0; - tSLInformation.usEventOrDataReceived = 0; - tSLInformation.pucReceivedData = 0; - - // Allocate the memory for the RX/TX data transactions - tSLInformation.pucTxCommandBuffer = (unsigned char *)wlan_tx_buffer; - - // init spi - SpiOpen(SpiReceiveHandler); - - // Check the IRQ line - ulSpiIRQState = tSLInformation.ReadWlanInterruptPin(); - - // ASIC 1273 chip enable: toggle WLAN EN line - tSLInformation.WriteWlanPin( WLAN_ENABLE ); - - if (ulSpiIRQState) - { - // wait till the IRQ line goes low - while(tSLInformation.ReadWlanInterruptPin() != 0) - { - } - } - else - { - // wait till the IRQ line goes high and than low - while(tSLInformation.ReadWlanInterruptPin() == 0) - { - } - - while(tSLInformation.ReadWlanInterruptPin() != 0) - { - } - } - DEBUGPRINT_F("SimpleLink start\n\r"); - SimpleLink_Init_Start(usPatchesAvailableAtHost); - - // Read Buffer's size and finish - DEBUGPRINT_F("Read buffer\n\r"); - hci_command_send(HCI_CMND_READ_BUFFER_SIZE, tSLInformation.pucTxCommandBuffer, 0); - SimpleLinkWaitEvent(HCI_CMND_READ_BUFFER_SIZE, 0); -} - - -//***************************************************************************** -// -//! wlan_stop -//! -//! @param none -//! -//! @return none -//! -//! @brief Stop WLAN device by putting it into reset state. -//! -//! @sa wlan_start -// -//***************************************************************************** - -void -wlan_stop(void) -{ - // ASIC 1273 chip disable - tSLInformation.WriteWlanPin( WLAN_DISABLE ); - - // Wait till IRQ line goes high... - while(tSLInformation.ReadWlanInterruptPin() == 0) - { - } - - // Free the used by WLAN Driver memory - if (tSLInformation.pucTxCommandBuffer) - { - tSLInformation.pucTxCommandBuffer = 0; - } - - SpiClose(); -} - - -//***************************************************************************** -// -//! wlan_connect -//! -//! @param sec_type security options: -//! WLAN_SEC_UNSEC, -//! WLAN_SEC_WEP (ASCII support only), -//! WLAN_SEC_WPA or WLAN_SEC_WPA2 -//! @param ssid up to 32 bytes and is ASCII SSID of the AP -//! @param ssid_len length of the SSID -//! @param bssid 6 bytes specified the AP bssid -//! @param key up to 16 bytes specified the AP security key -//! @param key_len key length -//! -//! @return On success, zero is returned. On error, negative is returned. -//! Note that even though a zero is returned on success to trigger -//! connection operation, it does not mean that CCC3000 is already -//! connected. An asynchronous "Connected" event is generated when -//! actual association process finishes and CC3000 is connected to -//! the AP. If DHCP is set, An asynchronous "DHCP" event is -//! generated when DHCP process is finish. -//! -//! -//! @brief Connect to AP -//! @warning Please Note that when connection to AP configured with security -//! type WEP, please confirm that the key is set as ASCII and not -//! as HEX. -//! @sa wlan_disconnect -// -//***************************************************************************** - -#ifndef CC3000_TINY_DRIVER -long -wlan_connect(unsigned long ulSecType, const char *ssid, long ssid_len, - unsigned char *bssid, unsigned char *key, long key_len) -{ - long ret; - unsigned char *ptr; - unsigned char *args; - unsigned char bssid_zero[] = {0, 0, 0, 0, 0, 0}; - - ret = EFAIL; - ptr = tSLInformation.pucTxCommandBuffer; - args = (ptr + HEADERS_SIZE_CMD); - - // Fill in command buffer - args = UINT32_TO_STREAM(args, 0x0000001c); - args = UINT32_TO_STREAM(args, ssid_len); - args = UINT32_TO_STREAM(args, ulSecType); - args = UINT32_TO_STREAM(args, 0x00000010 + ssid_len); - args = UINT32_TO_STREAM(args, key_len); - args = UINT16_TO_STREAM(args, 0); - - // padding shall be zeroed - if(bssid) - { - ARRAY_TO_STREAM(args, bssid, ETH_ALEN); - } - else - { - ARRAY_TO_STREAM(args, bssid_zero, ETH_ALEN); - } - - ARRAY_TO_STREAM(args, ssid, ssid_len); - - if(key_len && key) - { - ARRAY_TO_STREAM(args, key, key_len); - } - - // Initiate a HCI command - hci_command_send(HCI_CMND_WLAN_CONNECT, ptr, WLAN_CONNECT_PARAM_LEN + - ssid_len + key_len - 1); - - // Wait for command complete event - SimpleLinkWaitEvent(HCI_CMND_WLAN_CONNECT, &ret); - errno = ret; - - return(ret); -} -#else -long -wlan_connect(const char *ssid, long ssid_len) -{ - long ret; - unsigned char *ptr; - unsigned char *args; - unsigned char bssid_zero[] = {0, 0, 0, 0, 0, 0}; - - ret = EFAIL; - ptr = tSLInformation.pucTxCommandBuffer; - args = (ptr + HEADERS_SIZE_CMD); - - // Fill in command buffer - args = UINT32_TO_STREAM(args, 0x0000001c); - args = UINT32_TO_STREAM(args, ssid_len); - args = UINT32_TO_STREAM(args, 0); - args = UINT32_TO_STREAM(args, 0x00000010 + ssid_len); - args = UINT32_TO_STREAM(args, 0); - args = UINT16_TO_STREAM(args, 0); - - // padding shall be zeroed - ARRAY_TO_STREAM(args, bssid_zero, ETH_ALEN); - ARRAY_TO_STREAM(args, ssid, ssid_len); - - // Initiate a HCI command - hci_command_send(HCI_CMND_WLAN_CONNECT, ptr, WLAN_CONNECT_PARAM_LEN + - ssid_len - 1); - - // Wait for command complete event - SimpleLinkWaitEvent(HCI_CMND_WLAN_CONNECT, &ret); - errno = ret; - - return(ret); -} -#endif - -//***************************************************************************** -// -//! wlan_disconnect -//! -//! @return 0 disconnected done, other CC3000 already disconnected -//! -//! @brief Disconnect connection from AP. -//! -//! @sa wlan_connect -// -//***************************************************************************** - -long -wlan_disconnect() -{ - long ret; - unsigned char *ptr; - - ret = EFAIL; - ptr = tSLInformation.pucTxCommandBuffer; - - hci_command_send(HCI_CMND_WLAN_DISCONNECT, ptr, 0); - - // Wait for command complete event - SimpleLinkWaitEvent(HCI_CMND_WLAN_DISCONNECT, &ret); - errno = ret; - - return(ret); -} - -//***************************************************************************** -// -//! wlan_ioctl_set_connection_policy -//! -//! @param should_connect_to_open_ap enable(1), disable(0) connect to any -//! available AP. This parameter corresponds to the configuration of -//! item # 3 in the brief description. -//! @param should_use_fast_connect enable(1), disable(0). if enabled, tries -//! to connect to the last connected AP. This parameter corresponds -//! to the configuration of item # 1 in the brief description. -//! @param auto_start enable(1), disable(0) auto connect -//! after reset and periodically reconnect if needed. This -//! configuration configures option 2 in the above description. -//! -//! @return On success, zero is returned. On error, -1 is returned -//! -//! @brief When auto is enabled, the device tries to connect according -//! the following policy: -//! 1) If fast connect is enabled and last connection is valid, -//! the device will try to connect to it without the scanning -//! procedure (fast). The last connection will be marked as -//! invalid, due to adding/removing profile. -//! 2) If profile exists, the device will try to connect it -//! (Up to seven profiles). -//! 3) If fast and profiles are not found, and open mode is -//! enabled, the device will try to connect to any AP. -//! * Note that the policy settings are stored in the CC3000 NVMEM. -//! -//! @sa wlan_add_profile , wlan_ioctl_del_profile -// -//***************************************************************************** - -long -wlan_ioctl_set_connection_policy(unsigned long should_connect_to_open_ap, - unsigned long ulShouldUseFastConnect, - unsigned long ulUseProfiles) -{ - long ret; - unsigned char *ptr; - unsigned char *args; - - ret = EFAIL; - ptr = tSLInformation.pucTxCommandBuffer; - args = (unsigned char *)(ptr + HEADERS_SIZE_CMD); - - // Fill in HCI packet structure - args = UINT32_TO_STREAM(args, should_connect_to_open_ap); - args = UINT32_TO_STREAM(args, ulShouldUseFastConnect); - args = UINT32_TO_STREAM(args, ulUseProfiles); - - // Initiate a HCI command - hci_command_send(HCI_CMND_WLAN_IOCTL_SET_CONNECTION_POLICY, - ptr, WLAN_SET_CONNECTION_POLICY_PARAMS_LEN); - - // Wait for command complete event - SimpleLinkWaitEvent(HCI_CMND_WLAN_IOCTL_SET_CONNECTION_POLICY, &ret); - - return(ret); -} - -//***************************************************************************** -// -//! wlan_add_profile -//! -//! @param ulSecType WLAN_SEC_UNSEC,WLAN_SEC_WEP,WLAN_SEC_WPA,WLAN_SEC_WPA2 -//! @param ucSsid ssid SSID up to 32 bytes -//! @param ulSsidLen ssid length -//! @param ucBssid bssid 6 bytes -//! @param ulPriority ulPriority profile priority. Lowest priority:0. -//! @param ulPairwiseCipher_Or_TxKeyLen key length for WEP security -//! @param ulGroupCipher_TxKeyIndex key index -//! @param ulKeyMgmt KEY management -//! @param ucPf_OrKey security key -//! @param ulPassPhraseLen security key length for WPA\WPA2 -//! -//! @return On success, zero is returned. On error, -1 is returned -//! -//! @brief When auto start is enabled, the device connects to -//! station from the profiles table. Up to 7 profiles are supported. -//! If several profiles configured the device choose the highest -//! priority profile, within each priority group, device will choose -//! profile based on security policy, signal strength, etc -//! parameters. All the profiles are stored in CC3000 NVMEM. -//! -//! @sa wlan_ioctl_del_profile -// -//***************************************************************************** - -#ifndef CC3000_TINY_DRIVER -long -wlan_add_profile(unsigned long ulSecType, - unsigned char* ucSsid, - unsigned long ulSsidLen, - unsigned char *ucBssid, - unsigned long ulPriority, - unsigned long ulPairwiseCipher_Or_TxKeyLen, - unsigned long ulGroupCipher_TxKeyIndex, - unsigned long ulKeyMgmt, - unsigned char* ucPf_OrKey, - unsigned long ulPassPhraseLen) -{ - unsigned short arg_len = 0; - long ret; - unsigned char *ptr; - long i = 0; - unsigned char *args; - unsigned char bssid_zero[] = {0, 0, 0, 0, 0, 0}; - - ptr = tSLInformation.pucTxCommandBuffer; - args = (ptr + HEADERS_SIZE_CMD); - - args = UINT32_TO_STREAM(args, ulSecType); - - // Setup arguments in accordance with the security type - switch (ulSecType) - { - //OPEN - case WLAN_SEC_UNSEC: - { - args = UINT32_TO_STREAM(args, 0x00000014); - args = UINT32_TO_STREAM(args, ulSsidLen); - args = UINT16_TO_STREAM(args, 0); - if(ucBssid) - { - ARRAY_TO_STREAM(args, ucBssid, ETH_ALEN); - } - else - { - ARRAY_TO_STREAM(args, bssid_zero, ETH_ALEN); - } - args = UINT32_TO_STREAM(args, ulPriority); - ARRAY_TO_STREAM(args, ucSsid, ulSsidLen); - - arg_len = WLAN_ADD_PROFILE_NOSEC_PARAM_LEN + ulSsidLen; - } - break; - - //WEP - case WLAN_SEC_WEP: - { - args = UINT32_TO_STREAM(args, 0x00000020); - args = UINT32_TO_STREAM(args, ulSsidLen); - args = UINT16_TO_STREAM(args, 0); - if(ucBssid) - { - ARRAY_TO_STREAM(args, ucBssid, ETH_ALEN); - } - else - { - ARRAY_TO_STREAM(args, bssid_zero, ETH_ALEN); - } - args = UINT32_TO_STREAM(args, ulPriority); - args = UINT32_TO_STREAM(args, 0x0000000C + ulSsidLen); - args = UINT32_TO_STREAM(args, ulPairwiseCipher_Or_TxKeyLen); - args = UINT32_TO_STREAM(args, ulGroupCipher_TxKeyIndex); - ARRAY_TO_STREAM(args, ucSsid, ulSsidLen); - - for(i = 0; i < 4; i++) - { - unsigned char *p = &ucPf_OrKey[i * ulPairwiseCipher_Or_TxKeyLen]; - - ARRAY_TO_STREAM(args, p, ulPairwiseCipher_Or_TxKeyLen); - } - - arg_len = WLAN_ADD_PROFILE_WEP_PARAM_LEN + ulSsidLen + - ulPairwiseCipher_Or_TxKeyLen * 4; - - } - break; - - //WPA - //WPA2 - case WLAN_SEC_WPA: - case WLAN_SEC_WPA2: - { - args = UINT32_TO_STREAM(args, 0x00000028); - args = UINT32_TO_STREAM(args, ulSsidLen); - args = UINT16_TO_STREAM(args, 0); - if(ucBssid) - { - ARRAY_TO_STREAM(args, ucBssid, ETH_ALEN); - } - else - { - ARRAY_TO_STREAM(args, bssid_zero, ETH_ALEN); - } - args = UINT32_TO_STREAM(args, ulPriority); - args = UINT32_TO_STREAM(args, ulPairwiseCipher_Or_TxKeyLen); - args = UINT32_TO_STREAM(args, ulGroupCipher_TxKeyIndex); - args = UINT32_TO_STREAM(args, ulKeyMgmt); - args = UINT32_TO_STREAM(args, 0x00000008 + ulSsidLen); - args = UINT32_TO_STREAM(args, ulPassPhraseLen); - ARRAY_TO_STREAM(args, ucSsid, ulSsidLen); - ARRAY_TO_STREAM(args, ucPf_OrKey, ulPassPhraseLen); - - arg_len = WLAN_ADD_PROFILE_WPA_PARAM_LEN + ulSsidLen + ulPassPhraseLen; - } - - break; - } - - // Initiate a HCI command - hci_command_send(HCI_CMND_WLAN_IOCTL_ADD_PROFILE, ptr, arg_len); - - // Wait for command complete event - SimpleLinkWaitEvent(HCI_CMND_WLAN_IOCTL_ADD_PROFILE, &ret); - - return(ret); -} -#else -long -wlan_add_profile(unsigned long ulSecType, - unsigned char* ucSsid, - unsigned long ulSsidLen, - unsigned char *ucBssid, - unsigned long ulPriority, - unsigned long ulPairwiseCipher_Or_TxKeyLen, - unsigned long ulGroupCipher_TxKeyIndex, - unsigned long ulKeyMgmt, - unsigned char* ucPf_OrKey, - unsigned long ulPassPhraseLen) -{ - return -1; -} -#endif - -//***************************************************************************** -// -//! wlan_ioctl_del_profile -//! -//! @param index number of profile to delete -//! -//! @return On success, zero is returned. On error, -1 is returned -//! -//! @brief Delete WLAN profile -//! -//! @Note In order to delete all stored profile, set index to 255. -//! -//! @sa wlan_add_profile -// -//***************************************************************************** - -long -wlan_ioctl_del_profile(unsigned long ulIndex) -{ - long ret; - unsigned char *ptr; - unsigned char *args; - - ptr = tSLInformation.pucTxCommandBuffer; - args = (unsigned char *)(ptr + HEADERS_SIZE_CMD); - - // Fill in HCI packet structure - args = UINT32_TO_STREAM(args, ulIndex); - ret = EFAIL; - - // Initiate a HCI command - hci_command_send(HCI_CMND_WLAN_IOCTL_DEL_PROFILE, - ptr, WLAN_DEL_PROFILE_PARAMS_LEN); - - // Wait for command complete event - SimpleLinkWaitEvent(HCI_CMND_WLAN_IOCTL_DEL_PROFILE, &ret); - - return(ret); -} - -//***************************************************************************** -// -//! wlan_ioctl_get_scan_results -//! -//! @param[in] scan_timeout parameter not supported -//! @param[out] ucResults scan results (_wlan_full_scan_results_args_t) -//! -//! @return On success, zero is returned. On error, -1 is returned -//! -//! @brief Gets entry from scan result table. -//! The scan results are returned one by one, and each entry -//! represents a single AP found in the area. The following is a -//! format of the scan result: -//! - 4 Bytes: number of networks found -//! - 4 Bytes: The status of the scan: 0 - aged results, -//! 1 - results valid, 2 - no results -//! - 42 bytes: Result entry, where the bytes are arranged as follows: -//! -//! - 1 bit isValid - is result valid or not -//! - 7 bits rssi - RSSI value; -//! - 2 bits: securityMode - security mode of the AP: -//! 0 - Open, 1 - WEP, 2 WPA, 3 WPA2 -//! - 6 bits: SSID name length -//! - 2 bytes: the time at which the entry has entered into -//! scans result table -//! - 32 bytes: SSID name -//! - 6 bytes: BSSID -//! -//! @Note scan_timeout, is not supported on this version. -//! -//! @sa wlan_ioctl_set_scan_params -// -//***************************************************************************** - -#ifndef CC3000_TINY_DRIVER -long -wlan_ioctl_get_scan_results(unsigned long ulScanTimeout, - unsigned char *ucResults) -{ - unsigned char *ptr; - unsigned char *args; - - ptr = tSLInformation.pucTxCommandBuffer; - args = (ptr + HEADERS_SIZE_CMD); - - // Fill in temporary command buffer - args = UINT32_TO_STREAM(args, ulScanTimeout); - - // Initiate a HCI command - hci_command_send(HCI_CMND_WLAN_IOCTL_GET_SCAN_RESULTS, - ptr, WLAN_GET_SCAN_RESULTS_PARAMS_LEN); - - // Wait for command complete event - SimpleLinkWaitEvent(HCI_CMND_WLAN_IOCTL_GET_SCAN_RESULTS, ucResults); - - return(0); -} -#endif - -//***************************************************************************** -// -//! wlan_ioctl_set_scan_params -//! -//! @param uiEnable - start/stop application scan: -//! 1 = start scan with default interval value of 10 min. -//! in order to set a different scan interval value apply the value -//! in milliseconds. minimum 1 second. 0=stop). Wlan reset -//! (wlan_stop() wlan_start()) is needed when changing scan interval -//! value. Saved: No -//! @param uiMinDwellTime minimum dwell time value to be used for each -//! channel, in milliseconds. Saved: yes -//! Recommended Value: 100 (Default: 20) -//! @param uiMaxDwellTime maximum dwell time value to be used for each -//! channel, in milliseconds. Saved: yes -//! Recommended Value: 100 (Default: 30) -//! @param uiNumOfProbeRequests max probe request between dwell time. -//! Saved: yes. Recommended Value: 5 (Default:2) -//! @param uiChannelMask bitwise, up to 13 channels (0x1fff). -//! Saved: yes. Default: 0x7ff -//! @param uiRSSIThreshold RSSI threshold. Saved: yes (Default: -80) -//! @param uiSNRThreshold NSR threshold. Saved: yes (Default: 0) -//! @param uiDefaultTxPower probe Tx power. Saved: yes (Default: 205) -//! @param aiIntervalList pointer to array with 16 entries (16 channels) -//! each entry (unsigned long) holds timeout between periodic scan -//! (connection scan) - in millisecond. Saved: yes. Default 2000ms. -//! -//! @return On success, zero is returned. On error, -1 is returned -//! -//! @brief start and stop scan procedure. Set scan parameters. -//! -//! @Note uiDefaultTxPower, is not supported on this version. -//! -//! @sa wlan_ioctl_get_scan_results -// -//***************************************************************************** - -#ifndef CC3000_TINY_DRIVER -long -wlan_ioctl_set_scan_params(unsigned long uiEnable, unsigned long uiMinDwellTime, - unsigned long uiMaxDwellTime, - unsigned long uiNumOfProbeRequests, - unsigned long uiChannelMask,long iRSSIThreshold, - unsigned long uiSNRThreshold, - unsigned long uiDefaultTxPower, - unsigned long *aiIntervalList) -{ - unsigned long uiRes; - unsigned char *ptr; - unsigned char *args; - - ptr = tSLInformation.pucTxCommandBuffer; - args = (ptr + HEADERS_SIZE_CMD); - - // Fill in temporary command buffer - args = UINT32_TO_STREAM(args, 36); - args = UINT32_TO_STREAM(args, uiEnable); - args = UINT32_TO_STREAM(args, uiMinDwellTime); - args = UINT32_TO_STREAM(args, uiMaxDwellTime); - args = UINT32_TO_STREAM(args, uiNumOfProbeRequests); - args = UINT32_TO_STREAM(args, uiChannelMask); - args = UINT32_TO_STREAM(args, iRSSIThreshold); - args = UINT32_TO_STREAM(args, uiSNRThreshold); - args = UINT32_TO_STREAM(args, uiDefaultTxPower); - ARRAY_TO_STREAM(args, aiIntervalList, sizeof(unsigned long) * - SL_SET_SCAN_PARAMS_INTERVAL_LIST_SIZE); - - // Initiate a HCI command - hci_command_send(HCI_CMND_WLAN_IOCTL_SET_SCANPARAM, - ptr, WLAN_SET_SCAN_PARAMS_LEN); - - // Wait for command complete event - SimpleLinkWaitEvent(HCI_CMND_WLAN_IOCTL_SET_SCANPARAM, &uiRes); - - return(uiRes); -} -#endif - -//***************************************************************************** -// -//! wlan_set_event_mask -//! -//! @param mask mask option: -//! HCI_EVNT_WLAN_UNSOL_CONNECT connect event -//! HCI_EVNT_WLAN_UNSOL_DISCONNECT disconnect event -//! HCI_EVNT_WLAN_ASYNC_SIMPLE_CONFIG_DONE smart config done -//! HCI_EVNT_WLAN_UNSOL_INIT init done -//! HCI_EVNT_WLAN_UNSOL_DHCP dhcp event report -//! HCI_EVNT_WLAN_ASYNC_PING_REPORT ping report -//! HCI_EVNT_WLAN_KEEPALIVE keepalive -//! HCI_EVNT_WLAN_TX_COMPLETE - disable information on end of transmission -//! Saved: no. -//! -//! @return On success, zero is returned. On error, -1 is returned -//! -//! @brief Mask event according to bit mask. In case that event is -//! masked (1), the device will not send the masked event to host. -// -//***************************************************************************** - -long -wlan_set_event_mask(unsigned long ulMask) -{ - long ret; - unsigned char *ptr; - unsigned char *args; - - - if ((ulMask & HCI_EVNT_WLAN_TX_COMPLETE) == HCI_EVNT_WLAN_TX_COMPLETE) - { - tSLInformation.InformHostOnTxComplete = 0; - - // Since an event is a virtual event - i.e. it is not coming from CC3000 - // there is no need to send anything to the device if it was an only event - if (ulMask == HCI_EVNT_WLAN_TX_COMPLETE) - { - return 0; - } - - ulMask &= ~HCI_EVNT_WLAN_TX_COMPLETE; - ulMask |= HCI_EVNT_WLAN_UNSOL_BASE; - } - else - { - tSLInformation.InformHostOnTxComplete = 1; - } - - ret = EFAIL; - ptr = tSLInformation.pucTxCommandBuffer; - args = (unsigned char *)(ptr + HEADERS_SIZE_CMD); - - // Fill in HCI packet structure - args = UINT32_TO_STREAM(args, ulMask); - - // Initiate a HCI command - hci_command_send(HCI_CMND_EVENT_MASK, - ptr, WLAN_SET_MASK_PARAMS_LEN); - - // Wait for command complete event - SimpleLinkWaitEvent(HCI_CMND_EVENT_MASK, &ret); - - return(ret); -} - -//***************************************************************************** -// -//! wlan_ioctl_statusget -//! -//! @param none -//! -//! @return WLAN_STATUS_DISCONNECTED, WLAN_STATUS_SCANING, -//! STATUS_CONNECTING or WLAN_STATUS_CONNECTED -//! -//! @brief get wlan status: disconnected, scanning, connecting or connected -// -//***************************************************************************** - -#ifndef CC3000_TINY_DRIVER -long -wlan_ioctl_statusget(void) -{ - long ret; - unsigned char *ptr; - - ret = EFAIL; - ptr = tSLInformation.pucTxCommandBuffer; - - hci_command_send(HCI_CMND_WLAN_IOCTL_STATUSGET, - ptr, 0); - - // Wait for command complete event - SimpleLinkWaitEvent(HCI_CMND_WLAN_IOCTL_STATUSGET, &ret); - - return(ret); -} -#endif - -//***************************************************************************** -// -//! wlan_smart_config_start -//! -//! @param algoEncryptedFlag indicates whether the information is encrypted -//! -//! @return On success, zero is returned. On error, -1 is returned -//! -//! @brief Start to acquire device profile. The device acquire its own -//! profile, if profile message is found. The acquired AP information -//! is stored in CC3000 EEPROM only in case AES128 encryption is used. -//! In case AES128 encryption is not used, a profile is created by -//! CC3000 internally. -//! -//! @Note An asynchronous event - Smart Config Done will be generated as soon -//! as the process finishes successfully. -//! -//! @sa wlan_smart_config_set_prefix , wlan_smart_config_stop -// -//***************************************************************************** - -long -wlan_smart_config_start(unsigned long algoEncryptedFlag) -{ - long ret; - unsigned char *ptr; - unsigned char *args; - - ret = EFAIL; - ptr = tSLInformation.pucTxCommandBuffer; - args = (unsigned char *)(ptr + HEADERS_SIZE_CMD); - - // Fill in HCI packet structure - args = UINT32_TO_STREAM(args, algoEncryptedFlag); - ret = EFAIL; - - hci_command_send(HCI_CMND_WLAN_IOCTL_SIMPLE_CONFIG_START, ptr, - WLAN_SMART_CONFIG_START_PARAMS_LEN); - - // Wait for command complete event - SimpleLinkWaitEvent(HCI_CMND_WLAN_IOCTL_SIMPLE_CONFIG_START, &ret); - - return(ret); -} - -//***************************************************************************** -// -//! wlan_smart_config_stop -//! -//! @param algoEncryptedFlag indicates whether the information is encrypted -//! -//! @return On success, zero is returned. On error, -1 is returned -//! -//! @brief Stop the acquire profile procedure -//! -//! @sa wlan_smart_config_start , wlan_smart_config_set_prefix -// -//***************************************************************************** - -long -wlan_smart_config_stop(void) -{ - long ret; - unsigned char *ptr; - - ret = EFAIL; - ptr = tSLInformation.pucTxCommandBuffer; - - hci_command_send(HCI_CMND_WLAN_IOCTL_SIMPLE_CONFIG_STOP, ptr, 0); - - // Wait for command complete event - SimpleLinkWaitEvent(HCI_CMND_WLAN_IOCTL_SIMPLE_CONFIG_STOP, &ret); - - return(ret); -} - -//***************************************************************************** -// -//! wlan_smart_config_set_prefix -//! -//! @param newPrefix 3 bytes identify the SSID prefix for the Smart Config. -//! -//! @return On success, zero is returned. On error, -1 is returned -//! -//! @brief Configure station ssid prefix. The prefix is used internally -//! in CC3000. It should always be TTT. -//! -//! @Note The prefix is stored in CC3000 NVMEM -//! -//! @sa wlan_smart_config_start , wlan_smart_config_stop -// -//***************************************************************************** - -long -wlan_smart_config_set_prefix(char* cNewPrefix) -{ - long ret; - unsigned char *ptr; - unsigned char *args; - - ret = EFAIL; - ptr = tSLInformation.pucTxCommandBuffer; - args = (ptr + HEADERS_SIZE_CMD); - - if (cNewPrefix == NULL) - return ret; - else // with the new Smart Config, prefix must be TTT - { - *cNewPrefix = 'T'; - *(cNewPrefix + 1) = 'T'; - *(cNewPrefix + 2) = 'T'; - } - - ARRAY_TO_STREAM(args, cNewPrefix, SL_SIMPLE_CONFIG_PREFIX_LENGTH); - - hci_command_send(HCI_CMND_WLAN_IOCTL_SIMPLE_CONFIG_SET_PREFIX, ptr, - SL_SIMPLE_CONFIG_PREFIX_LENGTH); - - // Wait for command complete event - SimpleLinkWaitEvent(HCI_CMND_WLAN_IOCTL_SIMPLE_CONFIG_SET_PREFIX, &ret); - - return(ret); -} - -//***************************************************************************** -// -//! wlan_smart_config_process -//! -//! @param none -//! -//! @return On success, zero is returned. On error, -1 is returned -//! -//! @brief process the acquired data and store it as a profile. The acquired -//! AP information is stored in CC3000 EEPROM encrypted. -//! The encrypted data is decrypted and stored as a profile. -//! behavior is as defined by connection policy. -// -//***************************************************************************** - - -#ifndef CC3000_UNENCRYPTED_SMART_CONFIG -long -wlan_smart_config_process() -{ - signed long returnValue; - unsigned long ssidLen, keyLen; - unsigned char *decKeyPtr; - unsigned char *ssidPtr; - - // read the key from EEPROM - fileID 12 - returnValue = aes_read_key(key); - - if (returnValue != 0) - return returnValue; - - // read the received data from fileID #13 and parse it according to the followings: - // 1) SSID LEN - not encrypted - // 2) SSID - not encrypted - // 3) KEY LEN - not encrypted. always 32 bytes long - // 4) Security type - not encrypted - // 5) KEY - encrypted together with true key length as the first byte in KEY - // to elaborate, there are two corner cases: - // 1) the KEY is 32 bytes long. In this case, the first byte does not represent KEY length - // 2) the KEY is 31 bytes long. In this case, the first byte represent KEY length and equals 31 - returnValue = nvmem_read(NVMEM_SHARED_MEM_FILEID, SMART_CONFIG_PROFILE_SIZE, 0, profileArray); - - if (returnValue != 0) - return returnValue; - - ssidPtr = &profileArray[1]; - - ssidLen = profileArray[0]; - - decKeyPtr = &profileArray[profileArray[0] + 3]; - - aes_decrypt(decKeyPtr, key); - if (profileArray[profileArray[0] + 1] > 16) - aes_decrypt((unsigned char *)(decKeyPtr + 16), key); - - if (*(unsigned char *)(decKeyPtr +31) != 0) - { - if (*decKeyPtr == 31) - { - keyLen = 31; - decKeyPtr++; - } - else - { - keyLen = 32; - } - } - else - { - keyLen = *decKeyPtr; - decKeyPtr++; - } - - // add a profile - switch (profileArray[profileArray[0] + 2]) - { - case WLAN_SEC_UNSEC://None - { - returnValue = wlan_add_profile(profileArray[profileArray[0] + 2], // security type - ssidPtr, // SSID - ssidLen, // SSID length - NULL, // BSSID - 1, // Priority - 0, 0, 0, 0, 0); - - break; - } - - case WLAN_SEC_WEP://WEP - { - returnValue = wlan_add_profile(profileArray[profileArray[0] + 2], // security type - ssidPtr, // SSID - ssidLen, // SSID length - NULL, // BSSID - 1, // Priority - keyLen, // KEY length - 0, // KEY index - 0, - decKeyPtr, // KEY - 0); - - break; - } - - case WLAN_SEC_WPA://WPA - case WLAN_SEC_WPA2://WPA2 - { - returnValue = wlan_add_profile(WLAN_SEC_WPA2, // security type - ssidPtr, - ssidLen, - NULL, // BSSID - 1, // Priority - 0x18, // PairwiseCipher - 0x1e, // GroupCipher - 2, // KEY management - decKeyPtr, // KEY - keyLen); // KEY length - - break; - } - } - - return returnValue; -} -#endif //CC3000_UNENCRYPTED_SMART_CONFIG - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/stm/cc3k/wlan.h b/stm/cc3k/wlan.h deleted file mode 100644 index d5ccd363f..000000000 --- a/stm/cc3k/wlan.h +++ /dev/null @@ -1,533 +0,0 @@ -/***************************************************************************** -* -* wlan.h - CC3000 Host Driver Implementation. -* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ -* -* Adapted for use with the Arduino/AVR by KTOWN (Kevin Townsend) -* & Limor Fried for Adafruit Industries -* This library works with the Adafruit CC3000 breakout -* ----> https://www.adafruit.com/products/1469 -* Adafruit invests time and resources providing this open source code, -* please support Adafruit and open-source hardware by purchasing -* products from Adafruit! -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* - -Adapted for use with the Arduino/AVR by KTOWN for Adafruit Industries -This library works with the Adafruit CC3000 breakout - ----> https://www.adafruit.com/products/1469 -Adafruit invests time and resources providing this open source code, -please support Adafruit and open-source hardware by purchasing -products from Adafruit! - -*****************************************************************************/ -#ifndef __WLAN_H__ -#define __WLAN_H__ - -#include "cc3000_common.h" - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" { -#endif - -#define WLAN_SEC_UNSEC (0) -#define WLAN_SEC_WEP (1) -#define WLAN_SEC_WPA (2) -#define WLAN_SEC_WPA2 (3) -//***************************************************************************** -// -//! \addtogroup wlan_api -//! @{ -// -//***************************************************************************** - - -//***************************************************************************** -// -//! wlan_init -//! -//! @param sWlanCB Asynchronous events callback. -//! 0 no event call back. -//! -call back parameters: -//! 1) event_type: HCI_EVNT_WLAN_UNSOL_CONNECT connect event, -//! HCI_EVNT_WLAN_UNSOL_DISCONNECT disconnect event, -//! HCI_EVNT_WLAN_ASYNC_SIMPLE_CONFIG_DONE config done, -//! HCI_EVNT_WLAN_UNSOL_DHCP dhcp report, -//! HCI_EVNT_WLAN_ASYNC_PING_REPORT ping report OR -//! HCI_EVNT_WLAN_KEEPALIVE keepalive. -//! 2) data: pointer to extra data that received by the event -//! (NULL no data). -//! 3) length: data length. -//! -Events with extra data: -//! HCI_EVNT_WLAN_UNSOL_DHCP: 4 bytes IP, 4 bytes Mask, -//! 4 bytes default gateway, 4 bytes DHCP server and 4 bytes -//! for DNS server. -//! HCI_EVNT_WLAN_ASYNC_PING_REPORT: 4 bytes Packets sent, -//! 4 bytes Packets received, 4 bytes Min round time, -//! 4 bytes Max round time and 4 bytes for Avg round time. -//! -//! @param sFWPatches 0 no patch or pointer to FW patches -//! @param sDriverPatches 0 no patch or pointer to driver patches -//! @param sBootLoaderPatches 0 no patch or pointer to bootloader patches -//! @param sReadWlanInterruptPin init callback. the callback read wlan -//! interrupt status. -//! @param sWlanInterruptEnable init callback. the callback enable wlan -//! interrupt. -//! @param sWlanInterruptDisable init callback. the callback disable wlan -//! interrupt. -//! @param sWriteWlanPin init callback. the callback write value -//! to device pin. -//! -//! @return none -//! -//! @sa wlan_set_event_mask , wlan_start , wlan_stop -//! -//! @brief Initialize wlan driver -//! -//! @warning This function must be called before ANY other wlan driver function -// -//***************************************************************************** -extern void wlan_init( tWlanCB sWlanCB, - tFWPatches sFWPatches, - tDriverPatches sDriverPatches, - tBootLoaderPatches sBootLoaderPatches, - tWlanReadInteruptPin sReadWlanInterruptPin, - tWlanInterruptEnable sWlanInterruptEnable, - tWlanInterruptDisable sWlanInterruptDisable, - tWriteWlanPin sWriteWlanPin); - - - -//***************************************************************************** -// -//! wlan_start -//! -//! @param usPatchesAvailableAtHost - flag to indicate if patches available -//! from host or from EEPROM. Due to the -//! fact the patches are burn to the EEPROM -//! using the patch programmer utility, the -//! patches will be available from the EEPROM -//! and not from the host. -//! -//! @return none -//! -//! @brief Start WLAN device. This function asserts the enable pin of -//! the device (WLAN_EN), starting the HW initialization process. -//! The function blocked until device Initialization is completed. -//! Function also configure patches (FW, driver or bootloader) -//! and calls appropriate device callbacks. -//! -//! @Note Prior calling the function wlan_init shall be called. -//! @Warning This function must be called after wlan_init and before any -//! other wlan API -//! @sa wlan_init , wlan_stop -//! -// -//***************************************************************************** -extern void wlan_start(unsigned short usPatchesAvailableAtHost); - -//***************************************************************************** -// -//! wlan_stop -//! -//! @param none -//! -//! @return none -//! -//! @brief Stop WLAN device by putting it into reset state. -//! -//! @sa wlan_start -// -//***************************************************************************** -extern void wlan_stop(void); - -//***************************************************************************** -// -//! wlan_connect -//! -//! @param sec_type security options: -//! WLAN_SEC_UNSEC, -//! WLAN_SEC_WEP (ASCII support only), -//! WLAN_SEC_WPA or WLAN_SEC_WPA2 -//! @param ssid up to 32 bytes and is ASCII SSID of the AP -//! @param ssid_len length of the SSID -//! @param bssid 6 bytes specified the AP bssid -//! @param key up to 16 bytes specified the AP security key -//! @param key_len key length -//! -//! @return On success, zero is returned. On error, negative is returned. -//! Note that even though a zero is returned on success to trigger -//! connection operation, it does not mean that CCC3000 is already -//! connected. An asynchronous "Connected" event is generated when -//! actual association process finishes and CC3000 is connected to -//! the AP. If DHCP is set, An asynchronous "DHCP" event is -//! generated when DHCP process is finish. -//! -//! -//! @brief Connect to AP -//! @warning Please Note that when connection to AP configured with security -//! type WEP, please confirm that the key is set as ASCII and not -//! as HEX. -//! @sa wlan_disconnect -// -//***************************************************************************** -#ifndef CC3000_TINY_DRIVER -extern long wlan_connect(unsigned long ulSecType, const char *ssid, long ssid_len, - unsigned char *bssid, unsigned char *key, long key_len); -#else -extern long wlan_connect(const char *ssid, long ssid_len); - -#endif - -//***************************************************************************** -// -//! wlan_disconnect -//! -//! @return 0 disconnected done, other CC3000 already disconnected -//! -//! @brief Disconnect connection from AP. -//! -//! @sa wlan_connect -// -//***************************************************************************** - -extern long wlan_disconnect(void); - -//***************************************************************************** -// -//! wlan_add_profile -//! -//! @param ulSecType WLAN_SEC_UNSEC,WLAN_SEC_WEP,WLAN_SEC_WPA,WLAN_SEC_WPA2 -//! @param ucSsid ssid SSID up to 32 bytes -//! @param ulSsidLen ssid length -//! @param ucBssid bssid 6 bytes -//! @param ulPriority ulPriority profile priority. Lowest priority:0. -//! @param ulPairwiseCipher_Or_TxKeyLen key length for WEP security -//! @param ulGroupCipher_TxKeyIndex key index -//! @param ulKeyMgmt KEY management -//! @param ucPf_OrKey security key -//! @param ulPassPhraseLen security key length for WPA\WPA2 -//! -//! @return On success, zero is returned. On error, -1 is returned -//! -//! @brief When auto start is enabled, the device connects to -//! station from the profiles table. Up to 7 profiles are supported. -//! If several profiles configured the device choose the highest -//! priority profile, within each priority group, device will choose -//! profile based on security policy, signal strength, etc -//! parameters. All the profiles are stored in CC3000 NVMEM. -//! -//! @sa wlan_ioctl_del_profile -// -//***************************************************************************** - -extern long wlan_add_profile(unsigned long ulSecType, unsigned char* ucSsid, - unsigned long ulSsidLen, - unsigned char *ucBssid, - unsigned long ulPriority, - unsigned long ulPairwiseCipher_Or_Key, - unsigned long ulGroupCipher_TxKeyLen, - unsigned long ulKeyMgmt, - unsigned char* ucPf_OrKey, - unsigned long ulPassPhraseLen); - - - -//***************************************************************************** -// -//! wlan_ioctl_del_profile -//! -//! @param index number of profile to delete -//! -//! @return On success, zero is returned. On error, -1 is returned -//! -//! @brief Delete WLAN profile -//! -//! @Note In order to delete all stored profile, set index to 255. -//! -//! @sa wlan_add_profile -// -//***************************************************************************** -extern long wlan_ioctl_del_profile(unsigned long ulIndex); - -//***************************************************************************** -// -//! wlan_set_event_mask -//! -//! @param mask mask option: -//! HCI_EVNT_WLAN_UNSOL_CONNECT connect event -//! HCI_EVNT_WLAN_UNSOL_DISCONNECT disconnect event -//! HCI_EVNT_WLAN_ASYNC_SIMPLE_CONFIG_DONE smart config done -//! HCI_EVNT_WLAN_UNSOL_INIT init done -//! HCI_EVNT_WLAN_UNSOL_DHCP dhcp event report -//! HCI_EVNT_WLAN_ASYNC_PING_REPORT ping report -//! HCI_EVNT_WLAN_KEEPALIVE keepalive -//! HCI_EVNT_WLAN_TX_COMPLETE - disable information on end of transmission -//! Saved: no. -//! -//! @return On success, zero is returned. On error, -1 is returned -//! -//! @brief Mask event according to bit mask. In case that event is -//! masked (1), the device will not send the masked event to host. -// -//***************************************************************************** -extern long wlan_set_event_mask(unsigned long ulMask); - -//***************************************************************************** -// -//! wlan_ioctl_statusget -//! -//! @param none -//! -//! @return WLAN_STATUS_DISCONNECTED, WLAN_STATUS_SCANING, -//! STATUS_CONNECTING or WLAN_STATUS_CONNECTED -//! -//! @brief get wlan status: disconnected, scanning, connecting or connected -// -//***************************************************************************** -extern long wlan_ioctl_statusget(void); - - -//***************************************************************************** -// -//! wlan_ioctl_set_connection_policy -//! -//! @param should_connect_to_open_ap enable(1), disable(0) connect to any -//! available AP. This parameter corresponds to the configuration of -//! item # 3 in the brief description. -//! @param should_use_fast_connect enable(1), disable(0). if enabled, tries -//! to connect to the last connected AP. This parameter corresponds -//! to the configuration of item # 1 in the brief description. -//! @param auto_start enable(1), disable(0) auto connect -//! after reset and periodically reconnect if needed. This -//! configuration configures option 2 in the above description. -//! -//! @return On success, zero is returned. On error, -1 is returned -//! -//! @brief When auto is enabled, the device tries to connect according -//! the following policy: -//! 1) If fast connect is enabled and last connection is valid, -//! the device will try to connect to it without the scanning -//! procedure (fast). The last connection will be marked as -//! invalid, due to adding/removing profile. -//! 2) If profile exists, the device will try to connect it -//! (Up to seven profiles). -//! 3) If fast and profiles are not found, and open mode is -//! enabled, the device will try to connect to any AP. -//! * Note that the policy settings are stored in the CC3000 NVMEM. -//! -//! @sa wlan_add_profile , wlan_ioctl_del_profile -// -//***************************************************************************** -extern long wlan_ioctl_set_connection_policy( - unsigned long should_connect_to_open_ap, - unsigned long should_use_fast_connect, - unsigned long ulUseProfiles); - -//***************************************************************************** -// -//! wlan_ioctl_get_scan_results -//! -//! @param[in] scan_timeout parameter not supported -//! @param[out] ucResults scan result (_wlan_full_scan_results_args_t) -//! -//! @return On success, zero is returned. On error, -1 is returned -//! -//! @brief Gets entry from scan result table. -//! The scan results are returned one by one, and each entry -//! represents a single AP found in the area. The following is a -//! format of the scan result: -//! - 4 Bytes: number of networks found -//! - 4 Bytes: The status of the scan: 0 - aged results, -//! 1 - results valid, 2 - no results -//! - 42 bytes: Result entry, where the bytes are arranged as follows: -//! -//! - 1 bit isValid - is result valid or not -//! - 7 bits rssi - RSSI value; -//! - 2 bits: securityMode - security mode of the AP: -//! 0 - Open, 1 - WEP, 2 WPA, 3 WPA2 -//! - 6 bits: SSID name length -//! - 2 bytes: the time at which the entry has entered into -//! scans result table -//! - 32 bytes: SSID name -//! - 6 bytes: BSSID -//! -//! @Note scan_timeout, is not supported on this version. -//! -//! @sa wlan_ioctl_set_scan_params -// -//***************************************************************************** - - -extern long wlan_ioctl_get_scan_results(unsigned long ulScanTimeout, - unsigned char *ucResults); - -//***************************************************************************** -// -//! wlan_ioctl_set_scan_params -//! -//! @param uiEnable - start/stop application scan: -//! 1 = start scan with default interval value of 10 min. -//! in order to set a different scan interval value apply the value -//! in milliseconds. minimum 1 second. 0=stop). Wlan reset -//! (wlan_stop() wlan_start()) is needed when changing scan interval -//! value. Saved: No -//! @param uiMinDwellTime minimum dwell time value to be used for each -//! channel, in milliseconds. Saved: yes -//! Recommended Value: 100 (Default: 20) -//! @param uiMaxDwellTime maximum dwell time value to be used for each -//! channel, in milliseconds. Saved: yes -//! Recommended Value: 100 (Default: 30) -//! @param uiNumOfProbeRequests max probe request between dwell time. -//! Saved: yes. Recommended Value: 5 (Default:2) -//! @param uiChannelMask bitwise, up to 13 channels (0x1fff). -//! Saved: yes. Default: 0x7ff -//! @param uiRSSIThreshold RSSI threshold. Saved: yes (Default: -80) -//! @param uiSNRThreshold NSR threshold. Saved: yes (Default: 0) -//! @param uiDefaultTxPower probe Tx power. Saved: yes (Default: 205) -//! @param aiIntervalList pointer to array with 16 entries (16 channels) -//! each entry (unsigned long) holds timeout between periodic scan -//! (connection scan) - in milliseconds. Saved: yes. Default 2000ms. -//! -//! @return On success, zero is returned. On error, -1 is returned -//! -//! @brief start and stop scan procedure. Set scan parameters. -//! -//! @Note uiDefaultTxPower, is not supported on this version. -//! -//! @sa wlan_ioctl_get_scan_results -// -//***************************************************************************** -extern long wlan_ioctl_set_scan_params(unsigned long uiEnable, unsigned long - uiMinDwellTime,unsigned long uiMaxDwellTime, - unsigned long uiNumOfProbeRequests, - unsigned long uiChannelMask, - long iRSSIThreshold,unsigned long uiSNRThreshold, - unsigned long uiDefaultTxPower, - unsigned long *aiIntervalList); - - -//***************************************************************************** -// -//! wlan_smart_config_start -//! -//! @param algoEncryptedFlag indicates whether the information is encrypted -//! -//! @return On success, zero is returned. On error, -1 is returned -//! -//! @brief Start to acquire device profile. The device acquire its own -//! profile, if profile message is found. The acquired AP information -//! is stored in CC3000 EEPROM only in case AES128 encryption is used. -//! In case AES128 encryption is not used, a profile is created by -//! CC3000 internally. -//! -//! @Note An asynchronous event - Smart Config Done will be generated as soon -//! as the process finishes successfully. -//! -//! @sa wlan_smart_config_set_prefix , wlan_smart_config_stop -// -//***************************************************************************** -extern long wlan_smart_config_start(unsigned long algoEncryptedFlag); - - -//***************************************************************************** -// -//! wlan_smart_config_stop -//! -//! @param algoEncryptedFlag indicates whether the information is encrypted -//! -//! @return On success, zero is returned. On error, -1 is returned -//! -//! @brief Stop the acquire profile procedure -//! -//! @sa wlan_smart_config_start , wlan_smart_config_set_prefix -// -//***************************************************************************** -extern long wlan_smart_config_stop(void); - -//***************************************************************************** -// -//! wlan_smart_config_set_prefix -//! -//! @param newPrefix 3 bytes identify the SSID prefix for the Smart Config. -//! -//! @return On success, zero is returned. On error, -1 is returned -//! -//! @brief Configure station ssid prefix. The prefix is used internally -//! in CC3000. It should always be TTT. -//! -//! @Note The prefix is stored in CC3000 NVMEM -//! -//! @sa wlan_smart_config_start , wlan_smart_config_stop -// -//***************************************************************************** -extern long wlan_smart_config_set_prefix(char* cNewPrefix); - -//***************************************************************************** -// -//! wlan_smart_config_process -//! -//! @param none -//! -//! @return On success, zero is returned. On error, -1 is returned -//! -//! @brief process the acquired data and store it as a profile. The acquired -//! AP information is stored in CC3000 EEPROM encrypted. -//! The encrypted data is decrypted and stored as a profile. -//! behavior is as defined by connection policy. -// -//***************************************************************************** -extern long wlan_smart_config_process(void); - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - - - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif // __cplusplus - -#endif // __WLAN_H__ diff --git a/stm/cmsis/core_cm4.h b/stm/cmsis/core_cm4.h deleted file mode 100644 index 2c8b0882c..000000000 --- a/stm/cmsis/core_cm4.h +++ /dev/null @@ -1,1772 +0,0 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M4 - @{ - */ - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x04) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ -#include /* Compiler specific SIMD Intrinsics */ - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000 - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0 - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M4 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register */ -#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register */ -#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register */ -#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ -/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ - NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/stm/cmsis/core_cm4_simd.h b/stm/cmsis/core_cm4_simd.h deleted file mode 100644 index af1831ee1..000000000 --- a/stm/cmsis/core_cm4_simd.h +++ /dev/null @@ -1,673 +0,0 @@ -/**************************************************************************//** - * @file core_cm4_simd.h - * @brief CMSIS Cortex-M4 SIMD Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM4_SIMD_H -#define __CORE_CM4_SIMD_H - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32) ) >> 32)) - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -#include - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -#include - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SMLALD(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -#define __SMLALDX(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SMLSLD(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -#define __SMLSLDX(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -/* not yet supported */ -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - -#endif - -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CORE_CM4_SIMD_H */ - -#ifdef __cplusplus -} -#endif diff --git a/stm/cmsis/core_cmFunc.h b/stm/cmsis/core_cmFunc.h deleted file mode 100644 index 139bc3c5e..000000000 --- a/stm/cmsis/core_cmFunc.h +++ /dev/null @@ -1,636 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -#endif /* __CORE_CMFUNC_H */ diff --git a/stm/cmsis/core_cmInstr.h b/stm/cmsis/core_cmInstr.h deleted file mode 100644 index 8946c2c49..000000000 --- a/stm/cmsis/core_cmInstr.h +++ /dev/null @@ -1,688 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V3.20 - * @date 05. March 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - -#endif /* (__CORTEX_M >= 0x03) */ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constrant "l" - * Otherwise, use general registers, specified by constrant "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else - uint32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32 - op2)); -} - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return(result); -} - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return(result); -} - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/stm/delay.s b/stm/delay.s deleted file mode 100644 index 741dfd894..000000000 --- a/stm/delay.s +++ /dev/null @@ -1,28 +0,0 @@ - .syntax unified - .cpu cortex-m4 - .thumb - .text - .align 2 - .global delay_ms - .thumb - .thumb_func - .type delay_ms, %function -@ void delay_ms(int ms) -delay_ms: - @ r0 is argument, trashes r2, r3 - adds r3, r0, #0 - b .L2 -.L5: - movw r2, #55999 - b .L3 -.L4: - subs r2, r2, #1 -.L3: - cmp r2, #0 - bgt .L4 - subs r3, r3, #1 -.L2: - cmp r3, #0 - bgt .L5 - bx lr - .size delay_ms, .-delay_ms diff --git a/stm/exti.c b/stm/exti.c deleted file mode 100644 index a5d9fc16a..000000000 --- a/stm/exti.c +++ /dev/null @@ -1,432 +0,0 @@ -#include -#include -#include - -#include -#include - -#include "misc.h" -#include "mpconfig.h" -#include "qstr.h" -#include "obj.h" -#include "runtime.h" -#include "nlr.h" - -#include "pin.h" -#include "exti.h" - -// Usage Model: -// -// There are a total of 22 interrupt lines. 16 of these can come from GPIO pins -// and the remaining 6 are from internal sources. -// -// For lines 0 thru 15, a given line can map to the corresponding line from an -// arbitrary port. So line 0 can map to Px0 where x is A, B, C, ... and -// line 1 can map to Px1 where x is A, B, C, ... -// -// def callback(line): -// print("line =", line) -// -// # Configure the pin as a GPIO input. -// pin = pyb.Pin.board.X1 -// pyb.gpio_in(pin, pyb.PULL_UP) -// exti = pyb.Exti(pin, pyb.Exti.MODE_IRQ, pyb.Exti.TRIGGER_RISING, callback, 37) -// -// Now every time a rising edge is seen on the X1 pin, the callback will be -// called. Caution: mechanical pushbuttons have "bounce" and pushing or -// releasing a switch will often generate multiple edges. -// See: http://www.eng.utah.edu/~cs5780/debouncing.pdf for a detailed -// explanation, along with various techniques for debouncing. -// -// Trying to register 2 callbacks onto the same pin will throw an exception. -// -// If pin is passed as an integer, then it is assumed to map to one of the -// internal interrupt sources, and must be in the range 16 thru 22. -// -// All other pin objects go through the pin mapper to come up with one of the -// gpio pins. -// -// Valid modes are pyb.Exti.MODE_IRQ and pyb.Exti.MODE_EVENT (Only MODE_IRQ -// has been tested. MODE_EVENT has something to do with sleep mode and the -// WFE instruction). -// -// Valid edge triggers are pyb.Exti.TRIGGER_RISING, TRIGGER_FALLING, and TRIGGER_BOTH. -// -// exti.line() will return the line number that pin was mapped to. -// exti.disable() can be use to disable the interrupt associated with a given -// exti object. This could be useful for debouncing. -// exti.enable() enables a disabled interrupt -// exti.swint() will allow the callback to be triggered from software. -// -// pyb.Exti.regs() will dump the values of the EXTI registers. -// -// There is also a C API, so that drivers which require EXTI interrupt lines -// can also use this code. See exti.h for the available functions and -// usrsw.h for an example of using this. - -#define EXTI_OFFSET (EXTI_BASE - PERIPH_BASE) - -// Macro used to set/clear the bit corresponding to the line in the IMR/EMR -// register in an atomic fashion by using bitband addressing. -#define EXTI_MODE_BB(mode, line) (*(vu32 *)(PERIPH_BB_BASE + ((EXTI_OFFSET + (mode)) * 32) + ((line) * 4))) - -// This macro will work with the EXTI_Trigger_Rising and EXTI_Trigger_Falling constants -// but not EXTI_Trigger_Rising_Falling. -#define EXTI_EDGE_BB(edge, line) (*(vu32 *)(PERIPH_BB_BASE + ((EXTI_OFFSET + (edge)) * 32) + ((line) * 4))) - -#define EXTI_SWIER_BB(line) (*(vu32 *)(PERIPH_BB_BASE + ((EXTI_OFFSET + offsetof(EXTI_TypeDef, SWIER)) * 32) + ((line) * 4))) -#define EXTI_PR_BB(line) (*(vu32 *)(PERIPH_BB_BASE + ((EXTI_OFFSET + offsetof(EXTI_TypeDef, PR)) * 32) + ((line) * 4))) - -typedef struct { - mp_obj_base_t base; - mp_small_int_t line; -} exti_obj_t; - -typedef struct { - mp_obj_t callback_obj; - void *param; - EXTIMode_TypeDef mode; -} exti_vector_t; - -static exti_vector_t exti_vector[EXTI_NUM_VECTORS]; - -static const uint8_t nvic_irq_channel[EXTI_NUM_VECTORS] = { - EXTI0_IRQn, EXTI1_IRQn, EXTI2_IRQn, EXTI3_IRQn, EXTI4_IRQn, - EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn, EXTI9_5_IRQn, - EXTI15_10_IRQn, EXTI15_10_IRQn, EXTI15_10_IRQn, EXTI15_10_IRQn, EXTI15_10_IRQn, - EXTI15_10_IRQn, PVD_IRQn, RTC_Alarm_IRQn, OTG_FS_WKUP_IRQn, ETH_WKUP_IRQn, - OTG_HS_WKUP_IRQn, TAMP_STAMP_IRQn, RTC_WKUP_IRQn -}; - -// NOTE: param is for C callers. Python can use closure to get an object bound -// with the function. -uint exti_register(mp_obj_t pin_obj, mp_obj_t mode_obj, mp_obj_t trigger_obj, mp_obj_t callback_obj, void *param) { - const pin_obj_t *pin = NULL; - uint v_line; - - if (MP_OBJ_IS_INT(pin_obj)) { - // If an integer is passed in, then use it to identify lines 16 thru 22 - // We expect lines 0 thru 15 to be passed in as a pin, so that we can - // get both the port number and line number. - v_line = mp_obj_get_int(pin_obj); - if (v_line < 16) { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "EXTI vector %d < 16, use a Pin object", v_line)); - } - if (v_line >= EXTI_NUM_VECTORS) { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "EXTI vector %d >= max of %d", v_line, EXTI_NUM_VECTORS)); - } - } else { - pin = pin_map_user_obj(pin_obj); - v_line = pin->pin; - } - int mode = mp_obj_get_int(mode_obj); - if (!IS_EXTI_MODE(mode)) { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "Invalid EXTI Mode: %d", mode)); - } - int trigger = mp_obj_get_int(trigger_obj); - if (!IS_EXTI_TRIGGER(trigger)) { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "Invalid EXTI Trigger: %d", trigger)); - } - - exti_vector_t *v = &exti_vector[v_line]; - if (v->callback_obj != mp_const_none && callback_obj != mp_const_none) { - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "EXTI vector %d is already in use", v_line)); - } - - // We need to update callback and param atomically, so we disable the line - // before we update anything. - - exti_disable(v_line); - - if (pin && callback_obj) { - // Enable SYSCFG clock - RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); - - // For EXTI lines 0 thru 15, we need to configure which port controls - // the line. - SYSCFG_EXTILineConfig(pin->port, v_line); - } - v->callback_obj = callback_obj; - v->param = param; - v->mode = mode; - - if (v->callback_obj != mp_const_none) { - // The EXTI_Init function isn't atomic. It uses |= and &=. - // We use bit band operations to make it atomic. - EXTI_EDGE_BB(EXTI_Trigger_Rising, v_line) = - trigger == EXTI_Trigger_Rising || trigger == EXTI_Trigger_Rising_Falling; - EXTI_EDGE_BB(EXTI_Trigger_Falling, v_line) = - trigger == EXTI_Trigger_Falling || trigger == EXTI_Trigger_Rising_Falling; - exti_enable(v_line); - - /* Enable and set NVIC Interrupt to the lowest priority */ - NVIC_InitTypeDef NVIC_InitStructure; - NVIC_InitStructure.NVIC_IRQChannel = nvic_irq_channel[v_line]; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); - } - return v_line; -} - -void exti_enable(uint line) { - if (line >= EXTI_NUM_VECTORS) { - return; - } - // Since manipulating IMR/EMR is a read-modify-write, and we want this to - // be atomic, we use the bit-band area to just affect the bit we're - // interested in. - EXTI_MODE_BB(exti_vector[line].mode, line) = 1; -} - -void exti_disable(uint line) { - if (line >= EXTI_NUM_VECTORS) { - return; - } - // Since manipulating IMR/EMR is a read-modify-write, and we want this to - // be atomic, we use the bit-band area to just affect the bit we're - // interested in. - EXTI_MODE_BB(EXTI_Mode_Interrupt, line) = 0; - EXTI_MODE_BB(EXTI_Mode_Event, line) = 0; -} - -void exti_swint(uint line) { - if (line >= EXTI_NUM_VECTORS) { - return; - } - EXTI_SWIER_BB(line) = 1; -} - -static mp_obj_t exti_obj_line(mp_obj_t self_in) { - exti_obj_t *self = self_in; - return MP_OBJ_NEW_SMALL_INT(self->line); -} - -static mp_obj_t exti_obj_enable(mp_obj_t self_in) { - exti_obj_t *self = self_in; - exti_enable(self->line); - return mp_const_none; -} - -static mp_obj_t exti_obj_disable(mp_obj_t self_in) { - exti_obj_t *self = self_in; - exti_disable(self->line); - return mp_const_none; -} - -static mp_obj_t exti_obj_swint(mp_obj_t self_in) { - exti_obj_t *self = self_in; - exti_swint(self->line); - return mp_const_none; -} - -static MP_DEFINE_CONST_FUN_OBJ_1(exti_obj_line_obj, exti_obj_line); -static MP_DEFINE_CONST_FUN_OBJ_1(exti_obj_enable_obj, exti_obj_enable); -static MP_DEFINE_CONST_FUN_OBJ_1(exti_obj_disable_obj, exti_obj_disable); -static MP_DEFINE_CONST_FUN_OBJ_1(exti_obj_swint_obj, exti_obj_swint); - -STATIC const mp_map_elem_t exti_locals_dict_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR_line), (mp_obj_t) &exti_obj_line_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_enable), (mp_obj_t) &exti_obj_enable_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_disable), (mp_obj_t) &exti_obj_disable_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_swint), (mp_obj_t) &exti_obj_swint_obj }, -}; - -STATIC MP_DEFINE_CONST_DICT(exti_locals_dict, exti_locals_dict_table); - -static mp_obj_t exti_regs(void) { - printf("EXTI_IMR %08lx\n", EXTI->IMR); - printf("EXTI_EMR %08lx\n", EXTI->EMR); - printf("EXTI_RTSR %08lx\n", EXTI->RTSR); - printf("EXTI_FTSR %08lx\n", EXTI->FTSR); - printf("EXTI_SWIER %08lx\n", EXTI->SWIER); - printf("EXTI_PR %08lx\n", EXTI->PR); - return mp_const_none; -} -static MP_DEFINE_CONST_FUN_OBJ_0(exti_regs_obj, exti_regs); - -typedef struct { - const char *name; - uint val; -} exti_const_t; - -static const exti_const_t exti_const[] = { - { "MODE_IRQ", EXTI_Mode_Interrupt }, - { "MODE_EVENT", EXTI_Mode_Event }, - { "TRIGGER_RISING", EXTI_Trigger_Rising }, - { "TRIGGER_FALLING", EXTI_Trigger_Falling }, - { "TRIGGER_BOTH", EXTI_Trigger_Rising_Falling }, -}; -#define EXTI_NUM_CONST (sizeof(exti_const) / sizeof(exti_const[0])) - -static void exti_load_attr(mp_obj_t self_in, qstr attr_qstr, mp_obj_t *dest) { - (void)self_in; - const char *attr = qstr_str(attr_qstr); - - if (strcmp(attr, "regs") == 0) { - dest[0] = (mp_obj_t)&exti_regs_obj; - return; - } - const exti_const_t *entry = &exti_const[0]; - for (; entry < &exti_const[EXTI_NUM_CONST]; entry++) { - if (strcmp(attr, entry->name) == 0) { - dest[0] = MP_OBJ_NEW_SMALL_INT(entry->val); - dest[1] = MP_OBJ_NULL; - return; - } - } -} - -// line_obj = pyb.Exti(pin, mode, trigger, callback) - -static mp_obj_t exti_call(mp_obj_t type_in, uint n_args, uint n_kw, const mp_obj_t *args) { - // type_in == exti_obj_type - - mp_arg_check_num(n_args, n_kw, 4, 4, 0); - - exti_obj_t *self = m_new_obj(exti_obj_t); - self->base.type = type_in; - mp_obj_t line_obj = args[0]; - mp_obj_t mode_obj = args[1]; - mp_obj_t trigger_obj = args[2]; - mp_obj_t callback_obj = args[3]; - self->line = exti_register(line_obj, mode_obj, trigger_obj, callback_obj, NULL); - - return self; -} - -static void exti_meta_obj_print(void (*print)(void *env, const char *fmt, ...), void *env, mp_obj_t self_in, mp_print_kind_t kind) { - (void) self_in; - print(env, ""); -} - -static void exti_obj_print(void (*print)(void *env, const char *fmt, ...), void *env, mp_obj_t self_in, mp_print_kind_t kind) { - exti_obj_t *self = self_in; - print(env, "", self->line); -} - -static const mp_obj_type_t exti_meta_obj_type = { - { &mp_type_type }, - .name = MP_QSTR_ExtiMeta, - .print = exti_meta_obj_print, - .call = exti_call, - .load_attr = exti_load_attr, -}; - -const mp_obj_type_t exti_obj_type = { - { &exti_meta_obj_type }, - .name = MP_QSTR_Exti, - .print = exti_obj_print, - .locals_dict = (mp_obj_t)&exti_locals_dict, -}; - -void exti_init(void) { - for (exti_vector_t *v = exti_vector; v < &exti_vector[EXTI_NUM_VECTORS]; v++) { - v->callback_obj = mp_const_none; - v->param = NULL; - v->mode = EXTI_Mode_Interrupt; - } -} - -static void Handle_EXTI_Irq(uint32_t line) { - if (EXTI_PR_BB(line)) { - EXTI_PR_BB(line) = 1; // Clears bit - if (line < EXTI_NUM_VECTORS) { - exti_vector_t *v = &exti_vector[line]; - if (v->callback_obj != mp_const_none) { - mp_call_function_1(v->callback_obj, MP_OBJ_NEW_SMALL_INT(line)); - } - } - } -} - -void EXTI0_IRQHandler(void) { - Handle_EXTI_Irq(0); -} - -void EXTI1_IRQHandler(void) { - Handle_EXTI_Irq(1); -} - -void EXTI2_IRQHandler(void) { - Handle_EXTI_Irq(2); -} - -void EXTI3_IRQHandler(void) { - Handle_EXTI_Irq(3); -} - -void EXTI4_IRQHandler(void) { - Handle_EXTI_Irq(4); -} - -void EXTI9_5_IRQHandler(void) { - Handle_EXTI_Irq(5); - Handle_EXTI_Irq(6); - Handle_EXTI_Irq(7); - Handle_EXTI_Irq(8); - Handle_EXTI_Irq(9); -} - -void EXTI15_10_IRQHandler(void) { - Handle_EXTI_Irq(10); - Handle_EXTI_Irq(11); - Handle_EXTI_Irq(12); - Handle_EXTI_Irq(13); - Handle_EXTI_Irq(14); - Handle_EXTI_Irq(15); - -#if 0 - // for CC3000 support, needs to be re-written to use new EXTI code - if (EXTI_GetITStatus(EXTI_Line14) != RESET) { - led_toggle(PYB_LED_G2); - /* these are needed for CC3000 support - extern void SpiIntGPIOHandler(void); - extern uint32_t exti14_enabled; - extern uint32_t exti14_missed; - //printf("-> EXTI14 en=%lu miss=%lu\n", exti14_enabled, exti14_missed); - if (exti14_enabled) { - exti14_missed = 0; - SpiIntGPIOHandler(); // CC3000 interrupt - } else { - exti14_missed = 1; - } - */ - EXTI_ClearITPendingBit(EXTI_Line14); - //printf("<- EXTI14 done\n"); - } -#endif -} - -void PVD_IRQHandler(void) { - Handle_EXTI_Irq(16); -} - -void RTC_Alarm_IRQHandler(void) { - Handle_EXTI_Irq(17); -} - -#if 0 // dealt with in stm32fxxx_it.c -void OTG_FS_WKUP_IRQHandler(void) { - Handle_EXTI_Irq(18); -} -#endif - -void ETH_WKUP_IRQHandler(void) { - Handle_EXTI_Irq(19); -} - -#if 0 // dealt with in stm32fxxx_it.c -void OTG_HS_WKUP_IRQHandler(void) { - Handle_EXTI_Irq(20); -} -#endif - -void TAMP_STAMP_IRQHandler(void) { - Handle_EXTI_Irq(21); -} - -void RTC_WKUP_IRQHandler(void) { - Handle_EXTI_Irq(22); -} diff --git a/stm/exti.h b/stm/exti.h deleted file mode 100644 index 619e44fd3..000000000 --- a/stm/exti.h +++ /dev/null @@ -1,29 +0,0 @@ -// Vectors 0-15 are for regular pins -// Vectors 16-22 are for internal sources. -// -// Use the following constants for the internal sources: - -#define EXTI_PVD_OUTPUT (16) -#define EXTI_RTC_ALARM (17) -#define EXTI_USB_OTG_FS_WAKEUP (18) -#define EXTI_ETH_WAKEUP (19) -#define EXTI_USB_OTG_HS_WAKEUP (20) -#define EXTI_RTC_TIMESTAMP (21) -#define EXTI_RTC_WAKEUP (22) - -#define EXTI_NUM_VECTORS 23 - -void exti_init(void); - -uint exti_register(mp_obj_t pin_obj, mp_obj_t mode_obj, mp_obj_t trigger_obj, mp_obj_t callback_obj, void *param); - -void exti_enable(uint line); -void exti_disable(uint line); -void exti_swint(uint line); - -typedef struct { - mp_obj_t callback; - void *param; -} exti_t; - -extern const mp_obj_type_t exti_obj_type; diff --git a/stm/fatfs/00readme.txt b/stm/fatfs/00readme.txt deleted file mode 100644 index bd0939ffa..000000000 --- a/stm/fatfs/00readme.txt +++ /dev/null @@ -1,147 +0,0 @@ -FatFs Module Source Files R0.10 (C)ChaN, 2013 - - -FILES - - ffconf.h Configuration file for FatFs module. - ff.h Common include file for FatFs and application module. - ff.c FatFs module. - diskio.h Common include file for FatFs and disk I/O module. - diskio.c An example of glue function to attach existing disk I/O module to FatFs. - integer.h Integer type definitions for FatFs. - option Optional external functions. - - Low level disk I/O module is not included in this archive because the FatFs - module is only a generic file system layer and not depend on any specific - storage device. You have to provide a low level disk I/O module that written - to control your storage device. - - - -AGREEMENTS - - FatFs module is an open source software to implement FAT file system to - small embedded systems. This is a free software and is opened for education, - research and commercial developments under license policy of following trems. - - Copyright (C) 2013, ChaN, all right reserved. - - * The FatFs module is a free software and there is NO WARRANTY. - * No restriction on use. You can use, modify and redistribute it for - personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY. - * Redistributions of source code must retain the above copyright notice. - - - -REVISION HISTORY - - Feb 26, 2006 R0.00 Prototype - - Apr 29, 2006 R0.01 First release. - - Jun 01, 2006 R0.02 Added FAT12. - Removed unbuffered mode. - Fixed a problem on small (<32M) patition. - - Jun 10, 2006 R0.02a Added a configuration option _FS_MINIMUM. - - Sep 22, 2006 R0.03 Added f_rename. - Changed option _FS_MINIMUM to _FS_MINIMIZE. - - Dec 11, 2006 R0.03a Improved cluster scan algolithm to write files fast. - Fixed f_mkdir creates incorrect directory on FAT32. - - Feb 04, 2007 R0.04 Supported multiple drive system. (FatFs) - Changed some APIs for multiple drive system. - Added f_mkfs. (FatFs) - Added _USE_FAT32 option. (Tiny-FatFs) - - Apr 01, 2007 R0.04a Supported multiple partitions on a plysical drive. (FatFs) - Fixed an endian sensitive code in f_mkfs. (FatFs) - Added a capability of extending the file size to f_lseek. - Added minimization level 3. - Fixed a problem that can collapse a sector when recreate an - existing file in any sub-directory at non FAT32 cfg. (Tiny-FatFs) - - May 05, 2007 R0.04b Added _USE_NTFLAG option. - Added FSInfo support. - Fixed some problems corresponds to FAT32. (Tiny-FatFs) - Fixed DBCS name can result FR_INVALID_NAME. - Fixed short seek (0 < ofs <= csize) collapses the file object. - - Aug 25, 2007 R0.05 Changed arguments of f_read, f_write. - Changed arguments of f_mkfs. (FatFs) - Fixed f_mkfs on FAT32 creates incorrect FSInfo. (FatFs) - Fixed f_mkdir on FAT32 creates incorrect directory. (FatFs) - - Feb 03, 2008 R0.05a Added f_truncate(). - Added f_utime(). - Fixed off by one error at FAT sub-type determination. - Fixed btr in f_read() can be mistruncated. - Fixed cached sector is not flushed when create and close without write. - - Apr 01, 2008 R0.06 Added f_forward(). (Tiny-FatFs) - Added string functions: fputc(), fputs(), fprintf() and fgets(). - Improved performance of f_lseek() on move to the same or following cluster. - - Apr 01, 2009, R0.07 Merged Tiny-FatFs as a buffer configuration option. - Added long file name support. - Added multiple code page support. - Added re-entrancy for multitask operation. - Added auto cluster size selection to f_mkfs(). - Added rewind option to f_readdir(). - Changed result code of critical errors. - Renamed string functions to avoid name collision. - - Apr 14, 2009, R0.07a Separated out OS dependent code on reentrant cfg. - Added multiple sector size support. - - Jun 21, 2009, R0.07c Fixed f_unlink() may return FR_OK on error. - Fixed wrong cache control in f_lseek(). - Added relative path feature. - Added f_chdir(). - Added f_chdrive(). - Added proper case conversion for extended characters. - - Nov 03, 2009 R0.07e Separated out configuration options from ff.h to ffconf.h. - Added a configuration option, _LFN_UNICODE. - Fixed f_unlink() fails to remove a sub-dir on _FS_RPATH. - Fixed name matching error on the 13 char boundary. - Changed f_readdir() to return the SFN with always upper case on non-LFN cfg. - - May 15, 2010, R0.08 Added a memory configuration option. (_USE_LFN) - Added file lock feature. (_FS_SHARE) - Added fast seek feature. (_USE_FASTSEEK) - Changed some types on the API, XCHAR->TCHAR. - Changed fname member in the FILINFO structure on Unicode cfg. - String functions support UTF-8 encoding files on Unicode cfg. - - Aug 16,'10 R0.08a Added f_getcwd(). (_FS_RPATH = 2) - Added sector erase feature. (_USE_ERASE) - Moved file lock semaphore table from fs object to the bss. - Fixed a wrong directory entry is created on non-LFN cfg when the given name contains ';'. - Fixed f_mkfs() creates wrong FAT32 volume. - - Jan 15,'11 R0.08b Fast seek feature is also applied to f_read() and f_write(). - f_lseek() reports required table size on creating CLMP. - Extended format syntax of f_printf function. - Ignores duplicated directory separators in given path names. - - Sep 06,'11 R0.09 f_mkfs() supports multiple partition to finish the multiple partition feature. - Added f_fdisk(). (_MULTI_PARTITION = 2) - - Aug 27,'12 R0.09a Fixed assertion failure due to OS/2 EA on FAT12/16. - Changed f_open() and f_opendir() reject null object pointer to avoid crash. - Changed option name _FS_SHARE to _FS_LOCK. - - Jan 23,'13 R0.09b Added f_getlabel() and f_setlabel(). (_USE_LABEL == 1) - - Oct 02,'13 R0.10 Added selection of character encoding on the file. (_STRF_ENCODE) - Added f_closedir(). - Added forced full FAT scan for f_getfree(). (_FS_NOFSINFO) - Added forced mount feature with changes of f_mount(). - Improved behavior of volume auto detection. - Improved write throughput of f_puts() and f_printf(). - Changed argument of f_chdrive(), f_mkfs(), disk_read() and disk_write(). - Fixed f_write() can be truncated when the file size is close to 4GB. - Fixed f_open(), f_mkdir() and f_setlabel() can return incorrect error code. diff --git a/stm/fatfs/ccsbcs.c b/stm/fatfs/ccsbcs.c deleted file mode 100644 index 17897eae7..000000000 --- a/stm/fatfs/ccsbcs.c +++ /dev/null @@ -1,539 +0,0 @@ -/*------------------------------------------------------------------------*/ -/* Unicode - Local code bidirectional converter (C)ChaN, 2012 */ -/* (SBCS code pages) */ -/*------------------------------------------------------------------------*/ -/* 437 U.S. (OEM) -/ 720 Arabic (OEM) -/ 1256 Arabic (Windows) -/ 737 Greek (OEM) -/ 1253 Greek (Windows) -/ 1250 Central Europe (Windows) -/ 775 Baltic (OEM) -/ 1257 Baltic (Windows) -/ 850 Multilingual Latin 1 (OEM) -/ 852 Latin 2 (OEM) -/ 1252 Latin 1 (Windows) -/ 855 Cyrillic (OEM) -/ 1251 Cyrillic (Windows) -/ 866 Russian (OEM) -/ 857 Turkish (OEM) -/ 1254 Turkish (Windows) -/ 858 Multilingual Latin 1 + Euro (OEM) -/ 862 Hebrew (OEM) -/ 1255 Hebrew (Windows) -/ 874 Thai (OEM, Windows) -/ 1258 Vietnam (OEM, Windows) -*/ - -#include "ff.h" - - -#if _CODE_PAGE == 437 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP437(0x80-0xFF) to Unicode conversion table */ - 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, - 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, - 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, - 0x00FF, 0x00D6, 0x00DC, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192, - 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, - 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, - 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, - 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, - 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, - 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, - 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, - 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, - 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 720 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP720(0x80-0xFF) to Unicode conversion table */ - 0x0000, 0x0000, 0x00E9, 0x00E2, 0x0000, 0x00E0, 0x0000, 0x00E7, - 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0651, 0x0652, 0x00F4, 0x00A4, 0x0640, 0x00FB, 0x00F9, - 0x0621, 0x0622, 0x0623, 0x0624, 0x00A3, 0x0625, 0x0626, 0x0627, - 0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F, - 0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, - 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, - 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, - 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, - 0x0636, 0x0637, 0x0638, 0x0639, 0x063A, 0x0641, 0x00B5, 0x0642, - 0x0643, 0x0644, 0x0645, 0x0646, 0x0647, 0x0648, 0x0649, 0x064A, - 0x2261, 0x064B, 0x064C, 0x064D, 0x064E, 0x064F, 0x0650, 0x2248, - 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 737 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP737(0x80-0xFF) to Unicode conversion table */ - 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x0398, - 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, 0x03A0, - 0x03A1, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9, - 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, 0x03B8, - 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0, - 0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x03C5, 0x03C6, 0x03C7, 0x03C8, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, - 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, - 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, - 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, - 0x03C9, 0x03AC, 0x03AD, 0x03AE, 0x03CA, 0x03AF, 0x03CC, 0x03CD, - 0x03CB, 0x03CE, 0x0386, 0x0388, 0x0389, 0x038A, 0x038C, 0x038E, - 0x038F, 0x00B1, 0x2265, 0x2264, 0x03AA, 0x03AB, 0x00F7, 0x2248, - 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 775 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP775(0x80-0xFF) to Unicode conversion table */ - 0x0106, 0x00FC, 0x00E9, 0x0101, 0x00E4, 0x0123, 0x00E5, 0x0107, - 0x0142, 0x0113, 0x0156, 0x0157, 0x012B, 0x0179, 0x00C4, 0x00C5, - 0x00C9, 0x00E6, 0x00C6, 0x014D, 0x00F6, 0x0122, 0x00A2, 0x015A, - 0x015B, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x00A4, - 0x0100, 0x012A, 0x00F3, 0x017B, 0x017C, 0x017A, 0x201D, 0x00A6, - 0x00A9, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x0141, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0104, 0x010C, 0x0118, - 0x0116, 0x2563, 0x2551, 0x2557, 0x255D, 0x012E, 0x0160, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0172, 0x016A, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x017D, - 0x0105, 0x010D, 0x0119, 0x0117, 0x012F, 0x0161, 0x0173, 0x016B, - 0x017E, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, - 0x00D3, 0x00DF, 0x014C, 0x0143, 0x00F5, 0x00D5, 0x00B5, 0x0144, - 0x0136, 0x0137, 0x013B, 0x013C, 0x0146, 0x0112, 0x0145, 0x2019, - 0x00AD, 0x00B1, 0x201C, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x201E, - 0x00B0, 0x2219, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 850 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP850(0x80-0xFF) to Unicode conversion table */ - 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, - 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, - 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, - 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192, - 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, - 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, - 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, - 0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x0131, 0x00CD, 0x00CE, - 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580, - 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE, - 0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4, - 0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, - 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 852 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP852(0x80-0xFF) to Unicode conversion table */ - 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x016F, 0x0107, 0x00E7, - 0x0142, 0x00EB, 0x0150, 0x0151, 0x00EE, 0x0179, 0x00C4, 0x0106, - 0x00C9, 0x0139, 0x013A, 0x00F4, 0x00F6, 0x013D, 0x013E, 0x015A, - 0x015B, 0x00D6, 0x00DC, 0x0164, 0x0165, 0x0141, 0x00D7, 0x010D, - 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x0104, 0x0105, 0x017D, 0x017E, - 0x0118, 0x0119, 0x00AC, 0x017A, 0x010C, 0x015F, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x011A, - 0x015E, 0x2563, 0x2551, 0x2557, 0x255D, 0x017B, 0x017C, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0102, 0x0103, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, - 0x0111, 0x0110, 0x010E, 0x00CB, 0x010F, 0x0147, 0x00CD, 0x00CE, - 0x011B, 0x2518, 0x250C, 0x2588, 0x2584, 0x0162, 0x016E, 0x2580, - 0x00D3, 0x00DF, 0x00D4, 0x0143, 0x0144, 0x0148, 0x0160, 0x0161, - 0x0154, 0x00DA, 0x0155, 0x0170, 0x00FD, 0x00DD, 0x0163, 0x00B4, - 0x00AD, 0x02DD, 0x02DB, 0x02C7, 0x02D8, 0x00A7, 0x00F7, 0x00B8, - 0x00B0, 0x00A8, 0x02D9, 0x0171, 0x0158, 0x0159, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 855 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP855(0x80-0xFF) to Unicode conversion table */ - 0x0452, 0x0402, 0x0453, 0x0403, 0x0451, 0x0401, 0x0454, 0x0404, - 0x0455, 0x0405, 0x0456, 0x0406, 0x0457, 0x0407, 0x0458, 0x0408, - 0x0459, 0x0409, 0x045A, 0x040A, 0x045B, 0x040B, 0x045C, 0x040C, - 0x045E, 0x040E, 0x045F, 0x040F, 0x044E, 0x042E, 0x044A, 0x042A, - 0x0430, 0x0410, 0x0431, 0x0411, 0x0446, 0x0426, 0x0434, 0x0414, - 0x0435, 0x0415, 0x0444, 0x0424, 0x0433, 0x0413, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0445, 0x0425, 0x0438, - 0x0418, 0x2563, 0x2551, 0x2557, 0x255D, 0x0439, 0x0419, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x043A, 0x041A, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, - 0x043B, 0x041B, 0x043C, 0x041C, 0x043D, 0x041D, 0x043E, 0x041E, - 0x043F, 0x2518, 0x250C, 0x2588, 0x2584, 0x041F, 0x044F, 0x2580, - 0x042F, 0x0440, 0x0420, 0x0441, 0x0421, 0x0442, 0x0422, 0x0443, - 0x0423, 0x0436, 0x0416, 0x0432, 0x0412, 0x044C, 0x042C, 0x2116, - 0x00AD, 0x044B, 0x042B, 0x0437, 0x0417, 0x0448, 0x0428, 0x044D, - 0x042D, 0x0449, 0x0429, 0x0447, 0x0427, 0x00A7, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 857 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP857(0x80-0xFF) to Unicode conversion table */ - 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, - 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0131, 0x00C4, 0x00C5, - 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, - 0x0130, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x015E, 0x015F, - 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x011E, 0x011F, - 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, - 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, - 0x00BA, 0x00AA, 0x00CA, 0x00CB, 0x00C8, 0x0000, 0x00CD, 0x00CE, - 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580, - 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x0000, - 0x00D7, 0x00DA, 0x00DB, 0x00D9, 0x00EC, 0x00FF, 0x00AF, 0x00B4, - 0x00AD, 0x00B1, 0x0000, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, - 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 858 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP858(0x80-0xFF) to Unicode conversion table */ - 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, - 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, - 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, - 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192, - 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, - 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, - 0x00A9, 0x2563, 0x2551, 0x2557, 0x2550, 0x00A2, 0x00A5, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, - 0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x20AC, 0x00CD, 0x00CE, - 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00C6, 0x00CC, 0x2580, - 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE, - 0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4, - 0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, - 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 862 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP862(0x80-0xFF) to Unicode conversion table */ - 0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7, - 0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF, - 0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7, - 0x05E8, 0x05E9, 0x05EA, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192, - 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, - 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, - 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, - 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, - 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, - 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, - 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, - 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, - 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 866 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP866(0x80-0xFF) to Unicode conversion table */ - 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, - 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F, - 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, - 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F, - 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, - 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, - 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, - 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, - 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, - 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, - 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F, - 0x0401, 0x0451, 0x0404, 0x0454, 0x0407, 0x0457, 0x040E, 0x045E, - 0x00B0, 0x2219, 0x00B7, 0x221A, 0x2116, 0x00A4, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 874 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP874(0x80-0xFF) to Unicode conversion table */ - 0x20AC, 0x0000, 0x0000, 0x0000, 0x0000, 0x2026, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x00A0, 0x0E01, 0x0E02, 0x0E03, 0x0E04, 0x0E05, 0x0E06, 0x0E07, - 0x0E08, 0x0E09, 0x0E0A, 0x0E0B, 0x0E0C, 0x0E0D, 0x0E0E, 0x0E0F, - 0x0E10, 0x0E11, 0x0E12, 0x0E13, 0x0E14, 0x0E15, 0x0E16, 0x0E17, - 0x0E18, 0x0E19, 0x0E1A, 0x0E1B, 0x0E1C, 0x0E1D, 0x0E1E, 0x0E1F, - 0x0E20, 0x0E21, 0x0E22, 0x0E23, 0x0E24, 0x0E25, 0x0E26, 0x0E27, - 0x0E28, 0x0E29, 0x0E2A, 0x0E2B, 0x0E2C, 0x0E2D, 0x0E2E, 0x0E2F, - 0x0E30, 0x0E31, 0x0E32, 0x0E33, 0x0E34, 0x0E35, 0x0E36, 0x0E37, - 0x0E38, 0x0E39, 0x0E3A, 0x0000, 0x0000, 0x0000, 0x0000, 0x0E3F, - 0x0E40, 0x0E41, 0x0E42, 0x0E43, 0x0E44, 0x0E45, 0x0E46, 0x0E47, - 0x0E48, 0x0E49, 0x0E4A, 0x0E4B, 0x0E4C, 0x0E4D, 0x0E4E, 0x0E4F, - 0x0E50, 0x0E51, 0x0E52, 0x0E53, 0x0E54, 0x0E55, 0x0E56, 0x0E57, - 0x0E58, 0x0E59, 0x0E5A, 0x0E5B, 0x0000, 0x0000, 0x0000, 0x0000 -}; - -#elif _CODE_PAGE == 1250 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP1250(0x80-0xFF) to Unicode conversion table */ - 0x20AC, 0x0000, 0x201A, 0x0000, 0x201E, 0x2026, 0x2020, 0x2021, - 0x0000, 0x2030, 0x0160, 0x2039, 0x015A, 0x0164, 0x017D, 0x0179, - 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x0000, 0x2122, 0x0161, 0x203A, 0x015B, 0x0165, 0x017E, 0x017A, - 0x00A0, 0x02C7, 0x02D8, 0x0141, 0x00A4, 0x0104, 0x00A6, 0x00A7, - 0x00A8, 0x00A9, 0x015E, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x017B, - 0x00B0, 0x00B1, 0x02DB, 0x0142, 0x00B4, 0x00B5, 0x00B6, 0x00B7, - 0x00B8, 0x0105, 0x015F, 0x00BB, 0x013D, 0x02DD, 0x013E, 0x017C, - 0x0154, 0x00C1, 0x00C2, 0x0102, 0x00C4, 0x0139, 0x0106, 0x00C7, - 0x010C, 0x00C9, 0x0118, 0x00CB, 0x011A, 0x00CD, 0x00CE, 0x010E, - 0x0110, 0x0143, 0x0147, 0x00D3, 0x00D4, 0x0150, 0x00D6, 0x00D7, - 0x0158, 0x016E, 0x00DA, 0x0170, 0x00DC, 0x00DD, 0x0162, 0x00DF, - 0x0155, 0x00E1, 0x00E2, 0x0103, 0x00E4, 0x013A, 0x0107, 0x00E7, - 0x010D, 0x00E9, 0x0119, 0x00EB, 0x011B, 0x00ED, 0x00EE, 0x010F, - 0x0111, 0x0144, 0x0148, 0x00F3, 0x00F4, 0x0151, 0x00F6, 0x00F7, - 0x0159, 0x016F, 0x00FA, 0x0171, 0x00FC, 0x00FD, 0x0163, 0x02D9 -}; - -#elif _CODE_PAGE == 1251 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP1251(0x80-0xFF) to Unicode conversion table */ - 0x0402, 0x0403, 0x201A, 0x0453, 0x201E, 0x2026, 0x2020, 0x2021, - 0x20AC, 0x2030, 0x0409, 0x2039, 0x040A, 0x040C, 0x040B, 0x040F, - 0x0452, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x0000, 0x2111, 0x0459, 0x203A, 0x045A, 0x045C, 0x045B, 0x045F, - 0x00A0, 0x040E, 0x045E, 0x0408, 0x00A4, 0x0490, 0x00A6, 0x00A7, - 0x0401, 0x00A9, 0x0404, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x0407, - 0x00B0, 0x00B1, 0x0406, 0x0456, 0x0491, 0x00B5, 0x00B6, 0x00B7, - 0x0451, 0x2116, 0x0454, 0x00BB, 0x0458, 0x0405, 0x0455, 0x0457, - 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, - 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F, - 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, - 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F, - 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, - 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F, - 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, - 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F -}; - -#elif _CODE_PAGE == 1252 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP1252(0x80-0xFF) to Unicode conversion table */ - 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, - 0x02C6, 0x2030, 0x0160, 0x2039, 0x0152, 0x0000, 0x017D, 0x0000, - 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x02DC, 0x2122, 0x0161, 0x203A, 0x0153, 0x0000, 0x017E, 0x0178, - 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, - 0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, - 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, - 0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, - 0x00C0, 0x00C1, 0x00C2, 0x00C3, 0x00C4, 0x00C5, 0x00C6, 0x00C7, - 0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x00CC, 0x00CD, 0x00CE, 0x00CF, - 0x00D0, 0x00D1, 0x00D2, 0x00D3, 0x00D4, 0x00D5, 0x00D6, 0x00D7, - 0x00D8, 0x00D9, 0x00DA, 0x00DB, 0x00DC, 0x00DD, 0x00DE, 0x00DF, - 0x00E0, 0x00E1, 0x00E2, 0x00E3, 0x00E4, 0x00E5, 0x00E6, 0x00E7, - 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x00EC, 0x00ED, 0x00EE, 0x00EF, - 0x00F0, 0x00F1, 0x00F2, 0x00F3, 0x00F4, 0x00F5, 0x00F6, 0x00F7, - 0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x00FD, 0x00FE, 0x00FF -}; - -#elif _CODE_PAGE == 1253 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP1253(0x80-0xFF) to Unicode conversion table */ - 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, - 0x0000, 0x2030, 0x0000, 0x2039, 0x000C, 0x0000, 0x0000, 0x0000, - 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x0000, 0x2122, 0x0000, 0x203A, 0x0000, 0x0000, 0x0000, 0x0000, - 0x00A0, 0x0385, 0x0386, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, - 0x00A8, 0x00A9, 0x0000, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x2015, - 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x0384, 0x00B5, 0x00B6, 0x00B7, - 0x0388, 0x0389, 0x038A, 0x00BB, 0x038C, 0x00BD, 0x038E, 0x038F, - 0x0390, 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, - 0x0398, 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, - 0x03A0, 0x03A1, 0x0000, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, - 0x03A8, 0x03A9, 0x03AA, 0x03AD, 0x03AC, 0x03AD, 0x03AE, 0x03AF, - 0x03B0, 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, - 0x03B8, 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, - 0x03C0, 0x03C1, 0x03C2, 0x03C3, 0x03C4, 0x03C5, 0x03C6, 0x03C7, - 0x03C8, 0x03C9, 0x03CA, 0x03CB, 0x03CC, 0x03CD, 0x03CE, 0x0000 -}; - -#elif _CODE_PAGE == 1254 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP1254(0x80-0xFF) to Unicode conversion table */ - 0x20AC, 0x0000, 0x210A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, - 0x02C6, 0x2030, 0x0160, 0x2039, 0x0152, 0x0000, 0x0000, 0x0000, - 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x02DC, 0x2122, 0x0161, 0x203A, 0x0153, 0x0000, 0x0000, 0x0178, - 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, - 0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, - 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, - 0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, - 0x00C0, 0x00C1, 0x00C2, 0x00C3, 0x00C4, 0x00C5, 0x00C6, 0x00C7, - 0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x00CC, 0x00CD, 0x00CE, 0x00CF, - 0x011E, 0x00D1, 0x00D2, 0x00D3, 0x00D4, 0x00D5, 0x00D6, 0x00D7, - 0x00D8, 0x00D9, 0x00DA, 0x00BD, 0x00DC, 0x0130, 0x015E, 0x00DF, - 0x00E0, 0x00E1, 0x00E2, 0x00E3, 0x00E4, 0x00E5, 0x00E6, 0x00E7, - 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x00EC, 0x00ED, 0x00EE, 0x00EF, - 0x011F, 0x00F1, 0x00F2, 0x00F3, 0x00F4, 0x00F5, 0x00F6, 0x00F7, - 0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x0131, 0x015F, 0x00FF -}; - -#elif _CODE_PAGE == 1255 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP1255(0x80-0xFF) to Unicode conversion table */ - 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, - 0x02C6, 0x2030, 0x0000, 0x2039, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x02DC, 0x2122, 0x0000, 0x203A, 0x0000, 0x0000, 0x0000, 0x0000, - 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, - 0x00A8, 0x00A9, 0x00D7, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, - 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, - 0x00B8, 0x00B9, 0x00F7, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, - 0x05B0, 0x05B1, 0x05B2, 0x05B3, 0x05B4, 0x05B5, 0x05B6, 0x05B7, - 0x05B8, 0x05B9, 0x0000, 0x05BB, 0x05BC, 0x05BD, 0x05BE, 0x05BF, - 0x05C0, 0x05C1, 0x05C2, 0x05C3, 0x05F0, 0x05F1, 0x05F2, 0x05F3, - 0x05F4, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7, - 0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF, - 0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7, - 0x05E8, 0x05E9, 0x05EA, 0x0000, 0x0000, 0x200E, 0x200F, 0x0000 -}; - -#elif _CODE_PAGE == 1256 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP1256(0x80-0xFF) to Unicode conversion table */ - 0x20AC, 0x067E, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, - 0x02C6, 0x2030, 0x0679, 0x2039, 0x0152, 0x0686, 0x0698, 0x0688, - 0x06AF, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x06A9, 0x2122, 0x0691, 0x203A, 0x0153, 0x200C, 0x200D, 0x06BA, - 0x00A0, 0x060C, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, - 0x00A8, 0x00A9, 0x06BE, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, - 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, - 0x00B8, 0x00B9, 0x061B, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x061F, - 0x06C1, 0x0621, 0x0622, 0x0623, 0x0624, 0x0625, 0x0626, 0x0627, - 0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F, - 0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x0636, 0x00D7, - 0x0637, 0x0638, 0x0639, 0x063A, 0x0640, 0x0640, 0x0642, 0x0643, - 0x00E0, 0x0644, 0x00E2, 0x0645, 0x0646, 0x0647, 0x0648, 0x00E7, - 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x0649, 0x064A, 0x00EE, 0x00EF, - 0x064B, 0x064C, 0x064D, 0x064E, 0x00F4, 0x064F, 0x0650, 0x00F7, - 0x0651, 0x00F9, 0x0652, 0x00FB, 0x00FC, 0x200E, 0x200F, 0x06D2 -} - -#elif _CODE_PAGE == 1257 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP1257(0x80-0xFF) to Unicode conversion table */ - 0x20AC, 0x0000, 0x201A, 0x0000, 0x201E, 0x2026, 0x2020, 0x2021, - 0x0000, 0x2030, 0x0000, 0x2039, 0x0000, 0x00A8, 0x02C7, 0x00B8, - 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x0000, 0x2122, 0x0000, 0x203A, 0x0000, 0x00AF, 0x02DB, 0x0000, - 0x00A0, 0x0000, 0x00A2, 0x00A3, 0x00A4, 0x0000, 0x00A6, 0x00A7, - 0x00D8, 0x00A9, 0x0156, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, - 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, - 0x00B8, 0x00B9, 0x0157, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00E6, - 0x0104, 0x012E, 0x0100, 0x0106, 0x00C4, 0x00C5, 0x0118, 0x0112, - 0x010C, 0x00C9, 0x0179, 0x0116, 0x0122, 0x0136, 0x012A, 0x013B, - 0x0160, 0x0143, 0x0145, 0x00D3, 0x014C, 0x00D5, 0x00D6, 0x00D7, - 0x0172, 0x0141, 0x015A, 0x016A, 0x00DC, 0x017B, 0x017D, 0x00DF, - 0x0105, 0x012F, 0x0101, 0x0107, 0x00E4, 0x00E5, 0x0119, 0x0113, - 0x010D, 0x00E9, 0x017A, 0x0117, 0x0123, 0x0137, 0x012B, 0x013C, - 0x0161, 0x0144, 0x0146, 0x00F3, 0x014D, 0x00F5, 0x00F6, 0x00F7, - 0x0173, 0x014E, 0x015B, 0x016B, 0x00FC, 0x017C, 0x017E, 0x02D9 -}; - -#elif _CODE_PAGE == 1258 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP1258(0x80-0xFF) to Unicode conversion table */ - 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, - 0x02C6, 0x2030, 0x0000, 0x2039, 0x0152, 0x0000, 0x0000, 0x0000, - 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x02DC, 0x2122, 0x0000, 0x203A, 0x0153, 0x0000, 0x0000, 0x0178, - 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, - 0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, - 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, - 0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, - 0x00C0, 0x00C1, 0x00C2, 0x0102, 0x00C4, 0x00C5, 0x00C6, 0x00C7, - 0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x0300, 0x00CD, 0x00CE, 0x00CF, - 0x0110, 0x00D1, 0x0309, 0x00D3, 0x00D4, 0x01A0, 0x00D6, 0x00D7, - 0x00D8, 0x00D9, 0x00DA, 0x00DB, 0x00DC, 0x01AF, 0x0303, 0x00DF, - 0x00E0, 0x00E1, 0x00E2, 0x0103, 0x00E4, 0x00E5, 0x00E6, 0x00E7, - 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x0301, 0x00ED, 0x00EE, 0x00EF, - 0x0111, 0x00F1, 0x0323, 0x00F3, 0x00F4, 0x01A1, 0x00F6, 0x00F7, - 0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x01B0, 0x20AB, 0x00FF -}; - -#endif - - -#if _TBLDEF || _USE_LFN - - -WCHAR ff_convert ( /* Converted character, Returns zero on error */ - WCHAR chr, /* Character code to be converted */ - UINT dir /* 0: Unicode to OEMCP, 1: OEMCP to Unicode */ -) -{ - WCHAR c; - - - if (chr < 0x80) { /* ASCII */ - c = chr; - - } else { - if (dir) { /* OEMCP to Unicode */ - c = (chr >= 0x100) ? 0 : Tbl[chr - 0x80]; - - } else { /* Unicode to OEMCP */ - for (c = 0; c < 0x80; c++) { - if (chr == Tbl[c]) break; - } - c = (c + 0x80) & 0xFF; - } - } - - return c; -} - - -WCHAR ff_wtoupper ( /* Upper converted character */ - WCHAR chr /* Input character */ -) -{ - static const WCHAR tbl_lower[] = { 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0xA1, 0x00A2, 0x00A3, 0x00A5, 0x00AC, 0x00AF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0x0FF, 0x101, 0x103, 0x105, 0x107, 0x109, 0x10B, 0x10D, 0x10F, 0x111, 0x113, 0x115, 0x117, 0x119, 0x11B, 0x11D, 0x11F, 0x121, 0x123, 0x125, 0x127, 0x129, 0x12B, 0x12D, 0x12F, 0x131, 0x133, 0x135, 0x137, 0x13A, 0x13C, 0x13E, 0x140, 0x142, 0x144, 0x146, 0x148, 0x14B, 0x14D, 0x14F, 0x151, 0x153, 0x155, 0x157, 0x159, 0x15B, 0x15D, 0x15F, 0x161, 0x163, 0x165, 0x167, 0x169, 0x16B, 0x16D, 0x16F, 0x171, 0x173, 0x175, 0x177, 0x17A, 0x17C, 0x17E, 0x192, 0x3B1, 0x3B2, 0x3B3, 0x3B4, 0x3B5, 0x3B6, 0x3B7, 0x3B8, 0x3B9, 0x3BA, 0x3BB, 0x3BC, 0x3BD, 0x3BE, 0x3BF, 0x3C0, 0x3C1, 0x3C3, 0x3C4, 0x3C5, 0x3C6, 0x3C7, 0x3C8, 0x3C9, 0x3CA, 0x430, 0x431, 0x432, 0x433, 0x434, 0x435, 0x436, 0x437, 0x438, 0x439, 0x43A, 0x43B, 0x43C, 0x43D, 0x43E, 0x43F, 0x440, 0x441, 0x442, 0x443, 0x444, 0x445, 0x446, 0x447, 0x448, 0x449, 0x44A, 0x44B, 0x44C, 0x44D, 0x44E, 0x44F, 0x451, 0x452, 0x453, 0x454, 0x455, 0x456, 0x457, 0x458, 0x459, 0x45A, 0x45B, 0x45C, 0x45E, 0x45F, 0x2170, 0x2171, 0x2172, 0x2173, 0x2174, 0x2175, 0x2176, 0x2177, 0x2178, 0x2179, 0x217A, 0x217B, 0x217C, 0x217D, 0x217E, 0x217F, 0xFF41, 0xFF42, 0xFF43, 0xFF44, 0xFF45, 0xFF46, 0xFF47, 0xFF48, 0xFF49, 0xFF4A, 0xFF4B, 0xFF4C, 0xFF4D, 0xFF4E, 0xFF4F, 0xFF50, 0xFF51, 0xFF52, 0xFF53, 0xFF54, 0xFF55, 0xFF56, 0xFF57, 0xFF58, 0xFF59, 0xFF5A, 0 }; - static const WCHAR tbl_upper[] = { 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x21, 0xFFE0, 0xFFE1, 0xFFE5, 0xFFE2, 0xFFE3, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0x178, 0x100, 0x102, 0x104, 0x106, 0x108, 0x10A, 0x10C, 0x10E, 0x110, 0x112, 0x114, 0x116, 0x118, 0x11A, 0x11C, 0x11E, 0x120, 0x122, 0x124, 0x126, 0x128, 0x12A, 0x12C, 0x12E, 0x130, 0x132, 0x134, 0x136, 0x139, 0x13B, 0x13D, 0x13F, 0x141, 0x143, 0x145, 0x147, 0x14A, 0x14C, 0x14E, 0x150, 0x152, 0x154, 0x156, 0x158, 0x15A, 0x15C, 0x15E, 0x160, 0x162, 0x164, 0x166, 0x168, 0x16A, 0x16C, 0x16E, 0x170, 0x172, 0x174, 0x176, 0x179, 0x17B, 0x17D, 0x191, 0x391, 0x392, 0x393, 0x394, 0x395, 0x396, 0x397, 0x398, 0x399, 0x39A, 0x39B, 0x39C, 0x39D, 0x39E, 0x39F, 0x3A0, 0x3A1, 0x3A3, 0x3A4, 0x3A5, 0x3A6, 0x3A7, 0x3A8, 0x3A9, 0x3AA, 0x410, 0x411, 0x412, 0x413, 0x414, 0x415, 0x416, 0x417, 0x418, 0x419, 0x41A, 0x41B, 0x41C, 0x41D, 0x41E, 0x41F, 0x420, 0x421, 0x422, 0x423, 0x424, 0x425, 0x426, 0x427, 0x428, 0x429, 0x42A, 0x42B, 0x42C, 0x42D, 0x42E, 0x42F, 0x401, 0x402, 0x403, 0x404, 0x405, 0x406, 0x407, 0x408, 0x409, 0x40A, 0x40B, 0x40C, 0x40E, 0x40F, 0x2160, 0x2161, 0x2162, 0x2163, 0x2164, 0x2165, 0x2166, 0x2167, 0x2168, 0x2169, 0x216A, 0x216B, 0x216C, 0x216D, 0x216E, 0x216F, 0xFF21, 0xFF22, 0xFF23, 0xFF24, 0xFF25, 0xFF26, 0xFF27, 0xFF28, 0xFF29, 0xFF2A, 0xFF2B, 0xFF2C, 0xFF2D, 0xFF2E, 0xFF2F, 0xFF30, 0xFF31, 0xFF32, 0xFF33, 0xFF34, 0xFF35, 0xFF36, 0xFF37, 0xFF38, 0xFF39, 0xFF3A, 0 }; - int i; - - - for (i = 0; tbl_lower[i] && chr != tbl_lower[i]; i++) ; - - return tbl_lower[i] ? tbl_upper[i] : chr; -} -#endif diff --git a/stm/fatfs/diskio.c b/stm/fatfs/diskio.c deleted file mode 100644 index fb39c9594..000000000 --- a/stm/fatfs/diskio.c +++ /dev/null @@ -1,197 +0,0 @@ -/*-----------------------------------------------------------------------*/ -/* Low level disk I/O module skeleton for FatFs (C)ChaN, 2013 */ -/*-----------------------------------------------------------------------*/ -/* If a working storage control module is available, it should be */ -/* attached to the FatFs via a glue function rather than modifying it. */ -/* This is an example of glue functions to attach various exsisting */ -/* storage control module to the FatFs module with a defined API. */ -/*-----------------------------------------------------------------------*/ - -#include -#include -#include "ff.h" /* FatFs lower layer API */ -#include "diskio.h" /* FatFs lower layer API */ -#include "misc.h" -#include "storage.h" -#include "sdcard.h" - -PARTITION VolToPart[] = { - {0, 1}, // Logical drive 0 ==> Physical drive 0, 1st partition - {1, 0}, // Logical drive 1 ==> Physical drive 1 (auto detection) - /* - {0, 2}, // Logical drive 2 ==> Physical drive 0, 2nd partition - {0, 3}, // Logical drive 3 ==> Physical drive 0, 3rd partition - */ -}; - -/* Definitions of physical drive number for each media */ -#define PD_FLASH (0) -#define PD_SDCARD (1) - -/*-----------------------------------------------------------------------*/ -/* Initialize a Drive */ -/*-----------------------------------------------------------------------*/ - -DSTATUS disk_initialize ( - BYTE pdrv /* Physical drive nmuber (0..) */ -) -{ - switch (pdrv) { - case PD_FLASH: - storage_init(); - return 0; - - case PD_SDCARD: - if (!sdcard_power_on()) { - return STA_NODISK; - } - // TODO return STA_PROTECT if SD card is read only - return 0; - } - - return STA_NOINIT; -} - -/*-----------------------------------------------------------------------*/ -/* Get Disk Status */ -/*-----------------------------------------------------------------------*/ - -DSTATUS disk_status ( - BYTE pdrv /* Physical drive nmuber (0..) */ -) -{ - switch (pdrv) { - case PD_FLASH : - // flash is ready - return 0; - - case PD_SDCARD: - // TODO return STA_PROTECT if SD card is read only - return 0; - } - - return STA_NOINIT; -} - -/*-----------------------------------------------------------------------*/ -/* Read Sector(s) */ -/*-----------------------------------------------------------------------*/ - -DRESULT disk_read ( - BYTE pdrv, /* Physical drive nmuber (0..) */ - BYTE *buff, /* Data buffer to store read data */ - DWORD sector, /* Sector address (LBA) */ - UINT count /* Number of sectors to read (1..128) */ -) -{ - switch (pdrv) { - case PD_FLASH: - for (int i = 0; i < count; i++) { - if (!storage_read_block(buff + i * FLASH_BLOCK_SIZE, sector + i)) { - return RES_ERROR; - } - } - return RES_OK; - - case PD_SDCARD: - // TODO have a multi-block read function - for (int i = 0; i < count; i++) { - if (!sdcard_read_block(buff + i * SDCARD_BLOCK_SIZE, sector + i)) { - return RES_ERROR; - } - } - return RES_OK; - } - - return RES_PARERR; -} - -/*-----------------------------------------------------------------------*/ -/* Write Sector(s) */ -/*-----------------------------------------------------------------------*/ - -#if _USE_WRITE -DRESULT disk_write ( - BYTE pdrv, /* Physical drive nmuber (0..) */ - const BYTE *buff, /* Data to be written */ - DWORD sector, /* Sector address (LBA) */ - UINT count /* Number of sectors to write (1..128) */ -) -{ - switch (pdrv) { - case PD_FLASH: - for (int i = 0; i < count; i++) { - if (!storage_write_block(buff + i * FLASH_BLOCK_SIZE, sector + i)) { - return RES_ERROR; - } - } - return RES_OK; - - case PD_SDCARD: - // TODO have a multi-block write function - for (int i = 0; i < count; i++) { - if (!sdcard_write_block(buff + i * SDCARD_BLOCK_SIZE, sector + i)) { - return RES_ERROR; - } - } - return RES_OK; - } - - return RES_PARERR; -} -#endif - - -/*-----------------------------------------------------------------------*/ -/* Miscellaneous Functions */ -/*-----------------------------------------------------------------------*/ - -#if _USE_IOCTL -DRESULT disk_ioctl ( - BYTE pdrv, /* Physical drive nmuber (0..) */ - BYTE cmd, /* Control code */ - void *buff /* Buffer to send/receive control data */ -) -{ - switch (pdrv) { - case PD_FLASH: - switch (cmd) { - case CTRL_SYNC: - storage_flush(); - return RES_OK; - - case GET_BLOCK_SIZE: - *((DWORD*)buff) = 1; // high-level sector erase size in units of the small (512) block size - return RES_OK; - } - break; - - case PD_SDCARD: - switch (cmd) { - case CTRL_SYNC: - return RES_OK; - - case GET_BLOCK_SIZE: - *((DWORD*)buff) = 1; // high-level sector erase size in units of the small (512) block size - return RES_OK; - } - break; - } - - return RES_PARERR; -} -#endif - -DWORD get_fattime ( - void -) -{ - // TODO replace with call to RTC - int year = 2013; - int month = 10; - int day = 12; - int hour = 21; - int minute = 42; - int second = 13; - return ((year - 1980) << 25) | ((month) << 21) | ((day) << 16) | ((hour) << 11) | ((minute) << 5) | (second / 2); -} diff --git a/stm/fatfs/diskio.h b/stm/fatfs/diskio.h deleted file mode 100644 index 966bc89b1..000000000 --- a/stm/fatfs/diskio.h +++ /dev/null @@ -1,89 +0,0 @@ -/*----------------------------------------------------------------------- -/ Low level disk interface modlue include file (C)ChaN, 2013 -/-----------------------------------------------------------------------*/ - -#ifndef _DISKIO_DEFINED -#define _DISKIO_DEFINED - -#ifdef __cplusplus -extern "C" { -#endif - -#define _USE_WRITE 1 /* 1: Enable disk_write function */ -#define _USE_IOCTL 1 /* 1: Enable disk_ioctl fucntion */ - -#include "integer.h" - - -/* Status of Disk Functions */ -typedef BYTE DSTATUS; - -/* Results of Disk Functions */ -typedef enum { - RES_OK = 0, /* 0: Successful */ - RES_ERROR, /* 1: R/W Error */ - RES_WRPRT, /* 2: Write Protected */ - RES_NOTRDY, /* 3: Not Ready */ - RES_PARERR /* 4: Invalid Parameter */ -} DRESULT; - - -/*---------------------------------------*/ -/* Prototypes for disk control functions */ - - -DSTATUS disk_initialize (BYTE pdrv); -DSTATUS disk_status (BYTE pdrv); -DRESULT disk_read (BYTE pdrv, BYTE*buff, DWORD sector, UINT count); -DRESULT disk_write (BYTE pdrv, const BYTE* buff, DWORD sector, UINT count); -DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff); - -DWORD get_fattime (void); - -/* Disk Status Bits (DSTATUS) */ -#define STA_NOINIT 0x01 /* Drive not initialized */ -#define STA_NODISK 0x02 /* No medium in the drive */ -#define STA_PROTECT 0x04 /* Write protected */ - - -/* Command code for disk_ioctrl fucntion */ - -/* Generic command (used by FatFs) */ -#define CTRL_SYNC 0 /* Flush disk cache (for write functions) */ -#define GET_SECTOR_COUNT 1 /* Get media size (for only f_mkfs()) */ -#define GET_SECTOR_SIZE 2 /* Get sector size (for multiple sector size (_MAX_SS >= 1024)) */ -#define GET_BLOCK_SIZE 3 /* Get erase block size (for only f_mkfs()) */ -#define CTRL_ERASE_SECTOR 4 /* Force erased a block of sectors (for only _USE_ERASE) */ - -/* Generic command (not used by FatFs) */ -#define CTRL_POWER 5 /* Get/Set power status */ -#define CTRL_LOCK 6 /* Lock/Unlock media removal */ -#define CTRL_EJECT 7 /* Eject media */ -#define CTRL_FORMAT 8 /* Create physical format on the media */ - -/* MMC/SDC specific ioctl command */ -#define MMC_GET_TYPE 10 /* Get card type */ -#define MMC_GET_CSD 11 /* Get CSD */ -#define MMC_GET_CID 12 /* Get CID */ -#define MMC_GET_OCR 13 /* Get OCR */ -#define MMC_GET_SDSTAT 14 /* Get SD status */ - -/* ATA/CF specific ioctl command */ -#define ATA_GET_REV 20 /* Get F/W revision */ -#define ATA_GET_MODEL 21 /* Get model name */ -#define ATA_GET_SN 22 /* Get serial number */ - - -/* MMC card type flags (MMC_GET_TYPE) */ -#define CT_MMC 0x01 /* MMC ver 3 */ -#define CT_SD1 0x02 /* SD ver 1 */ -#define CT_SD2 0x04 /* SD ver 2 */ -#define CT_SDC (CT_SD1|CT_SD2) /* SD */ -#define CT_BLOCK 0x08 /* Block addressing */ - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/stm/fatfs/ff.c b/stm/fatfs/ff.c deleted file mode 100644 index 5c03644e7..000000000 --- a/stm/fatfs/ff.c +++ /dev/null @@ -1,4524 +0,0 @@ -/*----------------------------------------------------------------------------/ -/ FatFs - FAT file system module R0.10 (C)ChaN, 2013 -/-----------------------------------------------------------------------------/ -/ FatFs module is a generic FAT file system module for small embedded systems. -/ This is a free software that opened for education, research and commercial -/ developments under license policy of following terms. -/ -/ Copyright (C) 2013, ChaN, all right reserved. -/ -/ * The FatFs module is a free software and there is NO WARRANTY. -/ * No restriction on use. You can use, modify and redistribute it for -/ personal, non-profit or commercial products UNDER YOUR RESPONSIBILITY. -/ * Redistributions of source code must retain the above copyright notice. -/ -/-----------------------------------------------------------------------------/ -/ Feb 26,'06 R0.00 Prototype. -/ -/ Apr 29,'06 R0.01 First stable version. -/ -/ Jun 01,'06 R0.02 Added FAT12 support. -/ Removed unbuffered mode. -/ Fixed a problem on small (<32M) partition. -/ Jun 10,'06 R0.02a Added a configuration option (_FS_MINIMUM). -/ -/ Sep 22,'06 R0.03 Added f_rename(). -/ Changed option _FS_MINIMUM to _FS_MINIMIZE. -/ Dec 11,'06 R0.03a Improved cluster scan algorithm to write files fast. -/ Fixed f_mkdir() creates incorrect directory on FAT32. -/ -/ Feb 04,'07 R0.04 Supported multiple drive system. -/ Changed some interfaces for multiple drive system. -/ Changed f_mountdrv() to f_mount(). -/ Added f_mkfs(). -/ Apr 01,'07 R0.04a Supported multiple partitions on a physical drive. -/ Added a capability of extending file size to f_lseek(). -/ Added minimization level 3. -/ Fixed an endian sensitive code in f_mkfs(). -/ May 05,'07 R0.04b Added a configuration option _USE_NTFLAG. -/ Added FSINFO support. -/ Fixed DBCS name can result FR_INVALID_NAME. -/ Fixed short seek (<= csize) collapses the file object. -/ -/ Aug 25,'07 R0.05 Changed arguments of f_read(), f_write() and f_mkfs(). -/ Fixed f_mkfs() on FAT32 creates incorrect FSINFO. -/ Fixed f_mkdir() on FAT32 creates incorrect directory. -/ Feb 03,'08 R0.05a Added f_truncate() and f_utime(). -/ Fixed off by one error at FAT sub-type determination. -/ Fixed btr in f_read() can be mistruncated. -/ Fixed cached sector is not flushed when create and close without write. -/ -/ Apr 01,'08 R0.06 Added fputc(), fputs(), fprintf() and fgets(). -/ Improved performance of f_lseek() on moving to the same or following cluster. -/ -/ Apr 01,'09 R0.07 Merged Tiny-FatFs as a configuration option. (_FS_TINY) -/ Added long file name feature. -/ Added multiple code page feature. -/ Added re-entrancy for multitask operation. -/ Added auto cluster size selection to f_mkfs(). -/ Added rewind option to f_readdir(). -/ Changed result code of critical errors. -/ Renamed string functions to avoid name collision. -/ Apr 14,'09 R0.07a Separated out OS dependent code on reentrant cfg. -/ Added multiple sector size feature. -/ Jun 21,'09 R0.07c Fixed f_unlink() can return FR_OK on error. -/ Fixed wrong cache control in f_lseek(). -/ Added relative path feature. -/ Added f_chdir() and f_chdrive(). -/ Added proper case conversion to extended character. -/ Nov 03,'09 R0.07e Separated out configuration options from ff.h to ffconf.h. -/ Fixed f_unlink() fails to remove a sub-directory on _FS_RPATH. -/ Fixed name matching error on the 13 character boundary. -/ Added a configuration option, _LFN_UNICODE. -/ Changed f_readdir() to return the SFN with always upper case on non-LFN cfg. -/ -/ May 15,'10 R0.08 Added a memory configuration option. (_USE_LFN = 3) -/ Added file lock feature. (_FS_SHARE) -/ Added fast seek feature. (_USE_FASTSEEK) -/ Changed some types on the API, XCHAR->TCHAR. -/ Changed .fname in the FILINFO structure on Unicode cfg. -/ String functions support UTF-8 encoding files on Unicode cfg. -/ Aug 16,'10 R0.08a Added f_getcwd(). -/ Added sector erase feature. (_USE_ERASE) -/ Moved file lock semaphore table from fs object to the bss. -/ Fixed a wrong directory entry is created on non-LFN cfg when the given name contains ';'. -/ Fixed f_mkfs() creates wrong FAT32 volume. -/ Jan 15,'11 R0.08b Fast seek feature is also applied to f_read() and f_write(). -/ f_lseek() reports required table size on creating CLMP. -/ Extended format syntax of f_printf(). -/ Ignores duplicated directory separators in given path name. -/ -/ Sep 06,'11 R0.09 f_mkfs() supports multiple partition to complete the multiple partition feature. -/ Added f_fdisk(). -/ Aug 27,'12 R0.09a Changed f_open() and f_opendir() reject null object pointer to avoid crash. -/ Changed option name _FS_SHARE to _FS_LOCK. -/ Fixed assertion failure due to OS/2 EA on FAT12/16 volume. -/ Jan 24,'13 R0.09b Added f_setlabel() and f_getlabel(). -/ -/ Oct 02,'13 R0.10 Added selection of character encoding on the file. (_STRF_ENCODE) -/ Added f_closedir(). -/ Added forced full FAT scan for f_getfree(). (_FS_NOFSINFO) -/ Added forced mount feature with changes of f_mount(). -/ Improved behavior of volume auto detection. -/ Improved write throughput of f_puts() and f_printf(). -/ Changed argument of f_chdrive(), f_mkfs(), disk_read() and disk_write(). -/ Fixed f_write() can be truncated when the file size is close to 4GB. -/ Fixed f_open(), f_mkdir() and f_setlabel() can return incorrect error code. -/---------------------------------------------------------------------------*/ - -#include "ff.h" /* Declarations of FatFs API */ -#include "diskio.h" /* Declarations of disk I/O functions */ - - -/*-------------------------------------------------------------------------- - - Module Private Definitions - ----------------------------------------------------------------------------*/ - -#if _FATFS != 80960 /* Revision ID */ -#error Wrong include file (ff.h). -#endif - - -/* Definitions on sector size */ -#if _MAX_SS != 512 && _MAX_SS != 1024 && _MAX_SS != 2048 && _MAX_SS != 4096 -#error Wrong sector size. -#endif -#if _MAX_SS != 512 -#define SS(fs) ((fs)->ssize) /* Variable sector size */ -#else -#define SS(fs) 512U /* Fixed sector size */ -#endif - - -/* Reentrancy related */ -#if _FS_REENTRANT -#if _USE_LFN == 1 -#error Static LFN work area cannot be used at thread-safe configuration. -#endif -#define ENTER_FF(fs) { if (!lock_fs(fs)) return FR_TIMEOUT; } -#define LEAVE_FF(fs, res) { unlock_fs(fs, res); return res; } -#else -#define ENTER_FF(fs) -#define LEAVE_FF(fs, res) return res -#endif - -#define ABORT(fs, res) { fp->err = (BYTE)(res); LEAVE_FF(fs, res); } - - -/* File access control feature */ -#if _FS_LOCK -#if _FS_READONLY -#error _FS_LOCK must be 0 at read-only cfg. -#endif -typedef struct { - FATFS *fs; /* Object ID 1, volume (NULL:blank entry) */ - DWORD clu; /* Object ID 2, directory */ - WORD idx; /* Object ID 3, directory index */ - WORD ctr; /* Object open counter, 0:none, 0x01..0xFF:read mode open count, 0x100:write mode */ -} FILESEM; -#endif - - - -/* DBCS code ranges and SBCS extend character conversion table */ - -#if _CODE_PAGE == 932 /* Japanese Shift-JIS */ -#define _DF1S 0x81 /* DBC 1st byte range 1 start */ -#define _DF1E 0x9F /* DBC 1st byte range 1 end */ -#define _DF2S 0xE0 /* DBC 1st byte range 2 start */ -#define _DF2E 0xFC /* DBC 1st byte range 2 end */ -#define _DS1S 0x40 /* DBC 2nd byte range 1 start */ -#define _DS1E 0x7E /* DBC 2nd byte range 1 end */ -#define _DS2S 0x80 /* DBC 2nd byte range 2 start */ -#define _DS2E 0xFC /* DBC 2nd byte range 2 end */ - -#elif _CODE_PAGE == 936 /* Simplified Chinese GBK */ -#define _DF1S 0x81 -#define _DF1E 0xFE -#define _DS1S 0x40 -#define _DS1E 0x7E -#define _DS2S 0x80 -#define _DS2E 0xFE - -#elif _CODE_PAGE == 949 /* Korean */ -#define _DF1S 0x81 -#define _DF1E 0xFE -#define _DS1S 0x41 -#define _DS1E 0x5A -#define _DS2S 0x61 -#define _DS2E 0x7A -#define _DS3S 0x81 -#define _DS3E 0xFE - -#elif _CODE_PAGE == 950 /* Traditional Chinese Big5 */ -#define _DF1S 0x81 -#define _DF1E 0xFE -#define _DS1S 0x40 -#define _DS1E 0x7E -#define _DS2S 0xA1 -#define _DS2E 0xFE - -#elif _CODE_PAGE == 437 /* U.S. (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F,0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 720 /* Arabic (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x45,0x41,0x84,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x49,0x49,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 737 /* Greek (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \ - 0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xE7,0xE8,0xF1,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 775 /* Baltic (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ - 0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 850 /* Multilingual Latin 1 (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ - 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 852 /* Latin 2 (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F,0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0x9F, \ - 0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF} - -#elif _CODE_PAGE == 855 /* Cyrillic (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F,0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \ - 0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \ - 0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 857 /* Turkish (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x98,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \ - 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0x59,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 858 /* Multilingual Latin 1 + Euro (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ - 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 862 /* Hebrew (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 866 /* Russian (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0x90,0x91,0x92,0x93,0x9d,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F,0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 874 /* Thai (OEM, Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 1250 /* Central Europe (Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \ - 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xA3,0xB4,0xB5,0xB6,0xB7,0xB8,0xA5,0xAA,0xBB,0xBC,0xBD,0xBC,0xAF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF} - -#elif _CODE_PAGE == 1251 /* Cyrillic (Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x82,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x80,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \ - 0xA0,0xA2,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB2,0xA5,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xA3,0xBD,0xBD,0xAF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF} - -#elif _CODE_PAGE == 1252 /* Latin 1 (Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0xAd,0x9B,0x8C,0x9D,0xAE,0x9F, \ - 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F} - -#elif _CODE_PAGE == 1253 /* Greek (Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xA2,0xB8,0xB9,0xBA, \ - 0xE0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xFB,0xBC,0xFD,0xBF,0xFF} - -#elif _CODE_PAGE == 1254 /* Turkish (Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x9D,0x9E,0x9F, \ - 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F} - -#elif _CODE_PAGE == 1255 /* Hebrew (Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 1256 /* Arabic (Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x8C,0x9D,0x9E,0x9F, \ - 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0x41,0xE1,0x41,0xE3,0xE4,0xE5,0xE6,0x43,0x45,0x45,0x45,0x45,0xEC,0xED,0x49,0x49,0xF0,0xF1,0xF2,0xF3,0x4F,0xF5,0xF6,0xF7,0xF8,0x55,0xFA,0x55,0x55,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 1257 /* Baltic (Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xBC,0xBD,0xBE,0xAF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF} - -#elif _CODE_PAGE == 1258 /* Vietnam (OEM, Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0xAC,0x9D,0x9E,0x9F, \ - 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xEC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xFE,0x9F} - -#elif _CODE_PAGE == 1 /* ASCII (for only non-LFN cfg) */ -#if _USE_LFN -#error Cannot use LFN feature without valid code page. -#endif -#define _DF1S 0 - -#else -#error Unknown code page - -#endif - - -/* Character code support macros */ -#define IsUpper(c) (((c)>='A')&&((c)<='Z')) -#define IsLower(c) (((c)>='a')&&((c)<='z')) -#define IsDigit(c) (((c)>='0')&&((c)<='9')) - -#if _DF1S /* Code page is DBCS */ - -#ifdef _DF2S /* Two 1st byte areas */ -#define IsDBCS1(c) (((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) || ((BYTE)(c) >= _DF2S && (BYTE)(c) <= _DF2E)) -#else /* One 1st byte area */ -#define IsDBCS1(c) ((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) -#endif - -#ifdef _DS3S /* Three 2nd byte areas */ -#define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E) || ((BYTE)(c) >= _DS3S && (BYTE)(c) <= _DS3E)) -#else /* Two 2nd byte areas */ -#define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E)) -#endif - -#else /* Code page is SBCS */ - -#define IsDBCS1(c) 0 -#define IsDBCS2(c) 0 - -#endif /* _DF1S */ - - -/* Name status flags */ -#define NS 11 /* Index of name status byte in fn[] */ -#define NS_LOSS 0x01 /* Out of 8.3 format */ -#define NS_LFN 0x02 /* Force to create LFN entry */ -#define NS_LAST 0x04 /* Last segment */ -#define NS_BODY 0x08 /* Lower case flag (body) */ -#define NS_EXT 0x10 /* Lower case flag (ext) */ -#define NS_DOT 0x20 /* Dot entry */ - - -/* FAT sub-type boundaries */ -#define MIN_FAT16 4086U /* Minimum number of clusters for FAT16 */ -#define MIN_FAT32 65526U /* Minimum number of clusters for FAT32 */ - - -/* FatFs refers the members in the FAT structures as byte array instead of -/ structure member because the structure is not binary compatible between -/ different platforms */ - -#define BS_jmpBoot 0 /* Jump instruction (3) */ -#define BS_OEMName 3 /* OEM name (8) */ -#define BPB_BytsPerSec 11 /* Sector size [byte] (2) */ -#define BPB_SecPerClus 13 /* Cluster size [sector] (1) */ -#define BPB_RsvdSecCnt 14 /* Size of reserved area [sector] (2) */ -#define BPB_NumFATs 16 /* Number of FAT copies (1) */ -#define BPB_RootEntCnt 17 /* Number of root directory entries for FAT12/16 (2) */ -#define BPB_TotSec16 19 /* Volume size [sector] (2) */ -#define BPB_Media 21 /* Media descriptor (1) */ -#define BPB_FATSz16 22 /* FAT size [sector] (2) */ -#define BPB_SecPerTrk 24 /* Track size [sector] (2) */ -#define BPB_NumHeads 26 /* Number of heads (2) */ -#define BPB_HiddSec 28 /* Number of special hidden sectors (4) */ -#define BPB_TotSec32 32 /* Volume size [sector] (4) */ -#define BS_DrvNum 36 /* Physical drive number (2) */ -#define BS_BootSig 38 /* Extended boot signature (1) */ -#define BS_VolID 39 /* Volume serial number (4) */ -#define BS_VolLab 43 /* Volume label (8) */ -#define BS_FilSysType 54 /* File system type (1) */ -#define BPB_FATSz32 36 /* FAT size [sector] (4) */ -#define BPB_ExtFlags 40 /* Extended flags (2) */ -#define BPB_FSVer 42 /* File system version (2) */ -#define BPB_RootClus 44 /* Root directory first cluster (4) */ -#define BPB_FSInfo 48 /* Offset of FSINFO sector (2) */ -#define BPB_BkBootSec 50 /* Offset of backup boot sector (2) */ -#define BS_DrvNum32 64 /* Physical drive number (2) */ -#define BS_BootSig32 66 /* Extended boot signature (1) */ -#define BS_VolID32 67 /* Volume serial number (4) */ -#define BS_VolLab32 71 /* Volume label (8) */ -#define BS_FilSysType32 82 /* File system type (1) */ -#define FSI_LeadSig 0 /* FSI: Leading signature (4) */ -#define FSI_StrucSig 484 /* FSI: Structure signature (4) */ -#define FSI_Free_Count 488 /* FSI: Number of free clusters (4) */ -#define FSI_Nxt_Free 492 /* FSI: Last allocated cluster (4) */ -#define MBR_Table 446 /* MBR: Partition table offset (2) */ -#define SZ_PTE 16 /* MBR: Size of a partition table entry */ -#define BS_55AA 510 /* Boot sector signature (2) */ - -#define DIR_Name 0 /* Short file name (11) */ -#define DIR_Attr 11 /* Attribute (1) */ -#define DIR_NTres 12 /* NT flag (1) */ -#define DIR_CrtTimeTenth 13 /* Created time sub-second (1) */ -#define DIR_CrtTime 14 /* Created time (2) */ -#define DIR_CrtDate 16 /* Created date (2) */ -#define DIR_LstAccDate 18 /* Last accessed date (2) */ -#define DIR_FstClusHI 20 /* Higher 16-bit of first cluster (2) */ -#define DIR_WrtTime 22 /* Modified time (2) */ -#define DIR_WrtDate 24 /* Modified date (2) */ -#define DIR_FstClusLO 26 /* Lower 16-bit of first cluster (2) */ -#define DIR_FileSize 28 /* File size (4) */ -#define LDIR_Ord 0 /* LFN entry order and LLE flag (1) */ -#define LDIR_Attr 11 /* LFN attribute (1) */ -#define LDIR_Type 12 /* LFN type (1) */ -#define LDIR_Chksum 13 /* Sum of corresponding SFN entry */ -#define LDIR_FstClusLO 26 /* Filled by zero (0) */ -#define SZ_DIR 32 /* Size of a directory entry */ -#define LLE 0x40 /* Last long entry flag in LDIR_Ord */ -#define DDE 0xE5 /* Deleted directory entry mark in DIR_Name[0] */ -#define NDDE 0x05 /* Replacement of the character collides with DDE */ - - -/*------------------------------------------------------------*/ -/* Module private work area */ -/*------------------------------------------------------------*/ -/* Note that uninitialized variables with static duration are -/ zeroed/nulled at start-up. If not, the compiler or start-up -/ routine is out of ANSI-C standard. -*/ - -#if _VOLUMES -static -FATFS *FatFs[_VOLUMES]; /* Pointer to the file system objects (logical drives) */ -#else -#error Number of volumes must not be 0. -#endif - -static -WORD Fsid; /* File system mount ID */ - -#if _FS_RPATH && _VOLUMES >= 2 -static -BYTE CurrVol; /* Current drive */ -#endif - -#if _FS_LOCK -static -FILESEM Files[_FS_LOCK]; /* Open object lock semaphores */ -#endif - -#if _USE_LFN == 0 /* No LFN feature */ -#define DEF_NAMEBUF BYTE sfn[12] -#define INIT_BUF(dobj) (dobj).fn = sfn -#define FREE_BUF() - -#elif _USE_LFN == 1 /* LFN feature with static working buffer */ -static -WCHAR LfnBuf[_MAX_LFN+1]; -#define DEF_NAMEBUF BYTE sfn[12] -#define INIT_BUF(dobj) { (dobj).fn = sfn; (dobj).lfn = LfnBuf; } -#define FREE_BUF() - -#elif _USE_LFN == 2 /* LFN feature with dynamic working buffer on the stack */ -#define DEF_NAMEBUF BYTE sfn[12]; WCHAR lbuf[_MAX_LFN+1] -#define INIT_BUF(dobj) { (dobj).fn = sfn; (dobj).lfn = lbuf; } -#define FREE_BUF() - -#elif _USE_LFN == 3 /* LFN feature with dynamic working buffer on the heap */ -#define DEF_NAMEBUF BYTE sfn[12]; WCHAR *lfn -#define INIT_BUF(dobj) { lfn = ff_memalloc((_MAX_LFN + 1) * 2); \ - if (!lfn) LEAVE_FF((dobj).fs, FR_NOT_ENOUGH_CORE); \ - (dobj).lfn = lfn; (dobj).fn = sfn; } -#define FREE_BUF() ff_memfree(lfn) - -#else -#error Wrong LFN configuration. -#endif - - -#ifdef _EXCVT -static -const BYTE ExCvt[] = _EXCVT; /* Upper conversion table for extended characters */ -#endif - - - - - - -/*-------------------------------------------------------------------------- - - Module Private Functions - ----------------------------------------------------------------------------*/ - - -/*-----------------------------------------------------------------------*/ -/* String functions */ -/*-----------------------------------------------------------------------*/ - -/* Copy memory to memory */ -static -void mem_cpy (void* dst, const void* src, UINT cnt) { - BYTE *d = (BYTE*)dst; - const BYTE *s = (const BYTE*)src; - -#if _WORD_ACCESS == 1 - while (cnt >= sizeof (int)) { - *(int*)d = *(int*)s; - d += sizeof (int); s += sizeof (int); - cnt -= sizeof (int); - } -#endif - while (cnt--) - *d++ = *s++; -} - -/* Fill memory */ -static -void mem_set (void* dst, int val, UINT cnt) { - BYTE *d = (BYTE*)dst; - - while (cnt--) - *d++ = (BYTE)val; -} - -/* Compare memory to memory */ -static -int mem_cmp (const void* dst, const void* src, UINT cnt) { - const BYTE *d = (const BYTE *)dst, *s = (const BYTE *)src; - int r = 0; - - while (cnt-- && (r = *d++ - *s++) == 0) ; - return r; -} - -/* Check if chr is contained in the string */ -static -int chk_chr (const char* str, int chr) { - while (*str && *str != chr) str++; - return *str; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Request/Release grant to access the volume */ -/*-----------------------------------------------------------------------*/ -#if _FS_REENTRANT -static -int lock_fs ( - FATFS* fs /* File system object */ -) -{ - return ff_req_grant(fs->sobj); -} - - -static -void unlock_fs ( - FATFS* fs, /* File system object */ - FRESULT res /* Result code to be returned */ -) -{ - if (fs && - res != FR_NOT_ENABLED && - res != FR_INVALID_DRIVE && - res != FR_INVALID_OBJECT && - res != FR_TIMEOUT) { - ff_rel_grant(fs->sobj); - } -} -#endif - - - - -/*-----------------------------------------------------------------------*/ -/* File lock control functions */ -/*-----------------------------------------------------------------------*/ -#if _FS_LOCK - -static -FRESULT chk_lock ( /* Check if the file can be accessed */ - DIR* dp, /* Directory object pointing the file to be checked */ - int acc /* Desired access (0:Read, 1:Write, 2:Delete/Rename) */ -) -{ - UINT i, be; - - /* Search file semaphore table */ - for (i = be = 0; i < _FS_LOCK; i++) { - if (Files[i].fs) { /* Existing entry */ - if (Files[i].fs == dp->fs && /* Check if the object matched with an open object */ - Files[i].clu == dp->sclust && - Files[i].idx == dp->index) break; - } else { /* Blank entry */ - be = 1; - } - } - if (i == _FS_LOCK) /* The object is not opened */ - return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES; /* Is there a blank entry for new object? */ - - /* The object has been opened. Reject any open against writing file and all write mode open */ - return (acc || Files[i].ctr == 0x100) ? FR_LOCKED : FR_OK; -} - - -static -int enq_lock (void) /* Check if an entry is available for a new object */ -{ - UINT i; - - for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ; - return (i == _FS_LOCK) ? 0 : 1; -} - - -static -UINT inc_lock ( /* Increment object open counter and returns its index (0:Internal error) */ - DIR* dp, /* Directory object pointing the file to register or increment */ - int acc /* Desired access (0:Read, 1:Write, 2:Delete/Rename) */ -) -{ - UINT i; - - - for (i = 0; i < _FS_LOCK; i++) { /* Find the object */ - if (Files[i].fs == dp->fs && - Files[i].clu == dp->sclust && - Files[i].idx == dp->index) break; - } - - if (i == _FS_LOCK) { /* Not opened. Register it as new. */ - for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ; - if (i == _FS_LOCK) return 0; /* No free entry to register (int err) */ - Files[i].fs = dp->fs; - Files[i].clu = dp->sclust; - Files[i].idx = dp->index; - Files[i].ctr = 0; - } - - if (acc && Files[i].ctr) return 0; /* Access violation (int err) */ - - Files[i].ctr = acc ? 0x100 : Files[i].ctr + 1; /* Set semaphore value */ - - return i + 1; -} - - -static -FRESULT dec_lock ( /* Decrement object open counter */ - UINT i /* Semaphore index (1..) */ -) -{ - WORD n; - FRESULT res; - - - if (--i < _FS_LOCK) { /* Shift index number origin from 0 */ - n = Files[i].ctr; - if (n == 0x100) n = 0; /* If write mode open, delete the entry */ - if (n) n--; /* Decrement read mode open count */ - Files[i].ctr = n; - if (!n) Files[i].fs = 0; /* Delete the entry if open count gets zero */ - res = FR_OK; - } else { - res = FR_INT_ERR; /* Invalid index nunber */ - } - return res; -} - - -static -void clear_lock ( /* Clear lock entries of the volume */ - FATFS *fs -) -{ - UINT i; - - for (i = 0; i < _FS_LOCK; i++) { - if (Files[i].fs == fs) Files[i].fs = 0; - } -} -#endif - - - - -/*-----------------------------------------------------------------------*/ -/* Move/Flush disk access window in the file system object */ -/*-----------------------------------------------------------------------*/ -#if !_FS_READONLY -static -FRESULT sync_window ( - FATFS* fs /* File system object */ -) -{ - DWORD wsect; - UINT nf; - - - if (fs->wflag) { /* Write back the sector if it is dirty */ - wsect = fs->winsect; /* Current sector number */ - if (disk_write(fs->drv, fs->win, wsect, 1)) - return FR_DISK_ERR; - fs->wflag = 0; - if (wsect - fs->fatbase < fs->fsize) { /* Is it in the FAT area? */ - for (nf = fs->n_fats; nf >= 2; nf--) { /* Reflect the change to all FAT copies */ - wsect += fs->fsize; - disk_write(fs->drv, fs->win, wsect, 1); - } - } - } - return FR_OK; -} -#endif - - -static -FRESULT move_window ( - FATFS* fs, /* File system object */ - DWORD sector /* Sector number to make appearance in the fs->win[] */ -) -{ - if (sector != fs->winsect) { /* Changed current window */ -#if !_FS_READONLY - if (sync_window(fs) != FR_OK) - return FR_DISK_ERR; -#endif - if (disk_read(fs->drv, fs->win, sector, 1)) - return FR_DISK_ERR; - fs->winsect = sector; - } - - return FR_OK; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Synchronize file system and strage device */ -/*-----------------------------------------------------------------------*/ -#if !_FS_READONLY -static -FRESULT sync_fs ( /* FR_OK: successful, FR_DISK_ERR: failed */ - FATFS* fs /* File system object */ -) -{ - FRESULT res; - - - res = sync_window(fs); - if (res == FR_OK) { - /* Update FSINFO sector if needed */ - if (fs->fs_type == FS_FAT32 && fs->fsi_flag == 1) { - /* Create FSINFO structure */ - mem_set(fs->win, 0, SS(fs)); - ST_WORD(fs->win+BS_55AA, 0xAA55); - ST_DWORD(fs->win+FSI_LeadSig, 0x41615252); - ST_DWORD(fs->win+FSI_StrucSig, 0x61417272); - ST_DWORD(fs->win+FSI_Free_Count, fs->free_clust); - ST_DWORD(fs->win+FSI_Nxt_Free, fs->last_clust); - /* Write it into the FSINFO sector */ - fs->winsect = fs->volbase + 1; - disk_write(fs->drv, fs->win, fs->winsect, 1); - fs->fsi_flag = 0; - } - /* Make sure that no pending write process in the physical drive */ - if (disk_ioctl(fs->drv, CTRL_SYNC, 0) != RES_OK) - res = FR_DISK_ERR; - } - - return res; -} -#endif - - - - -/*-----------------------------------------------------------------------*/ -/* Get sector# from cluster# */ -/*-----------------------------------------------------------------------*/ - - -DWORD clust2sect ( /* !=0: Sector number, 0: Failed - invalid cluster# */ - FATFS* fs, /* File system object */ - DWORD clst /* Cluster# to be converted */ -) -{ - clst -= 2; - if (clst >= (fs->n_fatent - 2)) return 0; /* Invalid cluster# */ - return clst * fs->csize + fs->database; -} - - - - -/*-----------------------------------------------------------------------*/ -/* FAT access - Read value of a FAT entry */ -/*-----------------------------------------------------------------------*/ - - -DWORD get_fat ( /* 0xFFFFFFFF:Disk error, 1:Internal error, Else:Cluster status */ - FATFS* fs, /* File system object */ - DWORD clst /* Cluster# to get the link information */ -) -{ - UINT wc, bc; - BYTE *p; - - - if (clst < 2 || clst >= fs->n_fatent) /* Check range */ - return 1; - - switch (fs->fs_type) { - case FS_FAT12 : - bc = (UINT)clst; bc += bc / 2; - if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break; - wc = fs->win[bc % SS(fs)]; bc++; - if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break; - wc |= fs->win[bc % SS(fs)] << 8; - return clst & 1 ? wc >> 4 : (wc & 0xFFF); - - case FS_FAT16 : - if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2)))) break; - p = &fs->win[clst * 2 % SS(fs)]; - return LD_WORD(p); - - case FS_FAT32 : - if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4)))) break; - p = &fs->win[clst * 4 % SS(fs)]; - return LD_DWORD(p) & 0x0FFFFFFF; - } - - return 0xFFFFFFFF; /* An error occurred at the disk I/O layer */ -} - - - - -/*-----------------------------------------------------------------------*/ -/* FAT access - Change value of a FAT entry */ -/*-----------------------------------------------------------------------*/ -#if !_FS_READONLY - -FRESULT put_fat ( - FATFS* fs, /* File system object */ - DWORD clst, /* Cluster# to be changed in range of 2 to fs->n_fatent - 1 */ - DWORD val /* New value to mark the cluster */ -) -{ - UINT bc; - BYTE *p; - FRESULT res; - - - if (clst < 2 || clst >= fs->n_fatent) { /* Check range */ - res = FR_INT_ERR; - - } else { - switch (fs->fs_type) { - case FS_FAT12 : - bc = (UINT)clst; bc += bc / 2; - res = move_window(fs, fs->fatbase + (bc / SS(fs))); - if (res != FR_OK) break; - p = &fs->win[bc % SS(fs)]; - *p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val; - bc++; - fs->wflag = 1; - res = move_window(fs, fs->fatbase + (bc / SS(fs))); - if (res != FR_OK) break; - p = &fs->win[bc % SS(fs)]; - *p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F)); - break; - - case FS_FAT16 : - res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))); - if (res != FR_OK) break; - p = &fs->win[clst * 2 % SS(fs)]; - ST_WORD(p, (WORD)val); - break; - - case FS_FAT32 : - res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))); - if (res != FR_OK) break; - p = &fs->win[clst * 4 % SS(fs)]; - val |= LD_DWORD(p) & 0xF0000000; - ST_DWORD(p, val); - break; - - default : - res = FR_INT_ERR; - } - fs->wflag = 1; - } - - return res; -} -#endif /* !_FS_READONLY */ - - - - -/*-----------------------------------------------------------------------*/ -/* FAT handling - Remove a cluster chain */ -/*-----------------------------------------------------------------------*/ -#if !_FS_READONLY -static -FRESULT remove_chain ( - FATFS* fs, /* File system object */ - DWORD clst /* Cluster# to remove a chain from */ -) -{ - FRESULT res; - DWORD nxt; -#if _USE_ERASE - DWORD scl = clst, ecl = clst, rt[2]; -#endif - - if (clst < 2 || clst >= fs->n_fatent) { /* Check range */ - res = FR_INT_ERR; - - } else { - res = FR_OK; - while (clst < fs->n_fatent) { /* Not a last link? */ - nxt = get_fat(fs, clst); /* Get cluster status */ - if (nxt == 0) break; /* Empty cluster? */ - if (nxt == 1) { res = FR_INT_ERR; break; } /* Internal error? */ - if (nxt == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } /* Disk error? */ - res = put_fat(fs, clst, 0); /* Mark the cluster "empty" */ - if (res != FR_OK) break; - if (fs->free_clust != 0xFFFFFFFF) { /* Update FSINFO */ - fs->free_clust++; - fs->fsi_flag |= 1; - } -#if _USE_ERASE - if (ecl + 1 == nxt) { /* Is next cluster contiguous? */ - ecl = nxt; - } else { /* End of contiguous clusters */ - rt[0] = clust2sect(fs, scl); /* Start sector */ - rt[1] = clust2sect(fs, ecl) + fs->csize - 1; /* End sector */ - disk_ioctl(fs->drv, CTRL_ERASE_SECTOR, rt); /* Erase the block */ - scl = ecl = nxt; - } -#endif - clst = nxt; /* Next cluster */ - } - } - - return res; -} -#endif - - - - -/*-----------------------------------------------------------------------*/ -/* FAT handling - Stretch or Create a cluster chain */ -/*-----------------------------------------------------------------------*/ -#if !_FS_READONLY -static -DWORD create_chain ( /* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster# */ - FATFS* fs, /* File system object */ - DWORD clst /* Cluster# to stretch. 0 means create a new chain. */ -) -{ - DWORD cs, ncl, scl; - FRESULT res; - - - if (clst == 0) { /* Create a new chain */ - scl = fs->last_clust; /* Get suggested start point */ - if (!scl || scl >= fs->n_fatent) scl = 1; - } - else { /* Stretch the current chain */ - cs = get_fat(fs, clst); /* Check the cluster status */ - if (cs < 2) return 1; /* It is an invalid cluster */ - if (cs < fs->n_fatent) return cs; /* It is already followed by next cluster */ - scl = clst; - } - - ncl = scl; /* Start cluster */ - for (;;) { - ncl++; /* Next cluster */ - if (ncl >= fs->n_fatent) { /* Wrap around */ - ncl = 2; - if (ncl > scl) return 0; /* No free cluster */ - } - cs = get_fat(fs, ncl); /* Get the cluster status */ - if (cs == 0) break; /* Found a free cluster */ - if (cs == 0xFFFFFFFF || cs == 1)/* An error occurred */ - return cs; - if (ncl == scl) return 0; /* No free cluster */ - } - - res = put_fat(fs, ncl, 0x0FFFFFFF); /* Mark the new cluster "last link" */ - if (res == FR_OK && clst != 0) { - res = put_fat(fs, clst, ncl); /* Link it to the previous one if needed */ - } - if (res == FR_OK) { - fs->last_clust = ncl; /* Update FSINFO */ - if (fs->free_clust != 0xFFFFFFFF) { - fs->free_clust--; - fs->fsi_flag |= 1; - } - } else { - ncl = (res == FR_DISK_ERR) ? 0xFFFFFFFF : 1; - } - - return ncl; /* Return new cluster number or error code */ -} -#endif /* !_FS_READONLY */ - - - - -/*-----------------------------------------------------------------------*/ -/* FAT handling - Convert offset into cluster with link map table */ -/*-----------------------------------------------------------------------*/ - -#if _USE_FASTSEEK -static -DWORD clmt_clust ( /* <2:Error, >=2:Cluster number */ - FIL* fp, /* Pointer to the file object */ - DWORD ofs /* File offset to be converted to cluster# */ -) -{ - DWORD cl, ncl, *tbl; - - - tbl = fp->cltbl + 1; /* Top of CLMT */ - cl = ofs / SS(fp->fs) / fp->fs->csize; /* Cluster order from top of the file */ - for (;;) { - ncl = *tbl++; /* Number of cluters in the fragment */ - if (!ncl) return 0; /* End of table? (error) */ - if (cl < ncl) break; /* In this fragment? */ - cl -= ncl; tbl++; /* Next fragment */ - } - return cl + *tbl; /* Return the cluster number */ -} -#endif /* _USE_FASTSEEK */ - - - - -/*-----------------------------------------------------------------------*/ -/* Directory handling - Set directory index */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT dir_sdi ( - DIR* dp, /* Pointer to directory object */ - WORD idx /* Index of directory table */ -) -{ - DWORD clst; - WORD ic; - - - dp->index = idx; - clst = dp->sclust; - if (clst == 1 || clst >= dp->fs->n_fatent) /* Check start cluster range */ - return FR_INT_ERR; - if (!clst && dp->fs->fs_type == FS_FAT32) /* Replace cluster# 0 with root cluster# if in FAT32 */ - clst = dp->fs->dirbase; - - if (clst == 0) { /* Static table (root-directory in FAT12/16) */ - dp->clust = clst; - if (idx >= dp->fs->n_rootdir) /* Index is out of range */ - return FR_INT_ERR; - dp->sect = dp->fs->dirbase + idx / (SS(dp->fs) / SZ_DIR); /* Sector# */ - } - else { /* Dynamic table (sub-dirs or root-directory in FAT32) */ - ic = SS(dp->fs) / SZ_DIR * dp->fs->csize; /* Entries per cluster */ - while (idx >= ic) { /* Follow cluster chain */ - clst = get_fat(dp->fs, clst); /* Get next cluster */ - if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ - if (clst < 2 || clst >= dp->fs->n_fatent) /* Reached to end of table or int error */ - return FR_INT_ERR; - idx -= ic; - } - dp->clust = clst; - dp->sect = clust2sect(dp->fs, clst) + idx / (SS(dp->fs) / SZ_DIR); /* Sector# */ - } - - dp->dir = dp->fs->win + (idx % (SS(dp->fs) / SZ_DIR)) * SZ_DIR; /* Ptr to the entry in the sector */ - - return FR_OK; /* Seek succeeded */ -} - - - - -/*-----------------------------------------------------------------------*/ -/* Directory handling - Move directory table index next */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT dir_next ( /* FR_OK:Succeeded, FR_NO_FILE:End of table, FR_DENIED:Could not stretch */ - DIR* dp, /* Pointer to the directory object */ - int stretch /* 0: Do not stretch table, 1: Stretch table if needed */ -) -{ - DWORD clst; - WORD i; - - - i = dp->index + 1; - if (!i || !dp->sect) /* Report EOT when index has reached 65535 */ - return FR_NO_FILE; - - if (!(i % (SS(dp->fs) / SZ_DIR))) { /* Sector changed? */ - dp->sect++; /* Next sector */ - - if (!dp->clust) { /* Static table */ - if (i >= dp->fs->n_rootdir) /* Report EOT if it reached end of static table */ - return FR_NO_FILE; - } - else { /* Dynamic table */ - if (((i / (SS(dp->fs) / SZ_DIR)) & (dp->fs->csize - 1)) == 0) { /* Cluster changed? */ - clst = get_fat(dp->fs, dp->clust); /* Get next cluster */ - if (clst <= 1) return FR_INT_ERR; - if (clst == 0xFFFFFFFF) return FR_DISK_ERR; - if (clst >= dp->fs->n_fatent) { /* If it reached end of dynamic table, */ -#if !_FS_READONLY - BYTE c; - if (!stretch) return FR_NO_FILE; /* If do not stretch, report EOT */ - clst = create_chain(dp->fs, dp->clust); /* Stretch cluster chain */ - if (clst == 0) return FR_DENIED; /* No free cluster */ - if (clst == 1) return FR_INT_ERR; - if (clst == 0xFFFFFFFF) return FR_DISK_ERR; - /* Clean-up stretched table */ - if (sync_window(dp->fs)) return FR_DISK_ERR;/* Flush disk access window */ - mem_set(dp->fs->win, 0, SS(dp->fs)); /* Clear window buffer */ - dp->fs->winsect = clust2sect(dp->fs, clst); /* Cluster start sector */ - for (c = 0; c < dp->fs->csize; c++) { /* Fill the new cluster with 0 */ - dp->fs->wflag = 1; - if (sync_window(dp->fs)) return FR_DISK_ERR; - dp->fs->winsect++; - } - dp->fs->winsect -= c; /* Rewind window offset */ -#else - if (!stretch) return FR_NO_FILE; /* If do not stretch, report EOT */ - return FR_NO_FILE; /* Report EOT */ -#endif - } - dp->clust = clst; /* Initialize data for new cluster */ - dp->sect = clust2sect(dp->fs, clst); - } - } - } - - dp->index = i; /* Current index */ - dp->dir = dp->fs->win + (i % (SS(dp->fs) / SZ_DIR)) * SZ_DIR; /* Current entry in the window */ - - return FR_OK; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Directory handling - Reserve directory entry */ -/*-----------------------------------------------------------------------*/ - -#if !_FS_READONLY -static -FRESULT dir_alloc ( - DIR* dp, /* Pointer to the directory object */ - UINT nent /* Number of contiguous entries to allocate (1-21) */ -) -{ - FRESULT res; - UINT n; - - - res = dir_sdi(dp, 0); - if (res == FR_OK) { - n = 0; - do { - res = move_window(dp->fs, dp->sect); - if (res != FR_OK) break; - if (dp->dir[0] == DDE || dp->dir[0] == 0) { /* Is it a blank entry? */ - if (++n == nent) break; /* A block of contiguous entries is found */ - } else { - n = 0; /* Not a blank entry. Restart to search */ - } - res = dir_next(dp, 1); /* Next entry with table stretch enabled */ - } while (res == FR_OK); - } - if (res == FR_NO_FILE) res = FR_DENIED; /* No directory entry to allocate */ - return res; -} -#endif - - - - -/*-----------------------------------------------------------------------*/ -/* Directory handling - Load/Store start cluster number */ -/*-----------------------------------------------------------------------*/ - -static -DWORD ld_clust ( - FATFS* fs, /* Pointer to the fs object */ - BYTE* dir /* Pointer to the directory entry */ -) -{ - DWORD cl; - - cl = LD_WORD(dir+DIR_FstClusLO); - if (fs->fs_type == FS_FAT32) - cl |= (DWORD)LD_WORD(dir+DIR_FstClusHI) << 16; - - return cl; -} - - -#if !_FS_READONLY -static -void st_clust ( - BYTE* dir, /* Pointer to the directory entry */ - DWORD cl /* Value to be set */ -) -{ - ST_WORD(dir+DIR_FstClusLO, cl); - ST_WORD(dir+DIR_FstClusHI, cl >> 16); -} -#endif - - - - -/*-----------------------------------------------------------------------*/ -/* LFN handling - Test/Pick/Fit an LFN segment from/to directory entry */ -/*-----------------------------------------------------------------------*/ -#if _USE_LFN -static -const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30}; /* Offset of LFN characters in the directory entry */ - - -static -int cmp_lfn ( /* 1:Matched, 0:Not matched */ - WCHAR* lfnbuf, /* Pointer to the LFN to be compared */ - BYTE* dir /* Pointer to the directory entry containing a part of LFN */ -) -{ - UINT i, s; - WCHAR wc, uc; - - - i = ((dir[LDIR_Ord] & ~LLE) - 1) * 13; /* Get offset in the LFN buffer */ - s = 0; wc = 1; - do { - uc = LD_WORD(dir+LfnOfs[s]); /* Pick an LFN character from the entry */ - if (wc) { /* Last character has not been processed */ - wc = ff_wtoupper(uc); /* Convert it to upper case */ - if (i >= _MAX_LFN || wc != ff_wtoupper(lfnbuf[i++])) /* Compare it */ - return 0; /* Not matched */ - } else { - if (uc != 0xFFFF) return 0; /* Check filler */ - } - } while (++s < 13); /* Repeat until all characters in the entry are checked */ - - if ((dir[LDIR_Ord] & LLE) && wc && lfnbuf[i]) /* Last segment matched but different length */ - return 0; - - return 1; /* The part of LFN matched */ -} - - - -static -int pick_lfn ( /* 1:Succeeded, 0:Buffer overflow */ - WCHAR* lfnbuf, /* Pointer to the Unicode-LFN buffer */ - BYTE* dir /* Pointer to the directory entry */ -) -{ - UINT i, s; - WCHAR wc, uc; - - - i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13; /* Offset in the LFN buffer */ - - s = 0; wc = 1; - do { - uc = LD_WORD(dir+LfnOfs[s]); /* Pick an LFN character from the entry */ - if (wc) { /* Last character has not been processed */ - if (i >= _MAX_LFN) return 0; /* Buffer overflow? */ - lfnbuf[i++] = wc = uc; /* Store it */ - } else { - if (uc != 0xFFFF) return 0; /* Check filler */ - } - } while (++s < 13); /* Read all character in the entry */ - - if (dir[LDIR_Ord] & LLE) { /* Put terminator if it is the last LFN part */ - if (i >= _MAX_LFN) return 0; /* Buffer overflow? */ - lfnbuf[i] = 0; - } - - return 1; -} - - -#if !_FS_READONLY -static -void fit_lfn ( - const WCHAR* lfnbuf, /* Pointer to the LFN buffer */ - BYTE* dir, /* Pointer to the directory entry */ - BYTE ord, /* LFN order (1-20) */ - BYTE sum /* SFN sum */ -) -{ - UINT i, s; - WCHAR wc; - - - dir[LDIR_Chksum] = sum; /* Set check sum */ - dir[LDIR_Attr] = AM_LFN; /* Set attribute. LFN entry */ - dir[LDIR_Type] = 0; - ST_WORD(dir+LDIR_FstClusLO, 0); - - i = (ord - 1) * 13; /* Get offset in the LFN buffer */ - s = wc = 0; - do { - if (wc != 0xFFFF) wc = lfnbuf[i++]; /* Get an effective character */ - ST_WORD(dir+LfnOfs[s], wc); /* Put it */ - if (!wc) wc = 0xFFFF; /* Padding characters following last character */ - } while (++s < 13); - if (wc == 0xFFFF || !lfnbuf[i]) ord |= LLE; /* Bottom LFN part is the start of LFN sequence */ - dir[LDIR_Ord] = ord; /* Set the LFN order */ -} - -#endif -#endif - - - - -/*-----------------------------------------------------------------------*/ -/* Create numbered name */ -/*-----------------------------------------------------------------------*/ -#if _USE_LFN -void gen_numname ( - BYTE* dst, /* Pointer to generated SFN */ - const BYTE* src, /* Pointer to source SFN to be modified */ - const WCHAR* lfn, /* Pointer to LFN */ - WORD seq /* Sequence number */ -) -{ - BYTE ns[8], c; - UINT i, j; - - - mem_cpy(dst, src, 11); - - if (seq > 5) { /* On many collisions, generate a hash number instead of sequential number */ - do seq = (seq >> 1) + (seq << 15) + (WORD)*lfn++; while (*lfn); - } - - /* itoa (hexdecimal) */ - i = 7; - do { - c = (seq % 16) + '0'; - if (c > '9') c += 7; - ns[i--] = c; - seq /= 16; - } while (seq); - ns[i] = '~'; - - /* Append the number */ - for (j = 0; j < i && dst[j] != ' '; j++) { - if (IsDBCS1(dst[j])) { - if (j == i - 1) break; - j++; - } - } - do { - dst[j++] = (i < 8) ? ns[i++] : ' '; - } while (j < 8); -} -#endif - - - - -/*-----------------------------------------------------------------------*/ -/* Calculate sum of an SFN */ -/*-----------------------------------------------------------------------*/ -#if _USE_LFN -static -BYTE sum_sfn ( - const BYTE* dir /* Pointer to the SFN entry */ -) -{ - BYTE sum = 0; - UINT n = 11; - - do sum = (sum >> 1) + (sum << 7) + *dir++; while (--n); - return sum; -} -#endif - - - - -/*-----------------------------------------------------------------------*/ -/* Directory handling - Find an object in the directory */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT dir_find ( - DIR* dp /* Pointer to the directory object linked to the file name */ -) -{ - FRESULT res; - BYTE c, *dir; -#if _USE_LFN - BYTE a, ord, sum; -#endif - - res = dir_sdi(dp, 0); /* Rewind directory object */ - if (res != FR_OK) return res; - -#if _USE_LFN - ord = sum = 0xFF; -#endif - do { - res = move_window(dp->fs, dp->sect); - if (res != FR_OK) break; - dir = dp->dir; /* Ptr to the directory entry of current index */ - c = dir[DIR_Name]; - if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */ -#if _USE_LFN /* LFN configuration */ - a = dir[DIR_Attr] & AM_MASK; - if (c == DDE || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */ - ord = 0xFF; - } else { - if (a == AM_LFN) { /* An LFN entry is found */ - if (dp->lfn) { - if (c & LLE) { /* Is it start of LFN sequence? */ - sum = dir[LDIR_Chksum]; - c &= ~LLE; ord = c; /* LFN start order */ - dp->lfn_idx = dp->index; - } - /* Check validity of the LFN entry and compare it with given name */ - ord = (c == ord && sum == dir[LDIR_Chksum] && cmp_lfn(dp->lfn, dir)) ? ord - 1 : 0xFF; - } - } else { /* An SFN entry is found */ - if (!ord && sum == sum_sfn(dir)) break; /* LFN matched? */ - ord = 0xFF; dp->lfn_idx = 0xFFFF; /* Reset LFN sequence */ - if (!(dp->fn[NS] & NS_LOSS) && !mem_cmp(dir, dp->fn, 11)) break; /* SFN matched? */ - } - } -#else /* Non LFN configuration */ - if (!(dir[DIR_Attr] & AM_VOL) && !mem_cmp(dir, dp->fn, 11)) /* Is it a valid entry? */ - break; -#endif - res = dir_next(dp, 0); /* Next entry */ - } while (res == FR_OK); - - return res; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Read an object from the directory */ -/*-----------------------------------------------------------------------*/ -#if _FS_MINIMIZE <= 1 || _USE_LABEL || _FS_RPATH >= 2 -static -FRESULT dir_read ( - DIR* dp, /* Pointer to the directory object */ - int vol /* Filtered by 0:file/directory or 1:volume label */ -) -{ - FRESULT res; - BYTE a, c, *dir; -#if _USE_LFN - BYTE ord = 0xFF, sum = 0xFF; -#endif - - res = FR_NO_FILE; - while (dp->sect) { - res = move_window(dp->fs, dp->sect); - if (res != FR_OK) break; - dir = dp->dir; /* Ptr to the directory entry of current index */ - c = dir[DIR_Name]; - if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */ - a = dir[DIR_Attr] & AM_MASK; -#if _USE_LFN /* LFN configuration */ - if (c == DDE || (!_FS_RPATH && c == '.') || (int)(a == AM_VOL) != vol) { /* An entry without valid data */ - ord = 0xFF; - } else { - if (a == AM_LFN) { /* An LFN entry is found */ - if (c & LLE) { /* Is it start of LFN sequence? */ - sum = dir[LDIR_Chksum]; - c &= ~LLE; ord = c; - dp->lfn_idx = dp->index; - } - /* Check LFN validity and capture it */ - ord = (c == ord && sum == dir[LDIR_Chksum] && pick_lfn(dp->lfn, dir)) ? ord - 1 : 0xFF; - } else { /* An SFN entry is found */ - if (ord || sum != sum_sfn(dir)) /* Is there a valid LFN? */ - dp->lfn_idx = 0xFFFF; /* It has no LFN. */ - break; - } - } -#else /* Non LFN configuration */ - if (c != DDE && (_FS_RPATH || c != '.') && a != AM_LFN && (int)(a == AM_VOL) == vol) /* Is it a valid entry? */ - break; -#endif - res = dir_next(dp, 0); /* Next entry */ - if (res != FR_OK) break; - } - - if (res != FR_OK) dp->sect = 0; - - return res; -} -#endif /* _FS_MINIMIZE <= 1 || _USE_LABEL || _FS_RPATH >= 2 */ - - - - -/*-----------------------------------------------------------------------*/ -/* Register an object to the directory */ -/*-----------------------------------------------------------------------*/ -#if !_FS_READONLY -static -FRESULT dir_register ( /* FR_OK:Successful, FR_DENIED:No free entry or too many SFN collision, FR_DISK_ERR:Disk error */ - DIR* dp /* Target directory with object name to be created */ -) -{ - FRESULT res; -#if _USE_LFN /* LFN configuration */ - WORD n, ne; - BYTE sn[12], *fn, sum; - WCHAR *lfn; - - - fn = dp->fn; lfn = dp->lfn; - mem_cpy(sn, fn, 12); - - if (_FS_RPATH && (sn[NS] & NS_DOT)) /* Cannot create dot entry */ - return FR_INVALID_NAME; - - if (sn[NS] & NS_LOSS) { /* When LFN is out of 8.3 format, generate a numbered name */ - fn[NS] = 0; dp->lfn = 0; /* Find only SFN */ - for (n = 1; n < 100; n++) { - gen_numname(fn, sn, lfn, n); /* Generate a numbered name */ - res = dir_find(dp); /* Check if the name collides with existing SFN */ - if (res != FR_OK) break; - } - if (n == 100) return FR_DENIED; /* Abort if too many collisions */ - if (res != FR_NO_FILE) return res; /* Abort if the result is other than 'not collided' */ - fn[NS] = sn[NS]; dp->lfn = lfn; - } - - if (sn[NS] & NS_LFN) { /* When LFN is to be created, allocate entries for an SFN + LFNs. */ - for (n = 0; lfn[n]; n++) ; - ne = (n + 25) / 13; - } else { /* Otherwise allocate an entry for an SFN */ - ne = 1; - } - res = dir_alloc(dp, ne); /* Allocate entries */ - - if (res == FR_OK && --ne) { /* Set LFN entry if needed */ - res = dir_sdi(dp, (WORD)(dp->index - ne)); - if (res == FR_OK) { - sum = sum_sfn(dp->fn); /* Sum value of the SFN tied to the LFN */ - do { /* Store LFN entries in bottom first */ - res = move_window(dp->fs, dp->sect); - if (res != FR_OK) break; - fit_lfn(dp->lfn, dp->dir, (BYTE)ne, sum); - dp->fs->wflag = 1; - res = dir_next(dp, 0); /* Next entry */ - } while (res == FR_OK && --ne); - } - } -#else /* Non LFN configuration */ - res = dir_alloc(dp, 1); /* Allocate an entry for SFN */ -#endif - - if (res == FR_OK) { /* Set SFN entry */ - res = move_window(dp->fs, dp->sect); - if (res == FR_OK) { - mem_set(dp->dir, 0, SZ_DIR); /* Clean the entry */ - mem_cpy(dp->dir, dp->fn, 11); /* Put SFN */ -#if _USE_LFN - dp->dir[DIR_NTres] = dp->fn[NS] & (NS_BODY | NS_EXT); /* Put NT flag */ -#endif - dp->fs->wflag = 1; - } - } - - return res; -} -#endif /* !_FS_READONLY */ - - - - -/*-----------------------------------------------------------------------*/ -/* Remove an object from the directory */ -/*-----------------------------------------------------------------------*/ -#if !_FS_READONLY && !_FS_MINIMIZE -static -FRESULT dir_remove ( /* FR_OK: Successful, FR_DISK_ERR: A disk error */ - DIR* dp /* Directory object pointing the entry to be removed */ -) -{ - FRESULT res; -#if _USE_LFN /* LFN configuration */ - WORD i; - - i = dp->index; /* SFN index */ - res = dir_sdi(dp, (WORD)((dp->lfn_idx == 0xFFFF) ? i : dp->lfn_idx)); /* Goto the SFN or top of the LFN entries */ - if (res == FR_OK) { - do { - res = move_window(dp->fs, dp->sect); - if (res != FR_OK) break; - *dp->dir = DDE; /* Mark the entry "deleted" */ - dp->fs->wflag = 1; - if (dp->index >= i) break; /* When reached SFN, all entries of the object has been deleted. */ - res = dir_next(dp, 0); /* Next entry */ - } while (res == FR_OK); - if (res == FR_NO_FILE) res = FR_INT_ERR; - } - -#else /* Non LFN configuration */ - res = dir_sdi(dp, dp->index); - if (res == FR_OK) { - res = move_window(dp->fs, dp->sect); - if (res == FR_OK) { - *dp->dir = DDE; /* Mark the entry "deleted" */ - dp->fs->wflag = 1; - } - } -#endif - - return res; -} -#endif /* !_FS_READONLY */ - - - - -/*-----------------------------------------------------------------------*/ -/* Pick a segment and create the object name in directory form */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT create_name ( - DIR* dp, /* Pointer to the directory object */ - const TCHAR** path /* Pointer to pointer to the segment in the path string */ -) -{ -#if _USE_LFN /* LFN configuration */ - BYTE b, cf; - WCHAR w, *lfn; - UINT i, ni, si, di; - const TCHAR *p; - - /* Create LFN in Unicode */ - for (p = *path; *p == '/' || *p == '\\'; p++) ; /* Strip duplicated separator */ - lfn = dp->lfn; - si = di = 0; - for (;;) { - w = p[si++]; /* Get a character */ - if (w < ' ' || w == '/' || w == '\\') break; /* Break on end of segment */ - if (di >= _MAX_LFN) /* Reject too long name */ - return FR_INVALID_NAME; -#if !_LFN_UNICODE - w &= 0xFF; - if (IsDBCS1(w)) { /* Check if it is a DBC 1st byte (always false on SBCS cfg) */ - b = (BYTE)p[si++]; /* Get 2nd byte */ - if (!IsDBCS2(b)) - return FR_INVALID_NAME; /* Reject invalid sequence */ - w = (w << 8) + b; /* Create a DBC */ - } - w = ff_convert(w, 1); /* Convert ANSI/OEM to Unicode */ - if (!w) return FR_INVALID_NAME; /* Reject invalid code */ -#endif - if (w < 0x80 && chk_chr("\"*:<>\?|\x7F", w)) /* Reject illegal characters for LFN */ - return FR_INVALID_NAME; - lfn[di++] = w; /* Store the Unicode character */ - } - *path = &p[si]; /* Return pointer to the next segment */ - cf = (w < ' ') ? NS_LAST : 0; /* Set last segment flag if end of path */ -#if _FS_RPATH - if ((di == 1 && lfn[di-1] == '.') || /* Is this a dot entry? */ - (di == 2 && lfn[di-1] == '.' && lfn[di-2] == '.')) { - lfn[di] = 0; - for (i = 0; i < 11; i++) - dp->fn[i] = (i < di) ? '.' : ' '; - dp->fn[i] = cf | NS_DOT; /* This is a dot entry */ - return FR_OK; - } -#endif - while (di) { /* Strip trailing spaces and dots */ - w = lfn[di-1]; - if (w != ' ' && w != '.') break; - di--; - } - if (!di) return FR_INVALID_NAME; /* Reject nul string */ - - lfn[di] = 0; /* LFN is created */ - - /* Create SFN in directory form */ - mem_set(dp->fn, ' ', 11); - for (si = 0; lfn[si] == ' ' || lfn[si] == '.'; si++) ; /* Strip leading spaces and dots */ - if (si) cf |= NS_LOSS | NS_LFN; - while (di && lfn[di - 1] != '.') di--; /* Find extension (di<=si: no extension) */ - - b = i = 0; ni = 8; - for (;;) { - w = lfn[si++]; /* Get an LFN character */ - if (!w) break; /* Break on end of the LFN */ - if (w == ' ' || (w == '.' && si != di)) { /* Remove spaces and dots */ - cf |= NS_LOSS | NS_LFN; continue; - } - - if (i >= ni || si == di) { /* Extension or end of SFN */ - if (ni == 11) { /* Long extension */ - cf |= NS_LOSS | NS_LFN; break; - } - if (si != di) cf |= NS_LOSS | NS_LFN; /* Out of 8.3 format */ - if (si > di) break; /* No extension */ - si = di; i = 8; ni = 11; /* Enter extension section */ - b <<= 2; continue; - } - - if (w >= 0x80) { /* Non ASCII character */ -#ifdef _EXCVT - w = ff_convert(w, 0); /* Unicode -> OEM code */ - if (w) w = ExCvt[w - 0x80]; /* Convert extended character to upper (SBCS) */ -#else - w = ff_convert(ff_wtoupper(w), 0); /* Upper converted Unicode -> OEM code */ -#endif - cf |= NS_LFN; /* Force create LFN entry */ - } - - if (_DF1S && w >= 0x100) { /* Double byte character (always false on SBCS cfg) */ - if (i >= ni - 1) { - cf |= NS_LOSS | NS_LFN; i = ni; continue; - } - dp->fn[i++] = (BYTE)(w >> 8); - } else { /* Single byte character */ - if (!w || chk_chr("+,;=[]", w)) { /* Replace illegal characters for SFN */ - w = '_'; cf |= NS_LOSS | NS_LFN;/* Lossy conversion */ - } else { - if (IsUpper(w)) { /* ASCII large capital */ - b |= 2; - } else { - if (IsLower(w)) { /* ASCII small capital */ - b |= 1; w -= 0x20; - } - } - } - } - dp->fn[i++] = (BYTE)w; - } - - if (dp->fn[0] == DDE) dp->fn[0] = NDDE; /* If the first character collides with deleted mark, replace it with 0x05 */ - - if (ni == 8) b <<= 2; - if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03) /* Create LFN entry when there are composite capitals */ - cf |= NS_LFN; - if (!(cf & NS_LFN)) { /* When LFN is in 8.3 format without extended character, NT flags are created */ - if ((b & 0x03) == 0x01) cf |= NS_EXT; /* NT flag (Extension has only small capital) */ - if ((b & 0x0C) == 0x04) cf |= NS_BODY; /* NT flag (Filename has only small capital) */ - } - - dp->fn[NS] = cf; /* SFN is created */ - - return FR_OK; - - -#else /* Non-LFN configuration */ - BYTE b, c, d, *sfn; - UINT ni, si, i; - const char *p; - - /* Create file name in directory form */ - for (p = *path; *p == '/' || *p == '\\'; p++) ; /* Strip duplicated separator */ - sfn = dp->fn; - mem_set(sfn, ' ', 11); - si = i = b = 0; ni = 8; -#if _FS_RPATH - if (p[si] == '.') { /* Is this a dot entry? */ - for (;;) { - c = (BYTE)p[si++]; - if (c != '.' || si >= 3) break; - sfn[i++] = c; - } - if (c != '/' && c != '\\' && c > ' ') return FR_INVALID_NAME; - *path = &p[si]; /* Return pointer to the next segment */ - sfn[NS] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT; /* Set last segment flag if end of path */ - return FR_OK; - } -#endif - for (;;) { - c = (BYTE)p[si++]; - if (c <= ' ' || c == '/' || c == '\\') break; /* Break on end of segment */ - if (c == '.' || i >= ni) { - if (ni != 8 || c != '.') return FR_INVALID_NAME; - i = 8; ni = 11; - b <<= 2; continue; - } - if (c >= 0x80) { /* Extended character? */ - b |= 3; /* Eliminate NT flag */ -#ifdef _EXCVT - c = ExCvt[c - 0x80]; /* To upper extended characters (SBCS cfg) */ -#else -#if !_DF1S - return FR_INVALID_NAME; /* Reject extended characters (ASCII cfg) */ -#endif -#endif - } - if (IsDBCS1(c)) { /* Check if it is a DBC 1st byte (always false on SBCS cfg) */ - d = (BYTE)p[si++]; /* Get 2nd byte */ - if (!IsDBCS2(d) || i >= ni - 1) /* Reject invalid DBC */ - return FR_INVALID_NAME; - sfn[i++] = c; - sfn[i++] = d; - } else { /* Single byte code */ - if (chk_chr("\"*+,:;<=>\?[]|\x7F", c)) /* Reject illegal chrs for SFN */ - return FR_INVALID_NAME; - if (IsUpper(c)) { /* ASCII large capital? */ - b |= 2; - } else { - if (IsLower(c)) { /* ASCII small capital? */ - b |= 1; c -= 0x20; - } - } - sfn[i++] = c; - } - } - *path = &p[si]; /* Return pointer to the next segment */ - c = (c <= ' ') ? NS_LAST : 0; /* Set last segment flag if end of path */ - - if (!i) return FR_INVALID_NAME; /* Reject nul string */ - if (sfn[0] == DDE) sfn[0] = NDDE; /* When first character collides with DDE, replace it with 0x05 */ - - if (ni == 8) b <<= 2; - if ((b & 0x03) == 0x01) c |= NS_EXT; /* NT flag (Name extension has only small capital) */ - if ((b & 0x0C) == 0x04) c |= NS_BODY; /* NT flag (Name body has only small capital) */ - - sfn[NS] = c; /* Store NT flag, File name is created */ - - return FR_OK; -#endif -} - - - - -/*-----------------------------------------------------------------------*/ -/* Get file information from directory entry */ -/*-----------------------------------------------------------------------*/ -#if _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 -static -void get_fileinfo ( /* No return code */ - DIR* dp, /* Pointer to the directory object */ - FILINFO* fno /* Pointer to the file information to be filled */ -) -{ - UINT i; - TCHAR *p, c; - - - p = fno->fname; - if (dp->sect) { /* Get SFN */ - BYTE *dir = dp->dir; - - i = 0; - while (i < 11) { /* Copy name body and extension */ - c = (TCHAR)dir[i++]; - if (c == ' ') continue; /* Skip padding spaces */ - if (c == NDDE) c = (TCHAR)DDE; /* Restore replaced DDE character */ - if (i == 9) *p++ = '.'; /* Insert a . if extension is exist */ -#if _USE_LFN - if (IsUpper(c) && (dir[DIR_NTres] & (i >= 9 ? NS_EXT : NS_BODY))) - c += 0x20; /* To lower */ -#if _LFN_UNICODE - if (IsDBCS1(c) && i != 8 && i != 11 && IsDBCS2(dir[i])) - c = c << 8 | dir[i++]; - c = ff_convert(c, 1); /* OEM -> Unicode */ - if (!c) c = '?'; -#endif -#endif - *p++ = c; - } - fno->fattrib = dir[DIR_Attr]; /* Attribute */ - fno->fsize = LD_DWORD(dir+DIR_FileSize); /* Size */ - fno->fdate = LD_WORD(dir+DIR_WrtDate); /* Date */ - fno->ftime = LD_WORD(dir+DIR_WrtTime); /* Time */ - } - *p = 0; /* Terminate SFN string by a \0 */ - -#if _USE_LFN - if (fno->lfname) { - WCHAR w, *lfn; - - i = 0; p = fno->lfname; - if (dp->sect && fno->lfsize && dp->lfn_idx != 0xFFFF) { /* Get LFN if available */ - lfn = dp->lfn; - while ((w = *lfn++) != 0) { /* Get an LFN character */ -#if !_LFN_UNICODE - w = ff_convert(w, 0); /* Unicode -> OEM */ - if (!w) { i = 0; break; } /* No LFN if it could not be converted */ - if (_DF1S && w >= 0x100) /* Put 1st byte if it is a DBC (always false on SBCS cfg) */ - p[i++] = (TCHAR)(w >> 8); -#endif - if (i >= fno->lfsize - 1) { i = 0; break; } /* No LFN if buffer overflow */ - p[i++] = (TCHAR)w; - } - } - p[i] = 0; /* Terminate LFN string by a \0 */ - } -#endif -} -#endif /* _FS_MINIMIZE <= 1 || _FS_RPATH >= 2*/ - - - - -/*-----------------------------------------------------------------------*/ -/* Get logical drive number from path name */ -/*-----------------------------------------------------------------------*/ - -static -int get_ldnumber ( /* Returns logical drive number (-1:invalid drive) */ - const TCHAR** path /* Pointer to pointer to the path name */ -) -{ - int vol = -1; - - - if (*path) { - vol = (*path)[0] - '0'; - if ((UINT)vol < 9 && (*path)[1] == ':') { /* There is a drive number */ - *path += 2; /* Get value and strip it */ - if (vol >= _VOLUMES) vol = -1; /* Check if the drive number is valid */ - } else { /* No drive number use default drive */ -#if _FS_RPATH && _VOLUMES >= 2 - vol = CurrVol; /* Current drive */ -#else - vol = 0; /* Drive 0 */ -#endif - } - } - - return vol; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Follow a file path */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT follow_path ( /* FR_OK(0): successful, !=0: error code */ - DIR* dp, /* Directory object to return last directory and found object */ - const TCHAR* path /* Full-path string to find a file or directory */ -) -{ - FRESULT res; - BYTE *dir, ns; - - -#if _FS_RPATH - if (*path == '/' || *path == '\\') { /* There is a heading separator */ - path++; dp->sclust = 0; /* Strip it and start from the root directory */ - } else { /* No heading separator */ - dp->sclust = dp->fs->cdir; /* Start from the current directory */ - } -#else - if (*path == '/' || *path == '\\') /* Strip heading separator if exist */ - path++; - dp->sclust = 0; /* Always start from the root directory */ -#endif - - if ((UINT)*path < ' ') { /* Null path name is the origin directory itself */ - res = dir_sdi(dp, 0); - dp->dir = 0; - } else { /* Follow path */ - for (;;) { - res = create_name(dp, &path); /* Get a segment name of the path */ - if (res != FR_OK) break; - res = dir_find(dp); /* Find an object with the sagment name */ - ns = dp->fn[NS]; - if (res != FR_OK) { /* Failed to find the object */ - if (res == FR_NO_FILE) { /* Object is not found */ - if (_FS_RPATH && (ns & NS_DOT)) { /* If dot entry is not exist, */ - dp->sclust = 0; dp->dir = 0; /* it is the root directory and stay there */ - if (!(ns & NS_LAST)) continue; /* Continue to follow if not last segment */ - res = FR_OK; /* Ended at the root directroy. Function completed. */ - } else { /* Could not find the object */ - if (!(ns & NS_LAST)) res = FR_NO_PATH; /* Adjust error code if not last segment */ - } - } - break; - } - if (ns & NS_LAST) break; /* Last segment matched. Function completed. */ - dir = dp->dir; /* Follow the sub-directory */ - if (!(dir[DIR_Attr] & AM_DIR)) { /* It is not a sub-directory and cannot follow */ - res = FR_NO_PATH; break; - } - dp->sclust = ld_clust(dp->fs, dir); - } - } - - return res; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Load a sector and check if it is an FAT boot sector */ -/*-----------------------------------------------------------------------*/ - -static -BYTE check_fs ( /* 0:FAT boor sector, 1:Valid boor sector but not FAT, 2:Not a boot sector, 3:Disk error */ - FATFS* fs, /* File system object */ - DWORD sect /* Sector# (lba) to check if it is an FAT boot record or not */ -) -{ - fs->wflag = 0; fs->winsect = 0xFFFFFFFF; /* Invaidate window */ - if (move_window(fs, sect) != FR_OK) /* Load boot record */ - return 3; - - if (LD_WORD(&fs->win[BS_55AA]) != 0xAA55) /* Check boot record signature (always placed at offset 510 even if the sector size is >512) */ - return 2; - - if ((LD_DWORD(&fs->win[BS_FilSysType]) & 0xFFFFFF) == 0x544146) /* Check "FAT" string */ - return 0; - if ((LD_DWORD(&fs->win[BS_FilSysType32]) & 0xFFFFFF) == 0x544146) /* Check "FAT" string */ - return 0; - - return 1; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Find logical drive and check if the volume is mounted */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT find_volume ( /* FR_OK(0): successful, !=0: any error occurred */ - FATFS** rfs, /* Pointer to pointer to the found file system object */ - const TCHAR** path, /* Pointer to pointer to the path name (drive number) */ - BYTE wmode /* !=0: Check write protection for write access */ -) -{ - BYTE fmt; - int vol; - DSTATUS stat; - DWORD bsect, fasize, tsect, sysect, nclst, szbfat; - WORD nrsv; - FATFS *fs; - - - /* Get logical drive number from the path name */ - *rfs = 0; - vol = get_ldnumber(path); - if (vol < 0) return FR_INVALID_DRIVE; - - /* Check if the file system object is valid or not */ - fs = FatFs[vol]; /* Get pointer to the file system object */ - if (!fs) return FR_NOT_ENABLED; /* Is the file system object available? */ - - ENTER_FF(fs); /* Lock the volume */ - *rfs = fs; /* Return pointer to the file system object */ - - if (fs->fs_type) { /* If the volume has been mounted */ - stat = disk_status(fs->drv); - if (!(stat & STA_NOINIT)) { /* and the physical drive is kept initialized */ - if (!_FS_READONLY && wmode && (stat & STA_PROTECT)) /* Check write protection if needed */ - return FR_WRITE_PROTECTED; - return FR_OK; /* The file system object is valid */ - } - } - - /* The file system object is not valid. */ - /* Following code attempts to mount the volume. (analyze BPB and initialize the fs object) */ - - fs->fs_type = 0; /* Clear the file system object */ - fs->drv = LD2PD(vol); /* Bind the logical drive and a physical drive */ - stat = disk_initialize(fs->drv); /* Initialize the physical drive */ - if (stat & STA_NOINIT) /* Check if the initialization succeeded */ - return FR_NOT_READY; /* Failed to initialize due to no medium or hard error */ - if (!_FS_READONLY && wmode && (stat & STA_PROTECT)) /* Check disk write protection if needed */ - return FR_WRITE_PROTECTED; -#if _MAX_SS != 512 /* Get sector size (variable sector size cfg only) */ - if (disk_ioctl(fs->drv, GET_SECTOR_SIZE, &fs->ssize) != RES_OK) - return FR_DISK_ERR; -#endif - /* Find an FAT partition on the drive. Supports only generic partitioning, FDISK and SFD. */ - bsect = 0; - fmt = check_fs(fs, bsect); /* Load sector 0 and check if it is an FAT boot sector as SFD */ - if (fmt == 1 || (!fmt && (LD2PT(vol)))) { /* Not an FAT boot sector or forced partition number */ - UINT i; - DWORD br[4]; - - for (i = 0; i < 4; i++) { /* Get partition offset */ - BYTE *pt = fs->win+MBR_Table + i * SZ_PTE; - br[i] = pt[4] ? LD_DWORD(&pt[8]) : 0; - } - i = LD2PT(vol); /* Partition number: 0:auto, 1-4:forced */ - if (i) i--; - do { /* Find an FAT volume */ - bsect = br[i]; - fmt = bsect ? check_fs(fs, bsect) : 2; /* Check the partition */ - } while (!LD2PT(vol) && fmt && ++i < 4); - } - if (fmt == 3) return FR_DISK_ERR; /* An error occured in the disk I/O layer */ - if (fmt) return FR_NO_FILESYSTEM; /* No FAT volume is found */ - - /* An FAT volume is found. Following code initializes the file system object */ - - if (LD_WORD(fs->win+BPB_BytsPerSec) != SS(fs)) /* (BPB_BytsPerSec must be equal to the physical sector size) */ - return FR_NO_FILESYSTEM; - - fasize = LD_WORD(fs->win+BPB_FATSz16); /* Number of sectors per FAT */ - if (!fasize) fasize = LD_DWORD(fs->win+BPB_FATSz32); - fs->fsize = fasize; - - fs->n_fats = fs->win[BPB_NumFATs]; /* Number of FAT copies */ - if (fs->n_fats != 1 && fs->n_fats != 2) /* (Must be 1 or 2) */ - return FR_NO_FILESYSTEM; - fasize *= fs->n_fats; /* Number of sectors for FAT area */ - - fs->csize = fs->win[BPB_SecPerClus]; /* Number of sectors per cluster */ - if (!fs->csize || (fs->csize & (fs->csize - 1))) /* (Must be power of 2) */ - return FR_NO_FILESYSTEM; - - fs->n_rootdir = LD_WORD(fs->win+BPB_RootEntCnt); /* Number of root directory entries */ - if (fs->n_rootdir % (SS(fs) / SZ_DIR)) /* (Must be sector aligned) */ - return FR_NO_FILESYSTEM; - - tsect = LD_WORD(fs->win+BPB_TotSec16); /* Number of sectors on the volume */ - if (!tsect) tsect = LD_DWORD(fs->win+BPB_TotSec32); - - nrsv = LD_WORD(fs->win+BPB_RsvdSecCnt); /* Number of reserved sectors */ - if (!nrsv) return FR_NO_FILESYSTEM; /* (Must not be 0) */ - - /* Determine the FAT sub type */ - sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / SZ_DIR); /* RSV+FAT+DIR */ - if (tsect < sysect) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ - nclst = (tsect - sysect) / fs->csize; /* Number of clusters */ - if (!nclst) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ - fmt = FS_FAT12; - if (nclst >= MIN_FAT16) fmt = FS_FAT16; - if (nclst >= MIN_FAT32) fmt = FS_FAT32; - - /* Boundaries and Limits */ - fs->n_fatent = nclst + 2; /* Number of FAT entries */ - fs->volbase = bsect; /* Volume start sector */ - fs->fatbase = bsect + nrsv; /* FAT start sector */ - fs->database = bsect + sysect; /* Data start sector */ - if (fmt == FS_FAT32) { - if (fs->n_rootdir) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be 0) */ - fs->dirbase = LD_DWORD(fs->win+BPB_RootClus); /* Root directory start cluster */ - szbfat = fs->n_fatent * 4; /* (Required FAT size) */ - } else { - if (!fs->n_rootdir) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must not be 0) */ - fs->dirbase = fs->fatbase + fasize; /* Root directory start sector */ - szbfat = (fmt == FS_FAT16) ? /* (Required FAT size) */ - fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1); - } - if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs)) /* (BPB_FATSz must not be less than required) */ - return FR_NO_FILESYSTEM; - -#if !_FS_READONLY - /* Initialize cluster allocation information */ - fs->last_clust = fs->free_clust = 0xFFFFFFFF; - - /* Get fsinfo if available */ - fs->fsi_flag = 0x80; - if (fmt == FS_FAT32 /* Enable FSINFO only if FAT32 and BPB_FSInfo is 1 */ - && LD_WORD(fs->win+BPB_FSInfo) == 1 - && move_window(fs, bsect + 1) == FR_OK) - { - fs->fsi_flag = 0; - if (LD_WORD(fs->win+BS_55AA) == 0xAA55 /* Load FSINFO data if available */ - && LD_DWORD(fs->win+FSI_LeadSig) == 0x41615252 - && LD_DWORD(fs->win+FSI_StrucSig) == 0x61417272) - { -#if !_FS_NOFSINFO - fs->free_clust = LD_DWORD(fs->win+FSI_Free_Count); -#endif - fs->last_clust = LD_DWORD(fs->win+FSI_Nxt_Free); - } - } -#endif - fs->fs_type = fmt; /* FAT sub-type */ - fs->id = ++Fsid; /* File system mount ID */ -#if _FS_RPATH - fs->cdir = 0; /* Current directory (root dir) */ -#endif -#if _FS_LOCK /* Clear file lock semaphores */ - clear_lock(fs); -#endif - - return FR_OK; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Check if the file/directory object is valid or not */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT validate ( /* FR_OK(0): The object is valid, !=0: Invalid */ - void* obj /* Pointer to the object FIL/DIR to check validity */ -) -{ - FIL *fil = (FIL*)obj; /* Assuming offset of .fs and .id in the FIL/DIR structure is identical */ - - - if (!fil || !fil->fs || !fil->fs->fs_type || fil->fs->id != fil->id) - return FR_INVALID_OBJECT; - - ENTER_FF(fil->fs); /* Lock file system */ - - if (disk_status(fil->fs->drv) & STA_NOINIT) - return FR_NOT_READY; - - return FR_OK; -} - - - - -/*-------------------------------------------------------------------------- - - Public Functions - ---------------------------------------------------------------------------*/ - - - -/*-----------------------------------------------------------------------*/ -/* Mount/Unmount a Logical Drive */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_mount ( - FATFS* fs, /* Pointer to the file system object (NULL:unmount)*/ - const TCHAR* path, /* Logical drive number to be mounted/unmounted */ - BYTE opt /* 0:Do not mount (delayed mount), 1:Mount immediately */ -) -{ - FATFS *cfs; - int vol; - FRESULT res; - - - vol = get_ldnumber(&path); - if (vol < 0) return FR_INVALID_DRIVE; - cfs = FatFs[vol]; /* Pointer to fs object */ - - if (cfs) { -#if _FS_LOCK - clear_lock(cfs); -#endif -#if _FS_REENTRANT /* Discard sync object of the current volume */ - if (!ff_del_syncobj(cfs->sobj)) return FR_INT_ERR; -#endif - cfs->fs_type = 0; /* Clear old fs object */ - } - - if (fs) { - fs->fs_type = 0; /* Clear new fs object */ -#if _FS_REENTRANT /* Create sync object for the new volume */ - if (!ff_cre_syncobj(vol, &fs->sobj)) return FR_INT_ERR; -#endif - } - FatFs[vol] = fs; /* Register new fs object */ - - if (!fs || opt != 1) return FR_OK; /* Do not mount now, it will be mounted later */ - - res = find_volume(&fs, &path, 0); /* Force mounted the volume */ - LEAVE_FF(fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Open or Create a File */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_open ( - FIL* fp, /* Pointer to the blank file object */ - const TCHAR* path, /* Pointer to the file name */ - BYTE mode /* Access mode and file open mode flags */ -) -{ - FRESULT res; - DIR dj; - BYTE *dir; - DEF_NAMEBUF; - - - if (!fp) return FR_INVALID_OBJECT; - fp->fs = 0; /* Clear file object */ - - /* Get logical drive number */ -#if !_FS_READONLY - mode &= FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW; - res = find_volume(&dj.fs, &path, (BYTE)(mode & ~FA_READ)); -#else - mode &= FA_READ; - res = find_volume(&dj.fs, &path, 0); -#endif - if (res == FR_OK) { - INIT_BUF(dj); - res = follow_path(&dj, path); /* Follow the file path */ - dir = dj.dir; -#if !_FS_READONLY /* R/W configuration */ - if (res == FR_OK) { - if (!dir) /* Default directory itself */ - res = FR_INVALID_NAME; -#if _FS_LOCK - else - res = chk_lock(&dj, (mode & ~FA_READ) ? 1 : 0); -#endif - } - /* Create or Open a file */ - if (mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) { - DWORD dw, cl; - - if (res != FR_OK) { /* No file, create new */ - if (res == FR_NO_FILE) /* There is no file to open, create a new entry */ -#if _FS_LOCK - res = enq_lock() ? dir_register(&dj) : FR_TOO_MANY_OPEN_FILES; -#else - res = dir_register(&dj); -#endif - mode |= FA_CREATE_ALWAYS; /* File is created */ - dir = dj.dir; /* New entry */ - } - else { /* Any object is already existing */ - if (dir[DIR_Attr] & (AM_RDO | AM_DIR)) { /* Cannot overwrite it (R/O or DIR) */ - res = FR_DENIED; - } else { - if (mode & FA_CREATE_NEW) /* Cannot create as new file */ - res = FR_EXIST; - } - } - if (res == FR_OK && (mode & FA_CREATE_ALWAYS)) { /* Truncate it if overwrite mode */ - dw = get_fattime(); /* Created time */ - ST_DWORD(dir+DIR_CrtTime, dw); - dir[DIR_Attr] = 0; /* Reset attribute */ - ST_DWORD(dir+DIR_FileSize, 0); /* size = 0 */ - cl = ld_clust(dj.fs, dir); /* Get start cluster */ - st_clust(dir, 0); /* cluster = 0 */ - dj.fs->wflag = 1; - if (cl) { /* Remove the cluster chain if exist */ - dw = dj.fs->winsect; - res = remove_chain(dj.fs, cl); - if (res == FR_OK) { - dj.fs->last_clust = cl - 1; /* Reuse the cluster hole */ - res = move_window(dj.fs, dw); - } - } - } - } - else { /* Open an existing file */ - if (res == FR_OK) { /* Follow succeeded */ - if (dir[DIR_Attr] & AM_DIR) { /* It is a directory */ - res = FR_NO_FILE; - } else { - if ((mode & FA_WRITE) && (dir[DIR_Attr] & AM_RDO)) /* R/O violation */ - res = FR_DENIED; - } - } - } - if (res == FR_OK) { - if (mode & FA_CREATE_ALWAYS) /* Set file change flag if created or overwritten */ - mode |= FA__WRITTEN; - fp->dir_sect = dj.fs->winsect; /* Pointer to the directory entry */ - fp->dir_ptr = dir; -#if _FS_LOCK - fp->lockid = inc_lock(&dj, (mode & ~FA_READ) ? 1 : 0); - if (!fp->lockid) res = FR_INT_ERR; -#endif - } - -#else /* R/O configuration */ - if (res == FR_OK) { /* Follow succeeded */ - dir = dj.dir; - if (!dir) { /* Current directory itself */ - res = FR_INVALID_NAME; - } else { - if (dir[DIR_Attr] & AM_DIR) /* It is a directory */ - res = FR_NO_FILE; - } - } -#endif - FREE_BUF(); - - if (res == FR_OK) { - fp->flag = mode; /* File access mode */ - fp->err = 0; /* Clear error flag */ - fp->sclust = ld_clust(dj.fs, dir); /* File start cluster */ - fp->fsize = LD_DWORD(dir+DIR_FileSize); /* File size */ - fp->fptr = 0; /* File pointer */ - fp->dsect = 0; -#if _USE_FASTSEEK - fp->cltbl = 0; /* Normal seek mode */ -#endif - fp->fs = dj.fs; /* Validate file object */ - fp->id = fp->fs->id; - } - } - - LEAVE_FF(dj.fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Read File */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_read ( - FIL* fp, /* Pointer to the file object */ - void* buff, /* Pointer to data buffer */ - UINT btr, /* Number of bytes to read */ - UINT* br /* Pointer to number of bytes read */ -) -{ - FRESULT res; - DWORD clst, sect, remain; - UINT rcnt, cc; - BYTE csect, *rbuff = (BYTE*)buff; - - - *br = 0; /* Clear read byte counter */ - - res = validate(fp); /* Check validity */ - if (res != FR_OK) LEAVE_FF(fp->fs, res); - if (fp->err) /* Check error */ - LEAVE_FF(fp->fs, (FRESULT)fp->err); - if (!(fp->flag & FA_READ)) /* Check access mode */ - LEAVE_FF(fp->fs, FR_DENIED); - remain = fp->fsize - fp->fptr; - if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */ - - for ( ; btr; /* Repeat until all data read */ - rbuff += rcnt, fp->fptr += rcnt, *br += rcnt, btr -= rcnt) { - if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ - csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */ - if (!csect) { /* On the cluster boundary? */ - if (fp->fptr == 0) { /* On the top of the file? */ - clst = fp->sclust; /* Follow from the origin */ - } else { /* Middle or end of the file */ -#if _USE_FASTSEEK - if (fp->cltbl) - clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */ - else -#endif - clst = get_fat(fp->fs, fp->clust); /* Follow cluster chain on the FAT */ - } - if (clst < 2) ABORT(fp->fs, FR_INT_ERR); - if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); - fp->clust = clst; /* Update current cluster */ - } - sect = clust2sect(fp->fs, fp->clust); /* Get current sector */ - if (!sect) ABORT(fp->fs, FR_INT_ERR); - sect += csect; - cc = btr / SS(fp->fs); /* When remaining bytes >= sector size, */ - if (cc) { /* Read maximum contiguous sectors directly */ - if (csect + cc > fp->fs->csize) /* Clip at cluster boundary */ - cc = fp->fs->csize - csect; - if (disk_read(fp->fs->drv, rbuff, sect, cc)) - ABORT(fp->fs, FR_DISK_ERR); -#if !_FS_READONLY && _FS_MINIMIZE <= 2 /* Replace one of the read sectors with cached data if it contains a dirty sector */ -#if _FS_TINY - if (fp->fs->wflag && fp->fs->winsect - sect < cc) - mem_cpy(rbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), fp->fs->win, SS(fp->fs)); -#else - if ((fp->flag & FA__DIRTY) && fp->dsect - sect < cc) - mem_cpy(rbuff + ((fp->dsect - sect) * SS(fp->fs)), fp->buf, SS(fp->fs)); -#endif -#endif - rcnt = SS(fp->fs) * cc; /* Number of bytes transferred */ - continue; - } -#if !_FS_TINY - if (fp->dsect != sect) { /* Load data sector if not in cache */ -#if !_FS_READONLY - if (fp->flag & FA__DIRTY) { /* Write-back dirty sector cache */ - if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1)) - ABORT(fp->fs, FR_DISK_ERR); - fp->flag &= ~FA__DIRTY; - } -#endif - if (disk_read(fp->fs->drv, fp->buf, sect, 1)) /* Fill sector cache */ - ABORT(fp->fs, FR_DISK_ERR); - } -#endif - fp->dsect = sect; - } - rcnt = SS(fp->fs) - ((UINT)fp->fptr % SS(fp->fs)); /* Get partial sector data from sector buffer */ - if (rcnt > btr) rcnt = btr; -#if _FS_TINY - if (move_window(fp->fs, fp->dsect)) /* Move sector window */ - ABORT(fp->fs, FR_DISK_ERR); - mem_cpy(rbuff, &fp->fs->win[fp->fptr % SS(fp->fs)], rcnt); /* Pick partial sector */ -#else - mem_cpy(rbuff, &fp->buf[fp->fptr % SS(fp->fs)], rcnt); /* Pick partial sector */ -#endif - } - - LEAVE_FF(fp->fs, FR_OK); -} - - - - -#if !_FS_READONLY -/*-----------------------------------------------------------------------*/ -/* Write File */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_write ( - FIL* fp, /* Pointer to the file object */ - const void *buff, /* Pointer to the data to be written */ - UINT btw, /* Number of bytes to write */ - UINT* bw /* Pointer to number of bytes written */ -) -{ - FRESULT res; - DWORD clst, sect; - UINT wcnt, cc; - const BYTE *wbuff = (const BYTE*)buff; - BYTE csect; - - - *bw = 0; /* Clear write byte counter */ - - res = validate(fp); /* Check validity */ - if (res != FR_OK) LEAVE_FF(fp->fs, res); - if (fp->err) /* Check error */ - LEAVE_FF(fp->fs, (FRESULT)fp->err); - if (!(fp->flag & FA_WRITE)) /* Check access mode */ - LEAVE_FF(fp->fs, FR_DENIED); - if (fp->fptr + btw < fp->fptr) btw = 0; /* File size cannot reach 4GB */ - - for ( ; btw; /* Repeat until all data written */ - wbuff += wcnt, fp->fptr += wcnt, *bw += wcnt, btw -= wcnt) { - if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ - csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */ - if (!csect) { /* On the cluster boundary? */ - if (fp->fptr == 0) { /* On the top of the file? */ - clst = fp->sclust; /* Follow from the origin */ - if (clst == 0) /* When no cluster is allocated, */ - fp->sclust = clst = create_chain(fp->fs, 0); /* Create a new cluster chain */ - } else { /* Middle or end of the file */ -#if _USE_FASTSEEK - if (fp->cltbl) - clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */ - else -#endif - clst = create_chain(fp->fs, fp->clust); /* Follow or stretch cluster chain on the FAT */ - } - if (clst == 0) break; /* Could not allocate a new cluster (disk full) */ - if (clst == 1) ABORT(fp->fs, FR_INT_ERR); - if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); - fp->clust = clst; /* Update current cluster */ - } -#if _FS_TINY - if (fp->fs->winsect == fp->dsect && sync_window(fp->fs)) /* Write-back sector cache */ - ABORT(fp->fs, FR_DISK_ERR); -#else - if (fp->flag & FA__DIRTY) { /* Write-back sector cache */ - if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1)) - ABORT(fp->fs, FR_DISK_ERR); - fp->flag &= ~FA__DIRTY; - } -#endif - sect = clust2sect(fp->fs, fp->clust); /* Get current sector */ - if (!sect) ABORT(fp->fs, FR_INT_ERR); - sect += csect; - cc = btw / SS(fp->fs); /* When remaining bytes >= sector size, */ - if (cc) { /* Write maximum contiguous sectors directly */ - if (csect + cc > fp->fs->csize) /* Clip at cluster boundary */ - cc = fp->fs->csize - csect; - if (disk_write(fp->fs->drv, wbuff, sect, cc)) - ABORT(fp->fs, FR_DISK_ERR); -#if _FS_MINIMIZE <= 2 -#if _FS_TINY - if (fp->fs->winsect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */ - mem_cpy(fp->fs->win, wbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), SS(fp->fs)); - fp->fs->wflag = 0; - } -#else - if (fp->dsect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */ - mem_cpy(fp->buf, wbuff + ((fp->dsect - sect) * SS(fp->fs)), SS(fp->fs)); - fp->flag &= ~FA__DIRTY; - } -#endif -#endif - wcnt = SS(fp->fs) * cc; /* Number of bytes transferred */ - continue; - } -#if _FS_TINY - if (fp->fptr >= fp->fsize) { /* Avoid silly cache filling at growing edge */ - if (sync_window(fp->fs)) ABORT(fp->fs, FR_DISK_ERR); - fp->fs->winsect = sect; - } -#else - if (fp->dsect != sect) { /* Fill sector cache with file data */ - if (fp->fptr < fp->fsize && - disk_read(fp->fs->drv, fp->buf, sect, 1)) - ABORT(fp->fs, FR_DISK_ERR); - } -#endif - fp->dsect = sect; - } - wcnt = SS(fp->fs) - ((UINT)fp->fptr % SS(fp->fs));/* Put partial sector into file I/O buffer */ - if (wcnt > btw) wcnt = btw; -#if _FS_TINY - if (move_window(fp->fs, fp->dsect)) /* Move sector window */ - ABORT(fp->fs, FR_DISK_ERR); - mem_cpy(&fp->fs->win[fp->fptr % SS(fp->fs)], wbuff, wcnt); /* Fit partial sector */ - fp->fs->wflag = 1; -#else - mem_cpy(&fp->buf[fp->fptr % SS(fp->fs)], wbuff, wcnt); /* Fit partial sector */ - fp->flag |= FA__DIRTY; -#endif - } - - if (fp->fptr > fp->fsize) fp->fsize = fp->fptr; /* Update file size if needed */ - fp->flag |= FA__WRITTEN; /* Set file change flag */ - - LEAVE_FF(fp->fs, FR_OK); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Synchronize the File */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_sync ( - FIL* fp /* Pointer to the file object */ -) -{ - FRESULT res; - DWORD tm; - BYTE *dir; - - - res = validate(fp); /* Check validity of the object */ - if (res == FR_OK) { - if (fp->flag & FA__WRITTEN) { /* Has the file been written? */ - /* Write-back dirty buffer */ -#if !_FS_TINY - if (fp->flag & FA__DIRTY) { - if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1)) - LEAVE_FF(fp->fs, FR_DISK_ERR); - fp->flag &= ~FA__DIRTY; - } -#endif - /* Update the directory entry */ - res = move_window(fp->fs, fp->dir_sect); - if (res == FR_OK) { - dir = fp->dir_ptr; - dir[DIR_Attr] |= AM_ARC; /* Set archive bit */ - ST_DWORD(dir+DIR_FileSize, fp->fsize); /* Update file size */ - st_clust(dir, fp->sclust); /* Update start cluster */ - tm = get_fattime(); /* Update updated time */ - ST_DWORD(dir+DIR_WrtTime, tm); - ST_WORD(dir+DIR_LstAccDate, 0); - fp->flag &= ~FA__WRITTEN; - fp->fs->wflag = 1; - res = sync_fs(fp->fs); - } - } - } - - LEAVE_FF(fp->fs, res); -} - -#endif /* !_FS_READONLY */ - - - - -/*-----------------------------------------------------------------------*/ -/* Close File */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_close ( - FIL *fp /* Pointer to the file object to be closed */ -) -{ - FRESULT res; - - -#if _FS_READONLY - res = validate(fp); - { -#if _FS_REENTRANT - FATFS *fs = 0; - if (res == FR_OK) fs = fp->fs; /* Get corresponding file system object */ -#endif - if (res == FR_OK) fp->fs = 0; /* Invalidate file object */ - LEAVE_FF(fs, res); - } -#else - res = f_sync(fp); /* Flush cached data */ -#if _FS_LOCK - if (res == FR_OK) { /* Decrement open counter */ -#if _FS_REENTRANT - res = validate(fp); - if (res == FR_OK) { - res = dec_lock(fp->lockid); - unlock_fs(fp->fs, FR_OK); - } -#else - res = dec_lock(fp->lockid); -#endif - } -#endif - if (res == FR_OK) fp->fs = 0; /* Invalidate file object */ - return res; -#endif -} - - - - -/*-----------------------------------------------------------------------*/ -/* Change Current Directory or Current Drive, Get Current Directory */ -/*-----------------------------------------------------------------------*/ - -#if _FS_RPATH >= 1 -#if _VOLUMES >= 2 -FRESULT f_chdrive ( - const TCHAR* path /* Drive number */ -) -{ - int vol; - - - vol = get_ldnumber(&path); - if (vol < 0) return FR_INVALID_DRIVE; - - CurrVol = (BYTE)vol; - - return FR_OK; -} -#endif - - -FRESULT f_chdir ( - const TCHAR* path /* Pointer to the directory path */ -) -{ - FRESULT res; - DIR dj; - DEF_NAMEBUF; - - - /* Get logical drive number */ - res = find_volume(&dj.fs, &path, 0); - if (res == FR_OK) { - INIT_BUF(dj); - res = follow_path(&dj, path); /* Follow the path */ - FREE_BUF(); - if (res == FR_OK) { /* Follow completed */ - if (!dj.dir) { - dj.fs->cdir = dj.sclust; /* Start directory itself */ - } else { - if (dj.dir[DIR_Attr] & AM_DIR) /* Reached to the directory */ - dj.fs->cdir = ld_clust(dj.fs, dj.dir); - else - res = FR_NO_PATH; /* Reached but a file */ - } - } - if (res == FR_NO_FILE) res = FR_NO_PATH; - } - - LEAVE_FF(dj.fs, res); -} - - -#if _FS_RPATH >= 2 -FRESULT f_getcwd ( - TCHAR* buff, /* Pointer to the directory path */ - UINT len /* Size of path */ -) -{ - FRESULT res; - DIR dj; - UINT i, n; - DWORD ccl; - TCHAR *tp; - FILINFO fno; - DEF_NAMEBUF; - - - *buff = 0; - /* Get logical drive number */ - res = find_volume(&dj.fs, (const TCHAR**)&buff, 0); /* Get current volume */ - if (res == FR_OK) { - INIT_BUF(dj); - i = len; /* Bottom of buffer (directory stack base) */ - dj.sclust = dj.fs->cdir; /* Start to follow upper directory from current directory */ - while ((ccl = dj.sclust) != 0) { /* Repeat while current directory is a sub-directory */ - res = dir_sdi(&dj, 1); /* Get parent directory */ - if (res != FR_OK) break; - res = dir_read(&dj, 0); - if (res != FR_OK) break; - dj.sclust = ld_clust(dj.fs, dj.dir); /* Goto parent directory */ - res = dir_sdi(&dj, 0); - if (res != FR_OK) break; - do { /* Find the entry links to the child directory */ - res = dir_read(&dj, 0); - if (res != FR_OK) break; - if (ccl == ld_clust(dj.fs, dj.dir)) break; /* Found the entry */ - res = dir_next(&dj, 0); - } while (res == FR_OK); - if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */ - if (res != FR_OK) break; -#if _USE_LFN - fno.lfname = buff; - fno.lfsize = i; -#endif - get_fileinfo(&dj, &fno); /* Get the directory name and push it to the buffer */ - tp = fno.fname; -#if _USE_LFN - if (*buff) tp = buff; -#endif - for (n = 0; tp[n]; n++) ; - if (i < n + 3) { - res = FR_NOT_ENOUGH_CORE; break; - } - while (n) buff[--i] = tp[--n]; - buff[--i] = '/'; - } - tp = buff; - if (res == FR_OK) { -#if _VOLUMES >= 2 - *tp++ = '0' + CurrVol; /* Put drive number */ - *tp++ = ':'; -#endif - if (i == len) { /* Root-directory */ - *tp++ = '/'; - } else { /* Sub-directroy */ - do /* Add stacked path str */ - *tp++ = buff[i++]; - while (i < len); - } - } - *tp = 0; - FREE_BUF(); - } - - LEAVE_FF(dj.fs, res); -} -#endif /* _FS_RPATH >= 2 */ -#endif /* _FS_RPATH >= 1 */ - - - -#if _FS_MINIMIZE <= 2 -/*-----------------------------------------------------------------------*/ -/* Seek File R/W Pointer */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_lseek ( - FIL* fp, /* Pointer to the file object */ - DWORD ofs /* File pointer from top of file */ -) -{ - FRESULT res; - - - res = validate(fp); /* Check validity of the object */ - if (res != FR_OK) LEAVE_FF(fp->fs, res); - if (fp->err) /* Check error */ - LEAVE_FF(fp->fs, (FRESULT)fp->err); - -#if _USE_FASTSEEK - if (fp->cltbl) { /* Fast seek */ - DWORD cl, pcl, ncl, tcl, dsc, tlen, ulen, *tbl; - - if (ofs == CREATE_LINKMAP) { /* Create CLMT */ - tbl = fp->cltbl; - tlen = *tbl++; ulen = 2; /* Given table size and required table size */ - cl = fp->sclust; /* Top of the chain */ - if (cl) { - do { - /* Get a fragment */ - tcl = cl; ncl = 0; ulen += 2; /* Top, length and used items */ - do { - pcl = cl; ncl++; - cl = get_fat(fp->fs, cl); - if (cl <= 1) ABORT(fp->fs, FR_INT_ERR); - if (cl == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); - } while (cl == pcl + 1); - if (ulen <= tlen) { /* Store the length and top of the fragment */ - *tbl++ = ncl; *tbl++ = tcl; - } - } while (cl < fp->fs->n_fatent); /* Repeat until end of chain */ - } - *fp->cltbl = ulen; /* Number of items used */ - if (ulen <= tlen) - *tbl = 0; /* Terminate table */ - else - res = FR_NOT_ENOUGH_CORE; /* Given table size is smaller than required */ - - } else { /* Fast seek */ - if (ofs > fp->fsize) /* Clip offset at the file size */ - ofs = fp->fsize; - fp->fptr = ofs; /* Set file pointer */ - if (ofs) { - fp->clust = clmt_clust(fp, ofs - 1); - dsc = clust2sect(fp->fs, fp->clust); - if (!dsc) ABORT(fp->fs, FR_INT_ERR); - dsc += (ofs - 1) / SS(fp->fs) & (fp->fs->csize - 1); - if (fp->fptr % SS(fp->fs) && dsc != fp->dsect) { /* Refill sector cache if needed */ -#if !_FS_TINY -#if !_FS_READONLY - if (fp->flag & FA__DIRTY) { /* Write-back dirty sector cache */ - if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1)) - ABORT(fp->fs, FR_DISK_ERR); - fp->flag &= ~FA__DIRTY; - } -#endif - if (disk_read(fp->fs->drv, fp->buf, dsc, 1)) /* Load current sector */ - ABORT(fp->fs, FR_DISK_ERR); -#endif - fp->dsect = dsc; - } - } - } - } else -#endif - - /* Normal Seek */ - { - DWORD clst, bcs, nsect, ifptr; - - if (ofs > fp->fsize /* In read-only mode, clip offset with the file size */ -#if !_FS_READONLY - && !(fp->flag & FA_WRITE) -#endif - ) ofs = fp->fsize; - - ifptr = fp->fptr; - fp->fptr = nsect = 0; - if (ofs) { - bcs = (DWORD)fp->fs->csize * SS(fp->fs); /* Cluster size (byte) */ - if (ifptr > 0 && - (ofs - 1) / bcs >= (ifptr - 1) / bcs) { /* When seek to same or following cluster, */ - fp->fptr = (ifptr - 1) & ~(bcs - 1); /* start from the current cluster */ - ofs -= fp->fptr; - clst = fp->clust; - } else { /* When seek to back cluster, */ - clst = fp->sclust; /* start from the first cluster */ -#if !_FS_READONLY - if (clst == 0) { /* If no cluster chain, create a new chain */ - clst = create_chain(fp->fs, 0); - if (clst == 1) ABORT(fp->fs, FR_INT_ERR); - if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); - fp->sclust = clst; - } -#endif - fp->clust = clst; - } - if (clst != 0) { - while (ofs > bcs) { /* Cluster following loop */ -#if !_FS_READONLY - if (fp->flag & FA_WRITE) { /* Check if in write mode or not */ - clst = create_chain(fp->fs, clst); /* Force stretch if in write mode */ - if (clst == 0) { /* When disk gets full, clip file size */ - ofs = bcs; break; - } - } else -#endif - clst = get_fat(fp->fs, clst); /* Follow cluster chain if not in write mode */ - if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); - if (clst <= 1 || clst >= fp->fs->n_fatent) ABORT(fp->fs, FR_INT_ERR); - fp->clust = clst; - fp->fptr += bcs; - ofs -= bcs; - } - fp->fptr += ofs; - if (ofs % SS(fp->fs)) { - nsect = clust2sect(fp->fs, clst); /* Current sector */ - if (!nsect) ABORT(fp->fs, FR_INT_ERR); - nsect += ofs / SS(fp->fs); - } - } - } - if (fp->fptr % SS(fp->fs) && nsect != fp->dsect) { /* Fill sector cache if needed */ -#if !_FS_TINY -#if !_FS_READONLY - if (fp->flag & FA__DIRTY) { /* Write-back dirty sector cache */ - if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1)) - ABORT(fp->fs, FR_DISK_ERR); - fp->flag &= ~FA__DIRTY; - } -#endif - if (disk_read(fp->fs->drv, fp->buf, nsect, 1)) /* Fill sector cache */ - ABORT(fp->fs, FR_DISK_ERR); -#endif - fp->dsect = nsect; - } -#if !_FS_READONLY - if (fp->fptr > fp->fsize) { /* Set file change flag if the file size is extended */ - fp->fsize = fp->fptr; - fp->flag |= FA__WRITTEN; - } -#endif - } - - LEAVE_FF(fp->fs, res); -} - - - -#if _FS_MINIMIZE <= 1 -/*-----------------------------------------------------------------------*/ -/* Create a Directory Object */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_opendir ( - DIR* dp, /* Pointer to directory object to create */ - const TCHAR* path /* Pointer to the directory path */ -) -{ - FRESULT res; - FATFS* fs; - DEF_NAMEBUF; - - - if (!dp) return FR_INVALID_OBJECT; - - /* Get logical drive number */ - res = find_volume(&fs, &path, 0); - if (res == FR_OK) { - dp->fs = fs; - INIT_BUF(*dp); - res = follow_path(dp, path); /* Follow the path to the directory */ - FREE_BUF(); - if (res == FR_OK) { /* Follow completed */ - if (dp->dir) { /* It is not the origin directory itself */ - if (dp->dir[DIR_Attr] & AM_DIR) /* The object is a sub directory */ - dp->sclust = ld_clust(fs, dp->dir); - else /* The object is a file */ - res = FR_NO_PATH; - } - if (res == FR_OK) { - dp->id = fs->id; - res = dir_sdi(dp, 0); /* Rewind directory */ -#if _FS_LOCK - if (res == FR_OK) { - if (dp->sclust) { - dp->lockid = inc_lock(dp, 0); /* Lock the sub directory */ - if (!dp->lockid) - res = FR_TOO_MANY_OPEN_FILES; - } else { - dp->lockid = 0; /* Root directory need not to be locked */ - } - } -#endif - } - } - if (res == FR_NO_FILE) res = FR_NO_PATH; - } - if (res != FR_OK) dp->fs = 0; /* Invalidate the directory object if function faild */ - - LEAVE_FF(fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Close Directory */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_closedir ( - DIR *dp /* Pointer to the directory object to be closed */ -) -{ - FRESULT res; - - - res = validate(dp); -#if _FS_LOCK - if (res == FR_OK) { /* Decrement open counter */ - if (dp->lockid) - res = dec_lock(dp->lockid); -#if _FS_REENTRANT - unlock_fs(dp->fs, FR_OK); -#endif - } -#endif - if (res == FR_OK) dp->fs = 0; /* Invalidate directory object */ - return res; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Read Directory Entries in Sequence */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_readdir ( - DIR* dp, /* Pointer to the open directory object */ - FILINFO* fno /* Pointer to file information to return */ -) -{ - FRESULT res; - DEF_NAMEBUF; - - - res = validate(dp); /* Check validity of the object */ - if (res == FR_OK) { - if (!fno) { - res = dir_sdi(dp, 0); /* Rewind the directory object */ - } else { - INIT_BUF(*dp); - res = dir_read(dp, 0); /* Read an item */ - if (res == FR_NO_FILE) { /* Reached end of directory */ - dp->sect = 0; - res = FR_OK; - } - if (res == FR_OK) { /* A valid entry is found */ - get_fileinfo(dp, fno); /* Get the object information */ - res = dir_next(dp, 0); /* Increment index for next */ - if (res == FR_NO_FILE) { - dp->sect = 0; - res = FR_OK; - } - } - FREE_BUF(); - } - } - - LEAVE_FF(dp->fs, res); -} - - - -#if _FS_MINIMIZE == 0 -/*-----------------------------------------------------------------------*/ -/* Get File Status */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_stat ( - const TCHAR* path, /* Pointer to the file path */ - FILINFO* fno /* Pointer to file information to return */ -) -{ - FRESULT res; - DIR dj; - DEF_NAMEBUF; - - - /* Get logical drive number */ - res = find_volume(&dj.fs, &path, 0); - if (res == FR_OK) { - INIT_BUF(dj); - res = follow_path(&dj, path); /* Follow the file path */ - if (res == FR_OK) { /* Follow completed */ - if (dj.dir) { /* Found an object */ - if (fno) get_fileinfo(&dj, fno); - } else { /* It is root directory */ - res = FR_INVALID_NAME; - } - } - FREE_BUF(); - } - - LEAVE_FF(dj.fs, res); -} - - - -#if !_FS_READONLY -/*-----------------------------------------------------------------------*/ -/* Get Number of Free Clusters */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_getfree ( - const TCHAR* path, /* Path name of the logical drive number */ - DWORD* nclst, /* Pointer to a variable to return number of free clusters */ - FATFS** fatfs /* Pointer to return pointer to corresponding file system object */ -) -{ - FRESULT res; - FATFS *fs; - DWORD n, clst, sect, stat; - UINT i; - BYTE fat, *p; - - - /* Get logical drive number */ - res = find_volume(fatfs, &path, 0); - fs = *fatfs; - if (res == FR_OK) { - /* If free_clust is valid, return it without full cluster scan */ - if (fs->free_clust <= fs->n_fatent - 2) { - *nclst = fs->free_clust; - } else { - /* Get number of free clusters */ - fat = fs->fs_type; - n = 0; - if (fat == FS_FAT12) { - clst = 2; - do { - stat = get_fat(fs, clst); - if (stat == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } - if (stat == 1) { res = FR_INT_ERR; break; } - if (stat == 0) n++; - } while (++clst < fs->n_fatent); - } else { - clst = fs->n_fatent; - sect = fs->fatbase; - i = 0; p = 0; - do { - if (!i) { - res = move_window(fs, sect++); - if (res != FR_OK) break; - p = fs->win; - i = SS(fs); - } - if (fat == FS_FAT16) { - if (LD_WORD(p) == 0) n++; - p += 2; i -= 2; - } else { - if ((LD_DWORD(p) & 0x0FFFFFFF) == 0) n++; - p += 4; i -= 4; - } - } while (--clst); - } - fs->free_clust = n; - fs->fsi_flag |= 1; - *nclst = n; - } - } - LEAVE_FF(fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Truncate File */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_truncate ( - FIL* fp /* Pointer to the file object */ -) -{ - FRESULT res; - DWORD ncl; - - - res = validate(fp); /* Check validity of the object */ - if (res == FR_OK) { - if (fp->err) { /* Check error */ - res = (FRESULT)fp->err; - } else { - if (!(fp->flag & FA_WRITE)) /* Check access mode */ - res = FR_DENIED; - } - } - if (res == FR_OK) { - if (fp->fsize > fp->fptr) { - fp->fsize = fp->fptr; /* Set file size to current R/W point */ - fp->flag |= FA__WRITTEN; - if (fp->fptr == 0) { /* When set file size to zero, remove entire cluster chain */ - res = remove_chain(fp->fs, fp->sclust); - fp->sclust = 0; - } else { /* When truncate a part of the file, remove remaining clusters */ - ncl = get_fat(fp->fs, fp->clust); - res = FR_OK; - if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR; - if (ncl == 1) res = FR_INT_ERR; - if (res == FR_OK && ncl < fp->fs->n_fatent) { - res = put_fat(fp->fs, fp->clust, 0x0FFFFFFF); - if (res == FR_OK) res = remove_chain(fp->fs, ncl); - } - } -#if !_FS_TINY - if (res == FR_OK && (fp->flag & FA__DIRTY)) { - if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1)) - res = FR_DISK_ERR; - else - fp->flag &= ~FA__DIRTY; - } -#endif - } - if (res != FR_OK) fp->err = (FRESULT)res; - } - - LEAVE_FF(fp->fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Delete a File or Directory */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_unlink ( - const TCHAR* path /* Pointer to the file or directory path */ -) -{ - FRESULT res; - DIR dj, sdj; - BYTE *dir; - DWORD dclst; - DEF_NAMEBUF; - - - /* Get logical drive number */ - res = find_volume(&dj.fs, &path, 1); - if (res == FR_OK) { - INIT_BUF(dj); - res = follow_path(&dj, path); /* Follow the file path */ - if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT)) - res = FR_INVALID_NAME; /* Cannot remove dot entry */ -#if _FS_LOCK - if (res == FR_OK) res = chk_lock(&dj, 2); /* Cannot remove open file */ -#endif - if (res == FR_OK) { /* The object is accessible */ - dir = dj.dir; - if (!dir) { - res = FR_INVALID_NAME; /* Cannot remove the start directory */ - } else { - if (dir[DIR_Attr] & AM_RDO) - res = FR_DENIED; /* Cannot remove R/O object */ - } - dclst = ld_clust(dj.fs, dir); - if (res == FR_OK && (dir[DIR_Attr] & AM_DIR)) { /* Is it a sub-dir? */ - if (dclst < 2) { - res = FR_INT_ERR; - } else { - mem_cpy(&sdj, &dj, sizeof (DIR)); /* Check if the sub-directory is empty or not */ - sdj.sclust = dclst; - res = dir_sdi(&sdj, 2); /* Exclude dot entries */ - if (res == FR_OK) { - res = dir_read(&sdj, 0); /* Read an item */ - if (res == FR_OK /* Not empty directory */ -#if _FS_RPATH - || dclst == dj.fs->cdir /* Current directory */ -#endif - ) res = FR_DENIED; - if (res == FR_NO_FILE) res = FR_OK; /* Empty */ - } - } - } - if (res == FR_OK) { - res = dir_remove(&dj); /* Remove the directory entry */ - if (res == FR_OK) { - if (dclst) /* Remove the cluster chain if exist */ - res = remove_chain(dj.fs, dclst); - if (res == FR_OK) res = sync_fs(dj.fs); - } - } - } - FREE_BUF(); - } - - LEAVE_FF(dj.fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Create a Directory */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_mkdir ( - const TCHAR* path /* Pointer to the directory path */ -) -{ - FRESULT res; - DIR dj; - BYTE *dir, n; - DWORD dsc, dcl, pcl, tm = get_fattime(); - DEF_NAMEBUF; - - - /* Get logical drive number */ - res = find_volume(&dj.fs, &path, 1); - if (res == FR_OK) { - INIT_BUF(dj); - res = follow_path(&dj, path); /* Follow the file path */ - if (res == FR_OK) res = FR_EXIST; /* Any object with same name is already existing */ - if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NS] & NS_DOT)) - res = FR_INVALID_NAME; - if (res == FR_NO_FILE) { /* Can create a new directory */ - dcl = create_chain(dj.fs, 0); /* Allocate a cluster for the new directory table */ - res = FR_OK; - if (dcl == 0) res = FR_DENIED; /* No space to allocate a new cluster */ - if (dcl == 1) res = FR_INT_ERR; - if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR; - if (res == FR_OK) /* Flush FAT */ - res = sync_window(dj.fs); - if (res == FR_OK) { /* Initialize the new directory table */ - dsc = clust2sect(dj.fs, dcl); - dir = dj.fs->win; - mem_set(dir, 0, SS(dj.fs)); - mem_set(dir+DIR_Name, ' ', 11); /* Create "." entry */ - dir[DIR_Name] = '.'; - dir[DIR_Attr] = AM_DIR; - ST_DWORD(dir+DIR_WrtTime, tm); - st_clust(dir, dcl); - mem_cpy(dir+SZ_DIR, dir, SZ_DIR); /* Create ".." entry */ - dir[SZ_DIR+1] = '.'; pcl = dj.sclust; - if (dj.fs->fs_type == FS_FAT32 && pcl == dj.fs->dirbase) - pcl = 0; - st_clust(dir+SZ_DIR, pcl); - for (n = dj.fs->csize; n; n--) { /* Write dot entries and clear following sectors */ - dj.fs->winsect = dsc++; - dj.fs->wflag = 1; - res = sync_window(dj.fs); - if (res != FR_OK) break; - mem_set(dir, 0, SS(dj.fs)); - } - } - if (res == FR_OK) res = dir_register(&dj); /* Register the object to the directoy */ - if (res != FR_OK) { - remove_chain(dj.fs, dcl); /* Could not register, remove cluster chain */ - } else { - dir = dj.dir; - dir[DIR_Attr] = AM_DIR; /* Attribute */ - ST_DWORD(dir+DIR_WrtTime, tm); /* Created time */ - st_clust(dir, dcl); /* Table start cluster */ - dj.fs->wflag = 1; - res = sync_fs(dj.fs); - } - } - FREE_BUF(); - } - - LEAVE_FF(dj.fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Change Attribute */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_chmod ( - const TCHAR* path, /* Pointer to the file path */ - BYTE value, /* Attribute bits */ - BYTE mask /* Attribute mask to change */ -) -{ - FRESULT res; - DIR dj; - BYTE *dir; - DEF_NAMEBUF; - - - /* Get logical drive number */ - res = find_volume(&dj.fs, &path, 1); - if (res == FR_OK) { - INIT_BUF(dj); - res = follow_path(&dj, path); /* Follow the file path */ - FREE_BUF(); - if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT)) - res = FR_INVALID_NAME; - if (res == FR_OK) { - dir = dj.dir; - if (!dir) { /* Is it a root directory? */ - res = FR_INVALID_NAME; - } else { /* File or sub directory */ - mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC; /* Valid attribute mask */ - dir[DIR_Attr] = (value & mask) | (dir[DIR_Attr] & (BYTE)~mask); /* Apply attribute change */ - dj.fs->wflag = 1; - res = sync_fs(dj.fs); - } - } - } - - LEAVE_FF(dj.fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Change Timestamp */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_utime ( - const TCHAR* path, /* Pointer to the file/directory name */ - const FILINFO* fno /* Pointer to the time stamp to be set */ -) -{ - FRESULT res; - DIR dj; - BYTE *dir; - DEF_NAMEBUF; - - - /* Get logical drive number */ - res = find_volume(&dj.fs, &path, 1); - if (res == FR_OK) { - INIT_BUF(dj); - res = follow_path(&dj, path); /* Follow the file path */ - FREE_BUF(); - if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT)) - res = FR_INVALID_NAME; - if (res == FR_OK) { - dir = dj.dir; - if (!dir) { /* Root directory */ - res = FR_INVALID_NAME; - } else { /* File or sub-directory */ - ST_WORD(dir+DIR_WrtTime, fno->ftime); - ST_WORD(dir+DIR_WrtDate, fno->fdate); - dj.fs->wflag = 1; - res = sync_fs(dj.fs); - } - } - } - - LEAVE_FF(dj.fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Rename File/Directory */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_rename ( - const TCHAR* path_old, /* Pointer to the old name */ - const TCHAR* path_new /* Pointer to the new name */ -) -{ - FRESULT res; - DIR djo, djn; - BYTE buf[21], *dir; - DWORD dw; - DEF_NAMEBUF; - - - /* Get logical drive number of the source object */ - res = find_volume(&djo.fs, &path_old, 1); - if (res == FR_OK) { - djn.fs = djo.fs; - INIT_BUF(djo); - res = follow_path(&djo, path_old); /* Check old object */ - if (_FS_RPATH && res == FR_OK && (djo.fn[NS] & NS_DOT)) - res = FR_INVALID_NAME; -#if _FS_LOCK - if (res == FR_OK) res = chk_lock(&djo, 2); -#endif - if (res == FR_OK) { /* Old object is found */ - if (!djo.dir) { /* Is root dir? */ - res = FR_NO_FILE; - } else { - mem_cpy(buf, djo.dir+DIR_Attr, 21); /* Save the object information except for name */ - mem_cpy(&djn, &djo, sizeof (DIR)); /* Check new object */ - res = follow_path(&djn, path_new); - if (res == FR_OK) res = FR_EXIST; /* The new object name is already existing */ - if (res == FR_NO_FILE) { /* Is it a valid path and no name collision? */ -/* Start critical section that any interruption can cause a cross-link */ - res = dir_register(&djn); /* Register the new entry */ - if (res == FR_OK) { - dir = djn.dir; /* Copy object information except for name */ - mem_cpy(dir+13, buf+2, 19); - dir[DIR_Attr] = buf[0] | AM_ARC; - djo.fs->wflag = 1; - if (djo.sclust != djn.sclust && (dir[DIR_Attr] & AM_DIR)) { /* Update .. entry in the directory if needed */ - dw = clust2sect(djo.fs, ld_clust(djo.fs, dir)); - if (!dw) { - res = FR_INT_ERR; - } else { - res = move_window(djo.fs, dw); - dir = djo.fs->win+SZ_DIR; /* .. entry */ - if (res == FR_OK && dir[1] == '.') { - dw = (djo.fs->fs_type == FS_FAT32 && djn.sclust == djo.fs->dirbase) ? 0 : djn.sclust; - st_clust(dir, dw); - djo.fs->wflag = 1; - } - } - } - if (res == FR_OK) { - res = dir_remove(&djo); /* Remove old entry */ - if (res == FR_OK) - res = sync_fs(djo.fs); - } - } -/* End critical section */ - } - } - } - FREE_BUF(); - } - - LEAVE_FF(djo.fs, res); -} - -#endif /* !_FS_READONLY */ -#endif /* _FS_MINIMIZE == 0 */ -#endif /* _FS_MINIMIZE <= 1 */ -#endif /* _FS_MINIMIZE <= 2 */ - - - -#if _USE_LABEL -/*-----------------------------------------------------------------------*/ -/* Get volume label */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_getlabel ( - const TCHAR* path, /* Path name of the logical drive number */ - TCHAR* label, /* Pointer to a buffer to return the volume label */ - DWORD* sn /* Pointer to a variable to return the volume serial number */ -) -{ - FRESULT res; - DIR dj; - UINT i, j; - - - /* Get logical drive number */ - res = find_volume(&dj.fs, &path, 0); - - /* Get volume label */ - if (res == FR_OK && label) { - dj.sclust = 0; /* Open root directory */ - res = dir_sdi(&dj, 0); - if (res == FR_OK) { - res = dir_read(&dj, 1); /* Get an entry with AM_VOL */ - if (res == FR_OK) { /* A volume label is exist */ -#if _LFN_UNICODE - WCHAR w; - i = j = 0; - do { - w = (i < 11) ? dj.dir[i++] : ' '; - if (IsDBCS1(w) && i < 11 && IsDBCS2(dj.dir[i])) - w = w << 8 | dj.dir[i++]; - label[j++] = ff_convert(w, 1); /* OEM -> Unicode */ - } while (j < 11); -#else - mem_cpy(label, dj.dir, 11); -#endif - j = 11; - do { - label[j] = 0; - if (!j) break; - } while (label[--j] == ' '); - } - if (res == FR_NO_FILE) { /* No label, return nul string */ - label[0] = 0; - res = FR_OK; - } - } - } - - /* Get volume serial number */ - if (res == FR_OK && sn) { - res = move_window(dj.fs, dj.fs->volbase); - if (res == FR_OK) { - i = dj.fs->fs_type == FS_FAT32 ? BS_VolID32 : BS_VolID; - *sn = LD_DWORD(&dj.fs->win[i]); - } - } - - LEAVE_FF(dj.fs, res); -} - - - -#if !_FS_READONLY -/*-----------------------------------------------------------------------*/ -/* Set volume label */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_setlabel ( - const TCHAR* label /* Pointer to the volume label to set */ -) -{ - FRESULT res; - DIR dj; - BYTE vn[11]; - UINT i, j, sl; - WCHAR w; - DWORD tm; - - - /* Get logical drive number */ - res = find_volume(&dj.fs, &label, 1); - if (res) LEAVE_FF(dj.fs, res); - - /* Create a volume label in directory form */ - vn[0] = 0; - for (sl = 0; label[sl]; sl++) ; /* Get name length */ - for ( ; sl && label[sl-1] == ' '; sl--) ; /* Remove trailing spaces */ - if (sl) { /* Create volume label in directory form */ - i = j = 0; - do { -#if _LFN_UNICODE - w = ff_convert(ff_wtoupper(label[i++]), 0); -#else - w = (BYTE)label[i++]; - if (IsDBCS1(w)) - w = (j < 10 && i < sl && IsDBCS2(label[i])) ? w << 8 | (BYTE)label[i++] : 0; -#if _USE_LFN - w = ff_convert(ff_wtoupper(ff_convert(w, 1)), 0); -#else - if (IsLower(w)) w -= 0x20; /* To upper ASCII characters */ -#ifdef _EXCVT - if (w >= 0x80) w = ExCvt[w - 0x80]; /* To upper extended characters (SBCS cfg) */ -#else - if (!_DF1S && w >= 0x80) w = 0; /* Reject extended characters (ASCII cfg) */ -#endif -#endif -#endif - if (!w || chk_chr("\"*+,.:;<=>\?[]|\x7F", w) || j >= (UINT)((w >= 0x100) ? 10 : 11)) /* Reject invalid characters for volume label */ - LEAVE_FF(dj.fs, FR_INVALID_NAME); - if (w >= 0x100) vn[j++] = (BYTE)(w >> 8); - vn[j++] = (BYTE)w; - } while (i < sl); - while (j < 11) vn[j++] = ' '; - } - - /* Set volume label */ - dj.sclust = 0; /* Open root directory */ - res = dir_sdi(&dj, 0); - if (res == FR_OK) { - res = dir_read(&dj, 1); /* Get an entry with AM_VOL */ - if (res == FR_OK) { /* A volume label is found */ - if (vn[0]) { - mem_cpy(dj.dir, vn, 11); /* Change the volume label name */ - tm = get_fattime(); - ST_DWORD(dj.dir+DIR_WrtTime, tm); - } else { - dj.dir[0] = DDE; /* Remove the volume label */ - } - dj.fs->wflag = 1; - res = sync_fs(dj.fs); - } else { /* No volume label is found or error */ - if (res == FR_NO_FILE) { - res = FR_OK; - if (vn[0]) { /* Create volume label as new */ - res = dir_alloc(&dj, 1); /* Allocate an entry for volume label */ - if (res == FR_OK) { - mem_set(dj.dir, 0, SZ_DIR); /* Set volume label */ - mem_cpy(dj.dir, vn, 11); - dj.dir[DIR_Attr] = AM_VOL; - tm = get_fattime(); - ST_DWORD(dj.dir+DIR_WrtTime, tm); - dj.fs->wflag = 1; - res = sync_fs(dj.fs); - } - } - } - } - } - - LEAVE_FF(dj.fs, res); -} - -#endif /* !_FS_READONLY */ -#endif /* _USE_LABEL */ - - - -/*-----------------------------------------------------------------------*/ -/* Forward data to the stream directly (available on only tiny cfg) */ -/*-----------------------------------------------------------------------*/ -#if _USE_FORWARD && _FS_TINY - -FRESULT f_forward ( - FIL* fp, /* Pointer to the file object */ - UINT (*func)(const BYTE*,UINT), /* Pointer to the streaming function */ - UINT btf, /* Number of bytes to forward */ - UINT* bf /* Pointer to number of bytes forwarded */ -) -{ - FRESULT res; - DWORD remain, clst, sect; - UINT rcnt; - BYTE csect; - - - *bf = 0; /* Clear transfer byte counter */ - - res = validate(fp); /* Check validity of the object */ - if (res != FR_OK) LEAVE_FF(fp->fs, res); - if (fp->err) /* Check error */ - LEAVE_FF(fp->fs, (FRESULT)fp->err); - if (!(fp->flag & FA_READ)) /* Check access mode */ - LEAVE_FF(fp->fs, FR_DENIED); - - remain = fp->fsize - fp->fptr; - if (btf > remain) btf = (UINT)remain; /* Truncate btf by remaining bytes */ - - for ( ; btf && (*func)(0, 0); /* Repeat until all data transferred or stream becomes busy */ - fp->fptr += rcnt, *bf += rcnt, btf -= rcnt) { - csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */ - if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ - if (!csect) { /* On the cluster boundary? */ - clst = (fp->fptr == 0) ? /* On the top of the file? */ - fp->sclust : get_fat(fp->fs, fp->clust); - if (clst <= 1) ABORT(fp->fs, FR_INT_ERR); - if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); - fp->clust = clst; /* Update current cluster */ - } - } - sect = clust2sect(fp->fs, fp->clust); /* Get current data sector */ - if (!sect) ABORT(fp->fs, FR_INT_ERR); - sect += csect; - if (move_window(fp->fs, sect)) /* Move sector window */ - ABORT(fp->fs, FR_DISK_ERR); - fp->dsect = sect; - rcnt = SS(fp->fs) - (WORD)(fp->fptr % SS(fp->fs)); /* Forward data from sector window */ - if (rcnt > btf) rcnt = btf; - rcnt = (*func)(&fp->fs->win[(WORD)fp->fptr % SS(fp->fs)], rcnt); - if (!rcnt) ABORT(fp->fs, FR_INT_ERR); - } - - LEAVE_FF(fp->fs, FR_OK); -} -#endif /* _USE_FORWARD */ - - - -#if _USE_MKFS && !_FS_READONLY -/*-----------------------------------------------------------------------*/ -/* Create File System on the Drive */ -/*-----------------------------------------------------------------------*/ -#define N_ROOTDIR 512 /* Number of root directory entries for FAT12/16 */ -#define N_FATS 1 /* Number of FAT copies (1 or 2) */ - - -FRESULT f_mkfs ( - const TCHAR* path, /* Logical drive number */ - BYTE sfd, /* Partitioning rule 0:FDISK, 1:SFD */ - UINT au /* Allocation unit [bytes] */ -) -{ - static const WORD vst[] = { 1024, 512, 256, 128, 64, 32, 16, 8, 4, 2, 0}; - static const WORD cst[] = {32768, 16384, 8192, 4096, 2048, 16384, 8192, 4096, 2048, 1024, 512}; - int vol; - BYTE fmt, md, sys, *tbl, pdrv, part; - DWORD n_clst, vs, n, wsect; - UINT i; - DWORD b_vol, b_fat, b_dir, b_data; /* LBA */ - DWORD n_vol, n_rsv, n_fat, n_dir; /* Size */ - FATFS *fs; - DSTATUS stat; - - - /* Check mounted drive and clear work area */ - vol = get_ldnumber(&path); - if (vol < 0) return FR_INVALID_DRIVE; - if (sfd > 1) return FR_INVALID_PARAMETER; - if (au & (au - 1)) return FR_INVALID_PARAMETER; - fs = FatFs[vol]; - if (!fs) return FR_NOT_ENABLED; - fs->fs_type = 0; - pdrv = LD2PD(vol); /* Physical drive */ - part = LD2PT(vol); /* Partition (0:auto detect, 1-4:get from partition table)*/ - - /* Get disk statics */ - stat = disk_initialize(pdrv); - if (stat & STA_NOINIT) return FR_NOT_READY; - if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; -#if _MAX_SS != 512 /* Get disk sector size */ - if (disk_ioctl(pdrv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK || SS(fs) > _MAX_SS) - return FR_DISK_ERR; -#endif - if (_MULTI_PARTITION && part) { - /* Get partition information from partition table in the MBR */ - if (disk_read(pdrv, fs->win, 0, 1)) return FR_DISK_ERR; - if (LD_WORD(fs->win+BS_55AA) != 0xAA55) return FR_MKFS_ABORTED; - tbl = &fs->win[MBR_Table + (part - 1) * SZ_PTE]; - if (!tbl[4]) return FR_MKFS_ABORTED; /* No partition? */ - b_vol = LD_DWORD(tbl+8); /* Volume start sector */ - n_vol = LD_DWORD(tbl+12); /* Volume size */ - } else { - /* Create a partition in this function */ - if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &n_vol) != RES_OK || n_vol < 128) - return FR_DISK_ERR; - b_vol = (sfd) ? 0 : 63; /* Volume start sector */ - n_vol -= b_vol; /* Volume size */ - } - - if (!au) { /* AU auto selection */ - vs = n_vol / (2000 / (SS(fs) / 512)); - for (i = 0; vs < vst[i]; i++) ; - au = cst[i]; - } - au /= SS(fs); /* Number of sectors per cluster */ - if (au == 0) au = 1; - if (au > 128) au = 128; - - /* Pre-compute number of clusters and FAT sub-type */ - n_clst = n_vol / au; - fmt = FS_FAT12; - if (n_clst >= MIN_FAT16) fmt = FS_FAT16; - if (n_clst >= MIN_FAT32) fmt = FS_FAT32; - - /* Determine offset and size of FAT structure */ - if (fmt == FS_FAT32) { - n_fat = ((n_clst * 4) + 8 + SS(fs) - 1) / SS(fs); - n_rsv = 32; - n_dir = 0; - } else { - n_fat = (fmt == FS_FAT12) ? (n_clst * 3 + 1) / 2 + 3 : (n_clst * 2) + 4; - n_fat = (n_fat + SS(fs) - 1) / SS(fs); - n_rsv = 1; - n_dir = (DWORD)N_ROOTDIR * SZ_DIR / SS(fs); - } - b_fat = b_vol + n_rsv; /* FAT area start sector */ - b_dir = b_fat + n_fat * N_FATS; /* Directory area start sector */ - b_data = b_dir + n_dir; /* Data area start sector */ - if (n_vol < b_data + au - b_vol) return FR_MKFS_ABORTED; /* Too small volume */ - - /* Align data start sector to erase block boundary (for flash memory media) */ - if (disk_ioctl(pdrv, GET_BLOCK_SIZE, &n) != RES_OK || !n || n > 32768) n = 1; - n = (b_data + n - 1) & ~(n - 1); /* Next nearest erase block from current data start */ - n = (n - b_data) / N_FATS; - if (fmt == FS_FAT32) { /* FAT32: Move FAT offset */ - n_rsv += n; - b_fat += n; - } else { /* FAT12/16: Expand FAT size */ - n_fat += n; - } - - /* Determine number of clusters and final check of validity of the FAT sub-type */ - n_clst = (n_vol - n_rsv - n_fat * N_FATS - n_dir) / au; - if ( (fmt == FS_FAT16 && n_clst < MIN_FAT16) - || (fmt == FS_FAT32 && n_clst < MIN_FAT32)) - return FR_MKFS_ABORTED; - - /* Determine system ID in the partition table */ - if (fmt == FS_FAT32) { - sys = 0x0C; /* FAT32X */ - } else { - if (fmt == FS_FAT12 && n_vol < 0x10000) { - sys = 0x01; /* FAT12(<65536) */ - } else { - sys = (n_vol < 0x10000) ? 0x04 : 0x06; /* FAT16(<65536) : FAT12/16(>=65536) */ - } - } - - if (_MULTI_PARTITION && part) { - /* Update system ID in the partition table */ - tbl = &fs->win[MBR_Table + (part - 1) * SZ_PTE]; - tbl[4] = sys; - if (disk_write(pdrv, fs->win, 0, 1)) /* Write it to teh MBR */ - return FR_DISK_ERR; - md = 0xF8; - } else { - if (sfd) { /* No partition table (SFD) */ - md = 0xF0; - } else { /* Create partition table (FDISK) */ - mem_set(fs->win, 0, SS(fs)); - tbl = fs->win+MBR_Table; /* Create partition table for single partition in the drive */ - tbl[1] = 1; /* Partition start head */ - tbl[2] = 1; /* Partition start sector */ - tbl[3] = 0; /* Partition start cylinder */ - tbl[4] = sys; /* System type */ - tbl[5] = 254; /* Partition end head */ - n = (b_vol + n_vol) / 63 / 255; - tbl[6] = (BYTE)(n >> 2 | 63); /* Partition end sector */ - tbl[7] = (BYTE)n; /* End cylinder */ - ST_DWORD(tbl+8, 63); /* Partition start in LBA */ - ST_DWORD(tbl+12, n_vol); /* Partition size in LBA */ - ST_WORD(fs->win+BS_55AA, 0xAA55); /* MBR signature */ - if (disk_write(pdrv, fs->win, 0, 1)) /* Write it to the MBR */ - return FR_DISK_ERR; - md = 0xF8; - } - } - - /* Create BPB in the VBR */ - tbl = fs->win; /* Clear sector */ - mem_set(tbl, 0, SS(fs)); - mem_cpy(tbl, "\xEB\xFE\x90" "MSDOS5.0", 11);/* Boot jump code, OEM name */ - i = SS(fs); /* Sector size */ - ST_WORD(tbl+BPB_BytsPerSec, i); - tbl[BPB_SecPerClus] = (BYTE)au; /* Sectors per cluster */ - ST_WORD(tbl+BPB_RsvdSecCnt, n_rsv); /* Reserved sectors */ - tbl[BPB_NumFATs] = N_FATS; /* Number of FATs */ - i = (fmt == FS_FAT32) ? 0 : N_ROOTDIR; /* Number of root directory entries */ - ST_WORD(tbl+BPB_RootEntCnt, i); - if (n_vol < 0x10000) { /* Number of total sectors */ - ST_WORD(tbl+BPB_TotSec16, n_vol); - } else { - ST_DWORD(tbl+BPB_TotSec32, n_vol); - } - tbl[BPB_Media] = md; /* Media descriptor */ - ST_WORD(tbl+BPB_SecPerTrk, 63); /* Number of sectors per track */ - ST_WORD(tbl+BPB_NumHeads, 255); /* Number of heads */ - ST_DWORD(tbl+BPB_HiddSec, b_vol); /* Hidden sectors */ - n = get_fattime(); /* Use current time as VSN */ - if (fmt == FS_FAT32) { - ST_DWORD(tbl+BS_VolID32, n); /* VSN */ - ST_DWORD(tbl+BPB_FATSz32, n_fat); /* Number of sectors per FAT */ - ST_DWORD(tbl+BPB_RootClus, 2); /* Root directory start cluster (2) */ - ST_WORD(tbl+BPB_FSInfo, 1); /* FSINFO record offset (VBR+1) */ - ST_WORD(tbl+BPB_BkBootSec, 6); /* Backup boot record offset (VBR+6) */ - tbl[BS_DrvNum32] = 0x80; /* Drive number */ - tbl[BS_BootSig32] = 0x29; /* Extended boot signature */ - mem_cpy(tbl+BS_VolLab32, "NO NAME " "FAT32 ", 19); /* Volume label, FAT signature */ - } else { - ST_DWORD(tbl+BS_VolID, n); /* VSN */ - ST_WORD(tbl+BPB_FATSz16, n_fat); /* Number of sectors per FAT */ - tbl[BS_DrvNum] = 0x80; /* Drive number */ - tbl[BS_BootSig] = 0x29; /* Extended boot signature */ - mem_cpy(tbl+BS_VolLab, "NO NAME " "FAT ", 19); /* Volume label, FAT signature */ - } - ST_WORD(tbl+BS_55AA, 0xAA55); /* Signature (Offset is fixed here regardless of sector size) */ - if (disk_write(pdrv, tbl, b_vol, 1)) /* Write it to the VBR sector */ - return FR_DISK_ERR; - if (fmt == FS_FAT32) /* Write backup VBR if needed (VBR+6) */ - disk_write(pdrv, tbl, b_vol + 6, 1); - - /* Initialize FAT area */ - wsect = b_fat; - for (i = 0; i < N_FATS; i++) { /* Initialize each FAT copy */ - mem_set(tbl, 0, SS(fs)); /* 1st sector of the FAT */ - n = md; /* Media descriptor byte */ - if (fmt != FS_FAT32) { - n |= (fmt == FS_FAT12) ? 0x00FFFF00 : 0xFFFFFF00; - ST_DWORD(tbl+0, n); /* Reserve cluster #0-1 (FAT12/16) */ - } else { - n |= 0xFFFFFF00; - ST_DWORD(tbl+0, n); /* Reserve cluster #0-1 (FAT32) */ - ST_DWORD(tbl+4, 0xFFFFFFFF); - ST_DWORD(tbl+8, 0x0FFFFFFF); /* Reserve cluster #2 for root directory */ - } - if (disk_write(pdrv, tbl, wsect++, 1)) - return FR_DISK_ERR; - mem_set(tbl, 0, SS(fs)); /* Fill following FAT entries with zero */ - for (n = 1; n < n_fat; n++) { /* This loop may take a time on FAT32 volume due to many single sector writes */ - if (disk_write(pdrv, tbl, wsect++, 1)) - return FR_DISK_ERR; - } - } - - /* Initialize root directory */ - i = (fmt == FS_FAT32) ? au : n_dir; - do { - if (disk_write(pdrv, tbl, wsect++, 1)) - return FR_DISK_ERR; - } while (--i); - -#if _USE_ERASE /* Erase data area if needed */ - { - DWORD eb[2]; - - eb[0] = wsect; eb[1] = wsect + (n_clst - ((fmt == FS_FAT32) ? 1 : 0)) * au - 1; - disk_ioctl(pdrv, CTRL_ERASE_SECTOR, eb); - } -#endif - - /* Create FSINFO if needed */ - if (fmt == FS_FAT32) { - ST_DWORD(tbl+FSI_LeadSig, 0x41615252); - ST_DWORD(tbl+FSI_StrucSig, 0x61417272); - ST_DWORD(tbl+FSI_Free_Count, n_clst - 1); /* Number of free clusters */ - ST_DWORD(tbl+FSI_Nxt_Free, 2); /* Last allocated cluster# */ - ST_WORD(tbl+BS_55AA, 0xAA55); - disk_write(pdrv, tbl, b_vol + 1, 1); /* Write original (VBR+1) */ - disk_write(pdrv, tbl, b_vol + 7, 1); /* Write backup (VBR+7) */ - } - - return (disk_ioctl(pdrv, CTRL_SYNC, 0) == RES_OK) ? FR_OK : FR_DISK_ERR; -} - - - -#if _MULTI_PARTITION -/*-----------------------------------------------------------------------*/ -/* Divide Physical Drive */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_fdisk ( - BYTE pdrv, /* Physical drive number */ - const DWORD szt[], /* Pointer to the size table for each partitions */ - void* work /* Pointer to the working buffer */ -) -{ - UINT i, n, sz_cyl, tot_cyl, b_cyl, e_cyl, p_cyl; - BYTE s_hd, e_hd, *p, *buf = (BYTE*)work; - DSTATUS stat; - DWORD sz_disk, sz_part, s_part; - - - stat = disk_initialize(pdrv); - if (stat & STA_NOINIT) return FR_NOT_READY; - if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; - if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_disk)) return FR_DISK_ERR; - - /* Determine CHS in the table regardless of the drive geometry */ - for (n = 16; n < 256 && sz_disk / n / 63 > 1024; n *= 2) ; - if (n == 256) n--; - e_hd = n - 1; - sz_cyl = 63 * n; - tot_cyl = sz_disk / sz_cyl; - - /* Create partition table */ - mem_set(buf, 0, _MAX_SS); - p = buf + MBR_Table; b_cyl = 0; - for (i = 0; i < 4; i++, p += SZ_PTE) { - p_cyl = (szt[i] <= 100U) ? (DWORD)tot_cyl * szt[i] / 100 : szt[i] / sz_cyl; - if (!p_cyl) continue; - s_part = (DWORD)sz_cyl * b_cyl; - sz_part = (DWORD)sz_cyl * p_cyl; - if (i == 0) { /* Exclude first track of cylinder 0 */ - s_hd = 1; - s_part += 63; sz_part -= 63; - } else { - s_hd = 0; - } - e_cyl = b_cyl + p_cyl - 1; - if (e_cyl >= tot_cyl) return FR_INVALID_PARAMETER; - - /* Set partition table */ - p[1] = s_hd; /* Start head */ - p[2] = (BYTE)((b_cyl >> 2) + 1); /* Start sector */ - p[3] = (BYTE)b_cyl; /* Start cylinder */ - p[4] = 0x06; /* System type (temporary setting) */ - p[5] = e_hd; /* End head */ - p[6] = (BYTE)((e_cyl >> 2) + 63); /* End sector */ - p[7] = (BYTE)e_cyl; /* End cylinder */ - ST_DWORD(p + 8, s_part); /* Start sector in LBA */ - ST_DWORD(p + 12, sz_part); /* Partition size */ - - /* Next partition */ - b_cyl += p_cyl; - } - ST_WORD(p, 0xAA55); - - /* Write it to the MBR */ - return (disk_write(pdrv, buf, 0, 1) || disk_ioctl(pdrv, CTRL_SYNC, 0)) ? FR_DISK_ERR : FR_OK; -} - - -#endif /* _MULTI_PARTITION */ -#endif /* _USE_MKFS && !_FS_READONLY */ - - - - -#if _USE_STRFUNC -/*-----------------------------------------------------------------------*/ -/* Get a string from the file */ -/*-----------------------------------------------------------------------*/ - -TCHAR* f_gets ( - TCHAR* buff, /* Pointer to the string buffer to read */ - int len, /* Size of string buffer (characters) */ - FIL* fp /* Pointer to the file object */ -) -{ - int n = 0; - TCHAR c, *p = buff; - BYTE s[2]; - UINT rc; - - - while (n < len - 1) { /* Read characters until buffer gets filled */ -#if _LFN_UNICODE -#if _STRF_ENCODE == 3 /* Read a character in UTF-8 */ - f_read(fp, s, 1, &rc); - if (rc != 1) break; - c = s[0]; - if (c >= 0x80) { - if (c < 0xC0) continue; /* Skip stray trailer */ - if (c < 0xE0) { /* Two-byte sequence */ - f_read(fp, s, 1, &rc); - if (rc != 1) break; - c = (c & 0x1F) << 6 | (s[0] & 0x3F); - if (c < 0x80) c = '?'; - } else { - if (c < 0xF0) { /* Three-byte sequence */ - f_read(fp, s, 2, &rc); - if (rc != 2) break; - c = c << 12 | (s[0] & 0x3F) << 6 | (s[1] & 0x3F); - if (c < 0x800) c = '?'; - } else { /* Reject four-byte sequence */ - c = '?'; - } - } - } -#elif _STRF_ENCODE == 2 /* Read a character in UTF-16BE */ - f_read(fp, s, 2, &rc); - if (rc != 2) break; - c = s[1] + (s[0] << 8); -#elif _STRF_ENCODE == 1 /* Read a character in UTF-16LE */ - f_read(fp, s, 2, &rc); - if (rc != 2) break; - c = s[0] + (s[1] << 8); -#else /* Read a character in ANSI/OEM */ - f_read(fp, s, 1, &rc); - if (rc != 1) break; - c = s[0]; - if (IsDBCS1(c)) { - f_read(fp, s, 1, &rc); - if (rc != 1) break; - c = (c << 8) + s[0]; - } - c = ff_convert(c, 1); /* OEM -> Unicode */ - if (!c) c = '?'; -#endif -#else /* Read a character without conversion */ - f_read(fp, s, 1, &rc); - if (rc != 1) break; - c = s[0]; -#endif - if (_USE_STRFUNC == 2 && c == '\r') continue; /* Strip '\r' */ - *p++ = c; - n++; - if (c == '\n') break; /* Break on EOL */ - } - *p = 0; - return n ? buff : 0; /* When no data read (eof or error), return with error. */ -} - - - -#if !_FS_READONLY -#include -/*-----------------------------------------------------------------------*/ -/* Put a character to the file */ -/*-----------------------------------------------------------------------*/ - -typedef struct { - FIL* fp; - int idx, nchr; - BYTE buf[64]; -} putbuff; - - -static -void putc_bfd ( - putbuff* pb, - TCHAR c -) -{ - UINT bw; - int i; - - - if (_USE_STRFUNC == 2 && c == '\n') /* LF -> CRLF conversion */ - putc_bfd(pb, '\r'); - - i = pb->idx; /* Buffer write index (-1:error) */ - if (i < 0) return; - -#if _LFN_UNICODE -#if _STRF_ENCODE == 3 /* Write a character in UTF-8 */ - if (c < 0x80) { /* 7-bit */ - pb->buf[i++] = (BYTE)c; - } else { - if (c < 0x800) { /* 11-bit */ - pb->buf[i++] = (BYTE)(0xC0 | c >> 6); - } else { /* 16-bit */ - pb->buf[i++] = (BYTE)(0xE0 | c >> 12); - pb->buf[i++] = (BYTE)(0x80 | (c >> 6 & 0x3F)); - } - pb->buf[i++] = (BYTE)(0x80 | (c & 0x3F)); - } -#elif _STRF_ENCODE == 2 /* Write a character in UTF-16BE */ - pb->buf[i++] = (BYTE)(c >> 8); - pb->buf[i++] = (BYTE)c; -#elif _STRF_ENCODE == 1 /* Write a character in UTF-16LE */ - pb->buf[i++] = (BYTE)c; - pb->buf[i++] = (BYTE)(c >> 8); -#else /* Write a character in ANSI/OEM */ - c = ff_convert(c, 0); /* Unicode -> OEM */ - if (!c) c = '?'; - if (c >= 0x100) - pb->buf[i++] = (BYTE)(c >> 8); - pb->buf[i++] = (BYTE)c; -#endif -#else /* Write a character without conversion */ - pb->buf[i++] = (BYTE)c; -#endif - - if (i >= (int)(sizeof pb->buf) - 3) { /* Write buffered characters to the file */ - f_write(pb->fp, pb->buf, (UINT)i, &bw); - i = (bw == (UINT)i) ? 0 : -1; - } - pb->idx = i; - pb->nchr++; -} - - - -int f_putc ( - TCHAR c, /* A character to be output */ - FIL* fp /* Pointer to the file object */ -) -{ - putbuff pb; - UINT nw; - - - pb.fp = fp; /* Initialize output buffer */ - pb.nchr = pb.idx = 0; - - putc_bfd(&pb, c); /* Put a character */ - - if ( pb.idx >= 0 /* Flush buffered characters to the file */ - && f_write(pb.fp, pb.buf, (UINT)pb.idx, &nw) == FR_OK - && (UINT)pb.idx == nw) return pb.nchr; - return EOF; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Put a string to the file */ -/*-----------------------------------------------------------------------*/ - -int f_puts ( - const TCHAR* str, /* Pointer to the string to be output */ - FIL* fp /* Pointer to the file object */ -) -{ - putbuff pb; - UINT nw; - - - pb.fp = fp; /* Initialize output buffer */ - pb.nchr = pb.idx = 0; - - while (*str) /* Put the string */ - putc_bfd(&pb, *str++); - - if ( pb.idx >= 0 /* Flush buffered characters to the file */ - && f_write(pb.fp, pb.buf, (UINT)pb.idx, &nw) == FR_OK - && (UINT)pb.idx == nw) return pb.nchr; - return EOF; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Put a formatted string to the file */ -/*-----------------------------------------------------------------------*/ - -int f_printf ( - FIL* fp, /* Pointer to the file object */ - const TCHAR* fmt, /* Pointer to the format string */ - ... /* Optional arguments... */ -) -{ - va_list arp; - BYTE f, r; - UINT nw, i, j, w; - DWORD v; - TCHAR c, d, s[16], *p; - putbuff pb; - - - pb.fp = fp; /* Initialize output buffer */ - pb.nchr = pb.idx = 0; - - va_start(arp, fmt); - - for (;;) { - c = *fmt++; - if (c == 0) break; /* End of string */ - if (c != '%') { /* Non escape character */ - putc_bfd(&pb, c); - continue; - } - w = f = 0; - c = *fmt++; - if (c == '0') { /* Flag: '0' padding */ - f = 1; c = *fmt++; - } else { - if (c == '-') { /* Flag: left justified */ - f = 2; c = *fmt++; - } - } - while (IsDigit(c)) { /* Precision */ - w = w * 10 + c - '0'; - c = *fmt++; - } - if (c == 'l' || c == 'L') { /* Prefix: Size is long int */ - f |= 4; c = *fmt++; - } - if (!c) break; - d = c; - if (IsLower(d)) d -= 0x20; - switch (d) { /* Type is... */ - case 'S' : /* String */ - p = va_arg(arp, TCHAR*); - for (j = 0; p[j]; j++) ; - if (!(f & 2)) { - while (j++ < w) putc_bfd(&pb, ' '); - } - while (*p) putc_bfd(&pb, *p++); - while (j++ < w) putc_bfd(&pb, ' '); - continue; - case 'C' : /* Character */ - putc_bfd(&pb, (TCHAR)va_arg(arp, int)); continue; - case 'B' : /* Binary */ - r = 2; break; - case 'O' : /* Octal */ - r = 8; break; - case 'D' : /* Signed decimal */ - case 'U' : /* Unsigned decimal */ - r = 10; break; - case 'X' : /* Hexdecimal */ - r = 16; break; - default: /* Unknown type (pass-through) */ - putc_bfd(&pb, c); continue; - } - - /* Get an argument and put it in numeral */ - v = (f & 4) ? (DWORD)va_arg(arp, long) : ((d == 'D') ? (DWORD)(long)va_arg(arp, int) : (DWORD)va_arg(arp, unsigned int)); - if (d == 'D' && (v & 0x80000000)) { - v = 0 - v; - f |= 8; - } - i = 0; - do { - d = (TCHAR)(v % r); v /= r; - if (d > 9) d += (c == 'x') ? 0x27 : 0x07; - s[i++] = d + '0'; - } while (v && i < sizeof s / sizeof s[0]); - if (f & 8) s[i++] = '-'; - j = i; d = (f & 1) ? '0' : ' '; - while (!(f & 2) && j++ < w) putc_bfd(&pb, d); - do putc_bfd(&pb, s[--i]); while (i); - while (j++ < w) putc_bfd(&pb, d); - } - - va_end(arp); - - if ( pb.idx >= 0 /* Flush buffered characters to the file */ - && f_write(pb.fp, pb.buf, (UINT)pb.idx, &nw) == FR_OK - && (UINT)pb.idx == nw) return pb.nchr; - return EOF; -} - -#endif /* !_FS_READONLY */ -#endif /* _USE_STRFUNC */ diff --git a/stm/fatfs/ff.h b/stm/fatfs/ff.h deleted file mode 100644 index 626b476ce..000000000 --- a/stm/fatfs/ff.h +++ /dev/null @@ -1,342 +0,0 @@ -/*---------------------------------------------------------------------------/ -/ FatFs - FAT file system module include file R0.10 (C)ChaN, 2013 -/----------------------------------------------------------------------------/ -/ FatFs module is a generic FAT file system module for small embedded systems. -/ This is a free software that opened for education, research and commercial -/ developments under license policy of following terms. -/ -/ Copyright (C) 2013, ChaN, all right reserved. -/ -/ * The FatFs module is a free software and there is NO WARRANTY. -/ * No restriction on use. You can use, modify and redistribute it for -/ personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY. -/ * Redistributions of source code must retain the above copyright notice. -/ -/----------------------------------------------------------------------------*/ - -#ifndef _FATFS -#define _FATFS 80960 /* Revision ID */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "integer.h" /* Basic integer types */ -#include "ffconf.h" /* FatFs configuration options */ - -#if _FATFS != _FFCONF -#error Wrong configuration file (ffconf.h). -#endif - - - -/* Definitions of volume management */ - -#if _MULTI_PARTITION /* Multiple partition configuration */ -typedef struct { - BYTE pd; /* Physical drive number */ - BYTE pt; /* Partition: 0:Auto detect, 1-4:Forced partition) */ -} PARTITION; -extern PARTITION VolToPart[]; /* Volume - Partition resolution table */ -#define LD2PD(vol) (VolToPart[vol].pd) /* Get physical drive number */ -#define LD2PT(vol) (VolToPart[vol].pt) /* Get partition index */ - -#else /* Single partition configuration */ -#define LD2PD(vol) (BYTE)(vol) /* Each logical drive is bound to the same physical drive number */ -#define LD2PT(vol) 0 /* Find first valid partition or in SFD */ - -#endif - - - -/* Type of path name strings on FatFs API */ - -#if _LFN_UNICODE /* Unicode string */ -#if !_USE_LFN -#error _LFN_UNICODE must be 0 in non-LFN cfg. -#endif -#ifndef _INC_TCHAR -typedef WCHAR TCHAR; -#define _T(x) L ## x -#define _TEXT(x) L ## x -#endif - -#else /* ANSI/OEM string */ -#ifndef _INC_TCHAR -typedef char TCHAR; -#define _T(x) x -#define _TEXT(x) x -#endif - -#endif - - - -/* File system object structure (FATFS) */ - -typedef struct { - BYTE fs_type; /* FAT sub-type (0:Not mounted) */ - BYTE drv; /* Physical drive number */ - BYTE csize; /* Sectors per cluster (1,2,4...128) */ - BYTE n_fats; /* Number of FAT copies (1 or 2) */ - BYTE wflag; /* win[] flag (b0:dirty) */ - BYTE fsi_flag; /* FSINFO flags (b7:disabled, b0:dirty) */ - WORD id; /* File system mount ID */ - WORD n_rootdir; /* Number of root directory entries (FAT12/16) */ -#if _MAX_SS != 512 - WORD ssize; /* Bytes per sector (512, 1024, 2048 or 4096) */ -#endif -#if _FS_REENTRANT - _SYNC_t sobj; /* Identifier of sync object */ -#endif -#if !_FS_READONLY - DWORD last_clust; /* Last allocated cluster */ - DWORD free_clust; /* Number of free clusters */ -#endif -#if _FS_RPATH - DWORD cdir; /* Current directory start cluster (0:root) */ -#endif - DWORD n_fatent; /* Number of FAT entries (= number of clusters + 2) */ - DWORD fsize; /* Sectors per FAT */ - DWORD volbase; /* Volume start sector */ - DWORD fatbase; /* FAT start sector */ - DWORD dirbase; /* Root directory start sector (FAT32:Cluster#) */ - DWORD database; /* Data start sector */ - DWORD winsect; /* Current sector appearing in the win[] */ - BYTE win[_MAX_SS]; /* Disk access window for Directory, FAT (and file data at tiny cfg) */ -} FATFS; - - - -/* File object structure (FIL) */ - -typedef struct { - FATFS* fs; /* Pointer to the related file system object (**do not change order**) */ - WORD id; /* Owner file system mount ID (**do not change order**) */ - BYTE flag; /* File status flags */ - BYTE err; /* Abort flag (error code) */ - DWORD fptr; /* File read/write pointer (Zeroed on file open) */ - DWORD fsize; /* File size */ - DWORD sclust; /* File data start cluster (0:no data cluster, always 0 when fsize is 0) */ - DWORD clust; /* Current cluster of fpter */ - DWORD dsect; /* Current data sector of fpter */ -#if !_FS_READONLY - DWORD dir_sect; /* Sector containing the directory entry */ - BYTE* dir_ptr; /* Pointer to the directory entry in the window */ -#endif -#if _USE_FASTSEEK - DWORD* cltbl; /* Pointer to the cluster link map table (Nulled on file open) */ -#endif -#if _FS_LOCK - UINT lockid; /* File lock ID (index of file semaphore table Files[]) */ -#endif -#if !_FS_TINY - BYTE buf[_MAX_SS]; /* File data read/write buffer */ -#endif -} FIL; - - - -/* Directory object structure (DIR) */ - -typedef struct { - FATFS* fs; /* Pointer to the owner file system object (**do not change order**) */ - WORD id; /* Owner file system mount ID (**do not change order**) */ - WORD index; /* Current read/write index number */ - DWORD sclust; /* Table start cluster (0:Root dir) */ - DWORD clust; /* Current cluster */ - DWORD sect; /* Current sector */ - BYTE* dir; /* Pointer to the current SFN entry in the win[] */ - BYTE* fn; /* Pointer to the SFN (in/out) {file[8],ext[3],status[1]} */ -#if _FS_LOCK - UINT lockid; /* File lock ID (index of file semaphore table Files[]) */ -#endif -#if _USE_LFN - WCHAR* lfn; /* Pointer to the LFN working buffer */ - WORD lfn_idx; /* Last matched LFN index number (0xFFFF:No LFN) */ -#endif -} DIR; - - - -/* File status structure (FILINFO) */ - -typedef struct { - DWORD fsize; /* File size */ - WORD fdate; /* Last modified date */ - WORD ftime; /* Last modified time */ - BYTE fattrib; /* Attribute */ - TCHAR fname[13]; /* Short file name (8.3 format) */ -#if _USE_LFN - TCHAR* lfname; /* Pointer to the LFN buffer */ - UINT lfsize; /* Size of LFN buffer in TCHAR */ -#endif -} FILINFO; - - - -/* File function return code (FRESULT) */ - -typedef enum { - FR_OK = 0, /* (0) Succeeded */ - FR_DISK_ERR, /* (1) A hard error occurred in the low level disk I/O layer */ - FR_INT_ERR, /* (2) Assertion failed */ - FR_NOT_READY, /* (3) The physical drive cannot work */ - FR_NO_FILE, /* (4) Could not find the file */ - FR_NO_PATH, /* (5) Could not find the path */ - FR_INVALID_NAME, /* (6) The path name format is invalid */ - FR_DENIED, /* (7) Access denied due to prohibited access or directory full */ - FR_EXIST, /* (8) Access denied due to prohibited access */ - FR_INVALID_OBJECT, /* (9) The file/directory object is invalid */ - FR_WRITE_PROTECTED, /* (10) The physical drive is write protected */ - FR_INVALID_DRIVE, /* (11) The logical drive number is invalid */ - FR_NOT_ENABLED, /* (12) The volume has no work area */ - FR_NO_FILESYSTEM, /* (13) There is no valid FAT volume */ - FR_MKFS_ABORTED, /* (14) The f_mkfs() aborted due to any parameter error */ - FR_TIMEOUT, /* (15) Could not get a grant to access the volume within defined period */ - FR_LOCKED, /* (16) The operation is rejected according to the file sharing policy */ - FR_NOT_ENOUGH_CORE, /* (17) LFN working buffer could not be allocated */ - FR_TOO_MANY_OPEN_FILES, /* (18) Number of open files > _FS_SHARE */ - FR_INVALID_PARAMETER /* (19) Given parameter is invalid */ -} FRESULT; - - - -/*--------------------------------------------------------------*/ -/* FatFs module application interface */ - -FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode); /* Open or create a file */ -FRESULT f_close (FIL* fp); /* Close an open file object */ -FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br); /* Read data from a file */ -FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw); /* Write data to a file */ -FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf); /* Forward data to the stream */ -FRESULT f_lseek (FIL* fp, DWORD ofs); /* Move file pointer of a file object */ -FRESULT f_truncate (FIL* fp); /* Truncate file */ -FRESULT f_sync (FIL* fp); /* Flush cached data of a writing file */ -FRESULT f_opendir (DIR* dp, const TCHAR* path); /* Open a directory */ -FRESULT f_closedir (DIR* dp); /* Close an open directory */ -FRESULT f_readdir (DIR* dp, FILINFO* fno); /* Read a directory item */ -FRESULT f_mkdir (const TCHAR* path); /* Create a sub directory */ -FRESULT f_unlink (const TCHAR* path); /* Delete an existing file or directory */ -FRESULT f_rename (const TCHAR* path_old, const TCHAR* path_new); /* Rename/Move a file or directory */ -FRESULT f_stat (const TCHAR* path, FILINFO* fno); /* Get file status */ -FRESULT f_chmod (const TCHAR* path, BYTE value, BYTE mask); /* Change attribute of the file/dir */ -FRESULT f_utime (const TCHAR* path, const FILINFO* fno); /* Change times-tamp of the file/dir */ -FRESULT f_chdir (const TCHAR* path); /* Change current directory */ -FRESULT f_chdrive (const TCHAR* path); /* Change current drive */ -FRESULT f_getcwd (TCHAR* buff, UINT len); /* Get current directory */ -FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs); /* Get number of free clusters on the drive */ -FRESULT f_getlabel (const TCHAR* path, TCHAR* label, DWORD* sn); /* Get volume label */ -FRESULT f_setlabel (const TCHAR* label); /* Set volume label */ -FRESULT f_mount (FATFS* fs, const TCHAR* path, BYTE opt); /* Mount/Unmount a logical drive */ -FRESULT f_mkfs (const TCHAR* path, BYTE sfd, UINT au); /* Create a file system on the volume */ -FRESULT f_fdisk (BYTE pdrv, const DWORD szt[], void* work); /* Divide a physical drive into some partitions */ -int f_putc (TCHAR c, FIL* fp); /* Put a character to the file */ -int f_puts (const TCHAR* str, FIL* cp); /* Put a string to the file */ -int f_printf (FIL* fp, const TCHAR* str, ...); /* Put a formatted string to the file */ -TCHAR* f_gets (TCHAR* buff, int len, FIL* fp); /* Get a string from the file */ - -#define f_eof(fp) (((fp)->fptr == (fp)->fsize) ? 1 : 0) -#define f_error(fp) ((fp)->err) -#define f_tell(fp) ((fp)->fptr) -#define f_size(fp) ((fp)->fsize) - -#ifndef EOF -#define EOF (-1) -#endif - - - - -/*--------------------------------------------------------------*/ -/* Additional user defined functions */ - -/* RTC function */ -#if !_FS_READONLY -DWORD get_fattime (void); -#endif - -/* Unicode support functions */ -#if _USE_LFN /* Unicode - OEM code conversion */ -WCHAR ff_convert (WCHAR chr, UINT dir); /* OEM-Unicode bidirectional conversion */ -WCHAR ff_wtoupper (WCHAR chr); /* Unicode upper-case conversion */ -#if _USE_LFN == 3 /* Memory functions */ -void* ff_memalloc (UINT msize); /* Allocate memory block */ -void ff_memfree (void* mblock); /* Free memory block */ -#endif -#endif - -/* Sync functions */ -#if _FS_REENTRANT -int ff_cre_syncobj (BYTE vol, _SYNC_t* sobj); /* Create a sync object */ -int ff_req_grant (_SYNC_t sobj); /* Lock sync object */ -void ff_rel_grant (_SYNC_t sobj); /* Unlock sync object */ -int ff_del_syncobj (_SYNC_t sobj); /* Delete a sync object */ -#endif - - - - -/*--------------------------------------------------------------*/ -/* Flags and offset address */ - - -/* File access control and file status flags (FIL.flag) */ - -#define FA_READ 0x01 -#define FA_OPEN_EXISTING 0x00 - -#if !_FS_READONLY -#define FA_WRITE 0x02 -#define FA_CREATE_NEW 0x04 -#define FA_CREATE_ALWAYS 0x08 -#define FA_OPEN_ALWAYS 0x10 -#define FA__WRITTEN 0x20 -#define FA__DIRTY 0x40 -#endif - - -/* FAT sub type (FATFS.fs_type) */ - -#define FS_FAT12 1 -#define FS_FAT16 2 -#define FS_FAT32 3 - - -/* File attribute bits for directory entry */ - -#define AM_RDO 0x01 /* Read only */ -#define AM_HID 0x02 /* Hidden */ -#define AM_SYS 0x04 /* System */ -#define AM_VOL 0x08 /* Volume label */ -#define AM_LFN 0x0F /* LFN entry */ -#define AM_DIR 0x10 /* Directory */ -#define AM_ARC 0x20 /* Archive */ -#define AM_MASK 0x3F /* Mask of defined bits */ - - -/* Fast seek feature */ -#define CREATE_LINKMAP 0xFFFFFFFF - - - -/*--------------------------------*/ -/* Multi-byte word access macros */ - -#if _WORD_ACCESS == 1 /* Enable word access to the FAT structure */ -#define LD_WORD(ptr) (WORD)(*(WORD*)(BYTE*)(ptr)) -#define LD_DWORD(ptr) (DWORD)(*(DWORD*)(BYTE*)(ptr)) -#define ST_WORD(ptr,val) *(WORD*)(BYTE*)(ptr)=(WORD)(val) -#define ST_DWORD(ptr,val) *(DWORD*)(BYTE*)(ptr)=(DWORD)(val) -#else /* Use byte-by-byte access to the FAT structure */ -#define LD_WORD(ptr) (WORD)(((WORD)*((BYTE*)(ptr)+1)<<8)|(WORD)*(BYTE*)(ptr)) -#define LD_DWORD(ptr) (DWORD)(((DWORD)*((BYTE*)(ptr)+3)<<24)|((DWORD)*((BYTE*)(ptr)+2)<<16)|((WORD)*((BYTE*)(ptr)+1)<<8)|*(BYTE*)(ptr)) -#define ST_WORD(ptr,val) *(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8) -#define ST_DWORD(ptr,val) *(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8); *((BYTE*)(ptr)+2)=(BYTE)((DWORD)(val)>>16); *((BYTE*)(ptr)+3)=(BYTE)((DWORD)(val)>>24) -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* _FATFS */ diff --git a/stm/fatfs/ffconf.h b/stm/fatfs/ffconf.h deleted file mode 100644 index 2d075a68b..000000000 --- a/stm/fatfs/ffconf.h +++ /dev/null @@ -1,212 +0,0 @@ -/*---------------------------------------------------------------------------/ -/ FatFs - FAT file system module configuration file R0.10 (C)ChaN, 2013 -/----------------------------------------------------------------------------/ -/ -/ CAUTION! Do not forget to make clean the project after any changes to -/ the configuration options. -/ -/----------------------------------------------------------------------------*/ -#ifndef _FFCONF -#define _FFCONF 80960 /* Revision ID */ - -#include "mpconfigport.h" - -/*---------------------------------------------------------------------------/ -/ Functions and Buffer Configurations -/----------------------------------------------------------------------------*/ - -#define _FS_TINY 1 /* 0:Normal or 1:Tiny */ -/* When _FS_TINY is set to 1, FatFs uses the sector buffer in the file system -/ object instead of the sector buffer in the individual file object for file -/ data transfer. This reduces memory consumption 512 bytes each file object. */ - - -#define _FS_READONLY 0 /* 0:Read/Write or 1:Read only */ -/* Setting _FS_READONLY to 1 defines read only configuration. This removes -/ writing functions, f_write(), f_sync(), f_unlink(), f_mkdir(), f_chmod(), -/ f_rename(), f_truncate() and useless f_getfree(). */ - - -#define _FS_MINIMIZE 0 /* 0 to 3 */ -/* The _FS_MINIMIZE option defines minimization level to remove API functions. -/ -/ 0: All basic functions are enabled. -/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_chmod(), f_utime(), -/ f_truncate() and f_rename() function are removed. -/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1. -/ 3: f_lseek() function is removed in addition to 2. */ - - -#define _USE_STRFUNC 0 /* 0:Disable or 1-2:Enable */ -/* To enable string functions, set _USE_STRFUNC to 1 or 2. */ - - -#define _USE_MKFS 1 /* 0:Disable or 1:Enable */ -/* To enable f_mkfs() function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */ - - -#define _USE_FASTSEEK 0 /* 0:Disable or 1:Enable */ -/* To enable fast seek feature, set _USE_FASTSEEK to 1. */ - - -#define _USE_LABEL 0 /* 0:Disable or 1:Enable */ -/* To enable volume label functions, set _USE_LAVEL to 1 */ - - -#define _USE_FORWARD 0 /* 0:Disable or 1:Enable */ -/* To enable f_forward() function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */ - - -/*---------------------------------------------------------------------------/ -/ Locale and Namespace Configurations -/----------------------------------------------------------------------------*/ - -#define _CODE_PAGE (MICROPY_LFN_CODE_PAGE) -/* The _CODE_PAGE specifies the OEM code page to be used on the target system. -/ Incorrect setting of the code page can cause a file open failure. -/ -/ 932 - Japanese Shift-JIS (DBCS, OEM, Windows) -/ 936 - Simplified Chinese GBK (DBCS, OEM, Windows) -/ 949 - Korean (DBCS, OEM, Windows) -/ 950 - Traditional Chinese Big5 (DBCS, OEM, Windows) -/ 1250 - Central Europe (Windows) -/ 1251 - Cyrillic (Windows) -/ 1252 - Latin 1 (Windows) -/ 1253 - Greek (Windows) -/ 1254 - Turkish (Windows) -/ 1255 - Hebrew (Windows) -/ 1256 - Arabic (Windows) -/ 1257 - Baltic (Windows) -/ 1258 - Vietnam (OEM, Windows) -/ 437 - U.S. (OEM) -/ 720 - Arabic (OEM) -/ 737 - Greek (OEM) -/ 775 - Baltic (OEM) -/ 850 - Multilingual Latin 1 (OEM) -/ 858 - Multilingual Latin 1 + Euro (OEM) -/ 852 - Latin 2 (OEM) -/ 855 - Cyrillic (OEM) -/ 866 - Russian (OEM) -/ 857 - Turkish (OEM) -/ 862 - Hebrew (OEM) -/ 874 - Thai (OEM, Windows) -/ 1 - ASCII (Valid for only non-LFN cfg.) -*/ - -#define _USE_LFN (MICROPY_ENABLE_LFN) /* 0 to 3 */ -#define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */ -/* The _USE_LFN option switches the LFN feature. -/ -/ 0: Disable LFN feature. _MAX_LFN has no effect. -/ 1: Enable LFN with static working buffer on the BSS. Always NOT reentrant. -/ 2: Enable LFN with dynamic working buffer on the STACK. -/ 3: Enable LFN with dynamic working buffer on the HEAP. -/ -/ To enable LFN feature, Unicode handling functions ff_convert() and ff_wtoupper() -/ function must be added to the project. -/ The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. When use stack for the -/ working buffer, take care on stack overflow. When use heap memory for the working -/ buffer, memory management functions, ff_memalloc() and ff_memfree(), must be added -/ to the project. */ - - -#define _LFN_UNICODE 0 /* 0:ANSI/OEM or 1:Unicode */ -/* To switch the character encoding on the FatFs API to Unicode, enable LFN feature -/ and set _LFN_UNICODE to 1. */ - - -#define _STRF_ENCODE 3 /* 0:ANSI/OEM, 1:UTF-16LE, 2:UTF-16BE, 3:UTF-8 */ -/* When Unicode API is enabled, character encoding on the all FatFs API is switched -/ to Unicode. This option selects the character encoding on the file to be read/written -/ via string functions, f_gets(), f_putc(), f_puts and f_printf(). -/ This option has no effect when _LFN_UNICODE is 0. */ - - -#define _FS_RPATH 0 /* 0 to 2 */ -/* The _FS_RPATH option configures relative path feature. -/ -/ 0: Disable relative path feature and remove related functions. -/ 1: Enable relative path. f_chdrive() and f_chdir() function are available. -/ 2: f_getcwd() function is available in addition to 1. -/ -/ Note that output of the f_readdir() fnction is affected by this option. */ - - -/*---------------------------------------------------------------------------/ -/ Drive/Volume Configurations -/----------------------------------------------------------------------------*/ - -#define _VOLUMES 2 -/* Number of volumes (logical drives) to be used. */ - - -#define _MULTI_PARTITION 1 /* 0:Single partition, 1:Enable multiple partition */ -/* When set to 0, each volume is bound to the same physical drive number and -/ it can mount only first primaly partition. When it is set to 1, each volume -/ is tied to the partitions listed in VolToPart[]. */ - - -#define _MAX_SS 512 /* 512, 1024, 2048 or 4096 */ -/* Maximum sector size to be handled. -/ Always set 512 for memory card and hard disk but a larger value may be -/ required for on-board flash memory, floppy disk and optical disk. -/ When _MAX_SS is larger than 512, it configures FatFs to variable sector size -/ and GET_SECTOR_SIZE command must be implemented to the disk_ioctl() function. */ - - -#define _USE_ERASE 0 /* 0:Disable or 1:Enable */ -/* To enable sector erase feature, set _USE_ERASE to 1. Also CTRL_ERASE_SECTOR command -/ should be added to the disk_ioctl() function. */ - - -#define _FS_NOFSINFO 0 /* 0 or 1 */ -/* If you need to know the correct free space on the FAT32 volume, set this -/ option to 1 and f_getfree() function at first time after volume mount will -/ force a full FAT scan. -/ -/ 0: Load all informations in the FSINFO if available. -/ 1: Do not trust free cluster count in the FSINFO. -*/ - - - -/*---------------------------------------------------------------------------/ -/ System Configurations -/----------------------------------------------------------------------------*/ - -#define _WORD_ACCESS 0 /* 0 or 1 */ -/* The _WORD_ACCESS option is an only platform dependent option. It defines -/ which access method is used to the word data on the FAT volume. -/ -/ 0: Byte-by-byte access. Always compatible with all platforms. -/ 1: Word access. Do not choose this unless under both the following conditions. -/ -/ * Byte order on the memory is little-endian. -/ * Address miss-aligned word access is always allowed for all instructions. -/ -/ If it is the case, _WORD_ACCESS can also be set to 1 to improve performance -/ and reduce code size. -*/ - - -/* A header file that defines sync object types on the O/S, such as -/ windows.h, ucos_ii.h and semphr.h, must be included prior to ff.h. */ - -#define _FS_REENTRANT 0 /* 0:Disable or 1:Enable */ -#define _FS_TIMEOUT 1000 /* Timeout period in unit of time ticks */ -#define _SYNC_t HANDLE /* O/S dependent type of sync object. e.g. HANDLE, OS_EVENT*, ID and etc.. */ - -/* The _FS_REENTRANT option switches the re-entrancy (thread safe) of the FatFs module. -/ -/ 0: Disable re-entrancy. _SYNC_t and _FS_TIMEOUT have no effect. -/ 1: Enable re-entrancy. Also user provided synchronization handlers, -/ ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj() -/ function must be added to the project. */ - - -#define _FS_LOCK 0 /* 0:Disable or >=1:Enable */ -/* To enable file lock control feature, set _FS_LOCK to 1 or greater. - The value defines how many files can be opened simultaneously. */ - - -#endif /* _FFCONFIG */ diff --git a/stm/fatfs/integer.h b/stm/fatfs/integer.h deleted file mode 100644 index 074a46bd5..000000000 --- a/stm/fatfs/integer.h +++ /dev/null @@ -1,33 +0,0 @@ -/*-------------------------------------------*/ -/* Integer type definitions for FatFs module */ -/*-------------------------------------------*/ - -#ifndef _FF_INTEGER -#define _FF_INTEGER - -#ifdef _WIN32 /* FatFs development platform */ - -#include -#include - -#else /* Embedded platform */ - -/* This type MUST be 8 bit */ -typedef unsigned char BYTE; - -/* These types MUST be 16 bit */ -typedef short SHORT; -typedef unsigned short WORD; -typedef unsigned short WCHAR; - -/* These types MUST be 16 bit or 32 bit */ -typedef int INT; -typedef unsigned int UINT; - -/* These types MUST be 32 bit */ -typedef long LONG; -typedef unsigned long DWORD; - -#endif - -#endif diff --git a/stm/file.c b/stm/file.c deleted file mode 100644 index 44210d59d..000000000 --- a/stm/file.c +++ /dev/null @@ -1,97 +0,0 @@ -#include -#include - -#include "misc.h" -#include "mpconfig.h" -#include "qstr.h" -#include "obj.h" -#include "file.h" -#include "ff.h" - -typedef struct _pyb_file_obj_t { - mp_obj_base_t base; - FIL fp; -} pyb_file_obj_t; - -void file_obj_print(void (*print)(void *env, const char *fmt, ...), void *env, mp_obj_t self_in, mp_print_kind_t kind) { - printf("", self_in); -} - -mp_obj_t file_obj_read(mp_obj_t self_in, mp_obj_t arg) { - pyb_file_obj_t *self = self_in; - int n = mp_obj_get_int(arg); - byte *buf = m_new(byte, n); - UINT n_out; - f_read(&self->fp, buf, n, &n_out); - return mp_obj_new_str(buf, n_out, false); -} - -mp_obj_t file_obj_write(mp_obj_t self_in, mp_obj_t arg) { - pyb_file_obj_t *self = self_in; - uint l; - const char *s = mp_obj_str_get_data(arg, &l); - UINT n_out; - FRESULT res = f_write(&self->fp, s, l, &n_out); - if (res != FR_OK) { - printf("File error: could not write to file; error code %d\n", res); - } else if (n_out != l) { - printf("File error: could not write all data to file; wrote %d / %d bytes\n", n_out, l); - } - return mp_const_none; -} - -mp_obj_t file_obj_close(mp_obj_t self_in) { - pyb_file_obj_t *self = self_in; - f_close(&self->fp); - return mp_const_none; -} - -static MP_DEFINE_CONST_FUN_OBJ_2(file_obj_read_obj, file_obj_read); -static MP_DEFINE_CONST_FUN_OBJ_2(file_obj_write_obj, file_obj_write); -static MP_DEFINE_CONST_FUN_OBJ_1(file_obj_close_obj, file_obj_close); - -// TODO gc hook to close the file if not already closed - -STATIC const mp_map_elem_t file_locals_dict_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR_read), (mp_obj_t)&file_obj_read_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_write), (mp_obj_t)&file_obj_write_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_close), (mp_obj_t)&file_obj_close_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR___del__), (mp_obj_t)&file_obj_close_obj }, -}; - -STATIC MP_DEFINE_CONST_DICT(file_locals_dict, file_locals_dict_table); - -static const mp_obj_type_t file_obj_type = { - { &mp_type_type }, - .name = MP_QSTR_File, - .print = file_obj_print, - .locals_dict = (mp_obj_t)&file_locals_dict, -}; - -mp_obj_t pyb_io_open(mp_obj_t o_filename, mp_obj_t o_mode) { - const char *filename = mp_obj_str_get_str(o_filename); - const char *mode = mp_obj_str_get_str(o_mode); - pyb_file_obj_t *self = m_new_obj_with_finaliser(pyb_file_obj_t); - self->base.type = &file_obj_type; - if (mode[0] == 'r') { - // open for reading - FRESULT res = f_open(&self->fp, filename, FA_READ); - if (res != FR_OK) { - printf("FileNotFoundError: [Errno 2] No such file or directory: '%s'\n", filename); - return mp_const_none; - } - } else if (mode[0] == 'w') { - // open for writing, truncate the file first - FRESULT res = f_open(&self->fp, filename, FA_WRITE | FA_CREATE_ALWAYS); - if (res != FR_OK) { - printf("?FileError: could not create file: '%s'\n", filename); - return mp_const_none; - } - } else { - printf("ValueError: invalid mode: '%s'\n", mode); - return mp_const_none; - } - return self; -} - -MP_DEFINE_CONST_FUN_OBJ_2(mp_builtin_open_obj, pyb_io_open); diff --git a/stm/file.h b/stm/file.h deleted file mode 100644 index 3845635de..000000000 --- a/stm/file.h +++ /dev/null @@ -1 +0,0 @@ -mp_obj_t pyb_io_open(mp_obj_t o_filename, mp_obj_t o_mode); diff --git a/stm/flash.c b/stm/flash.c deleted file mode 100644 index 24dd3a1dc..000000000 --- a/stm/flash.c +++ /dev/null @@ -1,121 +0,0 @@ -#include -#include -#include -#include "flash.h" - -/* Base address of the Flash sectors */ -#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */ -#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */ -#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbytes */ -#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbytes */ -#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbytes */ -#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08020000) /* Base @ of Sector 5, 128 Kbytes */ -#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08040000) /* Base @ of Sector 6, 128 Kbytes */ -#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x08060000) /* Base @ of Sector 7, 128 Kbytes */ -#define ADDR_FLASH_SECTOR_8 ((uint32_t)0x08080000) /* Base @ of Sector 8, 128 Kbytes */ -#define ADDR_FLASH_SECTOR_9 ((uint32_t)0x080A0000) /* Base @ of Sector 9, 128 Kbytes */ -#define ADDR_FLASH_SECTOR_10 ((uint32_t)0x080C0000) /* Base @ of Sector 10, 128 Kbytes */ -#define ADDR_FLASH_SECTOR_11 ((uint32_t)0x080E0000) /* Base @ of Sector 11, 128 Kbytes */ - -static const uint32_t flash_info_table[26] = { - ADDR_FLASH_SECTOR_0, FLASH_Sector_0, - ADDR_FLASH_SECTOR_1, FLASH_Sector_1, - ADDR_FLASH_SECTOR_2, FLASH_Sector_2, - ADDR_FLASH_SECTOR_3, FLASH_Sector_3, - ADDR_FLASH_SECTOR_4, FLASH_Sector_4, - ADDR_FLASH_SECTOR_5, FLASH_Sector_5, - ADDR_FLASH_SECTOR_6, FLASH_Sector_6, - ADDR_FLASH_SECTOR_7, FLASH_Sector_7, - ADDR_FLASH_SECTOR_8, FLASH_Sector_8, - ADDR_FLASH_SECTOR_9, FLASH_Sector_9, - ADDR_FLASH_SECTOR_10, FLASH_Sector_10, - ADDR_FLASH_SECTOR_11, FLASH_Sector_11, - ADDR_FLASH_SECTOR_11 + 0x20000, 0, -}; - -uint32_t flash_get_sector_info(uint32_t addr, uint32_t *start_addr, uint32_t *size) { - if (addr >= flash_info_table[0]) { - for (int i = 0; i < 24; i += 2) { - if (addr < flash_info_table[i + 2]) { - if (start_addr != NULL) { - *start_addr = flash_info_table[i]; - } - if (size != NULL) { - *size = flash_info_table[i + 2] - flash_info_table[i]; - } - return flash_info_table[i + 1]; - } - } - } - return 0; -} - -#if 0 -/** - * @brief Gets the sector of a given address - * @param None - * @retval The sector of a given address - */ -uint32_t flash_get_sector(uint32_t addr) { - if ((addr < ADDR_FLASH_SECTOR_1) && (addr >= ADDR_FLASH_SECTOR_0)) { - return FLASH_Sector_0; - } else if ((addr < ADDR_FLASH_SECTOR_2) && (addr >= ADDR_FLASH_SECTOR_1)) { - return FLASH_Sector_1; - } else if ((addr < ADDR_FLASH_SECTOR_3) && (addr >= ADDR_FLASH_SECTOR_2)) { - return FLASH_Sector_2; - } else if ((addr < ADDR_FLASH_SECTOR_4) && (addr >= ADDR_FLASH_SECTOR_3)) { - return FLASH_Sector_3; - } else if ((addr < ADDR_FLASH_SECTOR_5) && (addr >= ADDR_FLASH_SECTOR_4)) { - return FLASH_Sector_4; - } else if ((addr < ADDR_FLASH_SECTOR_6) && (addr >= ADDR_FLASH_SECTOR_5)) { - return FLASH_Sector_5; - } else if ((addr < ADDR_FLASH_SECTOR_7) && (addr >= ADDR_FLASH_SECTOR_6)) { - return FLASH_Sector_6; - } else if ((addr < ADDR_FLASH_SECTOR_8) && (addr >= ADDR_FLASH_SECTOR_7)) { - return FLASH_Sector_7; - } else if ((addr < ADDR_FLASH_SECTOR_9) && (addr >= ADDR_FLASH_SECTOR_8)) { - return FLASH_Sector_8; - } else if ((addr < ADDR_FLASH_SECTOR_10) && (addr >= ADDR_FLASH_SECTOR_9)) { - return FLASH_Sector_9; - } else if ((addr < ADDR_FLASH_SECTOR_11) && (addr >= ADDR_FLASH_SECTOR_10)) { - return FLASH_Sector_10; - } else { - return FLASH_Sector_11; - } -} -#endif - -void flash_write(uint32_t flash_dest, const uint32_t *src, uint32_t num_word32) { - // unlock - FLASH_Unlock(); - - // Clear pending flags (if any) - FLASH_ClearFlag(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | - FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR|FLASH_FLAG_PGSERR); - - // Device voltage range supposed to be [2.7V to 3.6V], the operation will be done by word - if (FLASH_EraseSector(flash_get_sector_info(flash_dest, NULL, NULL), VoltageRange_3) != FLASH_COMPLETE) { - /* Error occurred while sector erase. - User can add here some code to deal with this error */ - return; - } - - /* Program the user Flash area word by word ********************************/ - - for (int i = 0; i < num_word32; i++) { - if (FLASH_ProgramWord(flash_dest, *src) == FLASH_COMPLETE) - { - flash_dest += 4; - src += 1; - } - else - { - /* Error occurred while writing data in Flash memory. - User can add here some code to deal with this error */ - return; - } - } - - // lock - FLASH_Lock(); -} diff --git a/stm/flash.h b/stm/flash.h deleted file mode 100644 index 33d31df7a..000000000 --- a/stm/flash.h +++ /dev/null @@ -1,2 +0,0 @@ -uint32_t flash_get_sector_info(uint32_t addr, uint32_t *start_addr, uint32_t *size); -void flash_write(uint32_t flash_dest, const uint32_t *src, uint32_t num_word32); diff --git a/stm/font_petme128_8x8.h b/stm/font_petme128_8x8.h deleted file mode 100644 index 923348ecc..000000000 --- a/stm/font_petme128_8x8.h +++ /dev/null @@ -1,98 +0,0 @@ -const uint8_t font_petme128_8x8[] = { - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, // 32= - 0x00,0x00,0x00,0x4f,0x4f,0x00,0x00,0x00, // 33=! - 0x00,0x07,0x07,0x00,0x00,0x07,0x07,0x00, // 34=" - 0x14,0x7f,0x7f,0x14,0x14,0x7f,0x7f,0x14, // 35=# - 0x00,0x24,0x2e,0x6b,0x6b,0x3a,0x12,0x00, // 36=$ - 0x00,0x63,0x33,0x18,0x0c,0x66,0x63,0x00, // 37=% - 0x00,0x32,0x7f,0x4d,0x4d,0x77,0x72,0x50, // 38=& - 0x00,0x00,0x00,0x04,0x06,0x03,0x01,0x00, // 39=' - 0x00,0x00,0x1c,0x3e,0x63,0x41,0x00,0x00, // 40=( - 0x00,0x00,0x41,0x63,0x3e,0x1c,0x00,0x00, // 41=) - 0x08,0x2a,0x3e,0x1c,0x1c,0x3e,0x2a,0x08, // 42=* - 0x00,0x08,0x08,0x3e,0x3e,0x08,0x08,0x00, // 43=+ - 0x00,0x00,0x80,0xe0,0x60,0x00,0x00,0x00, // 44=, - 0x00,0x08,0x08,0x08,0x08,0x08,0x08,0x00, // 45=- - 0x00,0x00,0x00,0x60,0x60,0x00,0x00,0x00, // 46=. - 0x00,0x40,0x60,0x30,0x18,0x0c,0x06,0x02, // 47=/ - 0x00,0x3e,0x7f,0x49,0x45,0x7f,0x3e,0x00, // 48=0 - 0x00,0x40,0x44,0x7f,0x7f,0x40,0x40,0x00, // 49=1 - 0x00,0x62,0x73,0x51,0x49,0x4f,0x46,0x00, // 50=2 - 0x00,0x22,0x63,0x49,0x49,0x7f,0x36,0x00, // 51=3 - 0x00,0x18,0x18,0x14,0x16,0x7f,0x7f,0x10, // 52=4 - 0x00,0x27,0x67,0x45,0x45,0x7d,0x39,0x00, // 53=5 - 0x00,0x3e,0x7f,0x49,0x49,0x7b,0x32,0x00, // 54=6 - 0x00,0x03,0x03,0x79,0x7d,0x07,0x03,0x00, // 55=7 - 0x00,0x36,0x7f,0x49,0x49,0x7f,0x36,0x00, // 56=8 - 0x00,0x26,0x6f,0x49,0x49,0x7f,0x3e,0x00, // 57=9 - 0x00,0x00,0x00,0x24,0x24,0x00,0x00,0x00, // 58=: - 0x00,0x00,0x80,0xe4,0x64,0x00,0x00,0x00, // 59=; - 0x00,0x08,0x1c,0x36,0x63,0x41,0x41,0x00, // 60=< - 0x00,0x14,0x14,0x14,0x14,0x14,0x14,0x00, // 61== - 0x00,0x41,0x41,0x63,0x36,0x1c,0x08,0x00, // 62=> - 0x00,0x02,0x03,0x51,0x59,0x0f,0x06,0x00, // 63=? - 0x00,0x3e,0x7f,0x41,0x4d,0x4f,0x2e,0x00, // 64=@ - 0x00,0x7c,0x7e,0x0b,0x0b,0x7e,0x7c,0x00, // 65=A - 0x00,0x7f,0x7f,0x49,0x49,0x7f,0x36,0x00, // 66=B - 0x00,0x3e,0x7f,0x41,0x41,0x63,0x22,0x00, // 67=C - 0x00,0x7f,0x7f,0x41,0x63,0x3e,0x1c,0x00, // 68=D - 0x00,0x7f,0x7f,0x49,0x49,0x41,0x41,0x00, // 69=E - 0x00,0x7f,0x7f,0x09,0x09,0x01,0x01,0x00, // 70=F - 0x00,0x3e,0x7f,0x41,0x49,0x7b,0x3a,0x00, // 71=G - 0x00,0x7f,0x7f,0x08,0x08,0x7f,0x7f,0x00, // 72=H - 0x00,0x00,0x41,0x7f,0x7f,0x41,0x00,0x00, // 73=I - 0x00,0x20,0x60,0x41,0x7f,0x3f,0x01,0x00, // 74=J - 0x00,0x7f,0x7f,0x1c,0x36,0x63,0x41,0x00, // 75=K - 0x00,0x7f,0x7f,0x40,0x40,0x40,0x40,0x00, // 76=L - 0x00,0x7f,0x7f,0x06,0x0c,0x06,0x7f,0x7f, // 77=M - 0x00,0x7f,0x7f,0x0e,0x1c,0x7f,0x7f,0x00, // 78=N - 0x00,0x3e,0x7f,0x41,0x41,0x7f,0x3e,0x00, // 79=O - 0x00,0x7f,0x7f,0x09,0x09,0x0f,0x06,0x00, // 80=P - 0x00,0x1e,0x3f,0x21,0x61,0x7f,0x5e,0x00, // 81=Q - 0x00,0x7f,0x7f,0x19,0x39,0x6f,0x46,0x00, // 82=R - 0x00,0x26,0x6f,0x49,0x49,0x7b,0x32,0x00, // 83=S - 0x00,0x01,0x01,0x7f,0x7f,0x01,0x01,0x00, // 84=T - 0x00,0x3f,0x7f,0x40,0x40,0x7f,0x3f,0x00, // 85=U - 0x00,0x1f,0x3f,0x60,0x60,0x3f,0x1f,0x00, // 86=V - 0x00,0x7f,0x7f,0x30,0x18,0x30,0x7f,0x7f, // 87=W - 0x00,0x63,0x77,0x1c,0x1c,0x77,0x63,0x00, // 88=X - 0x00,0x07,0x0f,0x78,0x78,0x0f,0x07,0x00, // 89=Y - 0x00,0x61,0x71,0x59,0x4d,0x47,0x43,0x00, // 90=Z - 0x00,0x00,0x7f,0x7f,0x41,0x41,0x00,0x00, // 91=[ - 0x00,0x02,0x06,0x0c,0x18,0x30,0x60,0x40, // 92='\' - 0x00,0x00,0x41,0x41,0x7f,0x7f,0x00,0x00, // 93=] - 0x00,0x08,0x0c,0x06,0x06,0x0c,0x08,0x00, // 94=^ - 0xc0,0xc0,0xc0,0xc0,0xc0,0xc0,0xc0,0xc0, // 95=_ - 0x00,0x00,0x01,0x03,0x06,0x04,0x00,0x00, // 96=` - 0x00,0x20,0x74,0x54,0x54,0x7c,0x78,0x00, // 97=a - 0x00,0x7f,0x7f,0x44,0x44,0x7c,0x38,0x00, // 98=b - 0x00,0x38,0x7c,0x44,0x44,0x6c,0x28,0x00, // 99=c - 0x00,0x38,0x7c,0x44,0x44,0x7f,0x7f,0x00, // 100=d - 0x00,0x38,0x7c,0x54,0x54,0x5c,0x58,0x00, // 101=e - 0x00,0x08,0x7e,0x7f,0x09,0x03,0x02,0x00, // 102=f - 0x00,0x98,0xbc,0xa4,0xa4,0xfc,0x7c,0x00, // 103=g - 0x00,0x7f,0x7f,0x04,0x04,0x7c,0x78,0x00, // 104=h - 0x00,0x00,0x00,0x7d,0x7d,0x00,0x00,0x00, // 105=i - 0x00,0x40,0xc0,0x80,0x80,0xfd,0x7d,0x00, // 106=j - 0x00,0x7f,0x7f,0x30,0x38,0x6c,0x44,0x00, // 107=k - 0x00,0x00,0x41,0x7f,0x7f,0x40,0x00,0x00, // 108=l - 0x00,0x7c,0x7c,0x18,0x30,0x18,0x7c,0x7c, // 109=m - 0x00,0x7c,0x7c,0x04,0x04,0x7c,0x78,0x00, // 110=n - 0x00,0x38,0x7c,0x44,0x44,0x7c,0x38,0x00, // 111=o - 0x00,0xfc,0xfc,0x24,0x24,0x3c,0x18,0x00, // 112=p - 0x00,0x18,0x3c,0x24,0x24,0xfc,0xfc,0x00, // 113=q - 0x00,0x7c,0x7c,0x04,0x04,0x0c,0x08,0x00, // 114=r - 0x00,0x48,0x5c,0x54,0x54,0x74,0x20,0x00, // 115=s - 0x04,0x04,0x3f,0x7f,0x44,0x64,0x20,0x00, // 116=t - 0x00,0x3c,0x7c,0x40,0x40,0x7c,0x3c,0x00, // 117=u - 0x00,0x1c,0x3c,0x60,0x60,0x3c,0x1c,0x00, // 118=v - 0x00,0x1c,0x7c,0x30,0x18,0x30,0x7c,0x1c, // 119=w - 0x00,0x44,0x6c,0x38,0x38,0x6c,0x44,0x00, // 120=x - 0x00,0x9c,0xbc,0xa0,0xa0,0xfc,0x7c,0x00, // 121=y - 0x00,0x44,0x64,0x74,0x5c,0x4c,0x44,0x00, // 122=z - 0x00,0x08,0x08,0x3e,0x77,0x41,0x41,0x00, // 123={ - 0x00,0x00,0x00,0xff,0xff,0x00,0x00,0x00, // 124=| - 0x00,0x41,0x41,0x77,0x3e,0x08,0x08,0x00, // 125=} - 0x00,0x02,0x03,0x01,0x03,0x02,0x03,0x01, // 126=~ - 0xaa,0x55,0xaa,0x55,0xaa,0x55,0xaa,0x55, // 127 -}; diff --git a/stm/gccollect.c b/stm/gccollect.c deleted file mode 100644 index e4b37f37f..000000000 --- a/stm/gccollect.c +++ /dev/null @@ -1,55 +0,0 @@ -#include - -#include "misc.h" -#include "mpconfig.h" -#include "qstr.h" -#include "obj.h" -#include "gc.h" -#include "gccollect.h" -#include "systick.h" - -machine_uint_t gc_helper_get_regs_and_sp(machine_uint_t *regs); - -// obsolete -// void gc_helper_get_regs_and_clean_stack(machine_uint_t *regs, machine_uint_t heap_end); - -void gc_collect(void) { - // get current time, in case we want to time the GC - uint32_t start = sys_tick_counter; - - // start the GC - gc_collect_start(); - - // scan everything in RAM before the heap - // this includes the data and bss segments - // TODO possibly don't need to scan data, since all pointers should start out NULL and be in bss - gc_collect_root((void**)&_ram_start, ((uint32_t)&_bss_end - (uint32_t)&_ram_start) / sizeof(uint32_t)); - - // get the registers and the sp - machine_uint_t regs[10]; - machine_uint_t sp = gc_helper_get_regs_and_sp(regs); - - // trace the stack, including the registers (since they live on the stack in this function) - gc_collect_root((void**)sp, ((uint32_t)&_ram_end - sp) / sizeof(uint32_t)); - - // end the GC - gc_collect_end(); - - if (0) { - // print GC info - uint32_t ticks = sys_tick_counter - start; // TODO implement a function that does this properly - gc_info_t info; - gc_info(&info); - printf("GC@%lu %lums\n", start, ticks); - printf(" %lu total\n", info.total); - printf(" %lu : %lu\n", info.used, info.free); - printf(" 1=%lu 2=%lu m=%lu\n", info.num_1block, info.num_2block, info.max_block); - } -} - -static mp_obj_t pyb_gc(void) { - gc_collect(); - return mp_const_none; -} - -MP_DEFINE_CONST_FUN_OBJ_0(pyb_gc_obj, pyb_gc); diff --git a/stm/gccollect.h b/stm/gccollect.h deleted file mode 100644 index a6471bf2e..000000000 --- a/stm/gccollect.h +++ /dev/null @@ -1,17 +0,0 @@ -// variables defining memory layout -// (these probably belong somewhere else...) -extern uint32_t _text_end; -extern uint32_t _data_start_init; -extern uint32_t _ram_start; -extern uint32_t _data_start; -extern uint32_t _data_end; -extern uint32_t _bss_start; -extern uint32_t _bss_end; -extern uint32_t _heap_start; -extern uint32_t _heap_end; -extern uint32_t _stack_end; -extern uint32_t _ram_end; - -void gc_collect(void); - -MP_DECLARE_CONST_FUN_OBJ(pyb_gc_obj); diff --git a/stm/gchelper.s b/stm/gchelper.s deleted file mode 100644 index 6baedcdd0..000000000 --- a/stm/gchelper.s +++ /dev/null @@ -1,62 +0,0 @@ - .syntax unified - .cpu cortex-m4 - .thumb - .text - .align 2 - -@ uint gc_helper_get_regs_and_sp(r0=uint regs[10]) - .global gc_helper_get_regs_and_sp - .thumb - .thumb_func - .type gc_helper_get_regs_and_sp, %function -gc_helper_get_regs_and_sp: - @ store registers into given array - str r4, [r0], #4 - str r5, [r0], #4 - str r6, [r0], #4 - str r7, [r0], #4 - str r8, [r0], #4 - str r9, [r0], #4 - str r10, [r0], #4 - str r11, [r0], #4 - str r12, [r0], #4 - str r13, [r0], #4 - - @ return the sp - mov r0, sp - bx lr - - -@ this next function is now obsolete - - .size gc_helper_get_regs_and_clean_stack, .-gc_helper_get_regs_and_clean_stack -@ void gc_helper_get_regs_and_clean_stack(r0=uint regs[10], r1=heap_end) - .global gc_helper_get_regs_and_clean_stack - .thumb - .thumb_func - .type gc_helper_get_regs_and_clean_stack, %function -gc_helper_get_regs_and_clean_stack: - @ store registers into given array - str r4, [r0], #4 - str r5, [r0], #4 - str r6, [r0], #4 - str r7, [r0], #4 - str r8, [r0], #4 - str r9, [r0], #4 - str r10, [r0], #4 - str r11, [r0], #4 - str r12, [r0], #4 - str r13, [r0], #4 - - @ clean the stack from given pointer up to current sp - movs r0, #0 - mov r2, sp - b.n .entry -.loop: - str r0, [r1], #4 -.entry: - cmp r1, r2 - bcc.n .loop - bx lr - - .size gc_helper_get_regs_and_clean_stack, .-gc_helper_get_regs_and_clean_stack diff --git a/stm/gpio.c b/stm/gpio.c deleted file mode 100644 index 936620893..000000000 --- a/stm/gpio.c +++ /dev/null @@ -1,94 +0,0 @@ -// This is a woefully inadequate set of bindings for GPIO control, and -// needs to be replaced with something much better. - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "mpconfig.h" -#include "nlr.h" -#include "misc.h" -#include "qstr.h" -#include "misc.h" -#include "parse.h" -#include "obj.h" -#include "compile.h" -#include "runtime0.h" -#include "runtime.h" -#include "systick.h" -#include "gpio.h" -#include "pin.h" - -mp_obj_t pyb_gpio(uint n_args, mp_obj_t *args) { - //assert(1 <= n_args && n_args <= 2); - - const pin_obj_t *pin = pin_map_user_obj(args[0]); - GPIO_TypeDef *port = pin->gpio; - uint16_t pin_mask = pin->pin_mask; - - if (n_args == 1) { - // get pin - if ((port->IDR & pin_mask) != (uint32_t)Bit_RESET) { - return MP_OBJ_NEW_SMALL_INT(1); - } else { - return MP_OBJ_NEW_SMALL_INT(0); - } - } else { - // set pin - if (mp_obj_is_true(args[1])) { - // set pin high - port->BSRRL = pin_mask; - } else { - // set pin low - port->BSRRH = pin_mask; - } - return mp_const_none; - } -} - -MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_gpio_obj, 1, 2, pyb_gpio); - -mp_obj_t pyb_gpio_input(mp_obj_t arg_pin, mp_obj_t arg_mode) { - const pin_obj_t *pin = pin_map_user_obj(arg_pin); - GPIO_TypeDef *port = pin->gpio; - uint16_t pin_mask = pin->pin_mask; - - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = pin_mask; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_PuPd = mp_obj_get_int(arg_mode); - GPIO_Init(port, &GPIO_InitStructure); - - return mp_const_none; -} - -MP_DEFINE_CONST_FUN_OBJ_2(pyb_gpio_input_obj, pyb_gpio_input); - -mp_obj_t pyb_gpio_output(mp_obj_t arg_pin, mp_obj_t arg_mode) { - const pin_obj_t *pin = pin_map_user_obj(arg_pin); - GPIO_TypeDef *port = pin->gpio; - uint16_t pin_mask = pin->pin_mask; - - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = pin_mask; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_Speed = GPIO_Fast_Speed; - GPIO_InitStructure.GPIO_OType = mp_obj_get_int(arg_mode); - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(port, &GPIO_InitStructure); - - return mp_const_none; -} - -MP_DEFINE_CONST_FUN_OBJ_2(pyb_gpio_output_obj, pyb_gpio_output); diff --git a/stm/gpio.h b/stm/gpio.h deleted file mode 100644 index f48e95347..000000000 --- a/stm/gpio.h +++ /dev/null @@ -1,5 +0,0 @@ -mp_obj_t pyb_gpio_input(mp_obj_t arg_pin, mp_obj_t arg_mode); - -MP_DECLARE_CONST_FUN_OBJ(pyb_gpio_obj); -MP_DECLARE_CONST_FUN_OBJ(pyb_gpio_input_obj); -MP_DECLARE_CONST_FUN_OBJ(pyb_gpio_output_obj); diff --git a/stm/i2c.c b/stm/i2c.c deleted file mode 100644 index 011362cb5..000000000 --- a/stm/i2c.c +++ /dev/null @@ -1,364 +0,0 @@ -#include - -#include - -#include "misc.h" -#include "systick.h" -#include "mpconfig.h" -#include "qstr.h" -#include "obj.h" - -typedef enum { - PYB_I2C_1 = 0, - PYB_I2C_2 = 1, -} pyb_i2c_t; - -typedef enum { - I2C_STATE_IDLE = 0, - I2C_STATE_WRITE = 1, - I2C_STATE_READ = 2, -} i2c_state_t; - -// set to true if the port has already been initialized -bool i2c1_port_initialized = false; -bool i2c2_port_initialized = false; - -static I2C_TypeDef * _i2c_port_addr(pyb_i2c_t i2c_port) { - if (i2c_port == PYB_I2C_1) { - return I2C1; - } - if (i2c_port == PYB_I2C_2) { - return I2C2; - } - return NULL; -} - -// todo - perhaps there should be some global resource management for gpio -// this function would fail if the i2c pins have already been defined for -// use by another python object -// as it is, this always returns true (unless i2c_port is invalid) -static bool _i2c_init(pyb_i2c_t i2c_port) { - GPIO_InitTypeDef GPIO_InitStructure; - - I2C_TypeDef *i2c = _i2c_port_addr(i2c_port); - if (i2c == NULL) - return false; - - if (i2c_port == PYB_I2C_1) { - if (i2c1_port_initialized == true) { - return true; - } - RCC->APB1ENR |= RCC_APB1ENR_I2C1EN; // enable I2C1 - - // PB6=SCL, PB7=SDA - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_25MHz; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(GPIOB, &GPIO_InitStructure); - - // alternate functions for SCL and SDA - GPIO_PinAFConfig(GPIOB, GPIO_PinSource6, GPIO_AF_I2C1); - GPIO_PinAFConfig(GPIOB, GPIO_PinSource7, GPIO_AF_I2C1); - - - i2c1_port_initialized = true; - } - - if (i2c_port == PYB_I2C_2) { - if (i2c2_port_initialized == true) { - return true; - } - RCC->APB1ENR |= RCC_APB1ENR_I2C2EN; // enable I2C2 - - // PB10=SCL, PB11=SDA - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10 | GPIO_Pin_11; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_25MHz; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(GPIOB, &GPIO_InitStructure); - - // alternate functions for SCL and SDA - GPIO_PinAFConfig(GPIOB, GPIO_PinSource10, GPIO_AF_I2C2); - GPIO_PinAFConfig(GPIOB, GPIO_PinSource11, GPIO_AF_I2C2); - - i2c2_port_initialized = true; - } - - // get clock speeds - RCC_ClocksTypeDef rcc_clocks; - RCC_GetClocksFreq(&rcc_clocks); - - // disable the I2C peripheral before we configure it - i2c->CR1 &= ~I2C_CR1_PE; - - // program peripheral input clock - i2c->CR2 = 4; // no interrupts; 4 MHz (hopefully!) (could go up to 42MHz) - - // configure clock control reg - uint32_t freq = rcc_clocks.PCLK1_Frequency / (100000 << 1); // want 100kHz, this is the formula for freq - i2c->CCR = freq; // standard mode (speed), freq calculated as above - - // configure rise time reg - i2c->TRISE = (rcc_clocks.PCLK1_Frequency / 1000000) + 1; // formula for trise, gives maximum rise time - - // enable the I2C peripheral - i2c->CR1 |= I2C_CR1_PE; - - return true; -} - -static uint32_t _i2c_get_sr(pyb_i2c_t i2c_port) { - // must read SR1 first, then SR2, as the read can clear some flags - I2C_TypeDef *i2c = _i2c_port_addr(i2c_port); - if (i2c == NULL) return 0; - - uint32_t sr1 = i2c->SR1; - uint32_t sr2 = i2c->SR2; - return (sr2 << 16) | sr1; -} - -static bool _i2c_restart(pyb_i2c_t i2c_port, uint8_t addr, int write) { - I2C_TypeDef *i2c = _i2c_port_addr(i2c_port); - if (i2c == NULL) return false; - - // send start condition - i2c->CR1 |= I2C_CR1_START; - - // wait for BUSY, MSL and SB --> Slave has acknowledged start condition - uint32_t timeout = 1000000; - while ((_i2c_get_sr(i2c_port) & 0x00030001) != 0x00030001) { - if (--timeout == 0) { - //printf("timeout in _i2c_restart\n"); - return false; - } - } - - if (write) { - // send address and write bit - i2c->DR = (addr << 1) | 0; - // wait for BUSY, MSL, ADDR, TXE and TRA - timeout = 1000000; - while ((_i2c_get_sr(i2c_port) & 0x00070082) != 0x00070082) { - if (--timeout == 0) { - //printf("timeout in _i2c_restart write\n"); - return false; - } - } - } else { - // send address and read bit - i2c->DR = (addr << 1) | 1; - // wait for BUSY, MSL and ADDR flags - timeout = 1000000; - while ((_i2c_get_sr(i2c_port) & 0x00030002) != 0x00030002) { - if (--timeout == 0) { - //printf("timeout in _i2c_restart read\n"); - return false; - } - } - } - return true; -} - -static bool _i2c_send_byte(pyb_i2c_t i2c_port, uint8_t data) { - I2C_TypeDef *i2c = _i2c_port_addr(i2c_port); - if (i2c == NULL) return false; - - // send byte - i2c->DR = data; - // wait for TRA, BUSY, MSL, TXE and BTF (byte transmitted) - uint32_t timeout = 1000000; - while ((_i2c_get_sr(i2c_port) & 0x00070084) != 0x00070084) { - if (--timeout == 0) { - //printf("timeout in _i2c_send_byte\n"); - return false; - } - } - return true; -} - -static uint8_t _i2c_read_ack(pyb_i2c_t i2c_port) { - I2C_TypeDef *i2c = _i2c_port_addr(i2c_port); - if (i2c == NULL) return 0; - - // enable ACK of received byte - i2c->CR1 |= I2C_CR1_ACK; - // wait for BUSY, MSL and RXNE (byte received) - uint32_t timeout = 1000000; - while ((_i2c_get_sr(i2c_port) & 0x00030040) != 0x00030040) { - if (--timeout == 0) { - //printf("timeout in _i2c_read_ack\n"); - break; - } - } - // read and return data - uint8_t data = i2c->DR; - return data; -} - -static uint8_t _i2c_read_nack(pyb_i2c_t i2c_port) { - I2C_TypeDef *i2c = _i2c_port_addr(i2c_port); - if (i2c == NULL) return 0; - - // disable ACK of received byte (to indicate end of receiving) - i2c->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ACK); - // last byte should apparently also generate a stop condition - i2c->CR1 |= I2C_CR1_STOP; - // wait for BUSY, MSL and RXNE (byte received) - uint32_t timeout = 1000000; - while ((_i2c_get_sr(i2c_port) & 0x00030040) != 0x00030040) { - if (--timeout == 0) { - //printf("timeout in _i2c_read_nack\n"); - break; - } - } - // read and return data - uint8_t data = i2c->DR; - return data; -} - -static bool _i2c_start(pyb_i2c_t i2c_port) { - I2C_TypeDef *i2c = _i2c_port_addr(i2c_port); - if (i2c == NULL) return false; - - // wait until I2C is not busy - uint32_t timeout = 1000000; - while (i2c->SR2 & I2C_SR2_BUSY) { - if (--timeout == 0) { - return false; - } - } - return true; -} - -static void _i2c_stop(pyb_i2c_t i2c_port) { - I2C_TypeDef *i2c = _i2c_port_addr(i2c_port); - if (i2c == NULL) return; - - // send stop condition - i2c->CR1 |= I2C_CR1_STOP; -} - -/******************************************************************************/ -/* Micro Python bindings */ - -typedef struct _pyb_i2c_obj_t { - mp_obj_base_t base; - pyb_i2c_t i2c_port; - int i2c_addr; - i2c_state_t i2c_state; -} pyb_i2c_obj_t; - -void i2c_obj_print(void (*print)(void *env, const char *fmt, ...), void *env, mp_obj_t self_in, mp_print_kind_t kind) { - pyb_i2c_obj_t *self = self_in; - print(env, "", (unsigned int)self->i2c_port, (unsigned int)self->i2c_addr); -} - -// calls _i2c_start with write=0,1 depending on LSB of i2c_addr -mp_obj_t i2c_obj_start(mp_obj_t self_in) { - pyb_i2c_obj_t *self = self_in; - if (self->i2c_state != I2C_STATE_IDLE) { - _i2c_stop(self->i2c_port); - self->i2c_state = I2C_STATE_IDLE; - } - if (_i2c_start(self->i2c_port) == true) - return mp_const_true; - return mp_const_false; -} - -mp_obj_t i2c_obj_write(mp_obj_t self_in, mp_obj_t data_in) { - pyb_i2c_obj_t *self = self_in; - if (self->i2c_state != I2C_STATE_WRITE) { - if (_i2c_restart(self->i2c_port, self->i2c_addr, 1) == false) { - _i2c_stop(self->i2c_port); - self->i2c_state = I2C_STATE_IDLE; - return mp_const_false; - } - self->i2c_state = I2C_STATE_WRITE; - } - uint8_t data = mp_obj_get_int(data_in); - if (_i2c_send_byte(self->i2c_port, data) == false) - return mp_const_false; - return mp_const_true; -} - -mp_obj_t i2c_obj_read(mp_obj_t self_in) { - pyb_i2c_obj_t *self = self_in; - if (self->i2c_state != I2C_STATE_READ) { - if (_i2c_restart(self->i2c_port, self->i2c_addr, 0) == false) { - _i2c_stop(self->i2c_port); - self->i2c_state = I2C_STATE_IDLE; - return mp_const_false; - } - self->i2c_state = I2C_STATE_READ; - } - uint8_t data = _i2c_read_ack(self->i2c_port); - return mp_obj_new_int(data); -} - -mp_obj_t i2c_obj_readAndStop(mp_obj_t self_in) { - pyb_i2c_obj_t *self = self_in; - if (self->i2c_state != I2C_STATE_READ) { - if (_i2c_restart(self->i2c_port, self->i2c_addr, 0) == false) { - _i2c_stop(self->i2c_port); - self->i2c_state = I2C_STATE_IDLE; - return mp_const_false; - } - } - uint8_t data = _i2c_read_nack(self->i2c_port); - self->i2c_state = I2C_STATE_IDLE; - return mp_obj_new_int(data); -} - -mp_obj_t i2c_obj_stop(mp_obj_t self_in) { - pyb_i2c_obj_t *self = self_in; - _i2c_stop(self->i2c_port); - self->i2c_state = I2C_STATE_IDLE; - return mp_const_none; -} - -static MP_DEFINE_CONST_FUN_OBJ_1(i2c_obj_start_obj, i2c_obj_start); -static MP_DEFINE_CONST_FUN_OBJ_2(i2c_obj_write_obj, i2c_obj_write); -static MP_DEFINE_CONST_FUN_OBJ_1(i2c_obj_read_obj, i2c_obj_read); -static MP_DEFINE_CONST_FUN_OBJ_1(i2c_obj_readAndStop_obj, i2c_obj_readAndStop); -static MP_DEFINE_CONST_FUN_OBJ_1(i2c_obj_stop_obj, i2c_obj_stop); - -STATIC const mp_map_elem_t i2c_locals_dict_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR_start), (mp_obj_t)&i2c_obj_start_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_write), (mp_obj_t)&i2c_obj_write_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_read), (mp_obj_t)&i2c_obj_read_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_readAndStop), (mp_obj_t)&i2c_obj_readAndStop_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_stop), (mp_obj_t)&i2c_obj_stop_obj }, -}; - -STATIC MP_DEFINE_CONST_DICT(i2c_locals_dict, i2c_locals_dict_table); - -static const mp_obj_type_t i2c_obj_type = { - { &mp_type_type }, - .name = MP_QSTR_I2C, - .print = i2c_obj_print, - .locals_dict = (mp_obj_t)&i2c_locals_dict, -}; - -// create the I2C object -// currently support either I2C1 (i2c_id = 0) or I2C2 (i2c_id = 1) - -mp_obj_t pyb_I2C(mp_obj_t i2c_id, mp_obj_t i2c_addr) { - pyb_i2c_t i2c_port; - switch(mp_obj_get_int(i2c_id)) { - case 0: i2c_port = PYB_I2C_1; break; - case 1: i2c_port = PYB_I2C_2; break; - default: return mp_const_none; - } - if (_i2c_init(i2c_port) == false) { - return mp_const_none; - } - pyb_i2c_obj_t *o = m_new_obj(pyb_i2c_obj_t); - o->base.type = &i2c_obj_type; - o->i2c_port = i2c_port; - o->i2c_addr = mp_obj_get_int(i2c_addr); - o->i2c_state = I2C_STATE_IDLE; - return o; -} diff --git a/stm/i2c.h b/stm/i2c.h deleted file mode 100644 index eacb7528c..000000000 --- a/stm/i2c.h +++ /dev/null @@ -1 +0,0 @@ -mp_obj_t pyb_I2C(mp_obj_t i2c_id, mp_obj_t i2c_addr); diff --git a/stm/import.c b/stm/import.c deleted file mode 100644 index 3d62c6425..000000000 --- a/stm/import.c +++ /dev/null @@ -1,20 +0,0 @@ -#include - -#include "misc.h" -#include "mpconfig.h" -#include "qstr.h" -#include "lexer.h" -#include "ff.h" - -mp_import_stat_t mp_import_stat(const char *path) { - FILINFO fno; - FRESULT res = f_stat(path, &fno); - if (res == FR_OK) { - if ((fno.fattrib & AM_DIR) != 0) { - return MP_IMPORT_STAT_DIR; - } else { - return MP_IMPORT_STAT_FILE; - } - } - return MP_IMPORT_STAT_NO_EXIST; -} diff --git a/stm/lcd.c b/stm/lcd.c deleted file mode 100644 index 44c4833a5..000000000 --- a/stm/lcd.c +++ /dev/null @@ -1,385 +0,0 @@ -#include -#include - -#include "mpconfig.h" -#include "nlr.h" -#include "misc.h" - -#if MICROPY_HW_HAS_LCD - -#include "qstr.h" -#include "parse.h" -#include "obj.h" -#include "runtime.h" - -#include "systick.h" -#include "font_petme128_8x8.h" -#include "lcd.h" - -#if defined(PYBOARD3) -#define PYB_LCD_PORT (GPIOA) -#define PYB_LCD_CS1_PIN (GPIO_Pin_0) -#define PYB_LCD_RST_PIN (GPIO_Pin_1) -#define PYB_LCD_A0_PIN (GPIO_Pin_2) -#define PYB_LCD_SCL_PIN (GPIO_Pin_3) -#define PYB_LCD_SI_PIN (GPIO_Pin_4) -#elif defined(PYBOARD4) -// X position -#define PYB_LCD_PORT (GPIOA) -#define PYB_LCD_CS1_PIN (GPIO_Pin_2) // X3 -#define PYB_LCD_RST_PIN (GPIO_Pin_3) // X4 -#define PYB_LCD_A0_PIN (GPIO_Pin_4) // X5 -#define PYB_LCD_SCL_PIN (GPIO_Pin_5) // X6 -#define PYB_LCD_SI_PIN (GPIO_Pin_7) // X8 -#define PYB_LCD_BL_PORT (GPIOC) -#define PYB_LCD_BL_PIN (GPIO_Pin_5) // X12 -/* -// Y position -#define PYB_LCD_PORT (GPIOB) -#define PYB_LCD_CS1_PIN (GPIO_Pin_8) // Y3 = PB8 -#define PYB_LCD_RST_PIN (GPIO_Pin_9) // Y4 = PB9 -#define PYB_LCD_A0_PIN (GPIO_Pin_12) // Y5 = PB12 -#define PYB_LCD_SCL_PIN (GPIO_Pin_13) // Y6 = PB13 -#define PYB_LCD_SI_PIN (GPIO_Pin_15) // Y8 = PB15 -#define PYB_LCD_BL_PORT (GPIOB) -#define PYB_LCD_BL_PIN (GPIO_Pin_1) // Y12 = PB1 -*/ -#elif defined(STM32F4DISC) -/* Configure if needed */ -#define PYB_LCD_PORT (GPIOA) -#define PYB_LCD_CS1_PIN (GPIO_Pin_2) // X3 -#define PYB_LCD_RST_PIN (GPIO_Pin_3) // X4 -#define PYB_LCD_A0_PIN (GPIO_Pin_4) // X5 -#define PYB_LCD_SCL_PIN (GPIO_Pin_5) // X6 -#define PYB_LCD_SI_PIN (GPIO_Pin_7) // X8 -#define PYB_LCD_BL_PORT (GPIOC) -#define PYB_LCD_BL_PIN (GPIO_Pin_5) // X12 -#endif - -#define LCD_INSTR (0) -#define LCD_DATA (1) - -static void lcd_out(int instr_data, uint8_t i) { - sys_tick_delay_ms(0); - PYB_LCD_PORT->BSRRH = PYB_LCD_CS1_PIN; // CS=0; enable - if (instr_data == LCD_INSTR) { - PYB_LCD_PORT->BSRRH = PYB_LCD_A0_PIN; // A0=0; select instr reg - } else { - PYB_LCD_PORT->BSRRL = PYB_LCD_A0_PIN; // A0=1; select data reg - } - // send byte bigendian, latches on rising clock - for (uint32_t n = 0; n < 8; n++) { - sys_tick_delay_ms(0); - PYB_LCD_PORT->BSRRH = PYB_LCD_SCL_PIN; // SCL=0 - if ((i & 0x80) == 0) { - PYB_LCD_PORT->BSRRH = PYB_LCD_SI_PIN; // SI=0 - } else { - PYB_LCD_PORT->BSRRL = PYB_LCD_SI_PIN; // SI=1 - } - i <<= 1; - sys_tick_delay_ms(0); - PYB_LCD_PORT->BSRRL = PYB_LCD_SCL_PIN; // SCL=1 - } - PYB_LCD_PORT->BSRRL = PYB_LCD_CS1_PIN; // CS=1; disable - - /* - in Python, native types: - CS1_PIN(const) = 0 - n = int(0) - delay_ms(0) - PORT[word:BSRRH] = 1 << CS1_PIN - for n in range(0, 8): - delay_ms(0) - PORT[word:BSRRH] = 1 << SCL_PIN - if i & 0x80 == 0: - PORT[word:BSRRH] = 1 << SI_PIN - else: - PORT[word:BSRRL] = 1 << SI_PIN - i <<= 1 - delay_ms(0) - PORT[word:BSRRL] = 1 << SCL_PIN - */ -} - -/* -static void lcd_data_out(uint8_t i) { - delay_ms(0); - PYB_LCD_PORT->BSRRH = PYB_LCD_CS1_PIN; // CS=0; enable - PYB_LCD_PORT->BSRRL = PYB_LCD_A0_PIN; // A0=1; select data reg - // send byte bigendian, latches on rising clock - for (uint32_t n = 0; n < 8; n++) { - delay_ms(0); - PYB_LCD_PORT->BSRRH = PYB_LCD_SCL_PIN; // SCL=0 - if ((i & 0x80) == 0) { - PYB_LCD_PORT->BSRRH = PYB_LCD_SI_PIN; // SI=0 - } else { - PYB_LCD_PORT->BSRRL = PYB_LCD_SI_PIN; // SI=1 - } - i <<= 1; - delay_ms(0); - PYB_LCD_PORT->BSRRL = PYB_LCD_SCL_PIN; // SCL=1 - } - PYB_LCD_PORT->BSRRL = PYB_LCD_CS1_PIN; // CS=1; disable -} -*/ - -// writes 8 vertical pixels -// pos 0 is upper left, pos 1 is 8 pixels to right of that, pos 128 is 8 pixels below that -mp_obj_t lcd_draw_pixel_8(mp_obj_t mp_pos, mp_obj_t mp_val) { - int pos = mp_obj_get_int(mp_pos); - int val = mp_obj_get_int(mp_val); - int page = pos / 128; - int offset = pos - (page * 128); - lcd_out(LCD_INSTR, 0xb0 | page); // page address set - lcd_out(LCD_INSTR, 0x10 | ((offset >> 4) & 0x0f)); // column address set upper - lcd_out(LCD_INSTR, 0x00 | (offset & 0x0f)); // column address set lower - lcd_out(LCD_DATA, val); // write data - return mp_const_none; -} - -#define LCD_BUF_W (16) -#define LCD_BUF_H (4) - -char lcd_char_buffer[LCD_BUF_W * LCD_BUF_H]; -int lcd_line; -int lcd_column; -int lcd_next_line; - -#define LCD_PIX_BUF_SIZE (128 * 32 / 8) -byte lcd_pix_buf[LCD_PIX_BUF_SIZE]; -byte lcd_pix_buf2[LCD_PIX_BUF_SIZE]; - -mp_obj_t lcd_pix_clear(void) { - memset(lcd_pix_buf, 0, LCD_PIX_BUF_SIZE); - memset(lcd_pix_buf2, 0, LCD_PIX_BUF_SIZE); - return mp_const_none; -} - -mp_obj_t lcd_pix_get(mp_obj_t mp_x, mp_obj_t mp_y) { - int x = mp_obj_get_int(mp_x); - int y = mp_obj_get_int(mp_y); - if (0 <= x && x <= 127 && 0 <= y && y <= 31) { - uint byte_pos = x + 128 * ((uint)y >> 3); - if (lcd_pix_buf[byte_pos] & (1 << (y & 7))) { - return mp_obj_new_int(1); - } - } - return mp_obj_new_int(0); -} - -mp_obj_t lcd_pix_set(mp_obj_t mp_x, mp_obj_t mp_y) { - int x = mp_obj_get_int(mp_x); - int y = mp_obj_get_int(mp_y); - if (0 <= x && x <= 127 && 0 <= y && y <= 31) { - uint byte_pos = x + 128 * ((uint)y >> 3); - lcd_pix_buf2[byte_pos] |= 1 << (y & 7); - } - return mp_const_none; -} - -mp_obj_t lcd_pix_reset(mp_obj_t mp_x, mp_obj_t mp_y) { - int x = mp_obj_get_int(mp_x); - int y = mp_obj_get_int(mp_y); - if (0 <= x && x <= 127 && 0 <= y && y <= 31) { - uint byte_pos = x + 128 * ((uint)y >> 3); - lcd_pix_buf2[byte_pos] &= ~(1 << (y & 7)); - } - return mp_const_none; -} - -mp_obj_t lcd_pix_show(void) { - memcpy(lcd_pix_buf, lcd_pix_buf2, LCD_PIX_BUF_SIZE); - for (uint page = 0; page < 4; page++) { - lcd_out(LCD_INSTR, 0xb0 | page); // page address set - lcd_out(LCD_INSTR, 0x10); // column address set upper; 0 - lcd_out(LCD_INSTR, 0x00); // column address set lower; 0 - for (uint i = 0; i < 128; i++) { - lcd_out(LCD_DATA, lcd_pix_buf[i + 128 * page]); - } - } - return mp_const_none; -} - -mp_obj_t lcd_print(mp_obj_t text) { - uint len; - const char *data = mp_obj_str_get_data(text, &len); - lcd_print_strn(data, len); - return mp_const_none; -} - -mp_obj_t lcd_light(mp_obj_t value) { -#if defined(PYB_LCD_BL_PORT) - if (mp_obj_is_true(value)) { - PYB_LCD_BL_PORT->BSRRL = PYB_LCD_BL_PIN; // set pin high to turn backlight on - } else { - PYB_LCD_BL_PORT->BSRRH = PYB_LCD_BL_PIN; // set pin low to turn backlight off - } -#endif - return mp_const_none; -} - -static mp_obj_t mp_lcd = MP_OBJ_NULL; - -static mp_obj_t pyb_lcd_init(void) { - if (mp_lcd != MP_OBJ_NULL) { - // already init'd - return mp_lcd; - } - - // set the outputs high - PYB_LCD_PORT->BSRRL = PYB_LCD_CS1_PIN; - PYB_LCD_PORT->BSRRL = PYB_LCD_RST_PIN; - PYB_LCD_PORT->BSRRL = PYB_LCD_A0_PIN; - PYB_LCD_PORT->BSRRL = PYB_LCD_SCL_PIN; - PYB_LCD_PORT->BSRRL = PYB_LCD_SI_PIN; - - // make them push/pull outputs - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = PYB_LCD_CS1_PIN | PYB_LCD_RST_PIN | PYB_LCD_A0_PIN | PYB_LCD_SCL_PIN | PYB_LCD_SI_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(PYB_LCD_PORT, &GPIO_InitStructure); - -#if defined(PYB_LCD_BL_PORT) - // backlight drive pin, starts low (off) - PYB_LCD_BL_PORT->BSRRH = PYB_LCD_BL_PIN; - GPIO_InitStructure.GPIO_Pin = PYB_LCD_BL_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(PYB_LCD_BL_PORT, &GPIO_InitStructure); -#endif - - // init the LCD - sys_tick_delay_ms(1); // wait a bit - PYB_LCD_PORT->BSRRH = PYB_LCD_RST_PIN; // RST=0; reset - sys_tick_delay_ms(1); // wait for reset; 2us min - PYB_LCD_PORT->BSRRL = PYB_LCD_RST_PIN; // RST=1; enable - sys_tick_delay_ms(1); // wait for reset; 2us min - lcd_out(LCD_INSTR, 0xa0); // ADC select, normal - lcd_out(LCD_INSTR, 0xc8); // common output mode select, reverse - lcd_out(LCD_INSTR, 0xa2); // LCD bias set, 1/9 bias - lcd_out(LCD_INSTR, 0x2f); // power control set, 0b111=(booster on, vreg on, vfollow on) - lcd_out(LCD_INSTR, 0x21); // v0 voltage regulator internal resistor ratio set, 0b001=small - lcd_out(LCD_INSTR, 0x81); // electronic volume mode set - lcd_out(LCD_INSTR, 0x34); // electronic volume register set, 0b110100 - lcd_out(LCD_INSTR, 0x40); // display start line set, 0 - lcd_out(LCD_INSTR, 0xaf); // LCD display, on - - // clear display - for (int page = 0; page < 4; page++) { - lcd_out(LCD_INSTR, 0xb0 | page); // page address set - lcd_out(LCD_INSTR, 0x10); // column address set upper - lcd_out(LCD_INSTR, 0x00); // column address set lower - for (int i = 0; i < 128; i++) { - lcd_out(LCD_DATA, 0x00); - } - } - - for (int i = 0; i < LCD_BUF_H * LCD_BUF_W; i++) { - lcd_char_buffer[i] = ' '; - } - lcd_line = 0; - lcd_column = 0; - lcd_next_line = 0; - - // Micro Python interface - mp_obj_t o = mp_obj_new_type(MP_QSTR_LCD, mp_const_empty_tuple, mp_obj_new_dict(0)); - mp_store_attr(o, qstr_from_str("lcd8"), mp_make_function_n(2, lcd_draw_pixel_8)); - mp_store_attr(o, qstr_from_str("clear"), mp_make_function_n(0, lcd_pix_clear)); - mp_store_attr(o, qstr_from_str("get"), mp_make_function_n(2, lcd_pix_get)); - mp_store_attr(o, qstr_from_str("set"), mp_make_function_n(2, lcd_pix_set)); - mp_store_attr(o, qstr_from_str("reset"), mp_make_function_n(2, lcd_pix_reset)); - mp_store_attr(o, qstr_from_str("show"), mp_make_function_n(0, lcd_pix_show)); - mp_store_attr(o, qstr_from_str("text"), mp_make_function_n(1, lcd_print)); - mp_store_attr(o, qstr_from_str("light"), mp_make_function_n(1, lcd_light)); - mp_lcd = o; - return o; -} - -static MP_DEFINE_CONST_FUN_OBJ_0(pyb_lcd_init_obj, pyb_lcd_init); - -void lcd_init(void) { - mp_lcd = MP_OBJ_NULL; - mp_store_name(qstr_from_str("LCD"), (mp_obj_t)&pyb_lcd_init_obj); -} - -void lcd_print_str(const char *str) { - lcd_print_strn(str, strlen(str)); -} - -void lcd_print_strn(const char *str, unsigned int len) { - int redraw_min = lcd_line * LCD_BUF_W + lcd_column; - int redraw_max = redraw_min; - int did_new_line = 0; - for (; len > 0; len--, str++) { - // move to next line if needed - if (lcd_next_line) { - if (lcd_line + 1 < LCD_BUF_H) { - lcd_line += 1; - } else { - lcd_line = LCD_BUF_H - 1; - for (int i = 0; i < LCD_BUF_W * (LCD_BUF_H - 1); i++) { - lcd_char_buffer[i] = lcd_char_buffer[i + LCD_BUF_W]; - } - for (int i = 0; i < LCD_BUF_W; i++) { - lcd_char_buffer[LCD_BUF_W * (LCD_BUF_H - 1) + i] = ' '; - } - redraw_min = 0; - redraw_max = LCD_BUF_W * LCD_BUF_H; - } - lcd_next_line = 0; - lcd_column = 0; - did_new_line = 1; - } - if (*str == '\n') { - lcd_next_line = 1; - } else if (*str == '\r') { - lcd_column = 0; - } else if (*str == '\b') { - if (lcd_column > 0) { - lcd_column--; - } - } else if (lcd_column >= LCD_BUF_W) { - lcd_next_line = 1; - str -= 1; - len += 1; - } else { - lcd_char_buffer[lcd_line * LCD_BUF_W + lcd_column] = *str; - lcd_column += 1; - int max = lcd_line * LCD_BUF_W + lcd_column; - if (max > redraw_max) { - redraw_max = max; - } - } - } - - int last_page = -1; - for (int i = redraw_min; i < redraw_max; i++) { - int page = i / LCD_BUF_W; - if (page != last_page) { - int offset = 8 * (i - (page * LCD_BUF_W)); - lcd_out(LCD_INSTR, 0xb0 | page); // page address set - lcd_out(LCD_INSTR, 0x10 | ((offset >> 4) & 0x0f)); // column address set upper - lcd_out(LCD_INSTR, 0x00 | (offset & 0x0f)); // column address set lower - last_page = page; - } - int chr = lcd_char_buffer[i]; - if (chr < 32 || chr > 126) { - chr = 127; - } - const uint8_t *chr_data = &font_petme128_8x8[(chr - 32) * 8]; - for (int j = 0; j < 8; j++) { - lcd_out(LCD_DATA, chr_data[j]); - } - } - - if (did_new_line) { - sys_tick_delay_ms(50); - } -} - -#endif // MICROPY_HW_HAS_LCD diff --git a/stm/lcd.h b/stm/lcd.h deleted file mode 100644 index 7b243ee7e..000000000 --- a/stm/lcd.h +++ /dev/null @@ -1,3 +0,0 @@ -void lcd_init(void); -void lcd_print_str(const char *str); -void lcd_print_strn(const char *str, unsigned int len); diff --git a/stm/led.c b/stm/led.c deleted file mode 100644 index 17bb593f5..000000000 --- a/stm/led.c +++ /dev/null @@ -1,134 +0,0 @@ -#include -#include -#include - -#include "misc.h" -#include "mpconfig.h" -#include "qstr.h" -#include "obj.h" -#include "led.h" -#include "pin.h" -#include "build/pins.h" - -static const pin_obj_t *gLed[] = { - &PYB_LED1, -#if defined(PYB_LED2) - &PYB_LED2, -#if defined(PYB_LED3) - &PYB_LED3, -#if defined(PYB_LED4) - &PYB_LED4, -#endif -#endif -#endif -}; -#define NUM_LEDS (sizeof(gLed) / sizeof(gLed[0])) - -void led_init(void) { - /* GPIO structure */ - GPIO_InitTypeDef GPIO_InitStructure; - - /* Configure I/O speed, mode, output type and pull */ - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_InitStructure.GPIO_OType = PYB_OTYPE; - - /* Turn off LEDs and initialize */ - for (int led = 0; led < NUM_LEDS; led++) { - PYB_LED_OFF(gLed[led]); - GPIO_InitStructure.GPIO_Pin = gLed[led]->pin_mask; - GPIO_Init(gLed[led]->gpio, &GPIO_InitStructure); - } -} - -void led_state(pyb_led_t led, int state) { - if (led < 1 || led > NUM_LEDS) { - return; - } - const pin_obj_t *led_pin = gLed[led - 1]; - if (state == 0) { - // turn LED off - PYB_LED_OFF(led_pin); - } else { - // turn LED on - PYB_LED_ON(led_pin); - } -} - -void led_toggle(pyb_led_t led) { - if (led < 1 || led > NUM_LEDS) { - return; - } - const pin_obj_t *led_pin = gLed[led - 1]; - GPIO_TypeDef *gpio = led_pin->gpio; - - // We don't know if we're turning the LED on or off, but we don't really - // care. Just invert the state. - if (gpio->ODR & led_pin->pin_mask) { - // pin is high, make it low - gpio->BSRRH = led_pin->pin_mask; - } else { - // pin is low, make it high - gpio->BSRRL = led_pin->pin_mask; - } -} - -/******************************************************************************/ -/* Micro Python bindings */ - -typedef struct _pyb_led_obj_t { - mp_obj_base_t base; - uint led_id; -} pyb_led_obj_t; - -void led_obj_print(void (*print)(void *env, const char *fmt, ...), void *env, mp_obj_t self_in, mp_print_kind_t kind) { - pyb_led_obj_t *self = self_in; - print(env, "", self->led_id); -} - -mp_obj_t led_obj_on(mp_obj_t self_in) { - pyb_led_obj_t *self = self_in; - led_state(self->led_id, 1); - return mp_const_none; -} - -mp_obj_t led_obj_off(mp_obj_t self_in) { - pyb_led_obj_t *self = self_in; - led_state(self->led_id, 0); - return mp_const_none; -} - -mp_obj_t led_obj_toggle(mp_obj_t self_in) { - pyb_led_obj_t *self = self_in; - led_toggle(self->led_id); - return mp_const_none; -} - -static MP_DEFINE_CONST_FUN_OBJ_1(led_obj_on_obj, led_obj_on); -static MP_DEFINE_CONST_FUN_OBJ_1(led_obj_off_obj, led_obj_off); -static MP_DEFINE_CONST_FUN_OBJ_1(led_obj_toggle_obj, led_obj_toggle); - -STATIC const mp_map_elem_t led_locals_dict_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR_on), (mp_obj_t)&led_obj_on_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_off), (mp_obj_t)&led_obj_off_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_toggle), (mp_obj_t)&led_obj_toggle_obj }, -}; - -STATIC MP_DEFINE_CONST_DICT(led_locals_dict, led_locals_dict_table); - -static const mp_obj_type_t led_obj_type = { - { &mp_type_type }, - .name = MP_QSTR_Led, - .print = led_obj_print, - .locals_dict = (mp_obj_t)&led_locals_dict, -}; - -static mp_obj_t pyb_Led(mp_obj_t led_id) { - pyb_led_obj_t *o = m_new_obj(pyb_led_obj_t); - o->base.type = &led_obj_type; - o->led_id = mp_obj_get_int(led_id); - return o; -} - -MP_DEFINE_CONST_FUN_OBJ_1(pyb_Led_obj, pyb_Led); diff --git a/stm/led.h b/stm/led.h deleted file mode 100644 index 44c68d4eb..000000000 --- a/stm/led.h +++ /dev/null @@ -1,23 +0,0 @@ -typedef enum { - // PYBv3 - PYB_LED_R1 = 1, - PYB_LED_R2 = 2, - PYB_LED_G1 = 3, - PYB_LED_G2 = 4, - // PYBv4 - PYB_LED_RED = 1, - PYB_LED_GREEN = 2, - PYB_LED_YELLOW = 3, - PYB_LED_BLUE = 4, - //STM32F4DISC - PYB_LED_R = 1, - PYB_LED_G = 2, - PYB_LED_B = 3, - PYB_LED_O = 4, -} pyb_led_t; - -void led_init(void); -void led_state(pyb_led_t led, int state); -void led_toggle(pyb_led_t led); - -MP_DECLARE_CONST_FUN_OBJ(pyb_Led_obj); diff --git a/stm/lexerfatfs.c b/stm/lexerfatfs.c deleted file mode 100644 index d1686cb22..000000000 --- a/stm/lexerfatfs.c +++ /dev/null @@ -1,53 +0,0 @@ -#include -#include - -#include "ff.h" - -#include "misc.h" -#include "mpconfig.h" -#include "qstr.h" -#include "lexer.h" -#include "lexerfatfs.h" - -typedef struct _mp_lexer_file_buf_t { - FIL fp; - char buf[20]; - uint16_t len; - uint16_t pos; -} mp_lexer_file_buf_t; - -static unichar file_buf_next_char(mp_lexer_file_buf_t *fb) { - if (fb->pos >= fb->len) { - if (fb->len < sizeof(fb->buf)) { - return MP_LEXER_CHAR_EOF; - } else { - UINT n; - f_read(&fb->fp, fb->buf, sizeof(fb->buf), &n); - if (n == 0) { - return MP_LEXER_CHAR_EOF; - } - fb->len = n; - fb->pos = 0; - } - } - return fb->buf[fb->pos++]; -} - -static void file_buf_close(mp_lexer_file_buf_t *fb) { - f_close(&fb->fp); - m_del_obj(mp_lexer_file_buf_t, fb); -} - -mp_lexer_t *mp_lexer_new_from_file(const char *filename) { - mp_lexer_file_buf_t *fb = m_new_obj(mp_lexer_file_buf_t); - FRESULT res = f_open(&fb->fp, filename, FA_READ); - if (res != FR_OK) { - m_del_obj(mp_lexer_file_buf_t, fb); - return NULL; - } - UINT n; - f_read(&fb->fp, fb->buf, sizeof(fb->buf), &n); - fb->len = n; - fb->pos = 0; - return mp_lexer_new(qstr_from_str(filename), fb, (mp_lexer_stream_next_char_t)file_buf_next_char, (mp_lexer_stream_close_t)file_buf_close); -} diff --git a/stm/lexerfatfs.h b/stm/lexerfatfs.h deleted file mode 100644 index 55902a300..000000000 --- a/stm/lexerfatfs.h +++ /dev/null @@ -1 +0,0 @@ -mp_lexer_t *mp_lexer_new_from_file(const char *filename); diff --git a/stm/main.c b/stm/main.c deleted file mode 100644 index d7f2624c3..000000000 --- a/stm/main.c +++ /dev/null @@ -1,480 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "std.h" - -#include "misc.h" -#include "ff.h" -#include "mpconfig.h" -#include "qstr.h" -#include "nlr.h" -#include "misc.h" -#include "lexer.h" -#include "lexerfatfs.h" -#include "parse.h" -#include "obj.h" -#include "objmodule.h" -#include "parsehelper.h" -#include "compile.h" -#include "runtime0.h" -#include "runtime.h" -#include "gc.h" -#include "gccollect.h" -#include "systick.h" -#include "pendsv.h" -#include "pyexec.h" -#include "led.h" -#include "servo.h" -#include "lcd.h" -#include "storage.h" -#include "sdcard.h" -#include "accel.h" -#include "usb.h" -#include "timer.h" -#include "pybwlan.h" -#include "usrsw.h" -#include "rtc.h" -#include "file.h" -#include "pin.h" -#include "exti.h" -#include "pybmodule.h" - -int errno; - -static FATFS fatfs0; -#if MICROPY_HW_HAS_SDCARD -static FATFS fatfs1; -#endif - -void flash_error(int n) { - for (int i = 0; i < n; i++) { - led_state(PYB_LED_R1, 1); - led_state(PYB_LED_R2, 0); - sys_tick_delay_ms(250); - led_state(PYB_LED_R1, 0); - led_state(PYB_LED_R2, 1); - sys_tick_delay_ms(250); - } - led_state(PYB_LED_R2, 0); -} - -void __fatal_error(const char *msg) { -#if MICROPY_HW_HAS_LCD - lcd_print_strn("\nFATAL ERROR:\n", 14); - lcd_print_strn(msg, strlen(msg)); -#endif - for (;;) { - flash_error(1); - } -} - -void nlr_jump_fail(void *val) { - printf("FATAL: uncaught exception %p\n", val); - __fatal_error(""); -} - -STATIC mp_obj_t pyb_config_source_dir = MP_OBJ_NULL; -STATIC mp_obj_t pyb_config_main = MP_OBJ_NULL; - -STATIC mp_obj_t pyb_source_dir(mp_obj_t source_dir) { - if (MP_OBJ_IS_STR(source_dir)) { - pyb_config_source_dir = source_dir; - } - return mp_const_none; -} - -MP_DEFINE_CONST_FUN_OBJ_1(pyb_source_dir_obj, pyb_source_dir); - -STATIC mp_obj_t pyb_main(mp_obj_t main) { - if (MP_OBJ_IS_STR(main)) { - pyb_config_main = main; - } - return mp_const_none; -} - -MP_DEFINE_CONST_FUN_OBJ_1(pyb_main_obj, pyb_main); - -void fatality(void) { - led_state(PYB_LED_R1, 1); - led_state(PYB_LED_G1, 1); - led_state(PYB_LED_R2, 1); - led_state(PYB_LED_G2, 1); -} - -static const char fresh_boot_py[] = -"# boot.py -- run on boot-up\n" -"# can run arbitrary Python, but best to keep it minimal\n" -"\n" -"pyb.source_dir('/src')\n" -"pyb.main('main.py')\n" -"#pyb.usb_usr('VCP')\n" -"#pyb.usb_msd(True, 'dual partition')\n" -"#pyb.flush_cache(False)\n" -"#pyb.error_log('error.txt')\n" -; - -static const char fresh_main_py[] = -"# main.py -- put your code here!\n" -; - -static const char *help_text = -"Welcome to Micro Python!\n\n" -"This is a *very* early version of Micro Python and has minimal functionality.\n\n" -"Specific commands for the board:\n" -" pyb.info() -- print some general information\n" -" pyb.gc() -- run the garbage collector\n" -" pyb.repl_info() -- enable/disable printing of info after each command\n" -" pyb.delay() -- wait for n milliseconds\n" -" pyb.udelay() -- wait for n microseconds\n" -" pyb.Led() -- create Led object for LED n (n=1,2)\n" -" Led methods: on(), off()\n" -" pyb.Servo() -- create Servo object for servo n (n=1,2,3,4)\n" -" Servo methods: angle()\n" -" pyb.switch() -- return True/False if switch pressed or not\n" -" pyb.accel() -- get accelerometer values\n" -" pyb.rand() -- get a 16-bit random number\n" -" pyb.gpio() -- get port value (port='A4' for example)\n" -" pyb.gpio(, ) -- set port value, True or False, 1 or 0\n" -" pyb.ADC() -- make an analog port object (port='C0' for example)\n" -" ADC methods: read()\n" -; - -// get some help about available functions -static mp_obj_t pyb_help(void) { - printf("%s", help_text); - return mp_const_none; -} - -int main(void) { - // TODO disable JTAG - - // update the SystemCoreClock variable - SystemCoreClockUpdate(); - - // set interrupt priority config to use all 4 bits for pre-empting - NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4); - - // enable the CCM RAM and the GPIO's - RCC->AHB1ENR |= RCC_AHB1ENR_CCMDATARAMEN | RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN; - -#if MICROPY_HW_HAS_SDCARD - { - // configure SDIO pins to be high to start with (apparently makes it more robust) - // FIXME this is not making them high, it just makes them outputs... - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_25MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(GPIOC, &GPIO_InitStructure); - - // Configure PD.02 CMD line - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; - GPIO_Init(GPIOD, &GPIO_InitStructure); - } -#endif -#if defined(NETDUINO_PLUS_2) - { - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_25MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - -#if MICROPY_HW_HAS_SDCARD - // Turn on the power enable for the sdcard (PB1) - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1; - GPIO_Init(GPIOB, &GPIO_InitStructure); - GPIO_WriteBit(GPIOB, GPIO_Pin_1, Bit_SET); -#endif - - // Turn on the power for the 5V on the expansion header (PB2) - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; - GPIO_Init(GPIOB, &GPIO_InitStructure); - GPIO_WriteBit(GPIOB, GPIO_Pin_2, Bit_SET); - } -#endif - - // basic sub-system init - sys_tick_init(); - pendsv_init(); - led_init(); - -#if MICROPY_HW_ENABLE_RTC - rtc_init(); -#endif - - // turn on LED to indicate bootup - led_state(PYB_LED_G1, 1); - - // more sub-system init -#if MICROPY_HW_HAS_SDCARD - sdcard_init(); -#endif - storage_init(); - - // uncomment these 2 lines if you want REPL on USART_6 (or another usart) as well as on USB VCP - //pyb_usart_global_debug = PYB_USART_YA; - //usart_init(pyb_usart_global_debug, 115200); - - int first_soft_reset = true; - -soft_reset: - - // GC init - gc_init(&_heap_start, &_heap_end); - - // Micro Python init - qstr_init(); - mp_init(); - mp_obj_list_init(mp_sys_path, 0); - mp_obj_list_append(mp_sys_path, MP_OBJ_NEW_QSTR(MP_QSTR_0_colon__slash_)); - mp_obj_list_append(mp_sys_path, MP_OBJ_NEW_QSTR(MP_QSTR_0_colon__slash_lib)); - mp_obj_list_init(mp_sys_argv, 0); - - exti_init(); - -#if MICROPY_HW_HAS_SWITCH - switch_init(); -#endif - -#if MICROPY_HW_HAS_LCD - // LCD init (just creates class, init hardware by calling LCD()) - lcd_init(); -#endif - -#if MICROPY_HW_ENABLE_SERVO - // servo - servo_init(); -#endif - -#if MICROPY_HW_ENABLE_TIMER - // timer - timer_init(); -#endif - -#if MICROPY_HW_ENABLE_RNG - // RNG - RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_RNG, ENABLE); - RNG_Cmd(ENABLE); -#endif - - pin_map_init(); - - // add some functions to the builtin Python namespace - mp_store_name(MP_QSTR_help, mp_make_function_n(0, pyb_help)); - mp_store_name(MP_QSTR_open, mp_make_function_n(2, pyb_io_open)); - - // load the pyb module - mp_module_register(MP_QSTR_pyb, (mp_obj_t)&pyb_module); - - // check if user switch held (initiates reset of filesystem) - bool reset_filesystem = false; -#if MICROPY_HW_HAS_SWITCH - if (switch_get()) { - reset_filesystem = true; - for (int i = 0; i < 50; i++) { - if (!switch_get()) { - reset_filesystem = false; - break; - } - sys_tick_delay_ms(10); - } - } -#endif - // local filesystem init - { - // try to mount the flash - FRESULT res = f_mount(&fatfs0, "0:", 1); - if (!reset_filesystem && res == FR_OK) { - // mount sucessful - } else if (reset_filesystem || res == FR_NO_FILESYSTEM) { - // no filesystem, so create a fresh one - // TODO doesn't seem to work correctly when reset_filesystem is true... - - // LED on to indicate creation of LFS - led_state(PYB_LED_R2, 1); - uint32_t stc = sys_tick_counter; - - res = f_mkfs("0:", 0, 0); - if (res == FR_OK) { - // success creating fresh LFS - } else { - __fatal_error("could not create LFS"); - } - - // create src directory - res = f_mkdir("0:/src"); - // ignore result from mkdir - - // create empty main.py - FIL fp; - f_open(&fp, "0:/src/main.py", FA_WRITE | FA_CREATE_ALWAYS); - UINT n; - f_write(&fp, fresh_main_py, sizeof(fresh_main_py) - 1 /* don't count null terminator */, &n); - // TODO check we could write n bytes - f_close(&fp); - - // keep LED on for at least 200ms - sys_tick_wait_at_least(stc, 200); - led_state(PYB_LED_R2, 0); - } else { - __fatal_error("could not access LFS"); - } - } - - // make sure we have a /boot.py - { - FILINFO fno; - FRESULT res = f_stat("0:/boot.py", &fno); - if (res == FR_OK) { - if (fno.fattrib & AM_DIR) { - // exists as a directory - // TODO handle this case - // see http://elm-chan.org/fsw/ff/img/app2.c for a "rm -rf" implementation - } else { - // exists as a file, good! - } - } else { - // doesn't exist, create fresh file - - // LED on to indicate creation of boot.py - led_state(PYB_LED_R2, 1); - uint32_t stc = sys_tick_counter; - - FIL fp; - f_open(&fp, "0:/boot.py", FA_WRITE | FA_CREATE_ALWAYS); - UINT n; - f_write(&fp, fresh_boot_py, sizeof(fresh_boot_py) - 1 /* don't count null terminator */, &n); - // TODO check we could write n bytes - f_close(&fp); - - // keep LED on for at least 200ms - sys_tick_wait_at_least(stc, 200); - led_state(PYB_LED_R2, 0); - } - } - - // run /boot.py - if (!pyexec_file("0:/boot.py")) { - flash_error(4); - } - - if (first_soft_reset) { -#if MICROPY_HW_HAS_MMA7660 - // MMA accel: init and reset address to zero - accel_init(); -#endif - } - - // turn boot-up LED off - led_state(PYB_LED_G1, 0); - -#if MICROPY_HW_HAS_SDCARD - // if an SD card is present then mount it on 1:/ - if (sdcard_is_present()) { - FRESULT res = f_mount(&fatfs1, "1:", 1); - if (res != FR_OK) { - printf("[SD] could not mount SD card\n"); - } else { - if (first_soft_reset) { - // use SD card as medium for the USB MSD - usbd_storage_select_medium(USBD_STORAGE_MEDIUM_SDCARD); - } - } - } -#endif - -#ifdef USE_HOST_MODE - // USB host - pyb_usb_host_init(); -#elif defined(USE_DEVICE_MODE) - // USB device - pyb_usb_dev_init(PYB_USB_DEV_VCP_MSC); -#endif - - // run main script - { - vstr_t *vstr = vstr_new(); - vstr_add_str(vstr, "0:/"); - if (pyb_config_source_dir == MP_OBJ_NULL) { - vstr_add_str(vstr, "src"); - } else { - vstr_add_str(vstr, mp_obj_str_get_str(pyb_config_source_dir)); - } - vstr_add_char(vstr, '/'); - if (pyb_config_main == MP_OBJ_NULL) { - vstr_add_str(vstr, "main.py"); - } else { - vstr_add_str(vstr, mp_obj_str_get_str(pyb_config_main)); - } - if (!pyexec_file(vstr_str(vstr))) { - flash_error(3); - } - vstr_free(vstr); - } - - -#if MICROPY_HW_HAS_MMA7660 - // HID example - if (0) { - uint8_t data[4]; - data[0] = 0; - data[1] = 1; - data[2] = -2; - data[3] = 0; - for (;;) { - #if MICROPY_HW_HAS_SWITCH - if (switch_get()) { - data[0] = 0x01; // 0x04 is middle, 0x02 is right - } else { - data[0] = 0x00; - } - #else - data[0] = 0x00; - #endif - accel_start(0x4c /* ACCEL_ADDR */, 1); - accel_send_byte(0); - accel_restart(0x4c /* ACCEL_ADDR */, 0); - for (int i = 0; i <= 1; i++) { - int v = accel_read_ack() & 0x3f; - if (v & 0x20) { - v |= ~0x1f; - } - data[1 + i] = v; - } - accel_read_nack(); - usb_hid_send_report(data); - sys_tick_delay_ms(15); - } - } -#endif - -#if MICROPY_HW_HAS_WLAN - // wifi - pyb_wlan_init(); - pyb_wlan_start(); -#endif - - pyexec_repl(); - - printf("PYB: sync filesystems\n"); - storage_flush(); - - printf("PYB: soft reboot\n"); - - first_soft_reset = false; - goto soft_reset; -} diff --git a/stm/malloc0.c b/stm/malloc0.c deleted file mode 100644 index 510fa0d74..000000000 --- a/stm/malloc0.c +++ /dev/null @@ -1,37 +0,0 @@ -#include -#include -#include "misc.h" -#include "mpconfig.h" -#include "gc.h" - -#if 0 -static uint32_t mem = 0; - -void *malloc(size_t n) { - if (mem == 0) { - extern uint32_t _heap_start; - mem = (uint32_t)&_heap_start; // need to use big ram block so we can execute code from it (is it true that we can't execute from CCM?) - } - void *ptr = (void*)mem; - mem = (mem + n + 3) & (~3); - if (mem > 0x20000000 + 0x18000) { - void __fatal_error(const char*); - __fatal_error("out of memory"); - } - return ptr; -} - -void free(void *ptr) { -} - -void *realloc(void *ptr, size_t n) { - return malloc(n); -} - -#endif - -void __assert_func(void) { - printf("\nASSERT FAIL!"); - for (;;) { - } -} diff --git a/stm/math.c b/stm/math.c deleted file mode 100644 index e75ec1d4b..000000000 --- a/stm/math.c +++ /dev/null @@ -1,454 +0,0 @@ -#include -typedef float float_t; -typedef union { - float f; - struct { - uint64_t m : 23; - uint64_t e : 8; - uint64_t s : 1; - }; -} float_s_t; - -typedef union { - double d; - struct { - uint64_t m : 52; - uint64_t e : 11; - uint64_t s : 1; - }; -} double_s_t; - -double __attribute__((pcs("aapcs"))) __aeabi_i2d(int32_t x) { - return (float)x; -} - -double __attribute__((pcs("aapcs"))) __aeabi_f2d(float x) { - float_s_t fx={0}; - double_s_t dx={0}; - - fx.f = x; - dx.s = (fx.s); - dx.e = (fx.e-127+1023) & 0x7FF; - dx.m = fx.m; - dx.m <<=(52-23); // left justify - return dx.d; -} - -float __attribute__((pcs("aapcs"))) __aeabi_d2f(double x) { - float_s_t fx={0}; - double_s_t dx={0}; - - dx.d = x; - fx.s = (dx.s); - fx.e = (dx.e-1023+127) & 0xFF; - fx.m = (dx.m>>(52-23)); // right justify - return fx.f; -} -double __aeabi_dmul(double x , double y) { - return 0.0; - -} -/* -double sqrt(double x) { - // TODO - return 0.0; -} -*/ - -float sqrtf(float x) { - asm volatile ( - "vsqrt.f32 %[r], %[x]\n" - : [r] "=t" (x) - : [x] "t" (x)); - return x; -} - -// TODO we need import these functions from some library (eg musl or newlib) -float powf(float x, float y) { return 0.0; } -float logf(float x) { return 0.0; } -float log2f(float x) { return 0.0; } -float log10f(float x) { return 0.0; } -float tanhf(float x) { return 0.0; } -float acoshf(float x) { return 0.0; } -float asinhf(float x) { return 0.0; } -float atanhf(float x) { return 0.0; } -float cosf(float x) { return 0.0; } -float sinf(float x) { return 0.0; } -float tanf(float x) { return 0.0; } -float acosf(float x) { return 0.0; } -float asinf(float x) { return 0.0; } -float atanf(float x) { return 0.0; } -float atan2f(float x, float y) { return 0.0; } -float ceilf(float x) { return 0.0; } -float floorf(float x) { return 0.0; } -float truncf(float x) { return 0.0; } -float fmodf(float x, float y) { return 0.0; } -float tgammaf(float x) { return 0.0; } -float lgammaf(float x) { return 0.0; } -float erff(float x) { return 0.0; } -float erfcf(float x) { return 0.0; } -float modff(float x, float *y) { return 0.0; } -float frexpf(float x, int *exp) { return 0.0; } -float ldexpf(float x, int exp) { return 0.0; } -int __fpclassifyf(float x) { return 0; } - -/*****************************************************************************/ -// from musl-0.9.15 libm.h - -/* origin: FreeBSD /usr/src/lib/msun/src/math_private.h */ -/* - * ==================================================== - * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved. - * - * Developed at SunPro, a Sun Microsystems, Inc. business. - * Permission to use, copy, modify, and distribute this - * software is freely granted, provided that this notice - * is preserved. - * ==================================================== - */ - -#define FORCE_EVAL(x) do { \ - if (sizeof(x) == sizeof(float)) { \ - volatile float __x; \ - __x = (x); \ - (void)__x; \ - } else if (sizeof(x) == sizeof(double)) { \ - volatile double __x; \ - __x = (x); \ - (void)__x; \ - } else { \ - volatile long double __x; \ - __x = (x); \ - (void)__x; \ - } \ -} while(0) - -/* Get a 32 bit int from a float. */ -#define GET_FLOAT_WORD(w,d) \ -do { \ - union {float f; uint32_t i;} __u; \ - __u.f = (d); \ - (w) = __u.i; \ -} while (0) - -/* Set a float from a 32 bit int. */ -#define SET_FLOAT_WORD(d,w) \ -do { \ - union {float f; uint32_t i;} __u; \ - __u.i = (w); \ - (d) = __u.f; \ -} while (0) - -/*****************************************************************************/ -// scalbnf from musl-0.9.15 - -float scalbnf(float x, int n) -{ - union {float f; uint32_t i;} u; - float_t y = x; - - if (n > 127) { - y *= 0x1p127f; - n -= 127; - if (n > 127) { - y *= 0x1p127f; - n -= 127; - if (n > 127) - n = 127; - } - } else if (n < -126) { - y *= 0x1p-126f; - n += 126; - if (n < -126) { - y *= 0x1p-126f; - n += 126; - if (n < -126) - n = -126; - } - } - u.i = (uint32_t)(0x7f+n)<<23; - x = y * u.f; - return x; -} - -/*****************************************************************************/ -// expf from musl-0.9.15 - -/* origin: FreeBSD /usr/src/lib/msun/src/e_expf.c */ -/* - * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com. - */ -/* - * ==================================================== - * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved. - * - * Developed at SunPro, a Sun Microsystems, Inc. business. - * Permission to use, copy, modify, and distribute this - * software is freely granted, provided that this notice - * is preserved. - * ==================================================== - */ - -static const float -half[2] = {0.5,-0.5}, -ln2hi = 6.9314575195e-1f, /* 0x3f317200 */ -ln2lo = 1.4286067653e-6f, /* 0x35bfbe8e */ -invln2 = 1.4426950216e+0f, /* 0x3fb8aa3b */ -/* - * Domain [-0.34568, 0.34568], range ~[-4.278e-9, 4.447e-9]: - * |x*(exp(x)+1)/(exp(x)-1) - p(x)| < 2**-27.74 - */ -P1 = 1.6666625440e-1f, /* 0xaaaa8f.0p-26 */ -P2 = -2.7667332906e-3f; /* -0xb55215.0p-32 */ - -float expf(float x) -{ - float_t hi, lo, c, xx, y; - int k, sign; - uint32_t hx; - - GET_FLOAT_WORD(hx, x); - sign = hx >> 31; /* sign bit of x */ - hx &= 0x7fffffff; /* high word of |x| */ - - /* special cases */ - if (hx >= 0x42aeac50) { /* if |x| >= -87.33655f or NaN */ - if (hx >= 0x42b17218 && !sign) { /* x >= 88.722839f */ - /* overflow */ - x *= 0x1p127f; - return x; - } - if (sign) { - /* underflow */ - FORCE_EVAL(-0x1p-149f/x); - if (hx >= 0x42cff1b5) /* x <= -103.972084f */ - return 0; - } - } - - /* argument reduction */ - if (hx > 0x3eb17218) { /* if |x| > 0.5 ln2 */ - if (hx > 0x3f851592) /* if |x| > 1.5 ln2 */ - k = invln2*x + half[sign]; - else - k = 1 - sign - sign; - hi = x - k*ln2hi; /* k*ln2hi is exact here */ - lo = k*ln2lo; - x = hi - lo; - } else if (hx > 0x39000000) { /* |x| > 2**-14 */ - k = 0; - hi = x; - lo = 0; - } else { - /* raise inexact */ - FORCE_EVAL(0x1p127f + x); - return 1 + x; - } - - /* x is now in primary range */ - xx = x*x; - c = x - xx*(P1+xx*P2); - y = 1 + (x*c/(2-c) - lo + hi); - if (k == 0) - return y; - return scalbnf(y, k); -} - -/*****************************************************************************/ -// expm1f from musl-0.9.15 - -/* origin: FreeBSD /usr/src/lib/msun/src/s_expm1f.c */ -/* - * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com. - */ -/* - * ==================================================== - * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved. - * - * Developed at SunPro, a Sun Microsystems, Inc. business. - * Permission to use, copy, modify, and distribute this - * software is freely granted, provided that this notice - * is preserved. - * ==================================================== - */ - -static const float -o_threshold = 8.8721679688e+01, /* 0x42b17180 */ -ln2_hi = 6.9313812256e-01, /* 0x3f317180 */ -ln2_lo = 9.0580006145e-06, /* 0x3717f7d1 */ -//invln2 = 1.4426950216e+00, /* 0x3fb8aa3b */ -/* - * Domain [-0.34568, 0.34568], range ~[-6.694e-10, 6.696e-10]: - * |6 / x * (1 + 2 * (1 / (exp(x) - 1) - 1 / x)) - q(x)| < 2**-30.04 - * Scaled coefficients: Qn_here = 2**n * Qn_for_q (see s_expm1.c): - */ -Q1 = -3.3333212137e-2, /* -0x888868.0p-28 */ -Q2 = 1.5807170421e-3; /* 0xcf3010.0p-33 */ - -float expm1f(float x) -{ - float_t y,hi,lo,c,t,e,hxs,hfx,r1,twopk; - union {float f; uint32_t i;} u = {x}; - uint32_t hx = u.i & 0x7fffffff; - int k, sign = u.i >> 31; - - /* filter out huge and non-finite argument */ - if (hx >= 0x4195b844) { /* if |x|>=27*ln2 */ - if (hx > 0x7f800000) /* NaN */ - return x; - if (sign) - return -1; - if (x > o_threshold) { - x *= 0x1p127f; - return x; - } - } - - /* argument reduction */ - if (hx > 0x3eb17218) { /* if |x| > 0.5 ln2 */ - if (hx < 0x3F851592) { /* and |x| < 1.5 ln2 */ - if (!sign) { - hi = x - ln2_hi; - lo = ln2_lo; - k = 1; - } else { - hi = x + ln2_hi; - lo = -ln2_lo; - k = -1; - } - } else { - k = invln2*x + (sign ? -0.5f : 0.5f); - t = k; - hi = x - t*ln2_hi; /* t*ln2_hi is exact here */ - lo = t*ln2_lo; - } - x = hi-lo; - c = (hi-x)-lo; - } else if (hx < 0x33000000) { /* when |x|<2**-25, return x */ - if (hx < 0x00800000) - FORCE_EVAL(x*x); - return x; - } else - k = 0; - - /* x is now in primary range */ - hfx = 0.5f*x; - hxs = x*hfx; - r1 = 1.0f+hxs*(Q1+hxs*Q2); - t = 3.0f - r1*hfx; - e = hxs*((r1-t)/(6.0f - x*t)); - if (k == 0) /* c is 0 */ - return x - (x*e-hxs); - e = x*(e-c) - c; - e -= hxs; - /* exp(x) ~ 2^k (x_reduced - e + 1) */ - if (k == -1) - return 0.5f*(x-e) - 0.5f; - if (k == 1) { - if (x < -0.25f) - return -2.0f*(e-(x+0.5f)); - return 1.0f + 2.0f*(x-e); - } - u.i = (0x7f+k)<<23; /* 2^k */ - twopk = u.f; - if (k < 0 || k > 56) { /* suffice to return exp(x)-1 */ - y = x - e + 1.0f; - if (k == 128) - y = y*2.0f*0x1p127f; - else - y = y*twopk; - return y - 1.0f; - } - u.i = (0x7f-k)<<23; /* 2^-k */ - if (k < 23) - y = (x-e+(1-u.f))*twopk; - else - y = (x-(e+u.f)+1)*twopk; - return y; -} - -/*****************************************************************************/ -// __expo2f from musl-0.9.15 - -/* k is such that k*ln2 has minimal relative error and x - kln2 > log(FLT_MIN) */ -static const int k = 235; -static const float kln2 = 0x1.45c778p+7f; - -/* expf(x)/2 for x >= log(FLT_MAX), slightly better than 0.5f*expf(x/2)*expf(x/2) */ -float __expo2f(float x) -{ - float scale; - - /* note that k is odd and scale*scale overflows */ - SET_FLOAT_WORD(scale, (uint32_t)(0x7f + k/2) << 23); - /* exp(x - k ln2) * 2**(k-1) */ - return expf(x - kln2) * scale * scale; -} - -/*****************************************************************************/ -// coshf from musl-0.9.15 - -float coshf(float x) -{ - union {float f; uint32_t i;} u = {.f = x}; - uint32_t w; - float t; - - /* |x| */ - u.i &= 0x7fffffff; - x = u.f; - w = u.i; - - /* |x| < log(2) */ - if (w < 0x3f317217) { - if (w < 0x3f800000 - (12<<23)) { - FORCE_EVAL(x + 0x1p120f); - return 1; - } - t = expm1f(x); - return 1 + t*t/(2*(1+t)); - } - - /* |x| < log(FLT_MAX) */ - if (w < 0x42b17217) { - t = expf(x); - return 0.5f*(t + 1/t); - } - - /* |x| > log(FLT_MAX) or nan */ - t = __expo2f(x); - return t; -} - -/*****************************************************************************/ -// sinhf from musl-0.9.15 - -float sinhf(float x) -{ - union {float f; uint32_t i;} u = {.f = x}; - uint32_t w; - float t, h, absx; - - h = 0.5; - if (u.i >> 31) - h = -h; - /* |x| */ - u.i &= 0x7fffffff; - absx = u.f; - w = u.i; - - /* |x| < log(FLT_MAX) */ - if (w < 0x42b17217) { - t = expm1f(absx); - if (w < 0x3f800000) { - if (w < 0x3f800000 - (12<<23)) - return x; - return h*(2*t - t*t/(t+1)); - } - return h*(t + t/(t+1)); - } - - /* |x| > logf(FLT_MAX) or nan */ - t = 2*h*__expo2f(absx); - return t; -} diff --git a/stm/mpconfigport.h b/stm/mpconfigport.h deleted file mode 100644 index c832f4388..000000000 --- a/stm/mpconfigport.h +++ /dev/null @@ -1,54 +0,0 @@ -#include - -// options to control how Micro Python is built - -#define MICROPY_EMIT_THUMB (1) -#define MICROPY_EMIT_INLINE_THUMB (1) -#define MICROPY_ENABLE_GC (1) -#define MICROPY_ENABLE_FINALISER (1) -#define MICROPY_ENABLE_REPL_HELPERS (1) -#define MICROPY_LONGINT_IMPL (MICROPY_LONGINT_IMPL_MPZ) -#define MICROPY_FLOAT_IMPL (MICROPY_FLOAT_IMPL_FLOAT) -#define MICROPY_PATH_MAX (128) -/* Enable FatFS LFNs - 0: Disable LFN feature. - 1: Enable LFN with static working buffer on the BSS. Always NOT reentrant. - 2: Enable LFN with dynamic working buffer on the STACK. - 3: Enable LFN with dynamic working buffer on the HEAP. -*/ -#define MICROPY_ENABLE_LFN (0) -#define MICROPY_LFN_CODE_PAGE (1) /* 1=SFN/ANSI 437=LFN/U.S.(OEM) */ - -extern const struct _mp_obj_fun_native_t mp_builtin_open_obj; - -// type definitions for the specific machine - -#define BYTES_PER_WORD (4) - -#define UINT_FMT "%lu" -#define INT_FMT "%ld" - -typedef int32_t machine_int_t; // must be pointer size -typedef uint32_t machine_uint_t; // must be pointer size -typedef void *machine_ptr_t; // must be of pointer size -typedef const void *machine_const_ptr_t; // must be of pointer size - -// There is no classical C heap in bare-metal ports, only Python -// garbage-collected heap. For completeness, emulate C heap via -// GC heap. Note that MicroPython core never uses malloc() and friends, -// so these defines are mostly to help extension module writers. -#define malloc gc_alloc -#define free gc_free -#define realloc gc_realloc - -// board specific definitions - -#include "mpconfigboard.h" - -#define STM32F40_41xxx -#define USE_STDPERIPH_DRIVER -#if !defined(HSE_VALUE) -#define HSE_VALUE (8000000) -#endif -#define USE_DEVICE_MODE -//#define USE_HOST_MODE diff --git a/stm/pendsv.c b/stm/pendsv.c deleted file mode 100644 index 216bb4db0..000000000 --- a/stm/pendsv.c +++ /dev/null @@ -1,83 +0,0 @@ -#include -#include - -#include "misc.h" -#include "mpconfig.h" -#include "qstr.h" -#include "obj.h" -#include "pendsv.h" - -static mp_obj_t pendsv_object = MP_OBJ_NULL; - -void pendsv_init(void) { - // set PendSV interrupt at lowest priority - NVIC_SetPriority(PendSV_IRQn, 0xff); -} - -// call this function to raise a pending exception during an interrupt -// it will wait until all interrupts are finished then raise the given -// exception object using nlr_jump in the context of the top-level thread -void pendsv_nlr_jump(mp_obj_t o) { - pendsv_object = o; - SCB->ICSR = SCB_ICSR_PENDSVSET_Msk; -} - -// since we play tricks with the stack, the compiler must not generate a -// prelude for this function -void pendsv_isr_handler(void) __attribute__((naked)); - -void pendsv_isr_handler(void) { - // re-jig the stack so that when we return from this interrupt handler - // it returns instead to nlr_jump with argument pendsv_object - // note that stack has a different layout if DEBUG is enabled - // - // on entry to this (naked) function, stack has the following layout: - // - // stack layout with DEBUG disabled: - // sp[6]: pc - // sp[5]: ? - // sp[4]: ? - // sp[3]: ? - // sp[2]: ? - // sp[1]: ? - // sp[0]: r0 - // - // stack layout with DEBUG enabled: - // sp[8]: pc - // sp[7]: lr - // sp[6]: ? - // sp[5]: ? - // sp[4]: ? - // sp[3]: ? - // sp[2]: r0 - // sp[1]: 0xfffffff9 - // sp[0]: ? - - __asm volatile ( - "ldr r0, pendsv_object_ptr\n" - "ldr r0, [r0]\n" -#if defined(PENDSV_DEBUG) - "str r0, [sp, #8]\n" -#else - "str r0, [sp, #0]\n" -#endif - "ldr r0, nlr_jump_ptr\n" -#if defined(PENDSV_DEBUG) - "str r0, [sp, #32]\n" -#else - "str r0, [sp, #24]\n" -#endif - "bx lr\n" - ".align 2\n" - "pendsv_object_ptr: .word pendsv_object\n" - "nlr_jump_ptr: .word nlr_jump\n" - ); - - /* - uint32_t x[2] = {0x424242, 0xdeaddead}; - printf("PendSV: %p\n", x); - for (uint32_t *p = (uint32_t*)(((uint32_t)x - 15) & 0xfffffff0), i = 64; i > 0; p += 4, i -= 4) { - printf(" %p: %08x %08x %08x %08x\n", p, (uint)p[0], (uint)p[1], (uint)p[2], (uint)p[3]); - } - */ -} diff --git a/stm/pendsv.h b/stm/pendsv.h deleted file mode 100644 index b07ab7137..000000000 --- a/stm/pendsv.h +++ /dev/null @@ -1,3 +0,0 @@ -void pendsv_init(void); -void pendsv_nlr_jump(mp_obj_t o); -void pendsv_isr_handler(void); diff --git a/stm/pin.c b/stm/pin.c deleted file mode 100644 index b201c41e1..000000000 --- a/stm/pin.c +++ /dev/null @@ -1,63 +0,0 @@ -#include -#include -#include -#include - -#include "misc.h" -#include "mpconfig.h" -#include "qstr.h" -#include "obj.h" - -#include "pin.h" - -void pin_obj_print(void (*print)(void *env, const char *fmt, ...), void *env, mp_obj_t self_in, mp_print_kind_t kind) { - pin_obj_t *self = self_in; - print(env, "", self->name); -} - -mp_obj_t pin_obj_name(mp_obj_t self_in) { - pin_obj_t *self = self_in; - return MP_OBJ_NEW_QSTR(qstr_from_str(self->name)); -} - -mp_obj_t pin_obj_port(mp_obj_t self_in) { - pin_obj_t *self = self_in; - return MP_OBJ_NEW_SMALL_INT((mp_small_int_t)self->port); -} - -mp_obj_t pin_obj_pin(mp_obj_t self_in) { - pin_obj_t *self = self_in; - return MP_OBJ_NEW_SMALL_INT((mp_small_int_t)self->pin); -} - -static MP_DEFINE_CONST_FUN_OBJ_1(pin_obj_name_obj, pin_obj_name); -static MP_DEFINE_CONST_FUN_OBJ_1(pin_obj_port_obj, pin_obj_port); -static MP_DEFINE_CONST_FUN_OBJ_1(pin_obj_pin_obj, pin_obj_pin); - -STATIC const mp_map_elem_t pin_locals_dict_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR_name), (mp_obj_t)&pin_obj_name_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_port), (mp_obj_t)&pin_obj_port_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_pin), (mp_obj_t)&pin_obj_pin_obj }, -}; - -STATIC MP_DEFINE_CONST_DICT(pin_locals_dict, pin_locals_dict_table); - -const mp_obj_type_t pin_obj_type = { - { &mp_type_type }, - .name = MP_QSTR_Pin, - .print = pin_obj_print, - .locals_dict = (mp_obj_t)&pin_locals_dict, -}; - -void pin_af_obj_print(void (*print)(void *env, const char *fmt, ...), void *env, mp_obj_t self_in, mp_print_kind_t kind) { - pin_af_obj_t *self = self_in; - print(env, "", self->idx, self->fn, - self->unit, self->type); -} - -const mp_obj_type_t pin_af_obj_type = { - { &mp_type_type }, - .name = MP_QSTR_PinAF, - .print = pin_af_obj_print, -}; - diff --git a/stm/pin.h b/stm/pin.h deleted file mode 100644 index d5d769058..000000000 --- a/stm/pin.h +++ /dev/null @@ -1,117 +0,0 @@ -enum { - PORT_A, - PORT_B, - PORT_C, - PORT_D, - PORT_E, - PORT_F, - PORT_G, - PORT_H, - PORT_I, - PORT_J, -}; - -enum { - AF_FN_TIM, - AF_FN_I2C, - AF_FN_USART, - AF_FN_UART = AF_FN_USART, - AF_FN_SPI -}; - -enum { - AF_PIN_TYPE_TIM_CH1 = 0, - AF_PIN_TYPE_TIM_CH2, - AF_PIN_TYPE_TIM_CH3, - AF_PIN_TYPE_TIM_CH4, - AF_PIN_TYPE_TIM_CH1N, - AF_PIN_TYPE_TIM_CH2N, - AF_PIN_TYPE_TIM_CH3N, - AF_PIN_TYPE_TIM_CH1_ETR, - AF_PIN_TYPE_TIM_ETR, - AF_PIN_TYPE_TIM_BKIN, - - AF_PIN_TYPE_I2C_SDA = 0, - AF_PIN_TYPE_I2C_SCL, - - AF_PIN_TYPE_USART_TX = 0, - AF_PIN_TYPE_USART_RX, - AF_PIN_TYPE_USART_CTS, - AF_PIN_TYPE_USART_RTS, - AF_PIN_TYPE_USART_CK, - AF_PIN_TYPE_UART_TX = AF_PIN_TYPE_USART_TX, - AF_PIN_TYPE_UART_RX = AF_PIN_TYPE_USART_RX, - AF_PIN_TYPE_UART_CTS = AF_PIN_TYPE_USART_CTS, - AF_PIN_TYPE_UART_RTS = AF_PIN_TYPE_USART_RTS, - - AF_PIN_TYPE_SPI_MOSI = 0, - AF_PIN_TYPE_SPI_MISO, - AF_PIN_TYPE_SPI_SCK, - AF_PIN_TYPE_SPI_NSS, -}; - -typedef struct { - mp_obj_base_t base; - uint8_t idx; - uint8_t fn; - uint8_t unit; - uint8_t type; - - union { - void *reg; - TIM_TypeDef *TIM; - I2C_TypeDef *I2C; - USART_TypeDef *USART; - USART_TypeDef *UART; - SPI_TypeDef *SPI; - }; -} pin_af_obj_t; - -typedef struct { - mp_obj_base_t base; - const char *name; - uint16_t port : 4; - uint16_t pin : 4; - uint16_t num_af : 4; - uint16_t pin_mask; - GPIO_TypeDef *gpio; - const pin_af_obj_t *af; -} pin_obj_t; - -extern const mp_obj_type_t pin_obj_type; -extern const mp_obj_type_t pin_af_obj_type; - -typedef struct { - const char *name; - const pin_obj_t *pin; -} pin_named_pin_t; - -extern const pin_named_pin_t pin_board_pins[]; -extern const pin_named_pin_t pin_cpu_pins[]; - -typedef struct { - mp_obj_base_t base; - mp_obj_t mapper; - mp_obj_t map_dict; - bool debug; -} pin_map_obj_t; - -extern pin_map_obj_t pin_map_obj; - -typedef struct { - mp_obj_base_t base; - const char *name; - const pin_named_pin_t *named_pins; -} pin_named_pins_obj_t; - -extern const pin_named_pins_obj_t pin_board_pins_obj; -extern const pin_named_pins_obj_t pin_cpu_pins_obj; - -const pin_obj_t *pin_find_named_pin(const pin_named_pin_t *pins, const char *name); -const pin_af_obj_t *pin_find_af(const pin_obj_t *pin, uint8_t fn, uint8_t unit, uint8_t pin_type); - -void pin_map_init(void); - -// C function for mapping python pin identifier into an ordinal pin number. -const pin_obj_t *pin_map_user_obj(mp_obj_t user_obj); - diff --git a/stm/pin_map.c b/stm/pin_map.c deleted file mode 100644 index bb2c054e7..000000000 --- a/stm/pin_map.c +++ /dev/null @@ -1,226 +0,0 @@ -#include -#include -#include -#include - -#include "misc.h" -#include "mpconfig.h" -#include "qstr.h" -#include "obj.h" -#include "runtime.h" -#include "nlr.h" - -#include "pin.h" - -// Usage Model: -// -// All Board Pins are predefined as pyb.Pin.board.Name -// -// x1_pin = pyb.Pin.board.X1 -// -// g = pyb.gpio(pyb.Pin.board.X1, 0) -// -// CPU pins which correspond to the board pins are available -// as pyb.cpu.Name. For the CPU pins, the names are the port letter -// followed by the pin number. On the PYBOARD4, pyb.Pin.board.X1 and -// pyb.Pin.cpu.B6 are the same pin. -// -// You can also use strings: -// -// g = pyb.gpio('X1', 0) -// -// Users can add their own names: -// -// pyb.Pin("LeftMotorDir", pyb.Pin.cpu.C12) -// g = pyb.gpio("LeftMotorDir", 0) -// -// and can query mappings -// -// pin = pyb.Pin("LeftMotorDir"); -// -// Users can also add their own mapping function: -// -// def MyMapper(pin_name): -// if pin_name == "LeftMotorDir": -// return pyb.Pin.cpu.A0 -// -// pyb.Pin.mapper(MyMapper) -// -// So, if you were to call: pyb.gpio("LeftMotorDir", 0) -// then "LeftMotorDir" is passed directly to the mapper function. -// -// To summarize, the following order determines how things get mapped into -// an ordinal pin number: -// -// 1 - Directly specify a pin object -// 2 - User supplied mapping function -// 3 - User supplied mapping (object must be usable as a dictionary key) -// 4 - Supply a string which matches a board pin -// 5 - Supply a string which matches a CPU port/pin -// -// You can set pyb.Pin.debug(True) to get some debug information about -// how a particular object gets mapped to a pin. - -static void pin_map_obj_print(void (*print)(void *env, const char *fmt, ...), void *env, mp_obj_t self_in, mp_print_kind_t kind) { - (void)self_in; - print(env, ""); -} - -static mp_obj_t pin_map_call(mp_obj_t self_in, uint n_args, uint n_kw, const mp_obj_t *args) { - pin_map_obj_t *self = self_in; - mp_arg_check_num(n_args, n_kw, 1, 2, false); - - if (n_args > 1) { - if (!self->map_dict) { - self->map_dict = mp_obj_new_dict(1); - } - mp_obj_dict_store(self->map_dict, args[0], args[1]); - return mp_const_none; - } - - // Run an argument through the mapper and return the result. - return (mp_obj_t)pin_map_user_obj(args[0]); -} - -static mp_obj_t pin_map_obj_mapper(uint n_args, mp_obj_t *args) { - pin_map_obj_t *self = args[0]; - if (n_args > 1) { - self->mapper = args[1]; - return mp_const_none; - } - return self->mapper; -} -static MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pin_map_obj_mapper_obj, 1, 2, pin_map_obj_mapper); - -static mp_obj_t pin_map_obj_debug(uint n_args, mp_obj_t *args) { - pin_map_obj_t *self = args[0]; - if (n_args > 1) { - self->debug = mp_obj_is_true(args[1]); - return mp_const_none; - } - return MP_BOOL(self->debug); -} -static MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pin_map_obj_debug_obj, 1, 2, pin_map_obj_debug); - -static void pin_map_load_attr(mp_obj_t self_in, qstr attr_qstr, mp_obj_t *dest) { - (void)self_in; - const char *attr = qstr_str(attr_qstr); - - if (strcmp(attr, "mapper") == 0) { - dest[0] = (mp_obj_t)&pin_map_obj_mapper_obj; - dest[1] = self_in; - } - if (strcmp(attr, "debug") == 0) { - dest[0] = (mp_obj_t)&pin_map_obj_debug_obj; - dest[1] = self_in; - } - if (strcmp(attr, pin_board_pins_obj.name) == 0) { - dest[0] = (mp_obj_t)&pin_board_pins_obj; - dest[1] = MP_OBJ_NULL; - } - if (strcmp(attr, pin_cpu_pins_obj.name) == 0) { - dest[0] = (mp_obj_t)&pin_cpu_pins_obj; - dest[1] = MP_OBJ_NULL; - } -} - -static const mp_obj_type_t pin_map_obj_type = { - { &mp_type_type }, - .name = MP_QSTR_PinMap, - .print = pin_map_obj_print, - .call = pin_map_call, - .load_attr = pin_map_load_attr, -}; - -static const pin_map_obj_t pin_map_obj_init = { - { &pin_map_obj_type }, - .mapper = MP_OBJ_NULL, - .map_dict = MP_OBJ_NULL, - .debug = false, -}; - -pin_map_obj_t pin_map_obj; - -void pin_map_init(void) { - pin_map_obj = pin_map_obj_init; -} - -// C API used to convert a user-supplied pin name into an ordinal pin number. -const pin_obj_t *pin_map_user_obj(mp_obj_t user_obj) { - const pin_obj_t *pin_obj; - - // If a pin was provided, then use it - if (MP_OBJ_IS_TYPE(user_obj, &pin_obj_type)) { - pin_obj = user_obj; - if (pin_map_obj.debug) { - printf("Pin map passed pin "); - mp_obj_print((mp_obj_t)pin_obj, PRINT_STR); - printf("\n"); - } - return pin_obj; - } - - if (pin_map_obj.mapper) { - pin_obj = mp_call_function_1(pin_map_obj.mapper, user_obj); - if (pin_obj != mp_const_none) { - if (!MP_OBJ_IS_TYPE(pin_obj, &pin_obj_type)) { - nlr_raise(mp_obj_new_exception_msg(&mp_type_ValueError, "Pin.mapper didn't return a Pin object")); - } - if (pin_map_obj.debug) { - printf("Pin.mapper maps "); - mp_obj_print(user_obj, PRINT_REPR); - printf(" to "); - mp_obj_print((mp_obj_t)pin_obj, PRINT_STR); - printf("\n"); - } - return pin_obj; - } - // The pin mapping function returned mp_const_none, fall through to - // other lookup methods. - } - - if (pin_map_obj.map_dict) { - mp_map_t *pin_map_map = mp_obj_dict_get_map(pin_map_obj.map_dict); - mp_map_elem_t *elem = mp_map_lookup(pin_map_map, user_obj, MP_MAP_LOOKUP); - if (elem != NULL && elem->value != NULL) { - pin_obj = elem->value; - if (pin_map_obj.debug) { - printf("Pin.map_dict maps "); - mp_obj_print(user_obj, PRINT_REPR); - printf(" to "); - mp_obj_print((mp_obj_t)pin_obj, PRINT_STR); - printf("\n"); - } - return pin_obj; - } - } - - // See if the pin name matches a board pin - const char *pin_name = mp_obj_str_get_str(user_obj); - pin_obj = pin_find_named_pin(pin_board_pins, pin_name); - if (pin_obj) { - if (pin_map_obj.debug) { - printf("Pin.board maps "); - mp_obj_print(user_obj, PRINT_REPR); - printf(" to "); - mp_obj_print((mp_obj_t)pin_obj, PRINT_STR); - printf("\n"); - } - return pin_obj; - } - - // See if the pin name matches a cpu pin - pin_obj = pin_find_named_pin(pin_cpu_pins, pin_name); - if (pin_obj) { - if (pin_map_obj.debug) { - printf("Pin.cpu maps "); - mp_obj_print(user_obj, PRINT_REPR); - printf(" to "); - mp_obj_print((mp_obj_t)pin_obj, PRINT_STR); - printf("\n"); - } - return pin_obj; - } - - nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "pin '%s' not a valid pin identifier", pin_name)); -} diff --git a/stm/pin_named_pins.c b/stm/pin_named_pins.c deleted file mode 100644 index d68722b4a..000000000 --- a/stm/pin_named_pins.c +++ /dev/null @@ -1,67 +0,0 @@ -#include -#include -#include -#include - -#include "misc.h" -#include "mpconfig.h" -#include "qstr.h" -#include "obj.h" -#include "runtime.h" - -#include "pin.h" - -static void pin_named_pins_obj_print(void (*print)(void *env, const char *fmt, ...), void *env, mp_obj_t self_in, mp_print_kind_t kind) { - pin_named_pins_obj_t *self = self_in; - print(env, "", self->name); -} - -static void pin_named_pins_obj_load_attr(mp_obj_t self_in, qstr attr_qstr, mp_obj_t *dest) { - pin_named_pins_obj_t *self = self_in; - const char *attr = qstr_str(attr_qstr); - const pin_obj_t *pin = pin_find_named_pin(self->named_pins, attr); - if (pin) { - dest[0] = (mp_obj_t)pin; - dest[1] = MP_OBJ_NULL; - } -} - -static const mp_obj_type_t pin_named_pins_obj_type = { - { &mp_type_type }, - .name = MP_QSTR_PinNamed, - .print = pin_named_pins_obj_print, - .load_attr = pin_named_pins_obj_load_attr, -}; - -const pin_named_pins_obj_t pin_board_pins_obj = { - { &pin_named_pins_obj_type }, - .name = "board", - .named_pins = pin_board_pins, -}; - -const pin_named_pins_obj_t pin_cpu_pins_obj = { - { &pin_named_pins_obj_type }, - .name = "cpu", - .named_pins = pin_cpu_pins, -}; - -const pin_obj_t *pin_find_named_pin(const pin_named_pin_t *named_pins, const char *name) { - const pin_named_pin_t *named_pin = named_pins; - while (named_pin->name) { - if (!strcmp(name, named_pin->name)) { - return named_pin->pin; - } - named_pin++; - } - return NULL; -} - -const pin_af_obj_t *pin_find_af(const pin_obj_t *pin, uint8_t fn, uint8_t unit, uint8_t type) { - const pin_af_obj_t *af = pin->af; - for (int i = 0; i < pin->num_af; i++, af++) { - if (af->fn == fn && af->unit == unit && af->type == type) { - return af; - } - } - return NULL; -} diff --git a/stm/printf.c b/stm/printf.c deleted file mode 100644 index 446b3182f..000000000 --- a/stm/printf.c +++ /dev/null @@ -1,363 +0,0 @@ -#include -#include -#include - -#include "std.h" -#include "misc.h" -#include "systick.h" -#include "mpconfig.h" -#include "qstr.h" -#include "obj.h" -#include "lcd.h" -#include "usart.h" -#include "usb.h" - -#if MICROPY_ENABLE_FLOAT -#include "formatfloat.h" -#endif - -#define PF_FLAG_LEFT_ADJUST (0x01) -#define PF_FLAG_SHOW_SIGN (0x02) -#define PF_FLAG_SPACE_SIGN (0x04) -#define PF_FLAG_NO_TRAILZ (0x08) -#define PF_FLAG_ZERO_PAD (0x10) - -// tricky; we compute pad string by: pad_chars + (flags & PF_FLAG_ZERO_PAD) -#define PF_PAD_SIZE PF_FLAG_ZERO_PAD -static const char *pad_chars = " 0000000000000000"; - -typedef struct _pfenv_t { - void *data; - void (*print_strn)(void *, const char *str, unsigned int len); -} pfenv_t; - -static void print_str_dummy(void *data, const char *str, unsigned int len) { -} - -const pfenv_t pfenv_dummy = {0, print_str_dummy}; - -static int pfenv_print_strn(const pfenv_t *pfenv, const char *str, unsigned int len, int flags, int width) { - int pad = width - len; - if (pad > 0 && (flags & PF_FLAG_LEFT_ADJUST) == 0) { - while (pad > 0) { - int p = pad; - if (p > PF_PAD_SIZE) - p = PF_PAD_SIZE; - pfenv->print_strn(pfenv->data, pad_chars + (flags & PF_FLAG_ZERO_PAD), p); - pad -= p; - } - } - pfenv->print_strn(pfenv->data, str, len); - while (pad > 0) { - int p = pad; - if (p > PF_PAD_SIZE) - p = PF_PAD_SIZE; - pfenv->print_strn(pfenv->data, pad_chars, p); - pad -= p; - } - return len; -} - -// enough room for 32 signed number -#define INT_BUF_SIZE (12) - -static int pfenv_print_int(const pfenv_t *pfenv, unsigned int x, int sgn, int base, int base_char, int flags, int width) { - char sign = 0; - if (sgn) { - if ((int)x < 0) { - sign = '-'; - x = -x; - } else if (flags & PF_FLAG_SHOW_SIGN) { - sign = '+'; - } else if (flags & PF_FLAG_SPACE_SIGN) { - sign = ' '; - } - } - - char buf[INT_BUF_SIZE]; - char *b = buf + INT_BUF_SIZE; - - if (x == 0) { - *(--b) = '0'; - } else { - do { - int c = x % base; - x /= base; - if (c >= 10) { - c += base_char - 10; - } else { - c += '0'; - } - *(--b) = c; - } while (b > buf && x != 0); - } - - if (b > buf && sign != 0) { - *(--b) = sign; - } - - return pfenv_print_strn(pfenv, b, buf + INT_BUF_SIZE - b, flags, width); -} - -void pfenv_prints(const pfenv_t *pfenv, const char *str) { - pfenv->print_strn(pfenv->data, str, strlen(str)); -} - -int pfenv_printf(const pfenv_t *pfenv, const char *fmt, va_list args) { - int chrs = 0; - for (;;) { - { - const char *f = fmt; - while (*f != '\0' && *f != '%') { - ++f; // XXX UTF8 advance char - } - if (f > fmt) { - pfenv->print_strn(pfenv->data, fmt, f - fmt); - chrs += f - fmt; - fmt = f; - } - } - - if (*fmt == '\0') { - break; - } - - // move past % character - ++fmt; - - // parse flags, if they exist - int flags = 0; - while (*fmt != '\0') { - if (*fmt == '-') flags |= PF_FLAG_LEFT_ADJUST; - else if (*fmt == '+') flags |= PF_FLAG_SHOW_SIGN; - else if (*fmt == ' ') flags |= PF_FLAG_SPACE_SIGN; - else if (*fmt == '!') flags |= PF_FLAG_NO_TRAILZ; - else if (*fmt == '0') flags |= PF_FLAG_ZERO_PAD; - else break; - ++fmt; - } - - // parse width, if it exists - int width = 0; - for (; '0' <= *fmt && *fmt <= '9'; ++fmt) { - width = width * 10 + *fmt - '0'; - } - - // parse precision, if it exists - int prec = -1; - if (*fmt == '.') { - ++fmt; - if (*fmt == '*') { - ++fmt; - prec = va_arg(args, int); - } else { - prec = 0; - for (; '0' <= *fmt && *fmt <= '9'; ++fmt) { - prec = prec * 10 + *fmt - '0'; - } - } - if (prec < 0) { - prec = 0; - } - } - - // parse long specifiers (current not used) - //bool long_arg = false; - if (*fmt == 'l') { - ++fmt; - //long_arg = true; - } - - if (*fmt == '\0') { - break; - } - - switch (*fmt) { - case 'b': - if (va_arg(args, int)) { - chrs += pfenv_print_strn(pfenv, "true", 4, flags, width); - } else { - chrs += pfenv_print_strn(pfenv, "false", 5, flags, width); - } - break; - case 'c': - { - char str = va_arg(args, int); - chrs += pfenv_print_strn(pfenv, &str, 1, flags, width); - break; - } - case 's': - { - const char *str = va_arg(args, const char*); - if (str) { - if (prec < 0) { - prec = strlen(str); - } - chrs += pfenv_print_strn(pfenv, str, prec, flags, width); - } else { - chrs += pfenv_print_strn(pfenv, "(null)", 6, flags, width); - } - break; - } - case 'u': - chrs += pfenv_print_int(pfenv, va_arg(args, int), 0, 10, 'a', flags, width); - break; - case 'd': - chrs += pfenv_print_int(pfenv, va_arg(args, int), 1, 10, 'a', flags, width); - break; - case 'x': - case 'p': // ? - chrs += pfenv_print_int(pfenv, va_arg(args, int), 0, 16, 'a', flags, width); - break; - case 'X': - case 'P': // ? - chrs += pfenv_print_int(pfenv, va_arg(args, int), 0, 16, 'A', flags, width); - break; -#if MICROPY_ENABLE_FLOAT - case 'e': - case 'E': - case 'f': - case 'F': - case 'g': - case 'G': - { - char buf[32]; - char sign = '\0'; - - if (flags & PF_FLAG_SHOW_SIGN) { - sign = '+'; - } - else - if (flags & PF_FLAG_SPACE_SIGN) { - sign = ' '; - } - float f = va_arg(args, double); - int len = format_float(f, buf, sizeof(buf), *fmt, prec, sign); - char *s = buf; - - // buf[0] < '0' returns true if the first character is space, + or - - // buf[1] < '9' matches a digit, and doesn't match when we get back +nan or +inf - if (buf[0] < '0' && buf[1] <= '9' && (flags & PF_FLAG_ZERO_PAD)) { - chrs += pfenv_print_strn(pfenv, &buf[0], 1, 0, 1); - s++; - width--; - len--; - } - if (*s < '0' || *s >= '9') { - // For inf or nan, we don't want to zero pad. - flags &= ~PF_FLAG_ZERO_PAD; - } - chrs += pfenv_print_strn(pfenv, s, len, flags, width); - break; - } -#endif - default: - pfenv->print_strn(pfenv->data, fmt, 1); - chrs += 1; - break; - } - ++fmt; - } - return chrs; -} - -void stdout_print_strn(void *data, const char *str, unsigned int len) { - // send stdout to USART, USB CDC VCP, and LCD if nothing else - bool any = false; - - if (pyb_usart_global_debug != PYB_USART_NONE) { - usart_tx_strn_cooked(pyb_usart_global_debug, str, len); - any = true; - } - if (usb_vcp_is_enabled()) { - usb_vcp_send_strn_cooked(str, len); - any = true; - } - if (!any) { -#if MICROPY_HW_HAS_LCD - lcd_print_strn(str, len); -#endif - } -} - -static const pfenv_t pfenv_stdout = {0, stdout_print_strn}; - -int printf(const char *fmt, ...) { - va_list ap; - va_start(ap, fmt); - int ret = pfenv_printf(&pfenv_stdout, fmt, ap); - va_end(ap); - return ret; -} - -int vprintf(const char *fmt, va_list ap) { - return pfenv_printf(&pfenv_stdout, fmt, ap); -} - -#if MICROPY_DEBUG_PRINTERS -int DEBUG_printf(const char *fmt, ...) { - (void)stream; - va_list ap; - va_start(ap, fmt); - int ret = pfenv_printf(&pfenv_stdout, fmt, ap); - va_end(ap); - return ret; -} -#endif - -// need this because gcc optimises printf("%c", c) -> putchar(c), and printf("a") -> putchar('a') -int putchar(int c) { - char chr = c; - stdout_print_strn(0, &chr, 1); - return chr; -} - -// need this because gcc optimises printf("string\n") -> puts("string") -int puts(const char *s) { - stdout_print_strn(0, s, strlen(s)); - char chr = '\n'; - stdout_print_strn(0, &chr, 1); - return 1; -} - -typedef struct _strn_pfenv_t { - char *cur; - size_t remain; -} strn_pfenv_t; - -void strn_print_strn(void *data, const char *str, unsigned int len) { - strn_pfenv_t *strn_pfenv = data; - if (len > strn_pfenv->remain) { - len = strn_pfenv->remain; - } - memcpy(strn_pfenv->cur, str, len); - strn_pfenv->cur += len; - strn_pfenv->remain -= len; -} - -int vsnprintf(char *str, size_t size, const char *fmt, va_list ap) { - strn_pfenv_t strn_pfenv; - strn_pfenv.cur = str; - strn_pfenv.remain = size; - pfenv_t pfenv; - pfenv.data = &strn_pfenv; - pfenv.print_strn = strn_print_strn; - int len = pfenv_printf(&pfenv, fmt, ap); - // add terminating null byte - if (size > 0) { - if (strn_pfenv.remain == 0) { - strn_pfenv.cur[-1] = 0; - } else { - strn_pfenv.cur[0] = 0; - } - } - return len; -} - -int snprintf(char *str, size_t size, const char *fmt, ...) { - va_list ap; - va_start(ap, fmt); - int ret = vsnprintf(str, size, fmt, ap); - va_end(ap); - return ret; -} diff --git a/stm/pybmodule.c b/stm/pybmodule.c deleted file mode 100644 index 40275949f..000000000 --- a/stm/pybmodule.c +++ /dev/null @@ -1,291 +0,0 @@ -#include -#include - -#include -#include - -#include "misc.h" -#include "ff.h" -#include "mpconfig.h" -#include "qstr.h" -#include "obj.h" -#include "gc.h" -#include "gccollect.h" -#include "systick.h" -#include "rtc.h" -#include "pyexec.h" -#include "servo.h" -#include "storage.h" -#include "usb.h" -#include "usrsw.h" -#include "sdcard.h" -#include "accel.h" -#include "led.h" -#include "i2c.h" -#include "usart.h" -#include "adc.h" -#include "audio.h" -#include "pin.h" -#include "gpio.h" -#include "exti.h" -#include "pybmodule.h" - -// get lots of info about the board -STATIC mp_obj_t pyb_info(void) { - // get and print unique id; 96 bits - { - byte *id = (byte*)0x1fff7a10; - printf("ID=%02x%02x%02x%02x:%02x%02x%02x%02x:%02x%02x%02x%02x\n", id[0], id[1], id[2], id[3], id[4], id[5], id[6], id[7], id[8], id[9], id[10], id[11]); - } - - // get and print clock speeds - // SYSCLK=168MHz, HCLK=168MHz, PCLK1=42MHz, PCLK2=84MHz - { - RCC_ClocksTypeDef rcc_clocks; - RCC_GetClocksFreq(&rcc_clocks); - printf("S=%lu\nH=%lu\nP1=%lu\nP2=%lu\n", rcc_clocks.SYSCLK_Frequency, rcc_clocks.HCLK_Frequency, rcc_clocks.PCLK1_Frequency, rcc_clocks.PCLK2_Frequency); - } - - // to print info about memory - { - printf("_text_end=%p\n", &_text_end); - printf("_data_start_init=%p\n", &_data_start_init); - printf("_data_start=%p\n", &_data_start); - printf("_data_end=%p\n", &_data_end); - printf("_bss_start=%p\n", &_bss_start); - printf("_bss_end=%p\n", &_bss_end); - printf("_stack_end=%p\n", &_stack_end); - printf("_ram_start=%p\n", &_ram_start); - printf("_heap_start=%p\n", &_heap_start); - printf("_heap_end=%p\n", &_heap_end); - printf("_ram_end=%p\n", &_ram_end); - } - - // qstr info - { - uint n_pool, n_qstr, n_str_data_bytes, n_total_bytes; - qstr_pool_info(&n_pool, &n_qstr, &n_str_data_bytes, &n_total_bytes); - printf("qstr:\n n_pool=%u\n n_qstr=%u\n n_str_data_bytes=%u\n n_total_bytes=%u\n", n_pool, n_qstr, n_str_data_bytes, n_total_bytes); - } - - // GC info - { - gc_info_t info; - gc_info(&info); - printf("GC:\n"); - printf(" %lu total\n", info.total); - printf(" %lu : %lu\n", info.used, info.free); - printf(" 1=%lu 2=%lu m=%lu\n", info.num_1block, info.num_2block, info.max_block); - } - - // free space on flash - { - DWORD nclst; - FATFS *fatfs; - f_getfree("0:", &nclst, &fatfs); - printf("LFS free: %u bytes\n", (uint)(nclst * fatfs->csize * 512)); - } - - return mp_const_none; -} - -STATIC MP_DEFINE_CONST_FUN_OBJ_0(pyb_info_obj, pyb_info); - -// sync all file systems -STATIC mp_obj_t pyb_sync(void) { - storage_flush(); - return mp_const_none; -} - -STATIC MP_DEFINE_CONST_FUN_OBJ_0(pyb_sync_obj, pyb_sync); - -STATIC mp_obj_t pyb_millis(void) { - return mp_obj_new_int(sys_tick_counter); -} - -STATIC MP_DEFINE_CONST_FUN_OBJ_0(pyb_millis_obj, pyb_millis); - -STATIC mp_obj_t pyb_delay(mp_obj_t count) { - sys_tick_delay_ms(mp_obj_get_int(count)); - return mp_const_none; -} - -STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_delay_obj, pyb_delay); - -STATIC mp_obj_t pyb_udelay(mp_obj_t usec) { - uint32_t count = 0; - const uint32_t utime = (168 * mp_obj_get_int(usec) / 5); - for (;;) { - if (++count > utime) { - return mp_const_none; - } - } -} - -STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_udelay_obj, pyb_udelay); - -STATIC mp_obj_t pyb_rng_get(void) { - return mp_obj_new_int(RNG_GetRandomNumber() >> 16); -} - -STATIC MP_DEFINE_CONST_FUN_OBJ_0(pyb_rng_get_obj, pyb_rng_get); - -STATIC void SYSCLKConfig_STOP(void) { - /* After wake-up from STOP reconfigure the system clock */ - /* Enable HSE */ - RCC_HSEConfig(RCC_HSE_ON); - - /* Wait till HSE is ready */ - while (RCC_GetFlagStatus(RCC_FLAG_HSERDY) == RESET) { - } - - /* Enable PLL */ - RCC_PLLCmd(ENABLE); - - /* Wait till PLL is ready */ - while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) { - } - - /* Select PLL as system clock source */ - RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); - - /* Wait till PLL is used as system clock source */ - while (RCC_GetSYSCLKSource() != 0x08) { - } -} - -STATIC mp_obj_t pyb_stop(void) { - PWR_EnterSTANDBYMode(); - //PWR_FlashPowerDownCmd(ENABLE); don't know what the logic is with this - - /* Enter Stop Mode */ - PWR_EnterSTOPMode(PWR_Regulator_LowPower, PWR_STOPEntry_WFI); - - /* Configures system clock after wake-up from STOP: enable HSE, PLL and select - * PLL as system clock source (HSE and PLL are disabled in STOP mode) */ - SYSCLKConfig_STOP(); - - //PWR_FlashPowerDownCmd(DISABLE); - - return mp_const_none; -} - -MP_DEFINE_CONST_FUN_OBJ_0(pyb_stop_obj, pyb_stop); - -STATIC mp_obj_t pyb_standby(void) { - PWR_EnterSTANDBYMode(); - return mp_const_none; -} - -MP_DEFINE_CONST_FUN_OBJ_0(pyb_standby_obj, pyb_standby); - -STATIC mp_obj_t pyb_hid_send_report(mp_obj_t arg) { - mp_obj_t *items; - mp_obj_get_array_fixed_n(arg, 4, &items); - uint8_t data[4]; - data[0] = mp_obj_get_int(items[0]); - data[1] = mp_obj_get_int(items[1]); - data[2] = mp_obj_get_int(items[2]); - data[3] = mp_obj_get_int(items[3]); - usb_hid_send_report(data); - return mp_const_none; -} - -MP_DEFINE_CONST_FUN_OBJ_1(pyb_hid_send_report_obj, pyb_hid_send_report); - -MP_DEFINE_CONST_FUN_OBJ_2(pyb_I2C_obj, pyb_I2C); // TODO put this in i2c.c - -MP_DECLARE_CONST_FUN_OBJ(pyb_source_dir_obj); // defined in main.c -MP_DECLARE_CONST_FUN_OBJ(pyb_main_obj); // defined in main.c - -STATIC const mp_map_elem_t pyb_module_globals_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_pyb) }, - - { MP_OBJ_NEW_QSTR(MP_QSTR_info), (mp_obj_t)&pyb_info_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_gc), (mp_obj_t)&pyb_gc_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_repl_info), (mp_obj_t)&pyb_set_repl_info_obj }, - - { MP_OBJ_NEW_QSTR(MP_QSTR_stop), (mp_obj_t)&pyb_stop_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_standby), (mp_obj_t)&pyb_standby_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_source_dir), (mp_obj_t)&pyb_source_dir_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_main), (mp_obj_t)&pyb_main_obj }, - - { MP_OBJ_NEW_QSTR(MP_QSTR_millis), (mp_obj_t)&pyb_millis_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_delay), (mp_obj_t)&pyb_delay_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_udelay), (mp_obj_t)&pyb_udelay_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_sync), (mp_obj_t)&pyb_sync_obj }, - -#if MICROPY_HW_ENABLE_RNG - { MP_OBJ_NEW_QSTR(MP_QSTR_rand), (mp_obj_t)&pyb_rng_get_obj }, -#endif - -#if MICROPY_HW_ENABLE_RTC - { MP_OBJ_NEW_QSTR(MP_QSTR_time), (mp_obj_t)&pyb_rtc_read_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_rtc_info), (mp_obj_t)&pyb_rtc_info_obj }, -#endif - -#if MICROPY_HW_ENABLE_SERVO - { MP_OBJ_NEW_QSTR(MP_QSTR_pwm), (mp_obj_t)&pyb_pwm_set_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_servo), (mp_obj_t)&pyb_servo_set_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_Servo), (mp_obj_t)&pyb_Servo_obj }, -#endif - -#if MICROPY_HW_HAS_SWITCH - { MP_OBJ_NEW_QSTR(MP_QSTR_switch), (mp_obj_t)&pyb_switch_obj }, -#endif - -#if MICROPY_HW_HAS_SDCARD - { MP_OBJ_NEW_QSTR(MP_QSTR_SD), (mp_obj_t)&pyb_sdcard_obj }, -#endif - -#if MICROPY_HW_HAS_MMA7660 - { MP_OBJ_NEW_QSTR(MP_QSTR_accel), (mp_obj_t)&pyb_accel_read_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_accel_read), (mp_obj_t)&pyb_accel_read_all_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_accel_mode), (mp_obj_t)&pyb_accel_write_mode_obj }, -#endif - - { MP_OBJ_NEW_QSTR(MP_QSTR_hid), (mp_obj_t)&pyb_hid_send_report_obj }, - - { MP_OBJ_NEW_QSTR(MP_QSTR_Led), (mp_obj_t)&pyb_Led_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_I2C), (mp_obj_t)&pyb_I2C_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_Usart), (mp_obj_t)&pyb_Usart_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_ADC_all), (mp_obj_t)&pyb_ADC_all_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_ADC), (mp_obj_t)&pyb_ADC_obj }, - -#if MICROPY_HW_ENABLE_AUDIO - { MP_OBJ_NEW_QSTR(MP_QSTR_Audio), (mp_obj_t)&pyb_Audio_obj }, -#endif - - // pin mapper - { MP_OBJ_NEW_QSTR(MP_QSTR_Pin), (mp_obj_t)&pin_map_obj }, - - // GPIO bindings - { MP_OBJ_NEW_QSTR(MP_QSTR_gpio), (mp_obj_t)&pyb_gpio_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_gpio_in), (mp_obj_t)&pyb_gpio_input_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_gpio_out), (mp_obj_t)&pyb_gpio_output_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_PULL_NONE), MP_OBJ_NEW_SMALL_INT(GPIO_PuPd_NOPULL) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_PULL_UP), MP_OBJ_NEW_SMALL_INT(GPIO_PuPd_UP) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_PULL_DOWN), MP_OBJ_NEW_SMALL_INT(GPIO_PuPd_DOWN) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_PUSH_PULL), MP_OBJ_NEW_SMALL_INT(GPIO_OType_PP) }, - { MP_OBJ_NEW_QSTR(MP_QSTR_OPEN_DRAIN), MP_OBJ_NEW_SMALL_INT(GPIO_OType_OD) }, - - // EXTI bindings - { MP_OBJ_NEW_QSTR(MP_QSTR_Exti), (mp_obj_t)&exti_obj_type }, -}; - -STATIC const mp_obj_dict_t pyb_module_globals = { - .base = {&mp_type_dict}, - .map = { - .all_keys_are_qstrs = 1, - .table_is_fixed_array = 1, - .used = sizeof(pyb_module_globals_table) / sizeof(mp_map_elem_t), - .alloc = sizeof(pyb_module_globals_table) / sizeof(mp_map_elem_t), - .table = (mp_map_elem_t*)pyb_module_globals_table, - }, -}; - -const mp_obj_module_t pyb_module = { - .base = { &mp_type_module }, - .name = MP_QSTR_pyb, - .globals = (mp_obj_dict_t*)&pyb_module_globals, -}; diff --git a/stm/pybmodule.h b/stm/pybmodule.h deleted file mode 100644 index 955aaefe3..000000000 --- a/stm/pybmodule.h +++ /dev/null @@ -1 +0,0 @@ -extern const mp_obj_module_t pyb_module; diff --git a/stm/pybwlan.c b/stm/pybwlan.c deleted file mode 100644 index f4e6f8021..000000000 --- a/stm/pybwlan.c +++ /dev/null @@ -1,389 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "std.h" - -#include "misc.h" -#include "mpconfig.h" -#include "qstr.h" -#include "systick.h" - -#include "nlr.h" -#include "misc.h" -#include "lexer.h" -#include "parse.h" -#include "obj.h" -#include "runtime.h" - -#include "cc3k/ccspi.h" -#include "cc3k/hci.h" -#include "cc3k/socket.h" -#include "cc3k/netapp.h" -#include "cc3k/wlan.h" -#include "cc3k/nvmem.h" - -mp_obj_t pyb_wlan_connect(uint n_args, const mp_obj_t *args) { - const char *ap; - const char *key; - if (n_args == 2) { - ap = qstr_str(mp_obj_get_qstr(args[0])); - key = qstr_str(mp_obj_get_qstr(args[1])); - } else { - ap = "your-ssid"; - key = "your-password"; - } - // might want to set wlan_ioctl_set_connection_policy - int ret = wlan_connect(WLAN_SEC_WPA2, ap, strlen(ap), NULL, (byte*)key, strlen(key)); - return mp_obj_new_int(ret); -} - -mp_obj_t pyb_wlan_disconnect(void) { - int ret = wlan_disconnect(); - return mp_obj_new_int(ret); -} - -mp_obj_t decode_addr(unsigned char *ip, int n_bytes) { - char data[64] = ""; - if (n_bytes == 4) { - snprintf(data, 64, "%u.%u.%u.%u", ip[3], ip[2], ip[1], ip[0]); - } else if (n_bytes == 6) { - snprintf(data, 64, "%02x:%02x:%02x:%02x:%02x:%02x", ip[5], ip[4], ip[3], ip[2], ip[1], ip[0]); - } else if (n_bytes == 32) { - snprintf(data, 64, "%s", ip); - } - return mp_obj_new_str(qstr_from_strn(data, strlen(data))); -} - -void decode_addr_and_store(mp_obj_t object, qstr q_attr, unsigned char *ip, int n_bytes) { - rt_store_attr(object, q_attr, decode_addr(ip, n_bytes)); -} - -static mp_obj_t net_address_type = MP_OBJ_NULL; - -mp_obj_t pyb_wlan_get_ip(void) { - tNetappIpconfigRetArgs ipconfig; - netapp_ipconfig(&ipconfig); - - // If byte 1 is 0 we don't have a valid address - if (ipconfig.aucIP[3] == 0) { - return mp_const_none; - } - - // if it doesn't already exist, make a new empty class for NetAddress objects - if (net_address_type == MP_OBJ_NULL) { - net_address_type = mp_obj_new_type(QSTR_FROM_STR_STATIC("NetAddress"), mp_const_empty_tuple, mp_obj_new_dict(0)); - } - - // make a new NetAddress object - mp_obj_t net_addr = rt_call_function_0(net_address_type); - - // fill the NetAddress object with data - decode_addr_and_store(net_addr, QSTR_FROM_STR_STATIC("ip"), &ipconfig.aucIP[0], 4); - decode_addr_and_store(net_addr, QSTR_FROM_STR_STATIC("subnet"), &ipconfig.aucSubnetMask[0], 4); - decode_addr_and_store(net_addr, QSTR_FROM_STR_STATIC("gateway"), &ipconfig.aucDefaultGateway[0], 4); - decode_addr_and_store(net_addr, QSTR_FROM_STR_STATIC("dhcp"), &ipconfig.aucDHCPServer[0], 4); - decode_addr_and_store(net_addr, QSTR_FROM_STR_STATIC("dns"), &ipconfig.aucDNSServer[0], 4); - decode_addr_and_store(net_addr, QSTR_FROM_STR_STATIC("mac"), &ipconfig.uaMacAddr[0], 6); - decode_addr_and_store(net_addr, QSTR_FROM_STR_STATIC("ssid"), &ipconfig.uaSSID[0], 32); - - return net_addr; -} - -uint32_t last_ip = 0; // XXX such a hack! -mp_obj_t pyb_wlan_get_host(mp_obj_t host_name) { - const char *host = qstr_str(mp_obj_get_qstr(host_name)); - uint32_t ip; - if (gethostbyname(host, strlen(host), &ip) < 0) { - printf("gethostbyname failed\n"); - return mp_const_none; - } - if (ip == 0) { - // unknown host - return mp_const_none; - } - last_ip = ip; - byte ip_data[4]; - ip_data[0] = ((ip >> 0) & 0xff); - ip_data[1] = ((ip >> 8) & 0xff); - ip_data[2] = ((ip >> 16) & 0xff); - ip_data[3] = ((ip >> 24) & 0xff); - return decode_addr(ip_data, 4); -} - -mp_obj_t pyb_wlan_http_get(mp_obj_t host_name, mp_obj_t host_path) { - if (host_name == mp_const_none) { - last_ip = (192 << 24) | (168 << 16) | (0 << 8) | (3); - } else { - if (pyb_wlan_get_host(host_name) == mp_const_none) { - nlr_raise(mp_obj_new_exception_msg(QSTR_FROM_STR_STATIC("WlanError"), "unknown host")); - } - } - int sd = socket(AF_INET, SOCK_STREAM, IPPROTO_TCP); - if (sd < 0) { - nlr_raise(mp_obj_new_exception_msg_varg(QSTR_FROM_STR_STATIC("WlanError"), "socket failed: %d", sd)); - } - //printf("socket seemed to work\n"); - //sys_tick_delay_ms(200); - sockaddr_in remote; - memset(&remote, 0, sizeof(sockaddr_in)); - remote.sin_family = AF_INET; - remote.sin_port = htons(80); - remote.sin_addr.s_addr = htonl(last_ip); - int ret = connect(sd, (sockaddr*)&remote, sizeof(sockaddr)); - if (ret != 0) { - nlr_raise(mp_obj_new_exception_msg_varg(QSTR_FROM_STR_STATIC("WlanError"), "connect failed: %d", ret)); - } - //printf("connect seemed to work\n"); - //sys_tick_delay_ms(200); - - vstr_t *vstr = vstr_new(); - vstr_printf(vstr, "GET %s HTTP/1.1\r\nHost: %s\r\nUser-Agent: PYBv2\r\n\r\n", qstr_str(mp_obj_get_qstr(host_path)), qstr_str(mp_obj_get_qstr(host_name))); - const char *query = vstr_str(vstr); - - // send query - { - int sent = 0; - while (sent < strlen(query)) { - /* - extern void SpiIntGPIOHandler(void); - SpiIntGPIOHandler(); - */ - //printf("sending %d bytes\n", strlen(query + sent)); - ret = send(sd, query + sent, strlen(query + sent), 0); - //printf("sent %d bytes\n", ret); - if (ret < 0) { - nlr_raise(mp_obj_new_exception_msg(QSTR_FROM_STR_STATIC("WlanError"), "send failed")); - } - sent += ret; - //sys_tick_delay_ms(200); - } - } - - //printf("send seemed to work!\n"); - //sys_tick_delay_ms(5000); - - // receive reply - mp_obj_t mp_ret = mp_const_none; - { - //printf("doing receive\n"); - char buf[64]; - vstr_reset(vstr); - - for (;;) { - // do a select() call on this socket - timeval timeout; - fd_set fd_read; - - memset(&fd_read, 0, sizeof(fd_read)); - FD_SET(sd, &fd_read); - - timeout.tv_sec = 0; - timeout.tv_usec = 500000; // 500 millisec - - int s = select(sd+1, &fd_read, NULL, NULL, &timeout); - if (s == 0) { - // no data available - break; - } - - // read data - ret = recv(sd, buf, 64, 0); - if (ret < 0) { - nlr_raise(mp_obj_new_exception_msg_varg(QSTR_FROM_STR_STATIC("WlanError"), "recv failed %d", ret)); - } - vstr_add_strn(vstr, buf, ret); - } - - mp_ret = mp_obj_new_str(qstr_from_strn_take(vstr->buf, vstr->alloc, vstr->len)); - } - - closesocket(sd); - - return mp_ret; -} - -mp_obj_t pyb_wlan_serve(void) { - printf("serve socket\n"); - int sd = socket(AF_INET, SOCK_STREAM, IPPROTO_TCP); - printf("serve socket got %d\n", sd); - sys_tick_delay_ms(500); - if (sd < 0) { - printf("socket fail\n"); - nlr_raise(mp_obj_new_exception_msg_varg(QSTR_FROM_STR_STATIC("WlanError"), "socket failed: %d", sd)); - } - - /* - if (setsockopt(sd, SOL_SOCKET, SOCKOPT_ACCEPT_NONBLOCK, SOCK_ON, sizeof(SOCK_ON)) < 0) { - printf("couldn't set socket as non-blocking\n"); - return mp_const_none; - } - */ - - sockaddr_in remote; - memset(&remote, 0, sizeof(sockaddr_in)); - remote.sin_family = AF_INET; - remote.sin_port = htons(8080); - remote.sin_addr.s_addr = htonl(0); - printf("serve bind\n"); - int ret = bind(sd, (sockaddr*)&remote, sizeof(sockaddr)); - printf("serve bind got %d\n", ret); - sys_tick_delay_ms(100); - if (ret != 0) { - printf("bind fail\n"); - nlr_raise(mp_obj_new_exception_msg_varg(QSTR_FROM_STR_STATIC("WlanError"), "bind failed: %d", ret)); - } - printf("bind seemed to work\n"); - - // listen - ret = listen(sd, 0); - printf("listen = %d\n", ret); - sys_tick_delay_ms(100); - - // accept connections - int fd = -1; - for (;;) { - sockaddr accept_addr; - socklen_t accept_len; - fd = accept(sd, &accept_addr, &accept_len); - printf("accept = %d\n", fd); - sys_tick_delay_ms(500); - if (fd >= 0) { - break; - } - } - - // receive some data - { - printf("receiving on sd=%d fd=%d\n", sd, fd); - char buf[64]; - ret = recv(fd, buf, 64, 0); - printf("recv = %d\n", ret); - if (ret > 0) { - printf("****%.*s****\n", ret, buf); - } - sys_tick_delay_ms(100); - } - - // send some data - ret = send(fd, "test data!", 10, 0); - printf("send = %d\n", ret); - sys_tick_delay_ms(100); - - closesocket(fd); - closesocket(sd); - - return mp_const_none; -} - -//***************************************************************************** -// -//! CC3000_UsynchCallback -//! -//! @param lEventType Event type -//! @param data -//! @param length -//! -//! @return none -//! -//! @brief The function handles asynchronous events that come from CC3000 -//! device and operates a led for indicate -// -//***************************************************************************** -void CC3000_UsynchCallback(long lEventType, char * data, unsigned char length) -{ - if (lEventType == HCI_EVNT_WLAN_ASYNC_SIMPLE_CONFIG_DONE) - { - //ulSmartConfigFinished = 1; - //ucStopSmartConfig = 1; - printf("WLAN: simple config done\n"); - } - - if (lEventType == HCI_EVNT_WLAN_UNSOL_CONNECT) - { - //ulCC3000Connected = 1; - printf("WLAN unsol connect\n"); - } - - if (lEventType == HCI_EVNT_WLAN_UNSOL_DISCONNECT) - { - //ulCC3000Connected = 0; - //ulCC3000DHCP = 0; - //ulCC3000DHCP_configured = 0; - printf("WLAN unsol disconnect\n"); - } - - if (lEventType == HCI_EVNT_WLAN_UNSOL_DHCP) - { - //ulCC3000DHCP = 1; - printf("WLAN unsol DHCP\n"); - } - - if (lEventType == HCI_EVENT_CC3000_CAN_SHUT_DOWN) - { - //OkToDoShutDown = 1; - printf("WLAN can shut down\n"); - } - - if (lEventType == HCI_EVNT_WLAN_ASYNC_PING_REPORT) - { - printf("WLAN async ping report\n"); - //PRINT_F("CC3000: Ping report\n\r"); - //pingReportnum++; - //memcpy(&pingReport, data, length); - } - - if (lEventType == HCI_EVNT_BSD_TCP_CLOSE_WAIT) { - printf("WLAN bsd tcp close wait\n"); - /* - uint8_t socketnum; - socketnum = data[0]; - //PRINT_F("TCP Close wait #"); printDec(socketnum); - if (socketnum < MAX_SOCKETS) - closed_sockets[socketnum] = true; - */ - } -} - -void pyb_wlan_init(void) { - SpiInit(); - wlan_init(CC3000_UsynchCallback, sendWLFWPatch, sendDriverPatch, sendBootLoaderPatch, ReadWlanInterruptPin, WlanInterruptEnable, WlanInterruptDisable, WriteWlanPin); - - mp_obj_t m = mp_obj_new_module(QSTR_FROM_STR_STATIC("wlan")); - rt_store_attr(m, QSTR_FROM_STR_STATIC("connect"), rt_make_function_var(0, pyb_wlan_connect)); - rt_store_attr(m, QSTR_FROM_STR_STATIC("disconnect"), rt_make_function_n(0, pyb_wlan_disconnect)); - rt_store_attr(m, QSTR_FROM_STR_STATIC("ip"), rt_make_function_n(0, pyb_wlan_get_ip)); - rt_store_attr(m, QSTR_FROM_STR_STATIC("get_host"), rt_make_function_n(1, pyb_wlan_get_host)); - rt_store_attr(m, QSTR_FROM_STR_STATIC("http_get"), rt_make_function_n(2, pyb_wlan_http_get)); - rt_store_attr(m, QSTR_FROM_STR_STATIC("serve"), rt_make_function_n(0, pyb_wlan_serve)); - rt_store_name(QSTR_FROM_STR_STATIC("wlan"), m); -} - -void pyb_wlan_start(void) { - wlan_start(0); - - // TODO: check return value !=0 - - wlan_ioctl_set_connection_policy(0, 0, 0); // don't auto-connect - wlan_ioctl_del_profile(255); // delete stored eeprom data - - // Mask out all non-required events from CC3000 - wlan_set_event_mask(HCI_EVNT_WLAN_UNSOL_INIT | - //HCI_EVNT_WLAN_ASYNC_PING_REPORT |// we want ping reports - //HCI_EVNT_BSD_TCP_CLOSE_WAIT | - //HCI_EVNT_WLAN_TX_COMPLETE | - HCI_EVNT_WLAN_KEEPALIVE); - - /* - byte ver[2]; - int ret = nvmem_read_sp_version(ver); - printf("nvmem_read_sp_version=%d; %02x %02x\n", ret, ver[0], ver[1]); - */ -} diff --git a/stm/pybwlan.h b/stm/pybwlan.h deleted file mode 100644 index 861e6a133..000000000 --- a/stm/pybwlan.h +++ /dev/null @@ -1,2 +0,0 @@ -void pyb_wlan_init(void); -void pyb_wlan_start(void); diff --git a/stm/pyexec.c b/stm/pyexec.c deleted file mode 100644 index 00d5f0bda..000000000 --- a/stm/pyexec.c +++ /dev/null @@ -1,318 +0,0 @@ -#include -#include -#include - -#include "mpconfig.h" -#include "nlr.h" -#include "misc.h" -#include "qstr.h" -#include "misc.h" -#include "lexer.h" -#include "parse.h" -#include "obj.h" -#include "parsehelper.h" -#include "compile.h" -#include "runtime.h" -#include "repl.h" -#include "gc.h" -#include "gccollect.h" -#include "systick.h" -#include "pyexec.h" -#include "storage.h" -#include "usb.h" -#include "usart.h" - -static bool repl_display_debugging_info = 0; - -void stdout_tx_str(const char *str) { - if (pyb_usart_global_debug != PYB_USART_NONE) { - usart_tx_str(pyb_usart_global_debug, str); - } -#if defined(USE_HOST_MODE) && MICROPY_HW_HAS_LCD - lcd_print_str(str); -#endif - usb_vcp_send_str(str); -} - -int stdin_rx_chr(void) { - for (;;) { -#ifdef USE_HOST_MODE - pyb_usb_host_process(); - int c = pyb_usb_host_get_keyboard(); - if (c != 0) { - return c; - } -#endif - if (usb_vcp_rx_any() != 0) { - return usb_vcp_rx_get(); - } else if (pyb_usart_global_debug != PYB_USART_NONE && usart_rx_any(pyb_usart_global_debug)) { - return usart_rx_char(pyb_usart_global_debug); - } - sys_tick_delay_ms(1); - if (storage_needs_flush()) { - storage_flush(); - } - } -} - -char *str_dup(const char *str) { - uint32_t len = strlen(str); - char *s2 = m_new(char, len + 1); - memcpy(s2, str, len); - s2[len] = 0; - return s2; -} - -#define READLINE_HIST_SIZE (8) - -static const char *readline_hist[READLINE_HIST_SIZE] = {NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL}; - -int readline(vstr_t *line, const char *prompt) { - stdout_tx_str(prompt); - int len = vstr_len(line); - int escape = 0; - int hist_num = 0; - for (;;) { - int c = stdin_rx_chr(); - if (escape == 0) { - if (VCP_CHAR_CTRL_A <= c && c <= VCP_CHAR_CTRL_D && vstr_len(line) == len) { - return c; - } else if (c == '\r') { - stdout_tx_str("\r\n"); - for (int i = READLINE_HIST_SIZE - 1; i > 0; i--) { - readline_hist[i] = readline_hist[i - 1]; - } - readline_hist[0] = str_dup(vstr_str(line)); - return 0; - } else if (c == 27) { - escape = true; - } else if (c == 127) { - if (vstr_len(line) > len) { - vstr_cut_tail_bytes(line, 1); - stdout_tx_str("\b \b"); - } - } else if (32 <= c && c <= 126) { - vstr_add_char(line, c); - stdout_tx_str(line->buf + line->len - 1); - } - } else if (escape == 1) { - if (c == '[') { - escape = 2; - } else { - escape = 0; - } - } else if (escape == 2) { - escape = 0; - if (c == 'A') { - // up arrow - if (hist_num < READLINE_HIST_SIZE && readline_hist[hist_num] != NULL) { - // erase line - for (int i = line->len - len; i > 0; i--) { - stdout_tx_str("\b \b"); - } - // set line to history - line->len = len; - vstr_add_str(line, readline_hist[hist_num]); - // draw line - stdout_tx_str(readline_hist[hist_num]); - // increase hist num - hist_num += 1; - } - } - } else { - escape = 0; - } - sys_tick_delay_ms(1); - } -} - -// parses, compiles and executes the code in the lexer -// frees the lexer before returning -bool parse_compile_execute(mp_lexer_t *lex, mp_parse_input_kind_t input_kind, bool is_repl) { - mp_parse_error_kind_t parse_error_kind; - mp_parse_node_t pn = mp_parse(lex, input_kind, &parse_error_kind); - qstr source_name = mp_lexer_source_name(lex); - - if (pn == MP_PARSE_NODE_NULL) { - // parse error - mp_parse_show_exception(lex, parse_error_kind); - mp_lexer_free(lex); - return false; - } - - mp_lexer_free(lex); - - mp_obj_t module_fun = mp_compile(pn, source_name, MP_EMIT_OPT_NONE, is_repl); - mp_parse_node_free(pn); - - if (module_fun == mp_const_none) { - return false; - } - - nlr_buf_t nlr; - bool ret; - uint32_t start = sys_tick_counter; - if (nlr_push(&nlr) == 0) { - usb_vcp_set_interrupt_char(VCP_CHAR_CTRL_C); // allow ctrl-C to interrupt us - mp_call_function_0(module_fun); - usb_vcp_set_interrupt_char(VCP_CHAR_NONE); // disable interrupt - nlr_pop(); - ret = true; - } else { - // uncaught exception - // FIXME it could be that an interrupt happens just before we disable it here - usb_vcp_set_interrupt_char(VCP_CHAR_NONE); // disable interrupt - mp_obj_print_exception((mp_obj_t)nlr.ret_val); - ret = false; - } - - // display debugging info if wanted - if (is_repl && repl_display_debugging_info) { - uint32_t ticks = sys_tick_counter - start; // TODO implement a function that does this properly - printf("took %lu ms\n", ticks); - gc_collect(); - // qstr info - { - uint n_pool, n_qstr, n_str_data_bytes, n_total_bytes; - qstr_pool_info(&n_pool, &n_qstr, &n_str_data_bytes, &n_total_bytes); - printf("qstr:\n n_pool=%u\n n_qstr=%u\n n_str_data_bytes=%u\n n_total_bytes=%u\n", n_pool, n_qstr, n_str_data_bytes, n_total_bytes); - } - - // GC info - { - gc_info_t info; - gc_info(&info); - printf("GC:\n"); - printf(" %lu total\n", info.total); - printf(" %lu : %lu\n", info.used, info.free); - printf(" 1=%lu 2=%lu m=%lu\n", info.num_1block, info.num_2block, info.max_block); - } - } - - return ret; -} - -void pyexec_raw_repl(void) { - vstr_t line; - vstr_init(&line, 32); - -raw_repl_reset: - stdout_tx_str("raw REPL; CTRL-C to exit\r\n"); - - for (;;) { - vstr_reset(&line); - stdout_tx_str(">"); - for (;;) { - char c = stdin_rx_chr(); - if (c == VCP_CHAR_CTRL_A) { - goto raw_repl_reset; - } else if (c == VCP_CHAR_CTRL_C) { - vstr_reset(&line); - break; - } else if (c == VCP_CHAR_CTRL_D) { - break; - } else if (c == '\r') { - vstr_add_char(&line, '\n'); - } else if (32 <= c && c <= 126) { - vstr_add_char(&line, c); - } - } - - stdout_tx_str("OK"); - - if (vstr_len(&line) == 0) { - // finished - break; - } - - mp_lexer_t *lex = mp_lexer_new_from_str_len(MP_QSTR__lt_stdin_gt_, vstr_str(&line), vstr_len(&line), 0); - parse_compile_execute(lex, MP_PARSE_FILE_INPUT, false); - - stdout_tx_str("\004"); - } - - vstr_clear(&line); - stdout_tx_str("\r\n"); -} - -void pyexec_repl(void) { -#if defined(USE_HOST_MODE) && MICROPY_HW_HAS_LCD - // in host mode, we enable the LCD for the repl - mp_obj_t lcd_o = mp_call_function_0(mp_load_name(qstr_from_str("LCD"))); - mp_call_function_1(mp_load_attr(lcd_o, qstr_from_str("light")), mp_const_true); -#endif - - stdout_tx_str("Micro Python build on 25/1/2014; " MICROPY_HW_BOARD_NAME " with STM32F405RG\r\n"); - stdout_tx_str("Type \"help()\" for more information.\r\n"); - - // to test ctrl-C - /* - { - uint32_t x[4] = {0x424242, 0xdeaddead, 0x242424, 0xdeadbeef}; - for (;;) { - nlr_buf_t nlr; - printf("pyexec_repl: %p\n", x); - usb_vcp_set_interrupt_char(VCP_CHAR_CTRL_C); - if (nlr_push(&nlr) == 0) { - for (;;) { - } - } else { - printf("break\n"); - } - } - } - */ - - vstr_t line; - vstr_init(&line, 32); - - for (;;) { - vstr_reset(&line); - int ret = readline(&line, ">>> "); - - if (ret == VCP_CHAR_CTRL_A) { - pyexec_raw_repl(); - continue; - } else if (ret == VCP_CHAR_CTRL_C) { - stdout_tx_str("\r\n"); - continue; - } else if (ret == VCP_CHAR_CTRL_D) { - // EOF - break; - } else if (vstr_len(&line) == 0) { - continue; - } - - while (mp_repl_continue_with_input(vstr_str(&line))) { - vstr_add_char(&line, '\n'); - int ret = readline(&line, "... "); - if (ret == VCP_CHAR_CTRL_D) { - // stop entering compound statement - break; - } - } - - mp_lexer_t *lex = mp_lexer_new_from_str_len(MP_QSTR__lt_stdin_gt_, vstr_str(&line), vstr_len(&line), 0); - parse_compile_execute(lex, MP_PARSE_SINGLE_INPUT, true); - } - - stdout_tx_str("\r\n"); -} - -bool pyexec_file(const char *filename) { - mp_lexer_t *lex = mp_lexer_new_from_file(filename); - - if (lex == NULL) { - printf("could not open file '%s' for reading\n", filename); - return false; - } - - return parse_compile_execute(lex, MP_PARSE_FILE_INPUT, false); -} - -mp_obj_t pyb_set_repl_info(mp_obj_t o_value) { - repl_display_debugging_info = mp_obj_get_int(o_value); - return mp_const_none; -} - -MP_DEFINE_CONST_FUN_OBJ_1(pyb_set_repl_info_obj, pyb_set_repl_info); diff --git a/stm/pyexec.h b/stm/pyexec.h deleted file mode 100644 index cad15af6f..000000000 --- a/stm/pyexec.h +++ /dev/null @@ -1,5 +0,0 @@ -void pyexec_raw_repl(void); -void pyexec_repl(void); -bool pyexec_file(const char *filename); - -MP_DECLARE_CONST_FUN_OBJ(pyb_set_repl_info_obj); diff --git a/stm/qstrdefsport.h b/stm/qstrdefsport.h deleted file mode 100644 index 5fba03eb9..000000000 --- a/stm/qstrdefsport.h +++ /dev/null @@ -1,90 +0,0 @@ -// qstrs specific to this port - -Q(help) -Q(pyb) -Q(info) -Q(sd_test) -Q(stop) -Q(standby) -Q(source_dir) -Q(main) -Q(sync) -Q(gc) -Q(repl_info) -Q(delay) -Q(udelay) -Q(switch) -Q(SW) -Q(servo) -Q(pwm) -Q(accel) -Q(accel_read) -Q(accel_mode) -Q(hid) -Q(time) -Q(rand) -Q(Led) -Q(LCD) -Q(Servo) -Q(SD) -Q(SDcard) -Q(I2C) -Q(gpio) -Q(gpio_in) -Q(gpio_out) -Q(Usart) -Q(ADC) -Q(ADC_all) -Q(Audio) -Q(File) -// Entries for sys.path -Q(0:/) -Q(0:/src) -Q(0:/lib) -Q(Pin) -Q(PinMap) -Q(PinAF) -Q(PinNamed) -Q(Exti) -Q(ExtiMeta) -Q(rtc_info) -Q(millis) -Q(PULL_NONE) -Q(PULL_UP) -Q(PULL_DOWN) -Q(PUSH_PULL) -Q(OPEN_DRAIN) -Q(on) -Q(off) -Q(toggle) -Q(line) -Q(enable) -Q(disable) -Q(swint) -Q(read_channel) -Q(read_core_temp) -Q(read_core_vbat) -Q(read_core_vref) -Q(noise) -Q(triangle) -Q(dac) -Q(dma) -Q(present) -Q(power) -Q(read) -Q(read) -Q(write) -Q(close) -Q(name) -Q(port) -Q(pin) -Q(angle) -Q(start) -Q(write) -Q(read) -Q(readAndStop) -Q(stop) -Q(status) -Q(recv_chr) -Q(send_chr) -Q(send) diff --git a/stm/rtc.c b/stm/rtc.c deleted file mode 100644 index a6ce64f94..000000000 --- a/stm/rtc.c +++ /dev/null @@ -1,130 +0,0 @@ -#include -#include - -#include "misc.h" -#include "mpconfig.h" -#include "qstr.h" -#include "obj.h" -#include "systick.h" -#include "rtc.h" - -machine_uint_t rtc_info; - -#define RTC_INFO_USE_EXISTING (0) -#define RTC_INFO_USE_LSE (1) -#define RTC_INFO_USE_LSI (3) - -void rtc_init(void) { - // Enable the PWR clock - RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); - - // Allow access to RTC - PWR_BackupAccessCmd(ENABLE); - - if (RTC_ReadBackupRegister(RTC_BKP_DR0) == 0x32F2) { - // RTC still alive, so don't re-init it - // wait for RTC APB register synchronisation - RTC_WaitForSynchro(); - rtc_info = RTC_INFO_USE_EXISTING; - return; - } - - uint32_t timeout = 10000000; - - // Enable the PWR clock - RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); - - // Allow access to RTC - PWR_BackupAccessCmd(ENABLE); - - // Enable the LSE OSC - RCC_LSEConfig(RCC_LSE_ON); - - // Wait till LSE is ready - machine_uint_t sys_tick = sys_tick_counter; - while((RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET) && (--timeout > 0)) { - } - - // record how long it took for the RTC to start up - rtc_info = (sys_tick_counter - sys_tick) << 2; - - // If LSE timed out, use LSI instead - if (timeout == 0) { - // Disable the LSE OSC - RCC_LSEConfig(RCC_LSE_OFF); - - // Enable the LSI OSC - RCC_LSICmd(ENABLE); - - // Wait till LSI is ready - while(RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET) { - } - - // Use LSI as the RTC Clock Source - RCC_RTCCLKConfig(RCC_RTCCLKSource_LSI); - - // record that we are using the LSI - rtc_info |= RTC_INFO_USE_LSI; - } else { - // Use LSE as the RTC Clock Source - RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE); - - // record that we are using the LSE - rtc_info |= RTC_INFO_USE_LSE; - } - - // Note: LSI is around (32KHz), these dividers should work either way - // ck_spre(1Hz) = RTCCLK(LSE) /(uwAsynchPrediv + 1)*(uwSynchPrediv + 1) - uint32_t uwSynchPrediv = 0xFF; - uint32_t uwAsynchPrediv = 0x7F; - - // Enable the RTC Clock - RCC_RTCCLKCmd(ENABLE); - - // Wait for RTC APB registers synchronisation - RTC_WaitForSynchro(); - - // Configure the RTC data register and RTC prescaler - RTC_InitTypeDef RTC_InitStructure; - RTC_InitStructure.RTC_AsynchPrediv = uwAsynchPrediv; - RTC_InitStructure.RTC_SynchPrediv = uwSynchPrediv; - RTC_InitStructure.RTC_HourFormat = RTC_HourFormat_24; - RTC_Init(&RTC_InitStructure); - - // Set the date (BCD) - RTC_DateTypeDef RTC_DateStructure; - RTC_DateStructure.RTC_Year = 0x13; - RTC_DateStructure.RTC_Month = RTC_Month_October; - RTC_DateStructure.RTC_Date = 0x26; - RTC_DateStructure.RTC_WeekDay = RTC_Weekday_Saturday; - RTC_SetDate(RTC_Format_BCD, &RTC_DateStructure); - - // Set the time (BCD) - RTC_TimeTypeDef RTC_TimeStructure; - RTC_TimeStructure.RTC_H12 = RTC_H12_AM; - RTC_TimeStructure.RTC_Hours = 0x01; - RTC_TimeStructure.RTC_Minutes = 0x53; - RTC_TimeStructure.RTC_Seconds = 0x00; - RTC_SetTime(RTC_Format_BCD, &RTC_TimeStructure); - - // Indicator for the RTC configuration - RTC_WriteBackupRegister(RTC_BKP_DR0, 0x32F2); -} - -/******************************************************************************/ -// Micro Python bindings - -mp_obj_t pyb_rtc_info(void) { - return mp_obj_new_int(rtc_info); -} - -MP_DEFINE_CONST_FUN_OBJ_0(pyb_rtc_info_obj, pyb_rtc_info); - -mp_obj_t pyb_rtc_read(void) { - RTC_TimeTypeDef RTC_TimeStructure; - RTC_GetTime(RTC_Format_BIN, &RTC_TimeStructure); - printf("%02d:%02d:%02d\n", RTC_TimeStructure.RTC_Hours, RTC_TimeStructure.RTC_Minutes, RTC_TimeStructure.RTC_Seconds); - return mp_const_none; -} - -MP_DEFINE_CONST_FUN_OBJ_0(pyb_rtc_read_obj, pyb_rtc_read); diff --git a/stm/rtc.h b/stm/rtc.h deleted file mode 100644 index fee4da888..000000000 --- a/stm/rtc.h +++ /dev/null @@ -1,4 +0,0 @@ -void rtc_init(void); - -MP_DECLARE_CONST_FUN_OBJ(pyb_rtc_info_obj); -MP_DECLARE_CONST_FUN_OBJ(pyb_rtc_read_obj); diff --git a/stm/sdcard.c b/stm/sdcard.c deleted file mode 100644 index ed79b855c..000000000 --- a/stm/sdcard.c +++ /dev/null @@ -1,211 +0,0 @@ -// TODO -// make it work with DMA - -#include -//#include "stm32f4xx_sdio.h" -#include "stm324x7i_eval_sdio_sd.h" -#include "misc.h" -#include "systick.h" -#include "mpconfig.h" -#include "qstr.h" -#include "obj.h" -#include "runtime.h" -#include "sdcard.h" - -#if 0 -#define BLOCK_SIZE 512 /* Block Size in Bytes */ - -uint8_t aBuffer_Block_Rx[BLOCK_SIZE]; - -void sdio_init(void) { - SD_Error error = SD_Init(); - printf("Init: %x\n", error); - uint8_t det = SD_Detect(); - printf("Detc: %x\n", det); - - if (!det) { - printf("no card detected\n"); - SD_PowerOFF(); - SD_DeInit(); - return; - } - - // read a block! - error = SD_ReadBlock(aBuffer_Block_Rx, 512, BLOCK_SIZE); - printf("ReadBlock: %d\n", error); - - /* - // Check if the Transfer is finished - error = SD_WaitReadOperation(); - printf("WaitReadOp: %d\n", error); - */ - - uint32_t stc = sys_tick_counter; - while (SD_GetStatus() != SD_TRANSFER_OK) { - if (sys_tick_has_passed(stc, 2000)) { - printf("timeout waiting for read to finish\n"); - break; - } - } - printf("done!!\n"); - - printf("%.16s", aBuffer_Block_Rx); - - /* - snprintf((char*)aBuffer_Block_Rx, BLOCK_SIZE, "Here is some data back for you!\nBLOCK_SIZE=%d\n", BLOCK_SIZE); - error = SD_WriteBlock(aBuffer_Block_Rx, 512, BLOCK_SIZE); - printf("WriteBlock: %d\n", error); - - while (SD_GetStatus() != SD_TRANSFER_OK) { - } - printf("done writing!\n"); - */ - - SD_PowerOFF(); - SD_DeInit(); -} -#endif - -void sdcard_init(void) { - // init the SD card detect pin - SD_LowLevel_Init_Detect(); -} - -bool sdcard_is_present(void) { - return SD_Detect() != 0; -} - -bool sdcard_power_on(void) { - if (!SD_Detect()) { - return false; - } - - SD_Error status = SD_Init(); - if (status != SD_OK) { - SD_PowerOFF(); - SD_DeInit(); - return false; - } - - return true; -} - -void sdcard_power_off(void) { - SD_PowerOFF(); - SD_DeInit(); -} - -uint64_t sdcard_get_capacity_in_bytes(void) { - SD_CardInfo SDCardInfo; - SD_GetCardInfo(&SDCardInfo); - return SDCardInfo.CardCapacity; -} - -bool sdcard_read_block(uint8_t *dest, uint32_t block_num) { - // TODO return error if not powered on - - SD_Error status; - - status = SD_ReadBlock(dest, block_num * SDCARD_BLOCK_SIZE, SDCARD_BLOCK_SIZE); - if (status != SD_OK) { - return false; - } - -#ifdef SD_DMA_MODE - // wait for DMA transfer to finish - status = SD_WaitReadOperation(); - if (status != SD_OK) { - return false; - } -#endif - - // wait for SD controller to finish - uint32_t stc = sys_tick_counter; - while (SD_GetStatus() != SD_TRANSFER_OK) { - if (sys_tick_has_passed(stc, 5000)) { - //printf("[ERROR] timeout waiting for SD card read to finish\n"); - return false; - } - } - - return true; -} - -bool sdcard_write_block(const uint8_t *src, uint32_t block_num) { - // TODO return error if not powered on - - SD_Error status; - - status = SD_WriteBlock((uint8_t*)src, block_num * SDCARD_BLOCK_SIZE, SDCARD_BLOCK_SIZE); - if (status != SD_OK) { - return false; - } - -#ifdef SD_DMA_MODE - // wait for DMA transfer to finish - status = SD_WaitReadOperation(); - if (status != SD_OK) { - return false; - } -#endif - - // wait for SD controller to finish - uint32_t stc = sys_tick_counter; - while (SD_GetStatus() != SD_TRANSFER_OK) { - if (sys_tick_has_passed(stc, 5000)) { - //printf("[ERROR] timeout waiting for SD card write to finish\n"); - return false; - } - } - - return true; -} - -/******************************************************************************/ -// Micro Python bindings - -static mp_obj_t sd_present(mp_obj_t self) { - return MP_BOOL(sdcard_is_present()); -} - -static MP_DEFINE_CONST_FUN_OBJ_1(sd_present_obj, sd_present); - -static mp_obj_t sd_power(mp_obj_t self, mp_obj_t state) { - bool result; - if (mp_obj_is_true(state)) { - result = sdcard_power_on(); - } else { - sdcard_power_off(); - result = true; - } - return MP_BOOL(result); -} - -static MP_DEFINE_CONST_FUN_OBJ_2(sd_power_obj, sd_power); - -static mp_obj_t sd_read(mp_obj_t self, mp_obj_t block_num) { - uint8_t *dest = m_new(uint8_t, SDCARD_BLOCK_SIZE); - if (!sdcard_read_block(dest, mp_obj_get_int(block_num))) { - m_free(dest, SDCARD_BLOCK_SIZE); - return mp_const_none; - } - return mp_obj_new_bytearray_by_ref(SDCARD_BLOCK_SIZE, dest); -} - -static MP_DEFINE_CONST_FUN_OBJ_2(sd_read_obj, sd_read); - -STATIC const mp_map_elem_t sdcard_locals_dict_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR_present), (mp_obj_t)&sd_present_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_power), (mp_obj_t)&sd_power_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_read), (mp_obj_t)&sd_read_obj }, -}; - -STATIC MP_DEFINE_CONST_DICT(sdcard_locals_dict, sdcard_locals_dict_table); - -static const mp_obj_type_t sdcard_type = { - { &mp_type_type }, - .name = MP_QSTR_SDcard, - .locals_dict = (mp_obj_t)&sdcard_locals_dict, -}; - -const mp_obj_base_t pyb_sdcard_obj = {&sdcard_type}; diff --git a/stm/sdcard.h b/stm/sdcard.h deleted file mode 100644 index da7dbddab..000000000 --- a/stm/sdcard.h +++ /dev/null @@ -1,12 +0,0 @@ -// this is a fixed size and should not be changed -#define SDCARD_BLOCK_SIZE (512) - -void sdcard_init(void); -bool sdcard_is_present(void); -bool sdcard_power_on(void); -void sdcard_power_off(void); -uint64_t sdcard_get_capacity_in_bytes(void); -bool sdcard_read_block(uint8_t *dest, uint32_t block_num); -bool sdcard_write_block(const uint8_t *src, uint32_t block_num); - -extern const struct _mp_obj_base_t pyb_sdcard_obj; diff --git a/stm/servo.c b/stm/servo.c deleted file mode 100644 index db38bb21c..000000000 --- a/stm/servo.c +++ /dev/null @@ -1,169 +0,0 @@ -#include -#include -#include -#include -#include - -#include "misc.h" -#include "mpconfig.h" -#include "qstr.h" -#include "obj.h" -#include "servo.h" - -// PWM -// TIM2 and TIM5 have CH1, CH2, CH3, CH4 on PA0-PA3 respectively -// they are both 32-bit counters -// 16-bit prescaler -// TIM2_CH3 also on PB10 (used below) -void servo_init(void) { - // TIM2 clock enable - RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE); - - // for PB10 - /* - // GPIOB Configuration: TIM2_CH3 (PB10) - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(GPIOB, &GPIO_InitStructure); - - // Connect TIM2 pins to AF1 - GPIO_PinAFConfig(GPIOB, GPIO_PinSource10, GPIO_AF_TIM2); - */ - - // for PA0, PA1, PA2, PA3 - { - // GPIOA Configuration: TIM2_CH0, TIM2_CH1 (PA0, PA1) - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(GPIOA, &GPIO_InitStructure); - - // Connect TIM2 pins to AF1 - GPIO_PinAFConfig(GPIOA, GPIO_PinSource0, GPIO_AF_TIM2); - GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_TIM2); - GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_TIM2); - GPIO_PinAFConfig(GPIOA, GPIO_PinSource3, GPIO_AF_TIM2); - } - - // Compute the prescaler value so TIM2 runs at 100kHz - uint16_t PrescalerValue = (uint16_t) ((SystemCoreClock / 2) / 100000) - 1; - - // Time base configuration - TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; - TIM_TimeBaseStructure.TIM_Period = 2000; // timer cycles at 50Hz - TIM_TimeBaseStructure.TIM_Prescaler = PrescalerValue; - TIM_TimeBaseStructure.TIM_ClockDivision = 0; - TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; - TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure); - - // PWM Mode configuration - TIM_OCInitTypeDef TIM_OCInitStructure; - TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1; - TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; - TIM_OCInitStructure.TIM_Pulse = 150; // units of 10us - TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High; - TIM_OC1Init(TIM2, &TIM_OCInitStructure); // channel 1 - TIM_OC2Init(TIM2, &TIM_OCInitStructure); // channel 2 - TIM_OC3Init(TIM2, &TIM_OCInitStructure); // channel 3 - TIM_OC4Init(TIM2, &TIM_OCInitStructure); // channel 4 - - // ? - TIM_OC1PreloadConfig(TIM2, TIM_OCPreload_Enable); // channel 1 - TIM_OC2PreloadConfig(TIM2, TIM_OCPreload_Enable); // channel 2 - TIM_OC3PreloadConfig(TIM2, TIM_OCPreload_Enable); // channel 3 - TIM_OC4PreloadConfig(TIM2, TIM_OCPreload_Enable); // channel 4 - - // ? - TIM_ARRPreloadConfig(TIM2, ENABLE); - - // TIM2 enable counter - TIM_Cmd(TIM2, ENABLE); -} - -/******************************************************************************/ -/* Micro Python bindings */ - -STATIC mp_obj_t pyb_servo_set(mp_obj_t port, mp_obj_t value) { - int p = mp_obj_get_int(port); - int v = mp_obj_get_int(value); - if (v < 50) { v = 50; } - if (v > 250) { v = 250; } - switch (p) { - case 1: TIM2->CCR1 = v; break; - case 2: TIM2->CCR2 = v; break; - case 3: TIM2->CCR3 = v; break; - case 4: TIM2->CCR4 = v; break; - } - return mp_const_none; -} - -MP_DEFINE_CONST_FUN_OBJ_2(pyb_servo_set_obj, pyb_servo_set); - -STATIC mp_obj_t pyb_pwm_set(mp_obj_t period, mp_obj_t pulse) { - int pe = mp_obj_get_int(period); - int pu = mp_obj_get_int(pulse); - TIM2->ARR = pe; - TIM2->CCR3 = pu; - return mp_const_none; -} - -MP_DEFINE_CONST_FUN_OBJ_2(pyb_pwm_set_obj, pyb_pwm_set); - -typedef struct _pyb_servo_obj_t { - mp_obj_base_t base; - uint servo_id; -} pyb_servo_obj_t; - -STATIC void servo_obj_print(void (*print)(void *env, const char *fmt, ...), void *env, mp_obj_t self_in, mp_print_kind_t kind) { - pyb_servo_obj_t *self = self_in; - print(env, "", self->servo_id); -} - -STATIC mp_obj_t servo_obj_angle(mp_obj_t self_in, mp_obj_t angle) { - pyb_servo_obj_t *self = self_in; -#if MICROPY_ENABLE_FLOAT - machine_int_t v = 152 + 85.0 * mp_obj_get_float(angle) / 90.0; -#else - machine_int_t v = 152 + 85 * mp_obj_get_int(angle) / 90; -#endif - if (v < 65) { v = 65; } - if (v > 210) { v = 210; } - switch (self->servo_id) { - case 1: TIM2->CCR1 = v; break; - case 2: TIM2->CCR2 = v; break; - case 3: TIM2->CCR3 = v; break; - case 4: TIM2->CCR4 = v; break; - } - return mp_const_none; -} - -STATIC MP_DEFINE_CONST_FUN_OBJ_2(servo_obj_angle_obj, servo_obj_angle); - -STATIC const mp_map_elem_t servo_locals_dict_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR_angle), (mp_obj_t)&servo_obj_angle_obj }, -}; - -STATIC MP_DEFINE_CONST_DICT(servo_locals_dict, servo_locals_dict_table); - -STATIC const mp_obj_type_t servo_obj_type = { - { &mp_type_type }, - .name = MP_QSTR_Servo, - .print = servo_obj_print, - .locals_dict = (mp_obj_t)&servo_locals_dict, -}; - -STATIC mp_obj_t pyb_Servo(mp_obj_t servo_id) { - pyb_servo_obj_t *o = m_new_obj(pyb_servo_obj_t); - o->base.type = &servo_obj_type; - o->servo_id = mp_obj_get_int(servo_id); - return o; -} - -MP_DEFINE_CONST_FUN_OBJ_1(pyb_Servo_obj, pyb_Servo); diff --git a/stm/servo.h b/stm/servo.h deleted file mode 100644 index bb3edd97a..000000000 --- a/stm/servo.h +++ /dev/null @@ -1,5 +0,0 @@ -void servo_init(void); - -MP_DECLARE_CONST_FUN_OBJ(pyb_servo_set_obj); -MP_DECLARE_CONST_FUN_OBJ(pyb_pwm_set_obj); -MP_DECLARE_CONST_FUN_OBJ(pyb_Servo_obj); diff --git a/stm/startup_stm32f40xx.s b/stm/startup_stm32f40xx.s deleted file mode 100644 index 9db2058bd..000000000 --- a/stm/startup_stm32f40xx.s +++ /dev/null @@ -1,542 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f40xx.s - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief STM32F40xxx/41xxx Devices vector table for RIDE7 toolchain. - * Same as startup_stm32f40xx.s and maintained for legacy purpose - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system and the external SRAM mounted on - * STM324xG-EVAL board to be used as data memory (optional, - * to be enabled by user) - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M4 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _data_start_init -/* start address for the .data section. defined in linker script */ -.word _data_start -/* end address for the .data section. defined in linker script */ -.word _data_end -/* start address for the .bss section. defined in linker script */ -.word _bss_start -/* end address for the .bss section. defined in linker script */ -.word _bss_end -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ -/* - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - */ - ldr r0, =_data_start_init @ source pointer - ldr r1, =_data_start @ destination pointer - ldr r2, =_data_end @ maximum destination pointer - b data_init_entry -data_init_loop: - ldr r3, [r0], #4 - str r3, [r1], #4 -data_init_entry: - cmp r1, r2 - bcc data_init_loop - - -/* Zero fill the bss segment. */ - /* - ldr r2, =_sbss - b LoopFillZerobss -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - */ - - movs r0, #0 @ source value - ldr r1, =_bss_start @ destination pointer - ldr r2, =_bss_end @ maximum destination pointer - b bss_init_entry -bss_init_loop: - str r0, [r1], #4 -bss_init_entry: - cmp r1, r2 - bcc bss_init_loop - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _stack_end - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_IRQHandler /* PVD through EXTI Line detection */ - .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ - .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_IRQHandler /* EXTI Line0 */ - .word EXTI1_IRQHandler /* EXTI Line1 */ - .word EXTI2_IRQHandler /* EXTI Line2 */ - .word EXTI3_IRQHandler /* EXTI Line3 */ - .word EXTI4_IRQHandler /* EXTI Line4 */ - .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ - .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ - .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ - .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ - .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ - .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ - .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ - .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ - .word CAN1_TX_IRQHandler /* CAN1 TX */ - .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ - .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ - .word CAN1_SCE_IRQHandler /* CAN1 SCE */ - .word EXTI9_5_IRQHandler /* External Line[9:5]s */ - .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ - .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ - .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word TIM4_IRQHandler /* TIM4 */ - .word I2C1_EV_IRQHandler /* I2C1 Event */ - .word I2C1_ER_IRQHandler /* I2C1 Error */ - .word I2C2_EV_IRQHandler /* I2C2 Event */ - .word I2C2_ER_IRQHandler /* I2C2 Error */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_IRQHandler /* USART3 */ - .word EXTI15_10_IRQHandler /* External Line[15:10]s */ - .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ - .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ - .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ - .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ - .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ - .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ - .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ - .word FSMC_IRQHandler /* FSMC */ - .word SDIO_IRQHandler /* SDIO */ - .word TIM5_IRQHandler /* TIM5 */ - .word SPI3_IRQHandler /* SPI3 */ - .word UART4_IRQHandler /* UART4 */ - .word UART5_IRQHandler /* UART5 */ - .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ - .word TIM7_IRQHandler /* TIM7 */ - .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ - .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ - .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ - .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ - .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ - .word ETH_IRQHandler /* Ethernet */ - .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ - .word CAN2_TX_IRQHandler /* CAN2 TX */ - .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ - .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ - .word CAN2_SCE_IRQHandler /* CAN2 SCE */ - .word OTG_FS_IRQHandler /* USB OTG FS */ - .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ - .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ - .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ - .word USART6_IRQHandler /* USART6 */ - .word I2C3_EV_IRQHandler /* I2C3 event */ - .word I2C3_ER_IRQHandler /* I2C3 error */ - .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ - .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ - .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ - .word OTG_HS_IRQHandler /* USB OTG HS */ - .word DCMI_IRQHandler /* DCMI */ - .word CRYP_IRQHandler /* CRYP crypto */ - .word HASH_RNG_IRQHandler /* Hash and Rng */ - .word FPU_IRQHandler /* FPU */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Stream0_IRQHandler - .thumb_set DMA1_Stream0_IRQHandler,Default_Handler - - .weak DMA1_Stream1_IRQHandler - .thumb_set DMA1_Stream1_IRQHandler,Default_Handler - - .weak DMA1_Stream2_IRQHandler - .thumb_set DMA1_Stream2_IRQHandler,Default_Handler - - .weak DMA1_Stream3_IRQHandler - .thumb_set DMA1_Stream3_IRQHandler,Default_Handler - - .weak DMA1_Stream4_IRQHandler - .thumb_set DMA1_Stream4_IRQHandler,Default_Handler - - .weak DMA1_Stream5_IRQHandler - .thumb_set DMA1_Stream5_IRQHandler,Default_Handler - - .weak DMA1_Stream6_IRQHandler - .thumb_set DMA1_Stream6_IRQHandler,Default_Handler - - .weak ADC_IRQHandler - .thumb_set ADC_IRQHandler,Default_Handler - - .weak CAN1_TX_IRQHandler - .thumb_set CAN1_TX_IRQHandler,Default_Handler - - .weak CAN1_RX0_IRQHandler - .thumb_set CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM9_IRQHandler - .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM10_IRQHandler - .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM11_IRQHandler - .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak OTG_FS_WKUP_IRQHandler - .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler - - .weak TIM8_BRK_TIM12_IRQHandler - .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler - - .weak TIM8_UP_TIM13_IRQHandler - .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler - - .weak TIM8_TRG_COM_TIM14_IRQHandler - .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler - - .weak TIM8_CC_IRQHandler - .thumb_set TIM8_CC_IRQHandler,Default_Handler - - .weak DMA1_Stream7_IRQHandler - .thumb_set DMA1_Stream7_IRQHandler,Default_Handler - - .weak FSMC_IRQHandler - .thumb_set FSMC_IRQHandler,Default_Handler - - .weak SDIO_IRQHandler - .thumb_set SDIO_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Stream0_IRQHandler - .thumb_set DMA2_Stream0_IRQHandler,Default_Handler - - .weak DMA2_Stream1_IRQHandler - .thumb_set DMA2_Stream1_IRQHandler,Default_Handler - - .weak DMA2_Stream2_IRQHandler - .thumb_set DMA2_Stream2_IRQHandler,Default_Handler - - .weak DMA2_Stream3_IRQHandler - .thumb_set DMA2_Stream3_IRQHandler,Default_Handler - - .weak DMA2_Stream4_IRQHandler - .thumb_set DMA2_Stream4_IRQHandler,Default_Handler - - .weak ETH_IRQHandler - .thumb_set ETH_IRQHandler,Default_Handler - - .weak ETH_WKUP_IRQHandler - .thumb_set ETH_WKUP_IRQHandler,Default_Handler - - .weak CAN2_TX_IRQHandler - .thumb_set CAN2_TX_IRQHandler,Default_Handler - - .weak CAN2_RX0_IRQHandler - .thumb_set CAN2_RX0_IRQHandler,Default_Handler - - .weak CAN2_RX1_IRQHandler - .thumb_set CAN2_RX1_IRQHandler,Default_Handler - - .weak CAN2_SCE_IRQHandler - .thumb_set CAN2_SCE_IRQHandler,Default_Handler - - .weak OTG_FS_IRQHandler - .thumb_set OTG_FS_IRQHandler,Default_Handler - - .weak DMA2_Stream5_IRQHandler - .thumb_set DMA2_Stream5_IRQHandler,Default_Handler - - .weak DMA2_Stream6_IRQHandler - .thumb_set DMA2_Stream6_IRQHandler,Default_Handler - - .weak DMA2_Stream7_IRQHandler - .thumb_set DMA2_Stream7_IRQHandler,Default_Handler - - .weak USART6_IRQHandler - .thumb_set USART6_IRQHandler,Default_Handler - - .weak I2C3_EV_IRQHandler - .thumb_set I2C3_EV_IRQHandler,Default_Handler - - .weak I2C3_ER_IRQHandler - .thumb_set I2C3_ER_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_OUT_IRQHandler - .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_IN_IRQHandler - .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler - - .weak OTG_HS_WKUP_IRQHandler - .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler - - .weak OTG_HS_IRQHandler - .thumb_set OTG_HS_IRQHandler,Default_Handler - - .weak DCMI_IRQHandler - .thumb_set DCMI_IRQHandler,Default_Handler - - .weak CRYP_IRQHandler - .thumb_set CRYP_IRQHandler,Default_Handler - - .weak HASH_RNG_IRQHandler - .thumb_set HASH_RNG_IRQHandler,Default_Handler - - .weak FPU_IRQHandler - .thumb_set FPU_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/std.h b/stm/std.h deleted file mode 100644 index 843ddd827..000000000 --- a/stm/std.h +++ /dev/null @@ -1,18 +0,0 @@ -typedef unsigned int size_t; - -void __assert_func(void); - -void *memcpy(void *dest, const void *src, size_t n); -void *memmove(void *dest, const void *src, size_t n); -void *memset(void *s, int c, size_t n); - -size_t strlen(const char *str); -int strcmp(const char *s1, const char *s2); -int strncmp(const char *s1, const char *s2, size_t n); -char *strcpy(char *dest, const char *src); -char *strcat(char *dest, const char *src); -char *strchr(const char *s, int c); -char *strstr(const char *haystack, const char *needle); - -int printf(const char *fmt, ...); -int snprintf(char *str, size_t size, const char *fmt, ...); diff --git a/stm/stm32f405.ld b/stm/stm32f405.ld deleted file mode 100644 index 57d712c35..000000000 --- a/stm/stm32f405.ld +++ /dev/null @@ -1,124 +0,0 @@ -/* - GNU linker script for STM32F405 -*/ - -/* Specify the memory areas */ -MEMORY -{ - FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 0x100000 /* entire flash, 1 MiB */ - FLASH_ISR (rx) : ORIGIN = 0x08000000, LENGTH = 0x004000 /* sector 0, 16 KiB */ - FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 0x080000 /* sectors 5,6,7,8, 4*128KiB = 512 KiB (could increase it more) */ - CCMRAM (xrw) : ORIGIN = 0x10000000, LENGTH = 0x010000 /* 64 KiB */ - RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 0x020000 /* 128 KiB */ -} - -/* produce a link error if there is not this amount of RAM for these sections */ -_minimum_stack_size = 2K; -_minimum_heap_size = 16K; - -/* top end of the stack */ -_stack_end = ORIGIN(RAM) + LENGTH(RAM); - -/* RAM extents for the garbage collector */ -_ram_end = ORIGIN(RAM) + LENGTH(RAM); -_heap_end = 0x2001c000; /* tunable */ - -/* define output sections */ -SECTIONS -{ - /* The startup code goes first into FLASH */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - - . = ALIGN(4); - } >FLASH_ISR - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - /* *(.glue_7) */ /* glue arm to thumb code */ - /* *(.glue_7t) */ /* glue thumb to arm code */ - - . = ALIGN(4); - _text_end = .; /* define a global symbol at end of code */ - _data_start_init = _text_end; /* This is used by the startup in order to initialize the .data secion */ - } >FLASH_TEXT - - /* - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } >FLASH - - .ARM : - { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } >FLASH - */ - - /* This is the initialized data section - The program executes knowing that the data is in the RAM - but the loader puts the initial values in the FLASH (inidata). - It is one task of the startup to copy the initial values from FLASH to RAM. */ - .data : AT ( _data_start_init ) - { - . = ALIGN(4); - _data_start = .; /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */ - _ram_start = .; /* create a global symbol at ram start for garbage collector */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _data_end = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */ - } >RAM - - /* Uninitialized data section */ - .bss : - { - . = ALIGN(4); - _bss_start = .; /* define a global symbol at bss start; used by startup code */ - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _bss_end = .; /* define a global symbol at bss end; used by startup code and GC */ - } >RAM - - /* this is to define the start of the heap, and make sure we have a minimum size */ - .heap : - { - . = ALIGN(4); - _heap_start = .; /* define a global symbol at heap start */ - . = . + _minimum_heap_size; - } >RAM - - /* this just checks there is enough RAM for the stack */ - .stack : - { - . = ALIGN(4); - . = . + _minimum_stack_size; - . = ALIGN(4); - } >RAM - - /* Remove information from the standard libraries */ - /* - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - */ - - .ARM.attributes 0 : { *(.ARM.attributes) } -} diff --git a/stm/stm32fxxx_it.c b/stm/stm32fxxx_it.c deleted file mode 100644 index 1cef4514c..000000000 --- a/stm/stm32fxxx_it.c +++ /dev/null @@ -1,287 +0,0 @@ -/** - ****************************************************************************** - * @file stm32fxxx_it.c - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief Main Interrupt Service Routines. - * This file provides all exceptions handler and peripherals interrupt - * service routine. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32fxxx_it.h" -#include "stm32f4xx_exti.h" -#include "usb_core.h" -//#include "usb_hcd_int.h" // for usb host mode only -//#include "usbd_core.h" - -//#include "usbd_cdc_core.h" - - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -extern USB_OTG_CORE_HANDLE USB_OTG_Core; - -/* Private function prototypes -----------------------------------------------*/ -extern uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev); -extern uint32_t USBH_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev); -//extern uint32_t STM32_USBO_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev); - -#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED -extern uint32_t USBD_OTG_EP1IN_ISR_Handler (USB_OTG_CORE_HANDLE *pdev); -extern uint32_t USBD_OTG_EP1OUT_ISR_Handler (USB_OTG_CORE_HANDLE *pdev); -#endif - -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************/ -/* Cortex-M Processor Exceptions Handlers */ -/******************************************************************************/ - -extern void fatality(); - -/** - * @brief This function handles NMI exception. - * @param None - * @retval None - */ -void NMI_Handler(void) -{ -} - -/** - * @brief This function handles Hard Fault exception. - * @param None - * @retval None - */ -void HardFault_Handler(void) -{ - /* Go to infinite loop when Hard Fault exception occurs */ - fatality(); - while (1) - { - } -} - -/** - * @brief This function handles Memory Manage exception. - * @param None - * @retval None - */ -void MemManage_Handler(void) -{ - /* Go to infinite loop when Memory Manage exception occurs */ - fatality(); - while (1) - { - } -} - -/** - * @brief This function handles Bus Fault exception. - * @param None - * @retval None - */ -void BusFault_Handler(void) -{ - /* Go to infinite loop when Bus Fault exception occurs */ - fatality(); - while (1) - { - } -} - -/** - * @brief This function handles Usage Fault exception. - * @param None - * @retval None - */ -void UsageFault_Handler(void) -{ - /* Go to infinite loop when Usage Fault exception occurs */ - fatality(); - while (1) - { - } -} - -/** - * @brief This function handles SVCall exception. - * @param None - * @retval None - */ -void SVC_Handler(void) -{ -} - -/** - * @brief This function handles Debug Monitor exception. - * @param None - * @retval None - */ -void DebugMon_Handler(void) -{ -} - -/** - * @brief This function handles PendSVC exception. - * @param None - * @retval None - */ -void PendSV_Handler(void) -{ - extern void pendsv_isr_handler(void); - pendsv_isr_handler(); -} - -/** - * @brief This function handles EXTI15_10_IRQ Handler. - * @param None - * @retval None - */ -#ifdef USE_USB_OTG_FS -void OTG_FS_WKUP_IRQHandler(void) -{ - if(USB_OTG_Core.cfg.low_power) - { - *(uint32_t *)(0xE000ED10) &= 0xFFFFFFF9 ; - SystemInit(); -#ifdef USE_DEVICE_MODE - USB_OTG_UngateClock(&USB_OTG_Core); -#endif - } - EXTI_ClearITPendingBit(EXTI_Line18); -} -#endif - -/** - * @brief This function handles EXTI15_10_IRQ Handler. - * @param None - * @retval None - */ -#ifdef USE_USB_OTG_HS -void OTG_HS_WKUP_IRQHandler(void) -{ - if(USB_OTG_Core.cfg.low_power) - { - *(uint32_t *)(0xE000ED10) &= 0xFFFFFFF9 ; - SystemInit(); - USB_OTG_UngateClock(&USB_OTG_Core); - } - EXTI_ClearITPendingBit(EXTI_Line20); -} -#endif - -/** - * @brief This function handles OTG_HS Handler. - * @param None - * @retval None - */ -#ifdef USE_USB_OTG_HS -void OTG_HS_IRQHandler(void) -#else -void OTG_FS_IRQHandler(void) -#endif -{ - if (USB_OTG_IsHostMode(&USB_OTG_Core)) { - // host mode -#ifdef USE_HOST_MODE - USBH_OTG_ISR_Handler(&USB_OTG_Core); -#endif - //STM32_USBO_OTG_ISR_Handler(&USB_OTG_Core); // USE_OTG_MODE - } else { - // device mode -#ifdef USE_DEVICE_MODE - USBD_OTG_ISR_Handler(&USB_OTG_Core); -#endif - } -} - -#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED -/** - * @brief This function handles EP1_IN Handler. - * @param None - * @retval None - */ -void OTG_HS_EP1_IN_IRQHandler(void) -{ - USBD_OTG_EP1IN_ISR_Handler (&USB_OTG_Core); -} - -/** - * @brief This function handles EP1_OUT Handler. - * @param None - * @retval None - */ -void OTG_HS_EP1_OUT_IRQHandler(void) -{ - USBD_OTG_EP1OUT_ISR_Handler (&USB_OTG_Core); -} -#endif - -/** - * @brief This function handles SDIO global interrupt request. - * @param None - * @retval None - */ -void SDIO_IRQHandler(void) -{ - /* Process All SDIO Interrupt Sources */ - // dpgeorge: i don't think this is used at the moment... - extern void SD_ProcessIRQSrc(void); - SD_ProcessIRQSrc(); -} - -/******************************************************************************/ -/* STM32Fxxx Peripherals Interrupt Handlers */ -/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ -/* available peripheral interrupt handler's name please refer to the startup */ -/* file (startup_stm32fxxx.s). */ -/******************************************************************************/ - -/** - * @brief This function handles PPP interrupt request. - * @param None - * @retval None - */ -/*void PPP_IRQHandler(void) -{ -}*/ - -// TIM6 Update event -#include "stm32f4xx_tim.h" -void TIM6_DAC_IRQHandler(void) { - // work out if it's TIM6 that had the interrupt - if (TIM_GetITStatus(TIM6, TIM_IT_Update) != RESET) { - extern void timer_interrupt(void); - timer_interrupt(); - TIM_ClearITPendingBit(TIM6, TIM_IT_Update); - } else { - // it seems we get 2 calls to this interrupt handler, and only 1 is the TIM_IT_Update... - // TODO work out what the other one is, and if we can disable it - //printf("unhandled TIM6_DAC\n"); - } -} - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stm32fxxx_it.h b/stm/stm32fxxx_it.h deleted file mode 100644 index c53b24340..000000000 --- a/stm/stm32fxxx_it.h +++ /dev/null @@ -1,59 +0,0 @@ -/** - ****************************************************************************** - * @file stm32fxxx_it.h - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief This file contains the headers of the interrupt handlers. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32Fxxx_IT_H -#define __STM32Fxxx_IT_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "usb_conf.h" - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -void NMI_Handler(void); -void HardFault_Handler(void); -void MemManage_Handler(void); -void BusFault_Handler(void); -void UsageFault_Handler(void); -void SVC_Handler(void); -void DebugMon_Handler(void); -void PendSV_Handler(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32Fxxx_IT_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm324x7i_eval.c b/stm/stmperiph/stm324x7i_eval.c deleted file mode 100644 index c5a9d425c..000000000 --- a/stm/stmperiph/stm324x7i_eval.c +++ /dev/null @@ -1,246 +0,0 @@ -/** - ****************************************************************************** - * @file STM324x7i_eval.c - * @author MCD Application Team - * @version V1.0.0 - * @date 11-January-2013 - * @brief This file provides - * - set of firmware functions to manage Leds, push-button and COM ports - * - low level initialization functions for SD card (on SDIO) and - * serial EEPROM (sEE) - * available on STM324x7I-EVAL evaluation board(MB786) from - * STMicroelectronics. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_dma.h" -#include "stm32f4xx_exti.h" -#include "stm32f4xx_gpio.h" -#include "stm32f4xx_rcc.h" -#include "stm32f4xx_sdio.h" -//#include "stm32f4xx_syscfg.h" -#include "stm_misc.h" -#include "stm324x7i_eval.h" -//#include "stm32f4xx_i2c.h" - -/** - * @brief DeInitializes the SDIO interface. - * @param None - * @retval None - */ -void SD_LowLevel_DeInit(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /*!< Disable SDIO Clock */ - SDIO_ClockCmd(DISABLE); - - /*!< Set Power State to OFF */ - SDIO_SetPowerState(SDIO_PowerState_OFF); - - /*!< DeInitializes the SDIO peripheral */ - SDIO_DeInit(); - - /* Disable the SDIO APB2 Clock */ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, DISABLE); - - GPIO_PinAFConfig(GPIOC, GPIO_PinSource8, GPIO_AF_MCO); - GPIO_PinAFConfig(GPIOC, GPIO_PinSource9, GPIO_AF_MCO); - GPIO_PinAFConfig(GPIOC, GPIO_PinSource10, GPIO_AF_MCO); - GPIO_PinAFConfig(GPIOC, GPIO_PinSource11, GPIO_AF_MCO); - GPIO_PinAFConfig(GPIOC, GPIO_PinSource12, GPIO_AF_MCO); - GPIO_PinAFConfig(GPIOD, GPIO_PinSource2, GPIO_AF_MCO); - - /* Configure PC.08, PC.09, PC.10, PC.11 pins: D0, D1, D2, D3 pins */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(GPIOC, &GPIO_InitStructure); - - /* Configure PD.02 CMD line */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; - GPIO_Init(GPIOD, &GPIO_InitStructure); - - /* Configure PC.12 pin: CLK pin */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; - GPIO_Init(GPIOC, &GPIO_InitStructure); -} - -/* Init just the detect pin. - * This is so we can save power by not enabling the whole SD card interface, - * yet still detect when a card is inserted. - */ -void SD_LowLevel_Init_Detect(void) { - - /* Periph clock enable */ - RCC_AHB1PeriphClockCmd(SD_DETECT_GPIO_CLK, ENABLE); - - /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */ -#if defined(PYBOARD3) - // dpgeorge: PYBv2-v3: switch is normally open, connected to VDD when card inserted - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; // needs to be 2MHz due to restrictions on PC13 - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN; - GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure); -#elif defined(PYBOARD4) - // dpgeorge: PYBv4: switch is normally open, connected to GND when card inserted - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure); -#endif -} - -/** - * @brief Initializes the SD Card and put it into StandBy State (Ready for - * data transfer). - * @param None - * @retval None - */ -void SD_LowLevel_Init(void) -{ - // init the detect pin first - SD_LowLevel_Init_Detect(); - - GPIO_InitTypeDef GPIO_InitStructure; - - /* GPIOC and GPIOD Periph clock enable */ - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD | SD_DETECT_GPIO_CLK, ENABLE); - - GPIO_PinAFConfig(GPIOC, GPIO_PinSource8, GPIO_AF_SDIO); - GPIO_PinAFConfig(GPIOC, GPIO_PinSource9, GPIO_AF_SDIO); - GPIO_PinAFConfig(GPIOC, GPIO_PinSource10, GPIO_AF_SDIO); - GPIO_PinAFConfig(GPIOC, GPIO_PinSource11, GPIO_AF_SDIO); - GPIO_PinAFConfig(GPIOC, GPIO_PinSource12, GPIO_AF_SDIO); - GPIO_PinAFConfig(GPIOD, GPIO_PinSource2, GPIO_AF_SDIO); - - /* Configure PC.08, PC.09, PC.10, PC.11 pins: D0, D1, D2, D3 pins */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_25MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(GPIOC, &GPIO_InitStructure); - - /* Configure PD.02 CMD line */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; - GPIO_Init(GPIOD, &GPIO_InitStructure); - - /* Configure PC.12 pin: CLK pin */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(GPIOC, &GPIO_InitStructure); - - /* Enable the SDIO APB2 Clock */ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE); - - /* Enable the DMA2 Clock */ - RCC_AHB1PeriphClockCmd(SD_SDIO_DMA_CLK, ENABLE); -} - -/** - * @brief Configures the DMA2 Channel4 for SDIO Tx request. - * @param BufferSRC: pointer to the source buffer - * @param BufferSize: buffer size - * @retval None - */ -void SD_LowLevel_DMA_TxConfig(uint32_t *BufferSRC, uint32_t BufferSize) -{ - DMA_InitTypeDef SDDMA_InitStructure; - - DMA_ClearFlag(SD_SDIO_DMA_STREAM, SD_SDIO_DMA_FLAG_FEIF | SD_SDIO_DMA_FLAG_DMEIF | SD_SDIO_DMA_FLAG_TEIF | SD_SDIO_DMA_FLAG_HTIF | SD_SDIO_DMA_FLAG_TCIF); - - /* DMA2 Stream3 or Stream6 disable */ - DMA_Cmd(SD_SDIO_DMA_STREAM, DISABLE); - - /* DMA2 Stream3 or Stream6 Config */ - DMA_DeInit(SD_SDIO_DMA_STREAM); - - SDDMA_InitStructure.DMA_Channel = SD_SDIO_DMA_CHANNEL; - SDDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SDIO_FIFO_ADDRESS; - SDDMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)BufferSRC; - SDDMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; - SDDMA_InitStructure.DMA_BufferSize = BufferSize; - SDDMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; - SDDMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; - SDDMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word; - SDDMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word; - SDDMA_InitStructure.DMA_Mode = DMA_Mode_Normal; - SDDMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; - SDDMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable; - SDDMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; - SDDMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_INC4; - SDDMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_INC4; - DMA_Init(SD_SDIO_DMA_STREAM, &SDDMA_InitStructure); - DMA_ITConfig(SD_SDIO_DMA_STREAM, DMA_IT_TC, ENABLE); - DMA_FlowControllerConfig(SD_SDIO_DMA_STREAM, DMA_FlowCtrl_Peripheral); - - /* DMA2 Stream3 or Stream6 enable */ - DMA_Cmd(SD_SDIO_DMA_STREAM, ENABLE); - -} - -/** - * @brief Configures the DMA2 Channel4 for SDIO Rx request. - * @param BufferDST: pointer to the destination buffer - * @param BufferSize: buffer size - * @retval None - */ -void SD_LowLevel_DMA_RxConfig(uint32_t *BufferDST, uint32_t BufferSize) -{ - DMA_InitTypeDef SDDMA_InitStructure; - - DMA_ClearFlag(SD_SDIO_DMA_STREAM, SD_SDIO_DMA_FLAG_FEIF | SD_SDIO_DMA_FLAG_DMEIF | SD_SDIO_DMA_FLAG_TEIF | SD_SDIO_DMA_FLAG_HTIF | SD_SDIO_DMA_FLAG_TCIF); - - /* DMA2 Stream3 or Stream6 disable */ - DMA_Cmd(SD_SDIO_DMA_STREAM, DISABLE); - - /* DMA2 Stream3 or Stream6 Config */ - DMA_DeInit(SD_SDIO_DMA_STREAM); - - SDDMA_InitStructure.DMA_Channel = SD_SDIO_DMA_CHANNEL; - SDDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SDIO_FIFO_ADDRESS; - SDDMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)BufferDST; - SDDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; - SDDMA_InitStructure.DMA_BufferSize = BufferSize; - SDDMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; - SDDMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; - SDDMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word; - SDDMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word; - SDDMA_InitStructure.DMA_Mode = DMA_Mode_Normal; - SDDMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; - SDDMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable; - SDDMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; - SDDMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_INC4; - SDDMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_INC4; - DMA_Init(SD_SDIO_DMA_STREAM, &SDDMA_InitStructure); - DMA_ITConfig(SD_SDIO_DMA_STREAM, DMA_IT_TC, ENABLE); - DMA_FlowControllerConfig(SD_SDIO_DMA_STREAM, DMA_FlowCtrl_Peripheral); - - /* DMA2 Stream3 or Stream6 enable */ - DMA_Cmd(SD_SDIO_DMA_STREAM, ENABLE); -} - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm324x7i_eval.h b/stm/stmperiph/stm324x7i_eval.h deleted file mode 100644 index de4c9b130..000000000 --- a/stm/stmperiph/stm324x7i_eval.h +++ /dev/null @@ -1,117 +0,0 @@ -/** - ****************************************************************************** - * @file STM324x7i_eval.h - * @author MCD Application Team - * @version V1.0.0 - * @date 11-January-2013 - * @brief This file contains definitions for STM324x7I_EVAL's Leds, push-buttons - * and COM ports hardware resources. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM324x7I_EVAL_H -#define __STM324x7I_EVAL_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" -#include "mpconfig.h" - -/** - * @brief SD FLASH SDIO Interface - */ -#if defined(PYBOARD3) -#define SD_DETECT_PIN GPIO_Pin_13 /* PC.13 */ -#define SD_DETECT_GPIO_PORT GPIOC /* GPIOC */ -#define SD_DETECT_GPIO_CLK RCC_AHB1Periph_GPIOC -#elif defined(PYBOARD4) -#define SD_DETECT_PIN GPIO_Pin_8 /* PA..8 */ -#define SD_DETECT_GPIO_PORT GPIOA /* GPIOA */ -#define SD_DETECT_GPIO_CLK RCC_AHB1Periph_GPIOA -#elif defined(STM32F4DISC) -// PB15 on the DM-STSTF4BB Base Board -#define SD_DETECT_PIN GPIO_Pin_15 /* PB.15 */ -#define SD_DETECT_GPIO_PORT GPIOB /* GPIOB */ -#define SD_DETECT_GPIO_CLK RCC_AHB1Periph_GPIOB -#elif defined(NETDUINO_PLUS_2) -#define SD_DETECT_PIN GPIO_Pin_5 /* PB.5 */ -#define SD_DETECT_GPIO_PORT GPIOB /* GPIOB */ -#define SD_DETECT_GPIO_CLK RCC_AHB1Periph_GPIOB -#endif - -#define SDIO_FIFO_ADDRESS ((uint32_t)0x40012C80) -/** - * @brief SDIO Intialization Frequency (400KHz max) - */ -#define SDIO_INIT_CLK_DIV ((uint8_t)0x76) -/** - * @brief SDIO Data Transfer Frequency (25MHz max) - */ -#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0) - -#define SD_SDIO_DMA DMA2 -#define SD_SDIO_DMA_CLK RCC_AHB1Periph_DMA2 - -#define SD_SDIO_DMA_STREAM3 3 -//#define SD_SDIO_DMA_STREAM6 6 - -#ifdef SD_SDIO_DMA_STREAM3 - #define SD_SDIO_DMA_STREAM DMA2_Stream3 - #define SD_SDIO_DMA_CHANNEL DMA_Channel_4 - #define SD_SDIO_DMA_FLAG_FEIF DMA_FLAG_FEIF3 - #define SD_SDIO_DMA_FLAG_DMEIF DMA_FLAG_DMEIF3 - #define SD_SDIO_DMA_FLAG_TEIF DMA_FLAG_TEIF3 - #define SD_SDIO_DMA_FLAG_HTIF DMA_FLAG_HTIF3 - #define SD_SDIO_DMA_FLAG_TCIF DMA_FLAG_TCIF3 - #define SD_SDIO_DMA_IRQn DMA2_Stream3_IRQn - #define SD_SDIO_DMA_IRQHANDLER DMA2_Stream3_IRQHandler -#elif defined SD_SDIO_DMA_STREAM6 - #define SD_SDIO_DMA_STREAM DMA2_Stream6 - #define SD_SDIO_DMA_CHANNEL DMA_Channel_4 - #define SD_SDIO_DMA_FLAG_FEIF DMA_FLAG_FEIF6 - #define SD_SDIO_DMA_FLAG_DMEIF DMA_FLAG_DMEIF6 - #define SD_SDIO_DMA_FLAG_TEIF DMA_FLAG_TEIF6 - #define SD_SDIO_DMA_FLAG_HTIF DMA_FLAG_HTIF6 - #define SD_SDIO_DMA_FLAG_TCIF DMA_FLAG_TCIF6 - #define SD_SDIO_DMA_IRQn DMA2_Stream6_IRQn - #define SD_SDIO_DMA_IRQHANDLER DMA2_Stream6_IRQHandler -#endif /* SD_SDIO_DMA_STREAM3 */ - - -/** @defgroup STM324x7I_EVAL_LOW_LEVEL_Exported_Functions - * @{ - */ -void SD_LowLevel_DeInit(void); -void SD_LowLevel_Init_Detect(void); -void SD_LowLevel_Init(void); -void SD_LowLevel_DMA_TxConfig(uint32_t *BufferSRC, uint32_t BufferSize); -void SD_LowLevel_DMA_RxConfig(uint32_t *BufferDST, uint32_t BufferSize); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM324x7I_EVAL_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm324x7i_eval_sdio_sd.c b/stm/stmperiph/stm324x7i_eval_sdio_sd.c deleted file mode 100644 index 2d6f4b8c9..000000000 --- a/stm/stmperiph/stm324x7i_eval_sdio_sd.c +++ /dev/null @@ -1,2948 +0,0 @@ -/** - ****************************************************************************** - * @file stm324x7i_eval_sdio_sd.c - * @author MCD Application Team - * @version V1.0.0 - * @date 11-January-2013 - * @brief This file provides a set of functions needed to manage the SDIO SD - * Card memory mounted on STM324x7I-EVAL evaluation board. - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * It implements a high level communication layer for read and write - * from/to this memory. The needed STM32 hardware resources (SDIO and - * GPIO) are defined in stm324x7i_eval.h file, and the initialization is - * performed in SD_LowLevel_Init() function declared in stm324x7i_eval.c - * file. - * You can easily tailor this driver to any other development board, - * by just adapting the defines for hardware resources and - * SD_LowLevel_Init() function. - * - * A - SD Card Initialization and configuration - * ============================================ - * - To initialize the SD Card, use the SD_Init() function. It - * Initializes the SD Card and put it into StandBy State (Ready - * for data transfer). This function provide the following operations: - * - * 1 - Apply the SD Card initialization process at 400KHz and check - * the SD Card type (Standard Capacity or High Capacity). You - * can change or adapt this frequency by adjusting the - * "SDIO_INIT_CLK_DIV" define inside the stm324x7i_eval.h file. - * The SD Card frequency (SDIO_CK) is computed as follows: - * - * +---------------------------------------------+ - * | SDIO_CK = SDIOCLK / (SDIO_INIT_CLK_DIV + 2) | - * +---------------------------------------------+ - * - * In initialization mode and according to the SD Card standard, - * make sure that the SDIO_CK frequency don't exceed 400KHz. - * - * 2 - Get the SD CID and CSD data. All these information are - * managed by the SDCardInfo structure. This structure provide - * also ready computed SD Card capacity and Block size. - * - * 3 - Configure the SD Card Data transfer frequency. By Default, - * the card transfer frequency is set to 24MHz. You can change - * or adapt this frequency by adjusting the "SDIO_TRANSFER_CLK_DIV" - * define inside the stm324x7i_eval.h file. - * The SD Card frequency (SDIO_CK) is computed as follows: - * - * +---------------------------------------------+ - * | SDIO_CK = SDIOCLK / (SDIO_INIT_CLK_DIV + 2) | - * +---------------------------------------------+ - * - * In transfer mode and according to the SD Card standard, - * make sure that the SDIO_CK frequency don't exceed 25MHz - * and 50MHz in High-speed mode switch. - * To be able to use a frequency higher than 24MHz, you should - * use the SDIO peripheral in bypass mode. Refer to the - * corresponding reference manual for more details. - * - * 4 - Select the corresponding SD Card according to the address - * read with the step 2. - * - * 5 - Configure the SD Card in wide bus mode: 4-bits data. - * - * B - SD Card Read operation - * ========================== - * - You can read SD card by using two function: SD_ReadBlock() and - * SD_ReadMultiBlocks() functions. These functions support only - * 512-byte block length. - * - The SD_ReadBlock() function read only one block (512-byte). This - * function can transfer the data using DMA controller or using - * polling mode. To select between DMA or polling mode refer to - * "SD_DMA_MODE" or "SD_POLLING_MODE" inside the stm324x7i_eval_sdio_sd.h - * file and uncomment the corresponding line. By default the SD DMA - * mode is selected - * - The SD_ReadMultiBlocks() function read only mutli blocks (multiple - * of 512-byte). - * - Any read operation should be followed by two functions to check - * if the DMA Controller and SD Card status. - * - SD_ReadWaitOperation(): this function insure that the DMA - * controller has finished all data transfer. - * - SD_GetStatus(): to check that the SD Card has finished the - * data transfer and it is ready for data. - * - * - The DMA transfer is finished by the SDIO Data End interrupt. - * User has to call the SD_ProcessIRQ() function inside the SDIO_IRQHandler() - * and SD_ProcessDMAIRQ() function inside the DMA2_Streamx_IRQHandler(). - * Don't forget to enable the SDIO_IRQn and DMA2_Stream3_IRQn or - * DMA2_Stream6_IRQn interrupts using the NVIC controller. - * - * C - SD Card Write operation - * =========================== - * - You can write SD card by using two function: SD_WriteBlock() and - * SD_WriteMultiBlocks() functions. These functions support only - * 512-byte block length. - * - The SD_WriteBlock() function write only one block (512-byte). This - * function can transfer the data using DMA controller or using - * polling mode. To select between DMA or polling mode refer to - * "SD_DMA_MODE" or "SD_POLLING_MODE" inside the stm324x7i_eval_sdio_sd.h - * file and uncomment the corresponding line. By default the SD DMA - * mode is selected - * - The SD_WriteMultiBlocks() function write only mutli blocks (multiple - * of 512-byte). - * - Any write operation should be followed by two functions to check - * if the DMA Controller and SD Card status. - * - SD_ReadWaitOperation(): this function insure that the DMA - * controller has finished all data transfer. - * - SD_GetStatus(): to check that the SD Card has finished the - * data transfer and it is ready for data. - * - * - The DMA transfer is finished by the SDIO Data End interrupt. - * User has to call the SD_ProcessIRQ() function inside the SDIO_IRQHandler() - * and SD_ProcessDMAIRQ() function inside the DMA2_Streamx_IRQHandler(). - * Don't forget to enable the SDIO_IRQn and DMA2_Stream3_IRQn or - * DMA2_Stream6_IRQn interrupts using the NVIC controller. - * - * - * D - SD card status - * ================== - * - At any time, you can check the SD Card status and get the SD card - * state by using the SD_GetStatus() function. This function checks - * first if the SD card is still connected and then get the internal - * SD Card transfer state. - * - You can also get the SD card SD Status register by using the - * SD_SendSDStatus() function. - * - * E - Programming Model (Selecting DMA for SDIO data Transfer) - * ============================================================ - * Status = SD_Init(); // Initialization Step as described in section A - * - * // SDIO Interrupt ENABLE - * NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn; - * NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; - * NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; - * NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - * NVIC_Init(&NVIC_InitStructure); - * // DMA2 STREAMx Interrupt ENABLE - * NVIC_InitStructure.NVIC_IRQChannel = SD_SDIO_DMA_IRQn; - * NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; - * NVIC_Init(&NVIC_InitStructure); - * - * // Write operation as described in Section C - * Status = SD_WriteBlock(buffer, address, 512); - * Status = SD_WaitWriteOperation(); - * while(SD_GetStatus() != SD_TRANSFER_OK); - * - * Status = SD_WriteMultiBlocks(buffer, address, 512, NUMBEROFBLOCKS); - * Status = SD_WaitWriteOperation(); - * while(SD_GetStatus() != SD_TRANSFER_OK); - * - * // Read operation as described in Section B - * Status = SD_ReadBlock(buffer, address, 512); - * Status = SD_WaitReadOperation(); - * while(SD_GetStatus() != SD_TRANSFER_OK); - * - * Status = SD_ReadMultiBlocks(buffer, address, 512, NUMBEROFBLOCKS); - * Status = SD_WaitReadOperation(); - * while(SD_GetStatus() != SD_TRANSFER_OK); - * - * - Add the SDIO and DMA2 StreamX (3 or 6) IRQ Handlers: - * void SDIO_IRQHandler(void) - * { - * SD_ProcessIRQ(); - * } - * void SD_SDIO_DMA_IRQHANDLER(void) - * { - * SD_ProcessDMAIRQ(); - * } - * - * F - Programming Model (Selecting Polling for SDIO data Transfer) - * ================================================================ - * //Only SD Card Single Block operation are managed. - * Status = SD_Init(); // Initialization Step as described in section - * - * // Write operation as described in Section C - * Status = SD_WriteBlock(buffer, address, 512); - * - * // Read operation as described in Section B - * Status = SD_ReadBlock(buffer, address, 512); - * - * STM32 SDIO Pin assignment - * ========================= - * +-----------------------------------------------------------+ - * | Pin assignment | - * +-----------------------------+---------------+-------------+ - * | STM32 SDIO Pins | SD | Pin | - * +-----------------------------+---------------+-------------+ - * | SDIO D2 | D2 | 1 | - * | SDIO D3 | D3 | 2 | - * | SDIO CMD | CMD | 3 | - * | | VCC | 4 (3.3 V)| - * | SDIO CLK | CLK | 5 | - * | | GND | 6 (0 V) | - * | SDIO D0 | D0 | 7 | - * | SDIO D1 | D1 | 8 | - * +-----------------------------+---------------+-------------+ - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_dma.h" -#include "stm32f4xx_gpio.h" -#include "stm32f4xx_sdio.h" -#include "stm324x7i_eval_sdio_sd.h" -//#include "std.h" - - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM324x7I_EVAL - * @{ - */ - -/** @addtogroup STM324x7I_EVAL_SDIO_SD - * @brief This file provides all the SD Card driver firmware functions. - * @{ - */ - -/** @defgroup STM324x7I_EVAL_SDIO_SD_Private_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup stm324x7i_EVAL_SDIO_SD_Private_Defines - * @{ - */ - -/** - * @brief SDIO Static flags, TimeOut, FIFO Address - */ -#define NULL 0 -#define SDIO_STATIC_FLAGS ((uint32_t)0x000005FF) -#define SDIO_CMD0TIMEOUT ((uint32_t)0x00080000) // dpgeorge: was 0x10000 - -/** - * @brief Mask for errors Card Status R1 (OCR Register) - */ -#define SD_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000) -#define SD_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000) -#define SD_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000) -#define SD_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000) -#define SD_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000) -#define SD_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000) -#define SD_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000) -#define SD_OCR_COM_CRC_FAILED ((uint32_t)0x00800000) -#define SD_OCR_ILLEGAL_CMD ((uint32_t)0x00400000) -#define SD_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000) -#define SD_OCR_CC_ERROR ((uint32_t)0x00100000) -#define SD_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000) -#define SD_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000) -#define SD_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000) -#define SD_OCR_CID_CSD_OVERWRIETE ((uint32_t)0x00010000) -#define SD_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000) -#define SD_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000) -#define SD_OCR_ERASE_RESET ((uint32_t)0x00002000) -#define SD_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008) -#define SD_OCR_ERRORBITS ((uint32_t)0xFDFFE008) - -/** - * @brief Masks for R6 Response - */ -#define SD_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000) -#define SD_R6_ILLEGAL_CMD ((uint32_t)0x00004000) -#define SD_R6_COM_CRC_FAILED ((uint32_t)0x00008000) - -#define SD_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000) -#define SD_HIGH_CAPACITY ((uint32_t)0x40000000) -#define SD_STD_CAPACITY ((uint32_t)0x00000000) -#define SD_CHECK_PATTERN ((uint32_t)0x000001AA) - -#define SD_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFF) -#define SD_ALLZERO ((uint32_t)0x00000000) - -#define SD_WIDE_BUS_SUPPORT ((uint32_t)0x00040000) -#define SD_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000) -#define SD_CARD_LOCKED ((uint32_t)0x02000000) - -#define SD_DATATIMEOUT ((uint32_t)0xFFFFFFFF) -#define SD_0TO7BITS ((uint32_t)0x000000FF) -#define SD_8TO15BITS ((uint32_t)0x0000FF00) -#define SD_16TO23BITS ((uint32_t)0x00FF0000) -#define SD_24TO31BITS ((uint32_t)0xFF000000) -#define SD_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFF) - -#define SD_HALFFIFO ((uint32_t)0x00000008) -#define SD_HALFFIFOBYTES ((uint32_t)0x00000020) - -/** - * @brief Command Class Supported - */ -#define SD_CCCC_LOCK_UNLOCK ((uint32_t)0x00000080) -#define SD_CCCC_WRITE_PROT ((uint32_t)0x00000040) -#define SD_CCCC_ERASE ((uint32_t)0x00000020) - -/** - * @brief Following commands are SD Card Specific commands. - * SDIO_APP_CMD should be sent before sending these commands. - */ -#define SDIO_SEND_IF_COND ((uint32_t)0x00000008) - -/** - * @} - */ - -/** @defgroup STM324x7I_EVAL_SDIO_SD_Private_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup STM324x7I_EVAL_SDIO_SD_Private_Variables - * @{ - */ - -static uint32_t CardType = SDIO_STD_CAPACITY_SD_CARD_V1_1; -static uint32_t CSD_Tab[4], CID_Tab[4], RCA = 0; -static uint8_t SDSTATUS_Tab[16]; -__IO uint32_t StopCondition = 0; -__IO SD_Error TransferError = SD_OK; -__IO uint32_t TransferEnd = 0, DMAEndOfTransfer = 0; -SD_CardInfo SDCardInfo; - -SDIO_InitTypeDef SDIO_InitStructure; -SDIO_CmdInitTypeDef SDIO_CmdInitStructure; -SDIO_DataInitTypeDef SDIO_DataInitStructure; -/** - * @} - */ - - -/** @defgroup STM324x7I_EVAL_SDIO_SD_Private_Function_Prototypes - * @{ - */ -static SD_Error CmdError(void); -static SD_Error CmdResp1Error(uint8_t cmd); -static SD_Error CmdResp7Error(void); -static SD_Error CmdResp3Error(void); -static SD_Error CmdResp2Error(void); -static SD_Error CmdResp6Error(uint8_t cmd, uint16_t *prca); -static SD_Error SDEnWideBus(FunctionalState NewState); -static SD_Error IsCardProgramming(uint8_t *pstatus); -static SD_Error FindSCR(uint16_t rca, uint32_t *pscr); -uint8_t convert_from_bytes_to_power_of_two(uint16_t NumberOfBytes); - -/** - * @} - */ - - -/** @defgroup STM324x7I_EVAL_SDIO_SD_Private_Functions - * @{ - */ - -/** - * @brief DeInitializes the SDIO interface. - * @param None - * @retval None - */ -void SD_DeInit(void) -{ - SD_LowLevel_DeInit(); -} - -/** - * @brief Initializes the SD Card and put it into StandBy State (Ready for data - * transfer). - * @param None - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_Init(void) -{ - __IO SD_Error errorstatus = SD_OK; - - /* SDIO Peripheral Low Level Init */ - SD_LowLevel_Init(); - - SDIO_DeInit(); - - errorstatus = SD_PowerON(); - - if (errorstatus != SD_OK) - { - /*!< CMD Response TimeOut (wait for CMDSENT flag) */ - return(errorstatus); - } - - errorstatus = SD_InitializeCards(); - - if (errorstatus != SD_OK) - { - /*!< CMD Response TimeOut (wait for CMDSENT flag) */ - return(errorstatus); - } - - /*!< Configure the SDIO peripheral */ - /*!< SDIO_CK = SDIOCLK / (SDIO_TRANSFER_CLK_DIV + 2) */ - /*!< on STM32F4xx devices, SDIOCLK is fixed to 48MHz */ - SDIO_InitStructure.SDIO_ClockDiv = SDIO_TRANSFER_CLK_DIV; - SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising; - SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable; - SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; - SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_1b; - SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; - SDIO_Init(&SDIO_InitStructure); - - /*----------------- Read CSD/CID MSD registers ------------------*/ - errorstatus = SD_GetCardInfo(&SDCardInfo); - - if (errorstatus == SD_OK) - { - /*----------------- Select Card --------------------------------*/ - errorstatus = SD_SelectDeselect((uint32_t) (SDCardInfo.RCA << 16)); - } - - if (errorstatus == SD_OK) - { - errorstatus = SD_EnableWideBusOperation(SDIO_BusWide_4b); - } - - return(errorstatus); -} - -/** - * @brief Gets the cuurent sd card data transfer status. - * @param None - * @retval SDTransferState: Data Transfer state. - * This value can be: - * - SD_TRANSFER_OK: No data transfer is acting - * - SD_TRANSFER_BUSY: Data transfer is acting - */ -SDTransferState SD_GetStatus(void) -{ - SDCardState cardstate = SD_CARD_TRANSFER; - - cardstate = SD_GetState(); - - if (cardstate == SD_CARD_TRANSFER) - { - return(SD_TRANSFER_OK); - } - else if(cardstate == SD_CARD_ERROR) - { - return (SD_TRANSFER_ERROR); - } - else - { - return(SD_TRANSFER_BUSY); - } -} - -/** - * @brief Returns the current card's state. - * @param None - * @retval SDCardState: SD Card Error or SD Card Current State. - */ -SDCardState SD_GetState(void) -{ - uint32_t resp1 = 0; - - if(SD_Detect()== SD_PRESENT) - { - if (SD_SendStatus(&resp1) != SD_OK) - { - return SD_CARD_ERROR; - } - else - { - return (SDCardState)((resp1 >> 9) & 0x0F); - } - } - else - { - return SD_CARD_ERROR; - } -} - -/** - * @brief Detect if SD card is correctly plugged in the memory slot. - * @param None - * @retval Return if SD is detected or not - */ -uint8_t SD_Detect(void) -{ - __IO uint8_t status = SD_PRESENT; - - /*!< Check GPIO to detect SD */ -#if defined(PYBOARD3) - if (GPIO_ReadInputDataBit(SD_DETECT_GPIO_PORT, SD_DETECT_PIN) != Bit_SET) -#elif defined(PYBOARD4) - if (GPIO_ReadInputDataBit(SD_DETECT_GPIO_PORT, SD_DETECT_PIN) == Bit_SET) -#endif - { - status = SD_NOT_PRESENT; - } - return status; -} - -/** - * @brief Enquires cards about their operating voltage and configures - * clock controls. - * @param None - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_PowerON(void) -{ - __IO SD_Error errorstatus = SD_OK; - uint32_t response = 0, count = 0, validvoltage = 0; - uint32_t SDType = SD_STD_CAPACITY; - - /*!< Power ON Sequence -----------------------------------------------------*/ - /*!< Configure the SDIO peripheral */ - /*!< SDIO_CK = SDIOCLK / (SDIO_INIT_CLK_DIV + 2) */ - /*!< on STM32F4xx devices, SDIOCLK is fixed to 48MHz */ - /*!< SDIO_CK for initialization should not exceed 400 KHz */ - SDIO_InitStructure.SDIO_ClockDiv = SDIO_INIT_CLK_DIV; - SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising; - SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable; - SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; - SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_1b; - SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; - SDIO_Init(&SDIO_InitStructure); - - /*!< Set Power State to ON */ - SDIO_SetPowerState(SDIO_PowerState_ON); - - /*!< Enable SDIO Clock */ - SDIO_ClockCmd(ENABLE); - - /*!< CMD0: GO_IDLE_STATE ---------------------------------------------------*/ - /*!< No CMD response required */ - SDIO_CmdInitStructure.SDIO_Argument = 0x0; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_GO_IDLE_STATE; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_No; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdError(); - - if (errorstatus != SD_OK) - { - /*!< CMD Response TimeOut (wait for CMDSENT flag) */ - return(errorstatus); - } - - /*!< CMD8: SEND_IF_COND ----------------------------------------------------*/ - /*!< Send CMD8 to verify SD card interface operating condition */ - /*!< Argument: - [31:12]: Reserved (shall be set to '0') - - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V) - - [7:0]: Check Pattern (recommended 0xAA) */ - /*!< CMD Response: R7 */ - SDIO_CmdInitStructure.SDIO_Argument = SD_CHECK_PATTERN; - SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_SEND_IF_COND; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp7Error(); - - if (errorstatus == SD_OK) - { - CardType = SDIO_STD_CAPACITY_SD_CARD_V2_0; /*!< SD Card 2.0 */ - SDType = SD_HIGH_CAPACITY; - } - else - { - /*!< CMD55 */ - SDIO_CmdInitStructure.SDIO_Argument = 0x00; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - errorstatus = CmdResp1Error(SD_CMD_APP_CMD); - } - /*!< CMD55 */ - SDIO_CmdInitStructure.SDIO_Argument = 0x00; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - errorstatus = CmdResp1Error(SD_CMD_APP_CMD); - - /*!< If errorstatus is Command TimeOut, it is a MMC card */ - /*!< If errorstatus is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch) - or SD card 1.x */ - if (errorstatus == SD_OK) - { - /*!< SD CARD */ - /*!< Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ - while ((!validvoltage) && (count < SD_MAX_VOLT_TRIAL)) - { - - /*!< SEND CMD55 APP_CMD with RCA as 0 */ - SDIO_CmdInitStructure.SDIO_Argument = 0x00; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_APP_CMD); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - SDIO_CmdInitStructure.SDIO_Argument = SD_VOLTAGE_WINDOW_SD | SDType; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_APP_OP_COND; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp3Error(); - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - response = SDIO_GetResponse(SDIO_RESP1); - validvoltage = (((response >> 31) == 1) ? 1 : 0); - count++; - } - if (count >= SD_MAX_VOLT_TRIAL) - { - errorstatus = SD_INVALID_VOLTRANGE; - return(errorstatus); - } - - if (response &= SD_HIGH_CAPACITY) - { - CardType = SDIO_HIGH_CAPACITY_SD_CARD; - } - - }/*!< else MMC Card */ - - return(errorstatus); -} - -/** - * @brief Turns the SDIO output signals off. - * @param None - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_PowerOFF(void) -{ - SD_Error errorstatus = SD_OK; - - /*!< Set Power State to OFF */ - SDIO_SetPowerState(SDIO_PowerState_OFF); - - return(errorstatus); -} - -/** - * @brief Intialises all cards or single card as the case may be Card(s) come - * into standby state. - * @param None - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_InitializeCards(void) -{ - SD_Error errorstatus = SD_OK; - uint16_t rca = 0x01; - - if (SDIO_GetPowerState() == SDIO_PowerState_OFF) - { - errorstatus = SD_REQUEST_NOT_APPLICABLE; - return(errorstatus); - } - - if (SDIO_SECURE_DIGITAL_IO_CARD != CardType) - { - /*!< Send CMD2 ALL_SEND_CID */ - SDIO_CmdInitStructure.SDIO_Argument = 0x0; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_ALL_SEND_CID; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Long; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp2Error(); - - if (SD_OK != errorstatus) - { - return(errorstatus); - } - - CID_Tab[0] = SDIO_GetResponse(SDIO_RESP1); - CID_Tab[1] = SDIO_GetResponse(SDIO_RESP2); - CID_Tab[2] = SDIO_GetResponse(SDIO_RESP3); - CID_Tab[3] = SDIO_GetResponse(SDIO_RESP4); - } - if ((SDIO_STD_CAPACITY_SD_CARD_V1_1 == CardType) || (SDIO_STD_CAPACITY_SD_CARD_V2_0 == CardType) || (SDIO_SECURE_DIGITAL_IO_COMBO_CARD == CardType) - || (SDIO_HIGH_CAPACITY_SD_CARD == CardType)) - { - /*!< Send CMD3 SET_REL_ADDR with argument 0 */ - /*!< SD Card publishes its RCA. */ - SDIO_CmdInitStructure.SDIO_Argument = 0x00; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_REL_ADDR; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp6Error(SD_CMD_SET_REL_ADDR, &rca); - - if (SD_OK != errorstatus) - { - return(errorstatus); - } - } - - if (SDIO_SECURE_DIGITAL_IO_CARD != CardType) - { - RCA = rca; - - /*!< Send CMD9 SEND_CSD with argument as card's RCA */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)(rca << 16); - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SEND_CSD; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Long; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp2Error(); - - if (SD_OK != errorstatus) - { - return(errorstatus); - } - - CSD_Tab[0] = SDIO_GetResponse(SDIO_RESP1); - CSD_Tab[1] = SDIO_GetResponse(SDIO_RESP2); - CSD_Tab[2] = SDIO_GetResponse(SDIO_RESP3); - CSD_Tab[3] = SDIO_GetResponse(SDIO_RESP4); - } - - errorstatus = SD_OK; /*!< All cards get intialized */ - - return(errorstatus); -} - -/** - * @brief Returns information about specific card. - * @param cardinfo: pointer to a SD_CardInfo structure that contains all SD card - * information. - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo) -{ - SD_Error errorstatus = SD_OK; - uint8_t tmp = 0; - - cardinfo->CardType = (uint8_t)CardType; - cardinfo->RCA = (uint16_t)RCA; - - /*!< Byte 0 */ - tmp = (uint8_t)((CSD_Tab[0] & 0xFF000000) >> 24); - cardinfo->SD_csd.CSDStruct = (tmp & 0xC0) >> 6; - cardinfo->SD_csd.SysSpecVersion = (tmp & 0x3C) >> 2; - cardinfo->SD_csd.Reserved1 = tmp & 0x03; - - /*!< Byte 1 */ - tmp = (uint8_t)((CSD_Tab[0] & 0x00FF0000) >> 16); - cardinfo->SD_csd.TAAC = tmp; - - /*!< Byte 2 */ - tmp = (uint8_t)((CSD_Tab[0] & 0x0000FF00) >> 8); - cardinfo->SD_csd.NSAC = tmp; - - /*!< Byte 3 */ - tmp = (uint8_t)(CSD_Tab[0] & 0x000000FF); - cardinfo->SD_csd.MaxBusClkFrec = tmp; - - /*!< Byte 4 */ - tmp = (uint8_t)((CSD_Tab[1] & 0xFF000000) >> 24); - cardinfo->SD_csd.CardComdClasses = tmp << 4; - - /*!< Byte 5 */ - tmp = (uint8_t)((CSD_Tab[1] & 0x00FF0000) >> 16); - cardinfo->SD_csd.CardComdClasses |= (tmp & 0xF0) >> 4; - cardinfo->SD_csd.RdBlockLen = tmp & 0x0F; - - /*!< Byte 6 */ - tmp = (uint8_t)((CSD_Tab[1] & 0x0000FF00) >> 8); - cardinfo->SD_csd.PartBlockRead = (tmp & 0x80) >> 7; - cardinfo->SD_csd.WrBlockMisalign = (tmp & 0x40) >> 6; - cardinfo->SD_csd.RdBlockMisalign = (tmp & 0x20) >> 5; - cardinfo->SD_csd.DSRImpl = (tmp & 0x10) >> 4; - cardinfo->SD_csd.Reserved2 = 0; /*!< Reserved */ - - if ((CardType == SDIO_STD_CAPACITY_SD_CARD_V1_1) || (CardType == SDIO_STD_CAPACITY_SD_CARD_V2_0)) - { - cardinfo->SD_csd.DeviceSize = (tmp & 0x03) << 10; - - /*!< Byte 7 */ - tmp = (uint8_t)(CSD_Tab[1] & 0x000000FF); - cardinfo->SD_csd.DeviceSize |= (tmp) << 2; - - /*!< Byte 8 */ - tmp = (uint8_t)((CSD_Tab[2] & 0xFF000000) >> 24); - cardinfo->SD_csd.DeviceSize |= (tmp & 0xC0) >> 6; - - cardinfo->SD_csd.MaxRdCurrentVDDMin = (tmp & 0x38) >> 3; - cardinfo->SD_csd.MaxRdCurrentVDDMax = (tmp & 0x07); - - /*!< Byte 9 */ - tmp = (uint8_t)((CSD_Tab[2] & 0x00FF0000) >> 16); - cardinfo->SD_csd.MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5; - cardinfo->SD_csd.MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2; - cardinfo->SD_csd.DeviceSizeMul = (tmp & 0x03) << 1; - /*!< Byte 10 */ - tmp = (uint8_t)((CSD_Tab[2] & 0x0000FF00) >> 8); - cardinfo->SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7; - - cardinfo->CardCapacity = (cardinfo->SD_csd.DeviceSize + 1) ; - cardinfo->CardCapacity *= (1 << (cardinfo->SD_csd.DeviceSizeMul + 2)); - cardinfo->CardBlockSize = 1 << (cardinfo->SD_csd.RdBlockLen); - cardinfo->CardCapacity *= cardinfo->CardBlockSize; - } - else if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) - { - /*!< Byte 7 */ - tmp = (uint8_t)(CSD_Tab[1] & 0x000000FF); - cardinfo->SD_csd.DeviceSize = (tmp & 0x3F) << 16; - - /*!< Byte 8 */ - tmp = (uint8_t)((CSD_Tab[2] & 0xFF000000) >> 24); - - cardinfo->SD_csd.DeviceSize |= (tmp << 8); - - /*!< Byte 9 */ - tmp = (uint8_t)((CSD_Tab[2] & 0x00FF0000) >> 16); - - cardinfo->SD_csd.DeviceSize |= (tmp); - - /*!< Byte 10 */ - tmp = (uint8_t)((CSD_Tab[2] & 0x0000FF00) >> 8); - - cardinfo->CardCapacity = ((uint64_t)cardinfo->SD_csd.DeviceSize + 1) * 512 * 1024; - cardinfo->CardBlockSize = 512; - } - - - cardinfo->SD_csd.EraseGrSize = (tmp & 0x40) >> 6; - cardinfo->SD_csd.EraseGrMul = (tmp & 0x3F) << 1; - - /*!< Byte 11 */ - tmp = (uint8_t)(CSD_Tab[2] & 0x000000FF); - cardinfo->SD_csd.EraseGrMul |= (tmp & 0x80) >> 7; - cardinfo->SD_csd.WrProtectGrSize = (tmp & 0x7F); - - /*!< Byte 12 */ - tmp = (uint8_t)((CSD_Tab[3] & 0xFF000000) >> 24); - cardinfo->SD_csd.WrProtectGrEnable = (tmp & 0x80) >> 7; - cardinfo->SD_csd.ManDeflECC = (tmp & 0x60) >> 5; - cardinfo->SD_csd.WrSpeedFact = (tmp & 0x1C) >> 2; - cardinfo->SD_csd.MaxWrBlockLen = (tmp & 0x03) << 2; - - /*!< Byte 13 */ - tmp = (uint8_t)((CSD_Tab[3] & 0x00FF0000) >> 16); - cardinfo->SD_csd.MaxWrBlockLen |= (tmp & 0xC0) >> 6; - cardinfo->SD_csd.WriteBlockPaPartial = (tmp & 0x20) >> 5; - cardinfo->SD_csd.Reserved3 = 0; - cardinfo->SD_csd.ContentProtectAppli = (tmp & 0x01); - - /*!< Byte 14 */ - tmp = (uint8_t)((CSD_Tab[3] & 0x0000FF00) >> 8); - cardinfo->SD_csd.FileFormatGrouop = (tmp & 0x80) >> 7; - cardinfo->SD_csd.CopyFlag = (tmp & 0x40) >> 6; - cardinfo->SD_csd.PermWrProtect = (tmp & 0x20) >> 5; - cardinfo->SD_csd.TempWrProtect = (tmp & 0x10) >> 4; - cardinfo->SD_csd.FileFormat = (tmp & 0x0C) >> 2; - cardinfo->SD_csd.ECC = (tmp & 0x03); - - /*!< Byte 15 */ - tmp = (uint8_t)(CSD_Tab[3] & 0x000000FF); - cardinfo->SD_csd.CSD_CRC = (tmp & 0xFE) >> 1; - cardinfo->SD_csd.Reserved4 = 1; - - - /*!< Byte 0 */ - tmp = (uint8_t)((CID_Tab[0] & 0xFF000000) >> 24); - cardinfo->SD_cid.ManufacturerID = tmp; - - /*!< Byte 1 */ - tmp = (uint8_t)((CID_Tab[0] & 0x00FF0000) >> 16); - cardinfo->SD_cid.OEM_AppliID = tmp << 8; - - /*!< Byte 2 */ - tmp = (uint8_t)((CID_Tab[0] & 0x000000FF00) >> 8); - cardinfo->SD_cid.OEM_AppliID |= tmp; - - /*!< Byte 3 */ - tmp = (uint8_t)(CID_Tab[0] & 0x000000FF); - cardinfo->SD_cid.ProdName1 = tmp << 24; - - /*!< Byte 4 */ - tmp = (uint8_t)((CID_Tab[1] & 0xFF000000) >> 24); - cardinfo->SD_cid.ProdName1 |= tmp << 16; - - /*!< Byte 5 */ - tmp = (uint8_t)((CID_Tab[1] & 0x00FF0000) >> 16); - cardinfo->SD_cid.ProdName1 |= tmp << 8; - - /*!< Byte 6 */ - tmp = (uint8_t)((CID_Tab[1] & 0x0000FF00) >> 8); - cardinfo->SD_cid.ProdName1 |= tmp; - - /*!< Byte 7 */ - tmp = (uint8_t)(CID_Tab[1] & 0x000000FF); - cardinfo->SD_cid.ProdName2 = tmp; - - /*!< Byte 8 */ - tmp = (uint8_t)((CID_Tab[2] & 0xFF000000) >> 24); - cardinfo->SD_cid.ProdRev = tmp; - - /*!< Byte 9 */ - tmp = (uint8_t)((CID_Tab[2] & 0x00FF0000) >> 16); - cardinfo->SD_cid.ProdSN = tmp << 24; - - /*!< Byte 10 */ - tmp = (uint8_t)((CID_Tab[2] & 0x0000FF00) >> 8); - cardinfo->SD_cid.ProdSN |= tmp << 16; - - /*!< Byte 11 */ - tmp = (uint8_t)(CID_Tab[2] & 0x000000FF); - cardinfo->SD_cid.ProdSN |= tmp << 8; - - /*!< Byte 12 */ - tmp = (uint8_t)((CID_Tab[3] & 0xFF000000) >> 24); - cardinfo->SD_cid.ProdSN |= tmp; - - /*!< Byte 13 */ - tmp = (uint8_t)((CID_Tab[3] & 0x00FF0000) >> 16); - cardinfo->SD_cid.Reserved1 |= (tmp & 0xF0) >> 4; - cardinfo->SD_cid.ManufactDate = (tmp & 0x0F) << 8; - - /*!< Byte 14 */ - tmp = (uint8_t)((CID_Tab[3] & 0x0000FF00) >> 8); - cardinfo->SD_cid.ManufactDate |= tmp; - - /*!< Byte 15 */ - tmp = (uint8_t)(CID_Tab[3] & 0x000000FF); - cardinfo->SD_cid.CID_CRC = (tmp & 0xFE) >> 1; - cardinfo->SD_cid.Reserved2 = 1; - - return(errorstatus); -} - -/** - * @brief Enables wide bus opeartion for the requeseted card if supported by - * card. - * @param WideMode: Specifies the SD card wide bus mode. - * This parameter can be one of the following values: - * @arg SDIO_BusWide_8b: 8-bit data transfer (Only for MMC) - * @arg SDIO_BusWide_4b: 4-bit data transfer - * @arg SDIO_BusWide_1b: 1-bit data transfer - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_GetCardStatus(SD_CardStatus *cardstatus) -{ - SD_Error errorstatus = SD_OK; - uint8_t tmp = 0; - - errorstatus = SD_SendSDStatus((uint32_t *)SDSTATUS_Tab); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - /*!< Byte 0 */ - tmp = (uint8_t)((SDSTATUS_Tab[0] & 0xC0) >> 6); - cardstatus->DAT_BUS_WIDTH = tmp; - - /*!< Byte 0 */ - tmp = (uint8_t)((SDSTATUS_Tab[0] & 0x20) >> 5); - cardstatus->SECURED_MODE = tmp; - - /*!< Byte 2 */ - tmp = (uint8_t)((SDSTATUS_Tab[2] & 0xFF)); - cardstatus->SD_CARD_TYPE = tmp << 8; - - /*!< Byte 3 */ - tmp = (uint8_t)((SDSTATUS_Tab[3] & 0xFF)); - cardstatus->SD_CARD_TYPE |= tmp; - - /*!< Byte 4 */ - tmp = (uint8_t)(SDSTATUS_Tab[4] & 0xFF); - cardstatus->SIZE_OF_PROTECTED_AREA = tmp << 24; - - /*!< Byte 5 */ - tmp = (uint8_t)(SDSTATUS_Tab[5] & 0xFF); - cardstatus->SIZE_OF_PROTECTED_AREA |= tmp << 16; - - /*!< Byte 6 */ - tmp = (uint8_t)(SDSTATUS_Tab[6] & 0xFF); - cardstatus->SIZE_OF_PROTECTED_AREA |= tmp << 8; - - /*!< Byte 7 */ - tmp = (uint8_t)(SDSTATUS_Tab[7] & 0xFF); - cardstatus->SIZE_OF_PROTECTED_AREA |= tmp; - - /*!< Byte 8 */ - tmp = (uint8_t)((SDSTATUS_Tab[8] & 0xFF)); - cardstatus->SPEED_CLASS = tmp; - - /*!< Byte 9 */ - tmp = (uint8_t)((SDSTATUS_Tab[9] & 0xFF)); - cardstatus->PERFORMANCE_MOVE = tmp; - - /*!< Byte 10 */ - tmp = (uint8_t)((SDSTATUS_Tab[10] & 0xF0) >> 4); - cardstatus->AU_SIZE = tmp; - - /*!< Byte 11 */ - tmp = (uint8_t)(SDSTATUS_Tab[11] & 0xFF); - cardstatus->ERASE_SIZE = tmp << 8; - - /*!< Byte 12 */ - tmp = (uint8_t)(SDSTATUS_Tab[12] & 0xFF); - cardstatus->ERASE_SIZE |= tmp; - - /*!< Byte 13 */ - tmp = (uint8_t)((SDSTATUS_Tab[13] & 0xFC) >> 2); - cardstatus->ERASE_TIMEOUT = tmp; - - /*!< Byte 13 */ - tmp = (uint8_t)((SDSTATUS_Tab[13] & 0x3)); - cardstatus->ERASE_OFFSET = tmp; - - return(errorstatus); -} - -/** - * @brief Enables wide bus opeartion for the requeseted card if supported by - * card. - * @param WideMode: Specifies the SD card wide bus mode. - * This parameter can be one of the following values: - * @arg SDIO_BusWide_8b: 8-bit data transfer (Only for MMC) - * @arg SDIO_BusWide_4b: 4-bit data transfer - * @arg SDIO_BusWide_1b: 1-bit data transfer - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_EnableWideBusOperation(uint32_t WideMode) -{ - SD_Error errorstatus = SD_OK; - - /*!< MMC Card doesn't support this feature */ - if (SDIO_MULTIMEDIA_CARD == CardType) - { - errorstatus = SD_UNSUPPORTED_FEATURE; - return(errorstatus); - } - else if ((SDIO_STD_CAPACITY_SD_CARD_V1_1 == CardType) || (SDIO_STD_CAPACITY_SD_CARD_V2_0 == CardType) || (SDIO_HIGH_CAPACITY_SD_CARD == CardType)) - { - if (SDIO_BusWide_8b == WideMode) - { - errorstatus = SD_UNSUPPORTED_FEATURE; - return(errorstatus); - } - else if (SDIO_BusWide_4b == WideMode) - { - errorstatus = SDEnWideBus(ENABLE); - - if (SD_OK == errorstatus) - { - /*!< Configure the SDIO peripheral */ - SDIO_InitStructure.SDIO_ClockDiv = SDIO_TRANSFER_CLK_DIV; - SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising; - SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable; - SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; - SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_4b; - SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; - SDIO_Init(&SDIO_InitStructure); - } - } - else - { - errorstatus = SDEnWideBus(DISABLE); - - if (SD_OK == errorstatus) - { - /*!< Configure the SDIO peripheral */ - SDIO_InitStructure.SDIO_ClockDiv = SDIO_TRANSFER_CLK_DIV; - SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising; - SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable; - SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; - SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_1b; - SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; - SDIO_Init(&SDIO_InitStructure); - } - } - } - - return(errorstatus); -} - -/** - * @brief Selects od Deselects the corresponding card. - * @param addr: Address of the Card to be selected. - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_SelectDeselect(uint64_t addr) -{ - SD_Error errorstatus = SD_OK; - - /*!< Send CMD7 SDIO_SEL_DESEL_CARD */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)addr; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SEL_DESEL_CARD; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_SEL_DESEL_CARD); - - return(errorstatus); -} - -/** - * @brief Allows to read one block from a specified address in a card. The Data - * transfer can be managed by DMA mode or Polling mode. - * @note This operation should be followed by two functions to check if the - * DMA Controller and SD Card status. - * - SD_ReadWaitOperation(): this function insure that the DMA - * controller has finished all data transfer. - * - SD_GetStatus(): to check that the SD Card has finished the - * data transfer and it is ready for data. - * @param readbuff: pointer to the buffer that will contain the received data - * @param ReadAddr: Address from where data are to be read. - * @param BlockSize: the SD card Data block size. The Block size should be 512. - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_ReadBlock(uint8_t *readbuff, uint64_t ReadAddr, uint16_t BlockSize) -{ - SD_Error errorstatus = SD_OK; -#if defined (SD_POLLING_MODE) - uint32_t count = 0, *tempbuff = (uint32_t *)readbuff; -#endif - - TransferError = SD_OK; - TransferEnd = 0; - StopCondition = 0; - - SDIO->DCTRL = 0x0; - -#if defined (SD_DMA_MODE) - SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | SDIO_IT_RXOVERR | SDIO_IT_STBITERR, ENABLE); - SDIO_DMACmd(ENABLE); - SD_LowLevel_DMA_RxConfig((uint32_t *)readbuff, BlockSize); -#endif - - if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) - { - BlockSize = 512; - ReadAddr /= 512; - } - - /* Set Block Size for Card */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) BlockSize; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN); - - if (SD_OK != errorstatus) - { - return(errorstatus); - } - - SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; - SDIO_DataInitStructure.SDIO_DataLength = BlockSize; - SDIO_DataInitStructure.SDIO_DataBlockSize = (uint32_t) 9 << 4; - SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO; - SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; - SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable; - SDIO_DataConfig(&SDIO_DataInitStructure); - - /*!< Send CMD17 READ_SINGLE_BLOCK */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)ReadAddr; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_READ_SINGLE_BLOCK; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_READ_SINGLE_BLOCK); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - -#if defined (SD_POLLING_MODE) - /*!< In case of single block transfer, no need of stop transfer at all.*/ - /*!< Polling mode */ - while (!(SDIO->STA &(SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))) - { - if (SDIO_GetFlagStatus(SDIO_FLAG_RXFIFOHF) != RESET) - { - for (count = 0; count < 8; count++) - { - *(tempbuff + count) = SDIO_ReadData(); - } - tempbuff += 8; - } - } - - if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT); - errorstatus = SD_DATA_TIMEOUT; - return(errorstatus); - } - else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL); - errorstatus = SD_DATA_CRC_FAIL; - return(errorstatus); - } - else if (SDIO_GetFlagStatus(SDIO_FLAG_RXOVERR) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_RXOVERR); - errorstatus = SD_RX_OVERRUN; - return(errorstatus); - } - else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_STBITERR); - errorstatus = SD_START_BIT_ERR; - return(errorstatus); - } - count = SD_DATATIMEOUT; - while ((SDIO_GetFlagStatus(SDIO_FLAG_RXDAVL) != RESET) && (count > 0)) - { - *tempbuff = SDIO_ReadData(); - tempbuff++; - count--; - } - - /*!< Clear all the static flags */ - SDIO_ClearFlag(SDIO_STATIC_FLAGS); - -#endif - - return(errorstatus); -} - -/** - * @brief Allows to read blocks from a specified address in a card. The Data - * transfer can be managed by DMA mode or Polling mode. - * @note This operation should be followed by two functions to check if the - * DMA Controller and SD Card status. - * - SD_ReadWaitOperation(): this function insure that the DMA - * controller has finished all data transfer. - * - SD_GetStatus(): to check that the SD Card has finished the - * data transfer and it is ready for data. - * @param readbuff: pointer to the buffer that will contain the received data. - * @param ReadAddr: Address from where data are to be read. - * @param BlockSize: the SD card Data block size. The Block size should be 512. - * @param NumberOfBlocks: number of blocks to be read. - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_ReadMultiBlocks(uint8_t *readbuff, uint64_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks) -{ - SD_Error errorstatus = SD_OK; - TransferError = SD_OK; - TransferEnd = 0; - StopCondition = 1; - - SDIO->DCTRL = 0x0; - - SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | SDIO_IT_RXOVERR | SDIO_IT_STBITERR, ENABLE); - SD_LowLevel_DMA_RxConfig((uint32_t *)readbuff, (NumberOfBlocks * BlockSize)); - SDIO_DMACmd(ENABLE); - - if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) - { - BlockSize = 512; - ReadAddr /= 512; - } - - /*!< Set Block Size for Card */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) BlockSize; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN); - - if (SD_OK != errorstatus) - { - return(errorstatus); - } - - SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; - SDIO_DataInitStructure.SDIO_DataLength = NumberOfBlocks * BlockSize; - SDIO_DataInitStructure.SDIO_DataBlockSize = (uint32_t) 9 << 4; - SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO; - SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; - SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable; - SDIO_DataConfig(&SDIO_DataInitStructure); - - /*!< Send CMD18 READ_MULT_BLOCK with argument data address */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)ReadAddr; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_READ_MULT_BLOCK; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_READ_MULT_BLOCK); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - return(errorstatus); -} - -/** - * @brief This function waits until the SDIO DMA data transfer is finished. - * This function should be called after SDIO_ReadMultiBlocks() function - * to insure that all data sent by the card are already transferred by - * the DMA controller. - * @param None. - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_WaitReadOperation(void) -{ - SD_Error errorstatus = SD_OK; - uint32_t timeout; - - timeout = SD_DATATIMEOUT; - - while ((DMAEndOfTransfer == 0x00) && (TransferEnd == 0) && (TransferError == SD_OK) && (timeout > 0)) - { - timeout--; - } - - DMAEndOfTransfer = 0x00; - - timeout = SD_DATATIMEOUT; - - while(((SDIO->STA & SDIO_FLAG_RXACT)) && (timeout > 0)) - { - timeout--; - } - - if (StopCondition == 1) - { - errorstatus = SD_StopTransfer(); - StopCondition = 0; - } - - if ((timeout == 0) && (errorstatus == SD_OK)) - { - errorstatus = SD_DATA_TIMEOUT; - } - - /*!< Clear all the static flags */ - SDIO_ClearFlag(SDIO_STATIC_FLAGS); - - if (TransferError != SD_OK) - { - return(TransferError); - } - else - { - return(errorstatus); - } -} - -/** - * @brief Allows to write one block starting from a specified address in a card. - * The Data transfer can be managed by DMA mode or Polling mode. - * @note This operation should be followed by two functions to check if the - * DMA Controller and SD Card status. - * - SD_ReadWaitOperation(): this function insure that the DMA - * controller has finished all data transfer. - * - SD_GetStatus(): to check that the SD Card has finished the - * data transfer and it is ready for data. - * @param writebuff: pointer to the buffer that contain the data to be transferred. - * @param WriteAddr: Address from where data are to be read. - * @param BlockSize: the SD card Data block size. The Block size should be 512. - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_WriteBlock(uint8_t *writebuff, uint64_t WriteAddr, uint16_t BlockSize) -{ - SD_Error errorstatus = SD_OK; - -#if defined (SD_POLLING_MODE) - uint32_t bytestransferred = 0, count = 0, restwords = 0; - uint32_t *tempbuff = (uint32_t *)writebuff; -#endif - - TransferError = SD_OK; - TransferEnd = 0; - StopCondition = 0; - - SDIO->DCTRL = 0x0; - -#if defined (SD_DMA_MODE) - SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | SDIO_IT_RXOVERR | SDIO_IT_STBITERR, ENABLE); - SD_LowLevel_DMA_TxConfig((uint32_t *)writebuff, BlockSize); - SDIO_DMACmd(ENABLE); -#endif - - if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) - { - BlockSize = 512; - WriteAddr /= 512; - } - - /* Set Block Size for Card */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) BlockSize; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN); - - if (SD_OK != errorstatus) - { - return(errorstatus); - } - - /*!< Send CMD24 WRITE_SINGLE_BLOCK */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)WriteAddr; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_WRITE_SINGLE_BLOCK); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; - SDIO_DataInitStructure.SDIO_DataLength = BlockSize; - SDIO_DataInitStructure.SDIO_DataBlockSize = (uint32_t) 9 << 4; - SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToCard; - SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; - SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable; - SDIO_DataConfig(&SDIO_DataInitStructure); - - /*!< In case of single data block transfer no need of stop command at all */ -#if defined (SD_POLLING_MODE) - while (!(SDIO->STA & (SDIO_FLAG_DBCKEND | SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_STBITERR))) - { - if (SDIO_GetFlagStatus(SDIO_FLAG_TXFIFOHE) != RESET) - { - if ((512 - bytestransferred) < 32) - { - restwords = ((512 - bytestransferred) % 4 == 0) ? ((512 - bytestransferred) / 4) : (( 512 - bytestransferred) / 4 + 1); - for (count = 0; count < restwords; count++, tempbuff++, bytestransferred += 4) - { - SDIO_WriteData(*tempbuff); - } - } - else - { - for (count = 0; count < 8; count++) - { - SDIO_WriteData(*(tempbuff + count)); - } - tempbuff += 8; - bytestransferred += 32; - } - } - } - if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT); - errorstatus = SD_DATA_TIMEOUT; - return(errorstatus); - } - else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL); - errorstatus = SD_DATA_CRC_FAIL; - return(errorstatus); - } - else if (SDIO_GetFlagStatus(SDIO_FLAG_TXUNDERR) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_TXUNDERR); - errorstatus = SD_TX_UNDERRUN; - return(errorstatus); - } - else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_STBITERR); - errorstatus = SD_START_BIT_ERR; - return(errorstatus); - } - -#endif - - return(errorstatus); -} - -/** - * @brief Allows to write blocks starting from a specified address in a card. - * The Data transfer can be managed by DMA mode only. - * @note This operation should be followed by two functions to check if the - * DMA Controller and SD Card status. - * - SD_ReadWaitOperation(): this function insure that the DMA - * controller has finished all data transfer. - * - SD_GetStatus(): to check that the SD Card has finished the - * data transfer and it is ready for data. - * @param WriteAddr: Address from where data are to be read. - * @param writebuff: pointer to the buffer that contain the data to be transferred. - * @param BlockSize: the SD card Data block size. The Block size should be 512. - * @param NumberOfBlocks: number of blocks to be written. - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_WriteMultiBlocks(uint8_t *writebuff, uint64_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks) -{ - SD_Error errorstatus = SD_OK; - - TransferError = SD_OK; - TransferEnd = 0; - StopCondition = 1; - SDIO->DCTRL = 0x0; - - SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | SDIO_IT_RXOVERR | SDIO_IT_STBITERR, ENABLE); - SD_LowLevel_DMA_TxConfig((uint32_t *)writebuff, (NumberOfBlocks * BlockSize)); - SDIO_DMACmd(ENABLE); - - if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) - { - BlockSize = 512; - WriteAddr /= 512; - } - - /* Set Block Size for Card */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) BlockSize; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN); - - if (SD_OK != errorstatus) - { - return(errorstatus); - } - - /*!< To improve performance */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) (RCA << 16); - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - - errorstatus = CmdResp1Error(SD_CMD_APP_CMD); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - /*!< To improve performance */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)NumberOfBlocks; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCK_COUNT; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_SET_BLOCK_COUNT); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - - /*!< Send CMD25 WRITE_MULT_BLOCK with argument data address */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)WriteAddr; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_WRITE_MULT_BLOCK; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_WRITE_MULT_BLOCK); - - if (SD_OK != errorstatus) - { - return(errorstatus); - } - - SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; - SDIO_DataInitStructure.SDIO_DataLength = NumberOfBlocks * BlockSize; - SDIO_DataInitStructure.SDIO_DataBlockSize = (uint32_t) 9 << 4; - SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToCard; - SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; - SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable; - SDIO_DataConfig(&SDIO_DataInitStructure); - - return(errorstatus); -} - -/** - * @brief This function waits until the SDIO DMA data transfer is finished. - * This function should be called after SDIO_WriteBlock() and - * SDIO_WriteMultiBlocks() function to insure that all data sent by the - * card are already transferred by the DMA controller. - * @param None. - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_WaitWriteOperation(void) -{ - SD_Error errorstatus = SD_OK; - uint32_t timeout; - - timeout = SD_DATATIMEOUT; - - while ((DMAEndOfTransfer == 0x00) && (TransferEnd == 0) && (TransferError == SD_OK) && (timeout > 0)) - { - timeout--; - } - - DMAEndOfTransfer = 0x00; - - timeout = SD_DATATIMEOUT; - - while(((SDIO->STA & SDIO_FLAG_TXACT)) && (timeout > 0)) - { - timeout--; - } - - if (StopCondition == 1) - { - errorstatus = SD_StopTransfer(); - StopCondition = 0; - } - - if ((timeout == 0) && (errorstatus == SD_OK)) - { - errorstatus = SD_DATA_TIMEOUT; - } - - /*!< Clear all the static flags */ - SDIO_ClearFlag(SDIO_STATIC_FLAGS); - - if (TransferError != SD_OK) - { - return(TransferError); - } - else - { - return(errorstatus); - } -} - -/** - * @brief Gets the cuurent data transfer state. - * @param None - * @retval SDTransferState: Data Transfer state. - * This value can be: - * - SD_TRANSFER_OK: No data transfer is acting - * - SD_TRANSFER_BUSY: Data transfer is acting - */ -SDTransferState SD_GetTransferState(void) -{ - if (SDIO->STA & (SDIO_FLAG_TXACT | SDIO_FLAG_RXACT)) - { - return(SD_TRANSFER_BUSY); - } - else - { - return(SD_TRANSFER_OK); - } -} - -/** - * @brief Aborts an ongoing data transfer. - * @param None - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_StopTransfer(void) -{ - SD_Error errorstatus = SD_OK; - - /*!< Send CMD12 STOP_TRANSMISSION */ - SDIO_CmdInitStructure.SDIO_Argument = 0x0; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_STOP_TRANSMISSION; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_STOP_TRANSMISSION); - - return(errorstatus); -} - -/** - * @brief Allows to erase memory area specified for the given card. - * @param startaddr: the start address. - * @param endaddr: the end address. - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_Erase(uint64_t startaddr, uint64_t endaddr) -{ - SD_Error errorstatus = SD_OK; - uint32_t delay = 0; - __IO uint32_t maxdelay = 0; - uint8_t cardstate = 0; - - /*!< Check if the card coomnd class supports erase command */ - if (((CSD_Tab[1] >> 20) & SD_CCCC_ERASE) == 0) - { - errorstatus = SD_REQUEST_NOT_APPLICABLE; - return(errorstatus); - } - - maxdelay = 120000 / ((SDIO->CLKCR & 0xFF) + 2); - - if (SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) - { - errorstatus = SD_LOCK_UNLOCK_FAILED; - return(errorstatus); - } - - if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) - { - startaddr /= 512; - endaddr /= 512; - } - - /*!< According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */ - if ((SDIO_STD_CAPACITY_SD_CARD_V1_1 == CardType) || (SDIO_STD_CAPACITY_SD_CARD_V2_0 == CardType) || (SDIO_HIGH_CAPACITY_SD_CARD == CardType)) - { - /*!< Send CMD32 SD_ERASE_GRP_START with argument as addr */ - SDIO_CmdInitStructure.SDIO_Argument =(uint32_t)startaddr; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_ERASE_GRP_START; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_SD_ERASE_GRP_START); - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - /*!< Send CMD33 SD_ERASE_GRP_END with argument as addr */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)endaddr; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_ERASE_GRP_END; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_SD_ERASE_GRP_END); - if (errorstatus != SD_OK) - { - return(errorstatus); - } - } - - /*!< Send CMD38 ERASE */ - SDIO_CmdInitStructure.SDIO_Argument = 0; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_ERASE; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_ERASE); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - for (delay = 0; delay < maxdelay; delay++) - {} - - /*!< Wait till the card is in programming state */ - errorstatus = IsCardProgramming(&cardstate); - delay = SD_DATATIMEOUT; - while ((delay > 0) && (errorstatus == SD_OK) && ((SD_CARD_PROGRAMMING == cardstate) || (SD_CARD_RECEIVING == cardstate))) - { - errorstatus = IsCardProgramming(&cardstate); - delay--; - } - - return(errorstatus); -} - -/** - * @brief Returns the current card's status. - * @param pcardstatus: pointer to the buffer that will contain the SD card - * status (Card Status register). - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_SendStatus(uint32_t *pcardstatus) -{ - SD_Error errorstatus = SD_OK; - - if (pcardstatus == NULL) - { - errorstatus = SD_INVALID_PARAMETER; - return(errorstatus); - } - - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SEND_STATUS; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_SEND_STATUS); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - *pcardstatus = SDIO_GetResponse(SDIO_RESP1); - - return(errorstatus); -} - -/** - * @brief Returns the current SD card's status. - * @param psdstatus: pointer to the buffer that will contain the SD card status - * (SD Status register). - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_SendSDStatus(uint32_t *psdstatus) -{ - SD_Error errorstatus = SD_OK; - uint32_t count = 0; - - if (SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) - { - errorstatus = SD_LOCK_UNLOCK_FAILED; - return(errorstatus); - } - - /*!< Set block size for card if it is not equal to current block size for card. */ - SDIO_CmdInitStructure.SDIO_Argument = 64; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - /*!< CMD55 */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - errorstatus = CmdResp1Error(SD_CMD_APP_CMD); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; - SDIO_DataInitStructure.SDIO_DataLength = 64; - SDIO_DataInitStructure.SDIO_DataBlockSize = SDIO_DataBlockSize_64b; - SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO; - SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; - SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable; - SDIO_DataConfig(&SDIO_DataInitStructure); - - /*!< Send ACMD13 SD_APP_STAUS with argument as card's RCA.*/ - SDIO_CmdInitStructure.SDIO_Argument = 0; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_APP_STAUS; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - errorstatus = CmdResp1Error(SD_CMD_SD_APP_STAUS); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - while (!(SDIO->STA &(SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))) - { - if (SDIO_GetFlagStatus(SDIO_FLAG_RXFIFOHF) != RESET) - { - for (count = 0; count < 8; count++) - { - *(psdstatus + count) = SDIO_ReadData(); - } - psdstatus += 8; - } - } - - if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT); - errorstatus = SD_DATA_TIMEOUT; - return(errorstatus); - } - else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL); - errorstatus = SD_DATA_CRC_FAIL; - return(errorstatus); - } - else if (SDIO_GetFlagStatus(SDIO_FLAG_RXOVERR) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_RXOVERR); - errorstatus = SD_RX_OVERRUN; - return(errorstatus); - } - else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_STBITERR); - errorstatus = SD_START_BIT_ERR; - return(errorstatus); - } - - count = SD_DATATIMEOUT; - while ((SDIO_GetFlagStatus(SDIO_FLAG_RXDAVL) != RESET) && (count > 0)) - { - *psdstatus = SDIO_ReadData(); - psdstatus++; - count--; - } - /*!< Clear all the static status flags*/ - SDIO_ClearFlag(SDIO_STATIC_FLAGS); - - return(errorstatus); -} - -/** - * @brief Allows to process all the interrupts that are high. - * @param None - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_ProcessIRQSrc(void) -{ - if (SDIO_GetITStatus(SDIO_IT_DATAEND) != RESET) - { - TransferError = SD_OK; - SDIO_ClearITPendingBit(SDIO_IT_DATAEND); - TransferEnd = 1; - } - else if (SDIO_GetITStatus(SDIO_IT_DCRCFAIL) != RESET) - { - SDIO_ClearITPendingBit(SDIO_IT_DCRCFAIL); - TransferError = SD_DATA_CRC_FAIL; - } - else if (SDIO_GetITStatus(SDIO_IT_DTIMEOUT) != RESET) - { - SDIO_ClearITPendingBit(SDIO_IT_DTIMEOUT); - TransferError = SD_DATA_TIMEOUT; - } - else if (SDIO_GetITStatus(SDIO_IT_RXOVERR) != RESET) - { - SDIO_ClearITPendingBit(SDIO_IT_RXOVERR); - TransferError = SD_RX_OVERRUN; - } - else if (SDIO_GetITStatus(SDIO_IT_TXUNDERR) != RESET) - { - SDIO_ClearITPendingBit(SDIO_IT_TXUNDERR); - TransferError = SD_TX_UNDERRUN; - } - else if (SDIO_GetITStatus(SDIO_IT_STBITERR) != RESET) - { - SDIO_ClearITPendingBit(SDIO_IT_STBITERR); - TransferError = SD_START_BIT_ERR; - } - - SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | - SDIO_IT_TXFIFOHE | SDIO_IT_RXFIFOHF | SDIO_IT_TXUNDERR | - SDIO_IT_RXOVERR | SDIO_IT_STBITERR, DISABLE); - return(TransferError); -} - -/** - * @brief This function waits until the SDIO DMA data transfer is finished. - * @param None. - * @retval None. - */ -void SD_ProcessDMAIRQ(void) -{ - if(DMA2->LISR & SD_SDIO_DMA_FLAG_TCIF) - { - DMAEndOfTransfer = 0x01; - DMA_ClearFlag(SD_SDIO_DMA_STREAM, SD_SDIO_DMA_FLAG_TCIF|SD_SDIO_DMA_FLAG_FEIF); - } -} - -/** - * @brief Checks for error conditions for CMD0. - * @param None - * @retval SD_Error: SD Card Error code. - */ -static SD_Error CmdError(void) -{ - SD_Error errorstatus = SD_OK; - uint32_t timeout; - - timeout = SDIO_CMD0TIMEOUT; /*!< 10000 */ - - while ((timeout > 0) && (SDIO_GetFlagStatus(SDIO_FLAG_CMDSENT) == RESET)) - { - timeout--; - } - - if (timeout == 0) - { - errorstatus = SD_CMD_RSP_TIMEOUT; - return(errorstatus); - } - - /*!< Clear all the static flags */ - SDIO_ClearFlag(SDIO_STATIC_FLAGS); - - return(errorstatus); -} - -/** - * @brief Checks for error conditions for R7 response. - * @param None - * @retval SD_Error: SD Card Error code. - */ -static SD_Error CmdResp7Error(void) -{ - SD_Error errorstatus = SD_OK; - uint32_t status; - uint32_t timeout = SDIO_CMD0TIMEOUT; - - status = SDIO->STA; - - while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) && (timeout > 0)) - { - timeout--; - status = SDIO->STA; - } - - if ((timeout == 0) || (status & SDIO_FLAG_CTIMEOUT)) - { - /*!< Card is not V2.0 complient or card does not support the set voltage range */ - errorstatus = SD_CMD_RSP_TIMEOUT; - SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT); - return(errorstatus); - } - - if (status & SDIO_FLAG_CMDREND) - { - /*!< Card is SD V2.0 compliant */ - errorstatus = SD_OK; - SDIO_ClearFlag(SDIO_FLAG_CMDREND); - return(errorstatus); - } - return(errorstatus); -} - -/** - * @brief Checks for error conditions for R1 response. - * @param cmd: The sent command index. - * @retval SD_Error: SD Card Error code. - */ -static SD_Error CmdResp1Error(uint8_t cmd) -{ - SD_Error errorstatus = SD_OK; - uint32_t status; - uint32_t response_r1; - - status = SDIO->STA; - - while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))) - { - status = SDIO->STA; - } - - if (status & SDIO_FLAG_CTIMEOUT) - { - errorstatus = SD_CMD_RSP_TIMEOUT; - SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT); - return(errorstatus); - } - else if (status & SDIO_FLAG_CCRCFAIL) - { - errorstatus = SD_CMD_CRC_FAIL; - SDIO_ClearFlag(SDIO_FLAG_CCRCFAIL); - return(errorstatus); - } - - /*!< Check response received is of desired command */ - if (SDIO_GetCommandResponse() != cmd) - { - errorstatus = SD_ILLEGAL_CMD; - return(errorstatus); - } - - /*!< Clear all the static flags */ - SDIO_ClearFlag(SDIO_STATIC_FLAGS); - - /*!< We have received response, retrieve it for analysis */ - response_r1 = SDIO_GetResponse(SDIO_RESP1); - - if ((response_r1 & SD_OCR_ERRORBITS) == SD_ALLZERO) - { - return(errorstatus); - } - - if (response_r1 & SD_OCR_ADDR_OUT_OF_RANGE) - { - return(SD_ADDR_OUT_OF_RANGE); - } - - if (response_r1 & SD_OCR_ADDR_MISALIGNED) - { - return(SD_ADDR_MISALIGNED); - } - - if (response_r1 & SD_OCR_BLOCK_LEN_ERR) - { - return(SD_BLOCK_LEN_ERR); - } - - if (response_r1 & SD_OCR_ERASE_SEQ_ERR) - { - return(SD_ERASE_SEQ_ERR); - } - - if (response_r1 & SD_OCR_BAD_ERASE_PARAM) - { - return(SD_BAD_ERASE_PARAM); - } - - if (response_r1 & SD_OCR_WRITE_PROT_VIOLATION) - { - return(SD_WRITE_PROT_VIOLATION); - } - - if (response_r1 & SD_OCR_LOCK_UNLOCK_FAILED) - { - return(SD_LOCK_UNLOCK_FAILED); - } - - if (response_r1 & SD_OCR_COM_CRC_FAILED) - { - return(SD_COM_CRC_FAILED); - } - - if (response_r1 & SD_OCR_ILLEGAL_CMD) - { - return(SD_ILLEGAL_CMD); - } - - if (response_r1 & SD_OCR_CARD_ECC_FAILED) - { - return(SD_CARD_ECC_FAILED); - } - - if (response_r1 & SD_OCR_CC_ERROR) - { - return(SD_CC_ERROR); - } - - if (response_r1 & SD_OCR_GENERAL_UNKNOWN_ERROR) - { - return(SD_GENERAL_UNKNOWN_ERROR); - } - - if (response_r1 & SD_OCR_STREAM_READ_UNDERRUN) - { - return(SD_STREAM_READ_UNDERRUN); - } - - if (response_r1 & SD_OCR_STREAM_WRITE_OVERRUN) - { - return(SD_STREAM_WRITE_OVERRUN); - } - - if (response_r1 & SD_OCR_CID_CSD_OVERWRIETE) - { - return(SD_CID_CSD_OVERWRITE); - } - - if (response_r1 & SD_OCR_WP_ERASE_SKIP) - { - return(SD_WP_ERASE_SKIP); - } - - if (response_r1 & SD_OCR_CARD_ECC_DISABLED) - { - return(SD_CARD_ECC_DISABLED); - } - - if (response_r1 & SD_OCR_ERASE_RESET) - { - return(SD_ERASE_RESET); - } - - if (response_r1 & SD_OCR_AKE_SEQ_ERROR) - { - return(SD_AKE_SEQ_ERROR); - } - return(errorstatus); -} - -/** - * @brief Checks for error conditions for R3 (OCR) response. - * @param None - * @retval SD_Error: SD Card Error code. - */ -static SD_Error CmdResp3Error(void) -{ - SD_Error errorstatus = SD_OK; - uint32_t status; - - status = SDIO->STA; - - while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))) - { - status = SDIO->STA; - } - - if (status & SDIO_FLAG_CTIMEOUT) - { - errorstatus = SD_CMD_RSP_TIMEOUT; - SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT); - return(errorstatus); - } - /*!< Clear all the static flags */ - SDIO_ClearFlag(SDIO_STATIC_FLAGS); - return(errorstatus); -} - -/** - * @brief Checks for error conditions for R2 (CID or CSD) response. - * @param None - * @retval SD_Error: SD Card Error code. - */ -static SD_Error CmdResp2Error(void) -{ - SD_Error errorstatus = SD_OK; - uint32_t status; - - status = SDIO->STA; - - while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CTIMEOUT | SDIO_FLAG_CMDREND))) - { - status = SDIO->STA; - } - - if (status & SDIO_FLAG_CTIMEOUT) - { - errorstatus = SD_CMD_RSP_TIMEOUT; - SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT); - return(errorstatus); - } - else if (status & SDIO_FLAG_CCRCFAIL) - { - errorstatus = SD_CMD_CRC_FAIL; - SDIO_ClearFlag(SDIO_FLAG_CCRCFAIL); - return(errorstatus); - } - - /*!< Clear all the static flags */ - SDIO_ClearFlag(SDIO_STATIC_FLAGS); - - return(errorstatus); -} - -/** - * @brief Checks for error conditions for R6 (RCA) response. - * @param cmd: The sent command index. - * @param prca: pointer to the variable that will contain the SD card relative - * address RCA. - * @retval SD_Error: SD Card Error code. - */ -static SD_Error CmdResp6Error(uint8_t cmd, uint16_t *prca) -{ - SD_Error errorstatus = SD_OK; - uint32_t status; - uint32_t response_r1; - - status = SDIO->STA; - - while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CTIMEOUT | SDIO_FLAG_CMDREND))) - { - status = SDIO->STA; - } - - if (status & SDIO_FLAG_CTIMEOUT) - { - errorstatus = SD_CMD_RSP_TIMEOUT; - SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT); - return(errorstatus); - } - else if (status & SDIO_FLAG_CCRCFAIL) - { - errorstatus = SD_CMD_CRC_FAIL; - SDIO_ClearFlag(SDIO_FLAG_CCRCFAIL); - return(errorstatus); - } - - /*!< Check response received is of desired command */ - if (SDIO_GetCommandResponse() != cmd) - { - errorstatus = SD_ILLEGAL_CMD; - return(errorstatus); - } - - /*!< Clear all the static flags */ - SDIO_ClearFlag(SDIO_STATIC_FLAGS); - - /*!< We have received response, retrieve it. */ - response_r1 = SDIO_GetResponse(SDIO_RESP1); - - if (SD_ALLZERO == (response_r1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED))) - { - *prca = (uint16_t) (response_r1 >> 16); - return(errorstatus); - } - - if (response_r1 & SD_R6_GENERAL_UNKNOWN_ERROR) - { - return(SD_GENERAL_UNKNOWN_ERROR); - } - - if (response_r1 & SD_R6_ILLEGAL_CMD) - { - return(SD_ILLEGAL_CMD); - } - - if (response_r1 & SD_R6_COM_CRC_FAILED) - { - return(SD_COM_CRC_FAILED); - } - - return(errorstatus); -} - -/** - * @brief Enables or disables the SDIO wide bus mode. - * @param NewState: new state of the SDIO wide bus mode. - * This parameter can be: ENABLE or DISABLE. - * @retval SD_Error: SD Card Error code. - */ -static SD_Error SDEnWideBus(FunctionalState NewState) -{ - SD_Error errorstatus = SD_OK; - - uint32_t scr[2] = {0, 0}; - - if (SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) - { - errorstatus = SD_LOCK_UNLOCK_FAILED; - return(errorstatus); - } - - /*!< Get SCR Register */ - errorstatus = FindSCR(RCA, scr); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - /*!< If wide bus operation to be enabled */ - if (NewState == ENABLE) - { - /*!< If requested card supports wide bus operation */ - if ((scr[1] & SD_WIDE_BUS_SUPPORT) != SD_ALLZERO) - { - /*!< Send CMD55 APP_CMD with argument as card's RCA.*/ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_APP_CMD); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - /*!< Send ACMD6 APP_CMD with argument as 2 for wide bus mode */ - SDIO_CmdInitStructure.SDIO_Argument = 0x2; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_APP_SD_SET_BUSWIDTH); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - return(errorstatus); - } - else - { - errorstatus = SD_REQUEST_NOT_APPLICABLE; - return(errorstatus); - } - } /*!< If wide bus operation to be disabled */ - else - { - /*!< If requested card supports 1 bit mode operation */ - if ((scr[1] & SD_SINGLE_BUS_SUPPORT) != SD_ALLZERO) - { - /*!< Send CMD55 APP_CMD with argument as card's RCA.*/ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - - errorstatus = CmdResp1Error(SD_CMD_APP_CMD); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - /*!< Send ACMD6 APP_CMD with argument as 2 for wide bus mode */ - SDIO_CmdInitStructure.SDIO_Argument = 0x00; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_APP_SD_SET_BUSWIDTH); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - return(errorstatus); - } - else - { - errorstatus = SD_REQUEST_NOT_APPLICABLE; - return(errorstatus); - } - } -} - -/** - * @brief Checks if the SD card is in programming state. - * @param pstatus: pointer to the variable that will contain the SD card state. - * @retval SD_Error: SD Card Error code. - */ -static SD_Error IsCardProgramming(uint8_t *pstatus) -{ - SD_Error errorstatus = SD_OK; - __IO uint32_t respR1 = 0, status = 0; - - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SEND_STATUS; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - status = SDIO->STA; - while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))) - { - status = SDIO->STA; - } - - if (status & SDIO_FLAG_CTIMEOUT) - { - errorstatus = SD_CMD_RSP_TIMEOUT; - SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT); - return(errorstatus); - } - else if (status & SDIO_FLAG_CCRCFAIL) - { - errorstatus = SD_CMD_CRC_FAIL; - SDIO_ClearFlag(SDIO_FLAG_CCRCFAIL); - return(errorstatus); - } - - status = (uint32_t)SDIO_GetCommandResponse(); - - /*!< Check response received is of desired command */ - if (status != SD_CMD_SEND_STATUS) - { - errorstatus = SD_ILLEGAL_CMD; - return(errorstatus); - } - - /*!< Clear all the static flags */ - SDIO_ClearFlag(SDIO_STATIC_FLAGS); - - - /*!< We have received response, retrieve it for analysis */ - respR1 = SDIO_GetResponse(SDIO_RESP1); - - /*!< Find out card status */ - *pstatus = (uint8_t) ((respR1 >> 9) & 0x0000000F); - - if ((respR1 & SD_OCR_ERRORBITS) == SD_ALLZERO) - { - return(errorstatus); - } - - if (respR1 & SD_OCR_ADDR_OUT_OF_RANGE) - { - return(SD_ADDR_OUT_OF_RANGE); - } - - if (respR1 & SD_OCR_ADDR_MISALIGNED) - { - return(SD_ADDR_MISALIGNED); - } - - if (respR1 & SD_OCR_BLOCK_LEN_ERR) - { - return(SD_BLOCK_LEN_ERR); - } - - if (respR1 & SD_OCR_ERASE_SEQ_ERR) - { - return(SD_ERASE_SEQ_ERR); - } - - if (respR1 & SD_OCR_BAD_ERASE_PARAM) - { - return(SD_BAD_ERASE_PARAM); - } - - if (respR1 & SD_OCR_WRITE_PROT_VIOLATION) - { - return(SD_WRITE_PROT_VIOLATION); - } - - if (respR1 & SD_OCR_LOCK_UNLOCK_FAILED) - { - return(SD_LOCK_UNLOCK_FAILED); - } - - if (respR1 & SD_OCR_COM_CRC_FAILED) - { - return(SD_COM_CRC_FAILED); - } - - if (respR1 & SD_OCR_ILLEGAL_CMD) - { - return(SD_ILLEGAL_CMD); - } - - if (respR1 & SD_OCR_CARD_ECC_FAILED) - { - return(SD_CARD_ECC_FAILED); - } - - if (respR1 & SD_OCR_CC_ERROR) - { - return(SD_CC_ERROR); - } - - if (respR1 & SD_OCR_GENERAL_UNKNOWN_ERROR) - { - return(SD_GENERAL_UNKNOWN_ERROR); - } - - if (respR1 & SD_OCR_STREAM_READ_UNDERRUN) - { - return(SD_STREAM_READ_UNDERRUN); - } - - if (respR1 & SD_OCR_STREAM_WRITE_OVERRUN) - { - return(SD_STREAM_WRITE_OVERRUN); - } - - if (respR1 & SD_OCR_CID_CSD_OVERWRIETE) - { - return(SD_CID_CSD_OVERWRITE); - } - - if (respR1 & SD_OCR_WP_ERASE_SKIP) - { - return(SD_WP_ERASE_SKIP); - } - - if (respR1 & SD_OCR_CARD_ECC_DISABLED) - { - return(SD_CARD_ECC_DISABLED); - } - - if (respR1 & SD_OCR_ERASE_RESET) - { - return(SD_ERASE_RESET); - } - - if (respR1 & SD_OCR_AKE_SEQ_ERROR) - { - return(SD_AKE_SEQ_ERROR); - } - - return(errorstatus); -} - -/** - * @brief Find the SD card SCR register value. - * @param rca: selected card address. - * @param pscr: pointer to the buffer that will contain the SCR value. - * @retval SD_Error: SD Card Error code. - */ -static SD_Error FindSCR(uint16_t rca, uint32_t *pscr) -{ - uint32_t index = 0; - SD_Error errorstatus = SD_OK; - uint32_t tempscr[2] = {0, 0}; - - /*!< Set Block Size To 8 Bytes */ - /*!< Send CMD55 APP_CMD with argument as card's RCA */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)8; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - /*!< Send CMD55 APP_CMD with argument as card's RCA */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_APP_CMD); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; - SDIO_DataInitStructure.SDIO_DataLength = 8; - SDIO_DataInitStructure.SDIO_DataBlockSize = SDIO_DataBlockSize_8b; - SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO; - SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; - SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable; - SDIO_DataConfig(&SDIO_DataInitStructure); - - - /*!< Send ACMD51 SD_APP_SEND_SCR with argument as 0 */ - SDIO_CmdInitStructure.SDIO_Argument = 0x0; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_APP_SEND_SCR; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_SD_APP_SEND_SCR); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - while (!(SDIO->STA & (SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))) - { - if (SDIO_GetFlagStatus(SDIO_FLAG_RXDAVL) != RESET) - { - *(tempscr + index) = SDIO_ReadData(); - index++; - } - } - - if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT); - errorstatus = SD_DATA_TIMEOUT; - return(errorstatus); - } - else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL); - errorstatus = SD_DATA_CRC_FAIL; - return(errorstatus); - } - else if (SDIO_GetFlagStatus(SDIO_FLAG_RXOVERR) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_RXOVERR); - errorstatus = SD_RX_OVERRUN; - return(errorstatus); - } - else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_STBITERR); - errorstatus = SD_START_BIT_ERR; - return(errorstatus); - } - - /*!< Clear all the static flags */ - SDIO_ClearFlag(SDIO_STATIC_FLAGS); - - *(pscr + 1) = ((tempscr[0] & SD_0TO7BITS) << 24) | ((tempscr[0] & SD_8TO15BITS) << 8) | ((tempscr[0] & SD_16TO23BITS) >> 8) | ((tempscr[0] & SD_24TO31BITS) >> 24); - - *(pscr) = ((tempscr[1] & SD_0TO7BITS) << 24) | ((tempscr[1] & SD_8TO15BITS) << 8) | ((tempscr[1] & SD_16TO23BITS) >> 8) | ((tempscr[1] & SD_24TO31BITS) >> 24); - - return(errorstatus); -} - -/** - * @brief Converts the number of bytes in power of two and returns the power. - * @param NumberOfBytes: number of bytes. - * @retval None - */ -uint8_t convert_from_bytes_to_power_of_two(uint16_t NumberOfBytes) -{ - uint8_t count = 0; - - while (NumberOfBytes != 1) - { - NumberOfBytes >>= 1; - count++; - } - return(count); -} - -/** -* @brief Switch mode High-Speed -* @note This function must be used after "Transfer State" -* @note This operation should be followed by the configuration -* of PLL to have SDIOCK clock between 67 and 75 MHz -* @param None -* @retval SD_Error: SD Card Error code. -*/ -SD_Error SD_HighSpeed (void) -{ - SD_Error errorstatus = SD_OK; - uint32_t scr[2] = {0, 0}; - uint32_t SD_SPEC = 0 ; - uint8_t hs[64] = {0} ; - uint32_t count = 0, *tempbuff = (uint32_t *)hs; - TransferError = SD_OK; - TransferEnd = 0; - StopCondition = 0; - - SDIO->DCTRL = 0x0; - - /*!< Get SCR Register */ - errorstatus = FindSCR(RCA, scr); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - /* Test the Version supported by the card*/ - SD_SPEC = (scr[1] & 0x01000000)||(scr[1] & 0x02000000); - - if (SD_SPEC != SD_ALLZERO) - { - /* Set Block Size for Card */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)64; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN); - if (errorstatus != SD_OK) - { - return(errorstatus); - } - SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; - SDIO_DataInitStructure.SDIO_DataLength = 64; - SDIO_DataInitStructure.SDIO_DataBlockSize = SDIO_DataBlockSize_64b ; - SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO; - SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; - SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable; - SDIO_DataConfig(&SDIO_DataInitStructure); - - /*!< Send CMD6 switch mode */ - SDIO_CmdInitStructure.SDIO_Argument = 0x80FFFF01; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_HS_SWITCH; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - errorstatus = CmdResp1Error(SD_CMD_HS_SWITCH); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - while (!(SDIO->STA &(SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))) - { - if (SDIO_GetFlagStatus(SDIO_FLAG_RXFIFOHF) != RESET) - { - for (count = 0; count < 8; count++) - { - *(tempbuff + count) = SDIO_ReadData(); - } - tempbuff += 8; - } - } - - if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT); - errorstatus = SD_DATA_TIMEOUT; - return(errorstatus); - } - else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL); - errorstatus = SD_DATA_CRC_FAIL; - return(errorstatus); - } - else if (SDIO_GetFlagStatus(SDIO_FLAG_RXOVERR) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_RXOVERR); - errorstatus = SD_RX_OVERRUN; - return(errorstatus); - } - else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_STBITERR); - errorstatus = SD_START_BIT_ERR; - return(errorstatus); - } - count = SD_DATATIMEOUT; - while ((SDIO_GetFlagStatus(SDIO_FLAG_RXDAVL) != RESET) && (count > 0)) - { - *tempbuff = SDIO_ReadData(); - tempbuff++; - count--; - } - - /*!< Clear all the static flags */ - SDIO_ClearFlag(SDIO_STATIC_FLAGS); - - /* Test if the switch mode HS is ok */ - if ((hs[13]& 0x2)==0x2) - { - errorstatus=SD_OK; - } - else - { - errorstatus=SD_UNSUPPORTED_FEATURE ; - } - } - return(errorstatus); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm324x7i_eval_sdio_sd.h b/stm/stmperiph/stm324x7i_eval_sdio_sd.h deleted file mode 100644 index 31214385c..000000000 --- a/stm/stmperiph/stm324x7i_eval_sdio_sd.h +++ /dev/null @@ -1,408 +0,0 @@ -/** - ****************************************************************************** - * @file stm324x7i_eval_sdio_sd.h - * @author MCD Application Team - * @version V1.0.0 - * @date 11-January-2013 - * @brief This file contains all the functions prototypes for the SD Card - * stm324x7i_eval_sdio_sd driver firmware library. - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM324x7I_EVAL_SDIO_SD_H -#define __STM324x7I_EVAL_SDIO_SD_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm324x7i_eval.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM324x7I_EVAL - * @{ - */ - -/** @addtogroup STM324x7I_EVAL_SDIO_SD - * @{ - */ - -/** @defgroup STM324x7I_EVAL_SDIO_SD_Exported_Types - * @{ - */ -typedef enum -{ -/** - * @brief SDIO specific error defines - */ - SD_CMD_CRC_FAIL = (1), /*!< Command response received (but CRC check failed) */ - SD_DATA_CRC_FAIL = (2), /*!< Data bock sent/received (CRC check Failed) */ - SD_CMD_RSP_TIMEOUT = (3), /*!< Command response timeout */ - SD_DATA_TIMEOUT = (4), /*!< Data time out */ - SD_TX_UNDERRUN = (5), /*!< Transmit FIFO under-run */ - SD_RX_OVERRUN = (6), /*!< Receive FIFO over-run */ - SD_START_BIT_ERR = (7), /*!< Start bit not detected on all data signals in widE bus mode */ - SD_CMD_OUT_OF_RANGE = (8), /*!< CMD's argument was out of range.*/ - SD_ADDR_MISALIGNED = (9), /*!< Misaligned address */ - SD_BLOCK_LEN_ERR = (10), /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */ - SD_ERASE_SEQ_ERR = (11), /*!< An error in the sequence of erase command occurs.*/ - SD_BAD_ERASE_PARAM = (12), /*!< An Invalid selection for erase groups */ - SD_WRITE_PROT_VIOLATION = (13), /*!< Attempt to program a write protect block */ - SD_LOCK_UNLOCK_FAILED = (14), /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */ - SD_COM_CRC_FAILED = (15), /*!< CRC check of the previous command failed */ - SD_ILLEGAL_CMD = (16), /*!< Command is not legal for the card state */ - SD_CARD_ECC_FAILED = (17), /*!< Card internal ECC was applied but failed to correct the data */ - SD_CC_ERROR = (18), /*!< Internal card controller error */ - SD_GENERAL_UNKNOWN_ERROR = (19), /*!< General or Unknown error */ - SD_STREAM_READ_UNDERRUN = (20), /*!< The card could not sustain data transfer in stream read operation. */ - SD_STREAM_WRITE_OVERRUN = (21), /*!< The card could not sustain data programming in stream mode */ - SD_CID_CSD_OVERWRITE = (22), /*!< CID/CSD overwrite error */ - SD_WP_ERASE_SKIP = (23), /*!< only partial address space was erased */ - SD_CARD_ECC_DISABLED = (24), /*!< Command has been executed without using internal ECC */ - SD_ERASE_RESET = (25), /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */ - SD_AKE_SEQ_ERROR = (26), /*!< Error in sequence of authentication. */ - SD_INVALID_VOLTRANGE = (27), - SD_ADDR_OUT_OF_RANGE = (28), - SD_SWITCH_ERROR = (29), - SD_SDIO_DISABLED = (30), - SD_SDIO_FUNCTION_BUSY = (31), - SD_SDIO_FUNCTION_FAILED = (32), - SD_SDIO_UNKNOWN_FUNCTION = (33), - -/** - * @brief Standard error defines - */ - SD_INTERNAL_ERROR, - SD_NOT_CONFIGURED, - SD_REQUEST_PENDING, - SD_REQUEST_NOT_APPLICABLE, - SD_INVALID_PARAMETER, - SD_UNSUPPORTED_FEATURE, - SD_UNSUPPORTED_HW, - SD_ERROR, - SD_OK = 0 -} SD_Error; - -/** - * @brief SDIO Transfer state - */ -typedef enum -{ - SD_TRANSFER_OK = 0, - SD_TRANSFER_BUSY = 1, - SD_TRANSFER_ERROR -} SDTransferState; - -/** - * @brief SD Card States - */ -typedef enum -{ - SD_CARD_READY = ((uint32_t)0x00000001), - SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002), - SD_CARD_STANDBY = ((uint32_t)0x00000003), - SD_CARD_TRANSFER = ((uint32_t)0x00000004), - SD_CARD_SENDING = ((uint32_t)0x00000005), - SD_CARD_RECEIVING = ((uint32_t)0x00000006), - SD_CARD_PROGRAMMING = ((uint32_t)0x00000007), - SD_CARD_DISCONNECTED = ((uint32_t)0x00000008), - SD_CARD_ERROR = ((uint32_t)0x000000FF) -}SDCardState; - - -/** - * @brief Card Specific Data: CSD Register - */ -typedef struct -{ - __IO uint8_t CSDStruct; /*!< CSD structure */ - __IO uint8_t SysSpecVersion; /*!< System specification version */ - __IO uint8_t Reserved1; /*!< Reserved */ - __IO uint8_t TAAC; /*!< Data read access-time 1 */ - __IO uint8_t NSAC; /*!< Data read access-time 2 in CLK cycles */ - __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */ - __IO uint16_t CardComdClasses; /*!< Card command classes */ - __IO uint8_t RdBlockLen; /*!< Max. read data block length */ - __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */ - __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */ - __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */ - __IO uint8_t DSRImpl; /*!< DSR implemented */ - __IO uint8_t Reserved2; /*!< Reserved */ - __IO uint32_t DeviceSize; /*!< Device Size */ - __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */ - __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */ - __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */ - __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */ - __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */ - __IO uint8_t EraseGrSize; /*!< Erase group size */ - __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */ - __IO uint8_t WrProtectGrSize; /*!< Write protect group size */ - __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */ - __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */ - __IO uint8_t WrSpeedFact; /*!< Write speed factor */ - __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */ - __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */ - __IO uint8_t Reserved3; /*!< Reserded */ - __IO uint8_t ContentProtectAppli; /*!< Content protection application */ - __IO uint8_t FileFormatGrouop; /*!< File format group */ - __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */ - __IO uint8_t PermWrProtect; /*!< Permanent write protection */ - __IO uint8_t TempWrProtect; /*!< Temporary write protection */ - __IO uint8_t FileFormat; /*!< File Format */ - __IO uint8_t ECC; /*!< ECC code */ - __IO uint8_t CSD_CRC; /*!< CSD CRC */ - __IO uint8_t Reserved4; /*!< always 1*/ -} SD_CSD; - -/** - * @brief Card Identification Data: CID Register - */ -typedef struct -{ - __IO uint8_t ManufacturerID; /*!< ManufacturerID */ - __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */ - __IO uint32_t ProdName1; /*!< Product Name part1 */ - __IO uint8_t ProdName2; /*!< Product Name part2*/ - __IO uint8_t ProdRev; /*!< Product Revision */ - __IO uint32_t ProdSN; /*!< Product Serial Number */ - __IO uint8_t Reserved1; /*!< Reserved1 */ - __IO uint16_t ManufactDate; /*!< Manufacturing Date */ - __IO uint8_t CID_CRC; /*!< CID CRC */ - __IO uint8_t Reserved2; /*!< always 1 */ -} SD_CID; - -/** - * @brief SD Card Status - */ -typedef struct -{ - __IO uint8_t DAT_BUS_WIDTH; - __IO uint8_t SECURED_MODE; - __IO uint16_t SD_CARD_TYPE; - __IO uint32_t SIZE_OF_PROTECTED_AREA; - __IO uint8_t SPEED_CLASS; - __IO uint8_t PERFORMANCE_MOVE; - __IO uint8_t AU_SIZE; - __IO uint16_t ERASE_SIZE; - __IO uint8_t ERASE_TIMEOUT; - __IO uint8_t ERASE_OFFSET; -} SD_CardStatus; - - -/** - * @brief SD Card information - */ -typedef struct -{ - SD_CSD SD_csd; - SD_CID SD_cid; - uint64_t CardCapacity; /*!< Card Capacity */ - uint32_t CardBlockSize; /*!< Card Block Size */ - uint16_t RCA; - uint8_t CardType; -} SD_CardInfo; - -/** - * @} - */ - -/** @defgroup STM324x7I_EVAL_SDIO_SD_Exported_Constants - * @{ - */ - -/** - * @brief SDIO Commands Index - */ -#define SD_CMD_GO_IDLE_STATE ((uint8_t)0) -#define SD_CMD_SEND_OP_COND ((uint8_t)1) -#define SD_CMD_ALL_SEND_CID ((uint8_t)2) -#define SD_CMD_SET_REL_ADDR ((uint8_t)3) /*!< SDIO_SEND_REL_ADDR for SD Card */ -#define SD_CMD_SET_DSR ((uint8_t)4) -#define SD_CMD_SDIO_SEN_OP_COND ((uint8_t)5) -#define SD_CMD_HS_SWITCH ((uint8_t)6) -#define SD_CMD_SEL_DESEL_CARD ((uint8_t)7) -#define SD_CMD_HS_SEND_EXT_CSD ((uint8_t)8) -#define SD_CMD_SEND_CSD ((uint8_t)9) -#define SD_CMD_SEND_CID ((uint8_t)10) -#define SD_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /*!< SD Card doesn't support it */ -#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12) -#define SD_CMD_SEND_STATUS ((uint8_t)13) -#define SD_CMD_HS_BUSTEST_READ ((uint8_t)14) -#define SD_CMD_GO_INACTIVE_STATE ((uint8_t)15) -#define SD_CMD_SET_BLOCKLEN ((uint8_t)16) -#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17) -#define SD_CMD_READ_MULT_BLOCK ((uint8_t)18) -#define SD_CMD_HS_BUSTEST_WRITE ((uint8_t)19) -#define SD_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /*!< SD Card doesn't support it */ -#define SD_CMD_SET_BLOCK_COUNT ((uint8_t)23) /*!< SD Card doesn't support it */ -#define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) -#define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25) -#define SD_CMD_PROG_CID ((uint8_t)26) /*!< reserved for manufacturers */ -#define SD_CMD_PROG_CSD ((uint8_t)27) -#define SD_CMD_SET_WRITE_PROT ((uint8_t)28) -#define SD_CMD_CLR_WRITE_PROT ((uint8_t)29) -#define SD_CMD_SEND_WRITE_PROT ((uint8_t)30) -#define SD_CMD_SD_ERASE_GRP_START ((uint8_t)32) /*!< To set the address of the first write - block to be erased. (For SD card only) */ -#define SD_CMD_SD_ERASE_GRP_END ((uint8_t)33) /*!< To set the address of the last write block of the - continuous range to be erased. (For SD card only) */ -#define SD_CMD_ERASE_GRP_START ((uint8_t)35) /*!< To set the address of the first write block to be erased. - (For MMC card only spec 3.31) */ - -#define SD_CMD_ERASE_GRP_END ((uint8_t)36) /*!< To set the address of the last write block of the - continuous range to be erased. (For MMC card only spec 3.31) */ - -#define SD_CMD_ERASE ((uint8_t)38) -#define SD_CMD_FAST_IO ((uint8_t)39) /*!< SD Card doesn't support it */ -#define SD_CMD_GO_IRQ_STATE ((uint8_t)40) /*!< SD Card doesn't support it */ -#define SD_CMD_LOCK_UNLOCK ((uint8_t)42) -#define SD_CMD_APP_CMD ((uint8_t)55) -#define SD_CMD_GEN_CMD ((uint8_t)56) -#define SD_CMD_NO_CMD ((uint8_t)64) - -/** - * @brief Following commands are SD Card Specific commands. - * SDIO_APP_CMD should be sent before sending these commands. - */ -#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< For SD Card only */ -#define SD_CMD_SD_APP_STAUS ((uint8_t)13) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< For SD Card only */ -#define SD_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51) /*!< For SD Card only */ -#define SD_CMD_SDIO_RW_DIRECT ((uint8_t)52) /*!< For SD I/O Card only */ -#define SD_CMD_SDIO_RW_EXTENDED ((uint8_t)53) /*!< For SD I/O Card only */ - -/** - * @brief Following commands are SD Card Specific security commands. - * SDIO_APP_CMD should be sent before sending these commands. - */ -#define SD_CMD_SD_APP_GET_MKB ((uint8_t)43) /*!< For SD Card only */ -#define SD_CMD_SD_APP_GET_MID ((uint8_t)44) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45) /*!< For SD Card only */ -#define SD_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47) /*!< For SD Card only */ -#define SD_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SECURE_ERASE ((uint8_t)38) /*!< For SD Card only */ -#define SD_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48) /*!< For SD Card only */ - -/* Uncomment the following line to select the SDIO Data transfer mode */ -#if !defined (SD_DMA_MODE) && !defined (SD_POLLING_MODE) -/*#define SD_DMA_MODE ((uint32_t)0x00000000)*/ -#define SD_POLLING_MODE ((uint32_t)0x00000002) -#endif - -/** - * @brief SD detection on its memory slot - */ -#define SD_PRESENT ((uint8_t)0x01) -#define SD_NOT_PRESENT ((uint8_t)0x00) - -/** - * @brief Supported SD Memory Cards - */ -#define SDIO_STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000) -#define SDIO_STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001) -#define SDIO_HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002) -#define SDIO_MULTIMEDIA_CARD ((uint32_t)0x00000003) -#define SDIO_SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004) -#define SDIO_HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005) -#define SDIO_SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006) -#define SDIO_HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007) - -/** - * @} - */ - -/** @defgroup STM324x7I_EVAL_SDIO_SD_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup STM324x7I_EVAL_SDIO_SD_Exported_Functions - * @{ - */ -void SD_DeInit(void); -SD_Error SD_Init(void); -SDTransferState SD_GetStatus(void); -SDCardState SD_GetState(void); -uint8_t SD_Detect(void); -SD_Error SD_PowerON(void); -SD_Error SD_PowerOFF(void); -SD_Error SD_InitializeCards(void); -SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo); -SD_Error SD_GetCardStatus(SD_CardStatus *cardstatus); -SD_Error SD_EnableWideBusOperation(uint32_t WideMode); -SD_Error SD_SelectDeselect(uint64_t addr); -SD_Error SD_ReadBlock(uint8_t *readbuff, uint64_t ReadAddr, uint16_t BlockSize); -SD_Error SD_ReadMultiBlocks(uint8_t *readbuff, uint64_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks); -SD_Error SD_WriteBlock(uint8_t *writebuff, uint64_t WriteAddr, uint16_t BlockSize); -SD_Error SD_WriteMultiBlocks(uint8_t *writebuff, uint64_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks); -SDTransferState SD_GetTransferState(void); -SD_Error SD_StopTransfer(void); -SD_Error SD_Erase(uint64_t startaddr, uint64_t endaddr); -SD_Error SD_SendStatus(uint32_t *pcardstatus); -SD_Error SD_SendSDStatus(uint32_t *psdstatus); -SD_Error SD_ProcessIRQSrc(void); -void SD_ProcessDMAIRQ(void); -SD_Error SD_WaitReadOperation(void); -SD_Error SD_WaitWriteOperation(void); -SD_Error SD_HighSpeed(void); -#ifdef __cplusplus -} -#endif - -#endif /* __STM324x7I_EVAL_SDIO_SD_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm32f4xx.h b/stm/stmperiph/stm32f4xx.h deleted file mode 100644 index 22b47f6b2..000000000 --- a/stm/stmperiph/stm32f4xx.h +++ /dev/null @@ -1,9156 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx.h - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File. - * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32F4xx devices. - * - * The file is the unique include file that the application programmer - * is using in the C source code, usually in main.c. This file contains: - * - Configuration section that allows to select: - * - The device used in the target application - * - To use or not the peripheral’s drivers in application code(i.e. - * code will be based on direct access to peripheral’s registers - * rather than drivers API), this option is controlled by - * "#define USE_STDPERIPH_DRIVER" - * - To change few application-specific parameters such as the HSE - * crystal frequency - * - Data structures and the address mapping for all peripherals - * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f4xx - * @{ - */ - -#ifndef __STM32F4xx_H -#define __STM32F4xx_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -// dpgeorge: we include mpconfigport.h here because it contains the settings for the STM -#include "mpconfigport.h" - -/** @addtogroup Library_configuration_section - * @{ - */ - -/* Uncomment the line below according to the target STM32 device used in your - application - */ - -#if !defined (STM32F40_41xxx) && !defined (STM32F427_437xx) && !defined (STM32F429_439xx) && !defined (STM32F401xx) - /* #define STM32F40_41xxx */ /*!< STM32F405RG, STM32F405VG, STM32F405ZG, STM32F415RG, STM32F415VG, STM32F415ZG, - STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG, STM32F407IE, - STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */ - - /* #define STM32F427_437xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG, STM32F427II, - STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG, STM32F437II Devices */ - - /* #define STM32F429_439xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, - STM32F429NG, STM32F439NI, STM32F429IG, STM32F429II, STM32F439VG, STM32F439VI, - STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, STM32F439NI, - STM32F439IG and STM32F439II Devices */ - - /* #define STM32F401xx */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB, STM32F401VC - STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CExx, STM32F401RE, STM32F401VE Devices */ - -#endif - -/* Old STM32F40XX definition, maintained for legacy purpose */ -#ifdef STM32F40XX - #define STM32F40_41xxx -#endif /* STM32F40XX */ - -/* Old STM32F427X definition, maintained for legacy purpose */ -#ifdef STM32F427X - #define STM32F427_437xx -#endif /* STM32F427X */ - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ - -#if !defined (STM32F40_41xxx) && !defined (STM32F427_437xx) && !defined (STM32F429_439xx) && !defined (STM32F401xx) - #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)" -#endif - -#if !defined (USE_STDPERIPH_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - /*#define USE_STDPERIPH_DRIVER */ -#endif /* USE_STDPERIPH_DRIVER */ - -/** - * @brief In the following line adjust the value of External High Speed oscillator (HSE) - used in your application - - Tip: To avoid modifying this file each time you need to use different HSE, you - can define the HSE value in your toolchain compiler preprocessor. - */ - -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ - -#endif /* HSE_VALUE */ - -/** - * @brief In the following line adjust the External High Speed oscillator (HSE) Startup - Timeout value - */ -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint16_t)0x05000) /*!< Time out for HSE start up */ -#endif /* HSE_STARTUP_TIMEOUT */ - -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief STM32F4XX Standard Peripherals Library version number V1.3.0 - */ -#define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ -#define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __STM32F4XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\ - |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\ - |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\ - |(__STM32F4XX_STDPERIPH_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ -#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ - -/** - * @brief STM32F4XX Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ -typedef enum IRQn -{ -/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ -/****** STM32 specific Interrupt Numbers **********************************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ - RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ - DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ - DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ - DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ - DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ - DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ - DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ - ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ - -#if defined (STM32F40_41xxx) - CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ - CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ - TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ - TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ - TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ - FSMC_IRQn = 48, /*!< FSMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ - TIM7_IRQn = 55, /*!< TIM7 global interrupt */ - DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ - DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ - DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ - DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ - DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ - ETH_IRQn = 61, /*!< Ethernet global Interrupt */ - ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ - OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ - DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ - DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ - DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ - USART6_IRQn = 71, /*!< USART6 global interrupt */ - I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ - I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ - OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ - OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ - OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ - OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ - DCMI_IRQn = 78, /*!< DCMI global interrupt */ - CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ - HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ - FPU_IRQn = 81 /*!< FPU global interrupt */ -#endif /* STM32F40_41xxx */ - -#if defined (STM32F427_437xx) - CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ - CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ - TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ - TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ - TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ - FMC_IRQn = 48, /*!< FMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ - TIM7_IRQn = 55, /*!< TIM7 global interrupt */ - DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ - DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ - DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ - DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ - DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ - ETH_IRQn = 61, /*!< Ethernet global Interrupt */ - ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ - OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ - DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ - DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ - DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ - USART6_IRQn = 71, /*!< USART6 global interrupt */ - I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ - I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ - OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ - OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ - OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ - OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ - DCMI_IRQn = 78, /*!< DCMI global interrupt */ - CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ - HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ - FPU_IRQn = 81, /*!< FPU global interrupt */ - UART7_IRQn = 82, /*!< UART7 global interrupt */ - UART8_IRQn = 83, /*!< UART8 global interrupt */ - SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ - SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ - SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ - SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ - DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */ -#endif /* STM32F427_437xx */ - -#if defined (STM32F429_439xx) - CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ - CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ - TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ - TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ - TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ - FMC_IRQn = 48, /*!< FMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ - TIM7_IRQn = 55, /*!< TIM7 global interrupt */ - DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ - DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ - DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ - DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ - DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ - ETH_IRQn = 61, /*!< Ethernet global Interrupt */ - ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ - OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ - DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ - DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ - DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ - USART6_IRQn = 71, /*!< USART6 global interrupt */ - I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ - I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ - OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ - OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ - OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ - OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ - DCMI_IRQn = 78, /*!< DCMI global interrupt */ - CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ - HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ - FPU_IRQn = 81, /*!< FPU global interrupt */ - UART7_IRQn = 82, /*!< UART7 global interrupt */ - UART8_IRQn = 83, /*!< UART8 global interrupt */ - SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ - SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ - SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ - SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ - LTDC_IRQn = 88, /*!< LTDC global Interrupt */ - LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ - DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */ -#endif /* STM32F429_439xx */ - -#if defined (STM32F401xx) - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ - DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ - DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ - DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ - DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ - DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ - OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ - DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ - DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ - DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ - USART6_IRQn = 71, /*!< USART6 global interrupt */ - I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ - I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ - FPU_IRQn = 81, /*!< FPU global interrupt */ - SPI4_IRQn = 84 /*!< SPI4 global Interrupt */ -#endif /* STM32F401xx */ - -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ -#include "system_stm32f4xx.h" -#include - -/** @addtogroup Exported_types - * @{ - */ -/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ -typedef int32_t s32; -typedef int16_t s16; -typedef int8_t s8; - -typedef const int32_t sc32; /*!< Read Only */ -typedef const int16_t sc16; /*!< Read Only */ -typedef const int8_t sc8; /*!< Read Only */ - -typedef __IO int32_t vs32; -typedef __IO int16_t vs16; -typedef __IO int8_t vs8; - -typedef __I int32_t vsc32; /*!< Read Only */ -typedef __I int16_t vsc16; /*!< Read Only */ -typedef __I int8_t vsc8; /*!< Read Only */ - -typedef uint32_t u32; -typedef uint16_t u16; -typedef uint8_t u8; - -typedef const uint32_t uc32; /*!< Read Only */ -typedef const uint16_t uc16; /*!< Read Only */ -typedef const uint8_t uc8; /*!< Read Only */ - -typedef __IO uint32_t vu32; -typedef __IO uint16_t vu16; -typedef __IO uint8_t vu8; - -typedef __I uint32_t vuc32; /*!< Read Only */ -typedef __I uint16_t vuc16; /*!< Read Only */ -typedef __I uint8_t vuc8; /*!< Read Only */ - -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; - -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; - -/** - * @} - */ - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ - __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ - __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ - __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ - __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ - __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ - __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ - __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ - __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ - __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ - __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ - __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ - __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ - __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ - __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ - __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ - __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ - __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ - __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual - AND triple modes, Address offset: ADC1 base address + 0x308 */ -} ADC_Common_TypeDef; - - -/** - * @brief Controller Area Network TxMailBox - */ - -typedef struct -{ - __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ - __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ - __IO uint32_t TDLR; /*!< CAN mailbox data low register */ - __IO uint32_t TDHR; /*!< CAN mailbox data high register */ -} CAN_TxMailBox_TypeDef; - -/** - * @brief Controller Area Network FIFOMailBox - */ - -typedef struct -{ - __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ - __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ - __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ - __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ -} CAN_FIFOMailBox_TypeDef; - -/** - * @brief Controller Area Network FilterRegister - */ - -typedef struct -{ - __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ - __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ -} CAN_FilterRegister_TypeDef; - -/** - * @brief Controller Area Network - */ - -typedef struct -{ - __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ - __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ - __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ - __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ - __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ - __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ - __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ - __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ - uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ - CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ - uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ - __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ - __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ - uint32_t RESERVED2; /*!< Reserved, 0x208 */ - __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ - uint32_t RESERVED3; /*!< Reserved, 0x210 */ - __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ - uint32_t RESERVED4; /*!< Reserved, 0x218 */ - __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ - uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ - CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ -} CAN_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - uint8_t RESERVED0; /*!< Reserved, 0x05 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DCMI - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ - __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ - __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ - __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ - __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ - __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ - __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ - __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ - __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ - __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ - __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ -} DCMI_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DMA stream x configuration register */ - __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ - __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ -} DMA_Stream_TypeDef; - -typedef struct -{ - __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ - __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ - __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ - __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ -} DMA_TypeDef; - -/** - * @brief DMA2D Controller - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ - __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ - __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ - __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ - __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ - __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ - __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ - __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ - __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ - __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ - __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ - __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ - __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ - __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ - __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ - __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ - __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ - __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ - __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ - __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ - uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ - __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ - __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ -} DMA2D_TypeDef; - -/** - * @brief Ethernet MAC - */ - -typedef struct -{ - __IO uint32_t MACCR; - __IO uint32_t MACFFR; - __IO uint32_t MACHTHR; - __IO uint32_t MACHTLR; - __IO uint32_t MACMIIAR; - __IO uint32_t MACMIIDR; - __IO uint32_t MACFCR; - __IO uint32_t MACVLANTR; /* 8 */ - uint32_t RESERVED0[2]; - __IO uint32_t MACRWUFFR; /* 11 */ - __IO uint32_t MACPMTCSR; - uint32_t RESERVED1[2]; - __IO uint32_t MACSR; /* 15 */ - __IO uint32_t MACIMR; - __IO uint32_t MACA0HR; - __IO uint32_t MACA0LR; - __IO uint32_t MACA1HR; - __IO uint32_t MACA1LR; - __IO uint32_t MACA2HR; - __IO uint32_t MACA2LR; - __IO uint32_t MACA3HR; - __IO uint32_t MACA3LR; /* 24 */ - uint32_t RESERVED2[40]; - __IO uint32_t MMCCR; /* 65 */ - __IO uint32_t MMCRIR; - __IO uint32_t MMCTIR; - __IO uint32_t MMCRIMR; - __IO uint32_t MMCTIMR; /* 69 */ - uint32_t RESERVED3[14]; - __IO uint32_t MMCTGFSCCR; /* 84 */ - __IO uint32_t MMCTGFMSCCR; - uint32_t RESERVED4[5]; - __IO uint32_t MMCTGFCR; - uint32_t RESERVED5[10]; - __IO uint32_t MMCRFCECR; - __IO uint32_t MMCRFAECR; - uint32_t RESERVED6[10]; - __IO uint32_t MMCRGUFCR; - uint32_t RESERVED7[334]; - __IO uint32_t PTPTSCR; - __IO uint32_t PTPSSIR; - __IO uint32_t PTPTSHR; - __IO uint32_t PTPTSLR; - __IO uint32_t PTPTSHUR; - __IO uint32_t PTPTSLUR; - __IO uint32_t PTPTSAR; - __IO uint32_t PTPTTHR; - __IO uint32_t PTPTTLR; - __IO uint32_t RESERVED8; - __IO uint32_t PTPTSSR; - uint32_t RESERVED9[565]; - __IO uint32_t DMABMR; - __IO uint32_t DMATPDR; - __IO uint32_t DMARPDR; - __IO uint32_t DMARDLAR; - __IO uint32_t DMATDLAR; - __IO uint32_t DMASR; - __IO uint32_t DMAOMR; - __IO uint32_t DMAIER; - __IO uint32_t DMAMFBOCR; - __IO uint32_t DMARSWTR; - uint32_t RESERVED10[8]; - __IO uint32_t DMACHTDR; - __IO uint32_t DMACHRDR; - __IO uint32_t DMACHTBAR; - __IO uint32_t DMACHRBAR; -} ETH_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ - __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ - __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ - __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ - __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ - __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ -} EXTI_TypeDef; - -/** - * @brief FLASH Registers - */ - -typedef struct -{ - __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ - __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ - __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ - __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ - __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ - __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */ -} FLASH_TypeDef; - -#if defined (STM32F40_41xxx) -/** - * @brief Flexible Static Memory Controller - */ - -typedef struct -{ - __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ -} FSMC_Bank1_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank1E - */ - -typedef struct -{ - __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ -} FSMC_Bank1E_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank2 - */ - -typedef struct -{ - __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ - __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ - __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ - __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ - uint32_t RESERVED0; /*!< Reserved, 0x70 */ - __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ -} FSMC_Bank2_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank3 - */ - -typedef struct -{ - __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ - __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ - __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ - __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ - uint32_t RESERVED0; /*!< Reserved, 0x90 */ - __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ -} FSMC_Bank3_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank4 - */ - -typedef struct -{ - __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ - __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ - __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ - __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ - __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ -} FSMC_Bank4_TypeDef; -#endif /* STM32F40_41xxx */ - -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) -/** - * @brief Flexible Memory Controller - */ - -typedef struct -{ - __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ -} FMC_Bank1_TypeDef; - -/** - * @brief Flexible Memory Controller Bank1E - */ - -typedef struct -{ - __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ -} FMC_Bank1E_TypeDef; - -/** - * @brief Flexible Memory Controller Bank2 - */ - -typedef struct -{ - __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ - __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ - __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ - __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ - uint32_t RESERVED0; /*!< Reserved, 0x70 */ - __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ -} FMC_Bank2_TypeDef; - -/** - * @brief Flexible Memory Controller Bank3 - */ - -typedef struct -{ - __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ - __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ - __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ - __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ - uint32_t RESERVED0; /*!< Reserved, 0x90 */ - __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ -} FMC_Bank3_TypeDef; - -/** - * @brief Flexible Memory Controller Bank4 - */ - -typedef struct -{ - __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ - __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ - __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ - __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ - __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ -} FMC_Bank4_TypeDef; - -/** - * @brief Flexible Memory Controller Bank5_6 - */ - -typedef struct -{ - __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ - __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ - __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ - __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ - __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ -} FMC_Bank5_6_TypeDef; -#endif /* STM32F427_437xx || STM32F429_439xx */ - -/** - * @brief General Purpose I/O - */ - -typedef struct -{ - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ - __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ -} GPIO_TypeDef; - -/** - * @brief System configuration controller - */ - -typedef struct -{ - __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ - __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ - __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ - uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ - __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ -} SYSCFG_TypeDef; - -/** - * @brief Inter-integrated Circuit Interface - */ - -typedef struct -{ - __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ - __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ - uint16_t RESERVED7; /*!< Reserved, 0x1E */ - __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ - uint16_t RESERVED8; /*!< Reserved, 0x22 */ - __IO uint16_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */ - uint16_t RESERVED9; /*!< Reserved, 0x26 */ -} I2C_TypeDef; - -/** - * @brief Independent WATCHDOG - */ - -typedef struct -{ - __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ - __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ - __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ -} IWDG_TypeDef; - -/** - * @brief LCD-TFT Display Controller - */ - -typedef struct -{ - uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ - __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ - __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ - __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ - __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ - __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ - uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ - __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ - uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ - __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ - uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ - __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ - __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ - __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ - __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ - __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ - __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ -} LTDC_TypeDef; - -/** - * @brief LCD-TFT Display layer x Controller - */ - -typedef struct -{ - __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ - __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ - __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ - __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ - __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ - __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ - __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ - __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ - uint32_t RESERVED0[2]; /*!< Reserved */ - __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ - __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ - __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ - uint32_t RESERVED1[3]; /*!< Reserved */ - __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ - -} LTDC_Layer_TypeDef; - -/** - * @brief Power Control - */ - -typedef struct -{ - __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ - __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ -} PWR_TypeDef; - -/** - * @brief Reset and Clock Control - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ - __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ - __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ - __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ - __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ - __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ - __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ - uint32_t RESERVED0; /*!< Reserved, 0x1C */ - __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ - __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ - uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ - __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ - __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ - __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ - uint32_t RESERVED2; /*!< Reserved, 0x3C */ - __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ - __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ - uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ - __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ - __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ - __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ - uint32_t RESERVED4; /*!< Reserved, 0x5C */ - __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ - __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ - uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ - __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ - __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ - uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ - __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ - __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ - __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */ - __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */ - -} RCC_TypeDef; - -/** - * @brief Real-Time Clock - */ - -typedef struct -{ - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ - __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ - __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */ - uint32_t RESERVED7; /*!< Reserved, 0x4C */ - __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ - __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ - __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ - __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ - __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ - __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ - __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ - __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ - __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ - __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ - __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ - __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ - __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ - __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ - __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ - __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ - __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ - __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ - __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ - __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ -} RTC_TypeDef; - - -/** - * @brief Serial Audio Interface - */ - -typedef struct -{ - __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ -} SAI_TypeDef; - -typedef struct -{ - __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ - __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ - __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ - __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ - __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ - __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ - __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ -} SAI_Block_TypeDef; - -/** - * @brief SD host Interface - */ - -typedef struct -{ - __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ - __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ - __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ - __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ - __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ - __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ - __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ - __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ - __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ - __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ - __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ - __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ - __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ - __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ - __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ - __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ - uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ - __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ - uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ - __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ -} SDIO_TypeDef; - -/** - * @brief Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ - __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ - uint16_t RESERVED7; /*!< Reserved, 0x1E */ - __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ - uint16_t RESERVED8; /*!< Reserved, 0x22 */ -} SPI_TypeDef; - -/** - * @brief TIM - */ - -typedef struct -{ - __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ - __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ - uint16_t RESERVED7; /*!< Reserved, 0x1E */ - __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ - uint16_t RESERVED8; /*!< Reserved, 0x22 */ - __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - uint16_t RESERVED9; /*!< Reserved, 0x2A */ - __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - uint16_t RESERVED10; /*!< Reserved, 0x32 */ - __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ - __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ - __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ - __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ - __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - uint16_t RESERVED11; /*!< Reserved, 0x46 */ - __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - uint16_t RESERVED12; /*!< Reserved, 0x4A */ - __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - uint16_t RESERVED13; /*!< Reserved, 0x4E */ - __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */ - uint16_t RESERVED14; /*!< Reserved, 0x52 */ -} TIM_TypeDef; - -/** - * @brief Universal Synchronous Asynchronous Receiver Transmitter - */ - -typedef struct -{ - __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ -} USART_TypeDef; - -/** - * @brief Window WATCHDOG - */ - -typedef struct -{ - __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ - __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ -} WWDG_TypeDef; - -/** - * @brief Crypto Processor - */ - -typedef struct -{ - __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */ - __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ - __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ - __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ - __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ - __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ - __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ - __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ - __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ - __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ - __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ - __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ - __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ - __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ - __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ - __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ - __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ - __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ - __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */ - __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */ - __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */ - __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */ - __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */ - __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */ - __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */ - __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */ - __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */ - __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */ - __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */ - __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */ - __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */ - __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */ - __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */ - __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */ -} CRYP_TypeDef; - -/** - * @brief HASH - */ - -typedef struct -{ - __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ - __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ - __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ - __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ - __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ - __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ - uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ - __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ -} HASH_TypeDef; - -/** - * @brief HASH_DIGEST - */ - -typedef struct -{ - __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ -} HASH_DIGEST_TypeDef; - -/** - * @brief RNG - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ -} RNG_TypeDef; - -/** - * @} - */ - -/** @addtogroup Peripheral_memory_map - * @{ - */ -#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */ -#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */ -#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */ -#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */ -#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ -#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */ - -#if defined (STM32F40_41xxx) -#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ -#endif /* STM32F40_41xxx */ - -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) -#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */ -#endif /* STM32F427_437xx || STM32F429_439xx */ - -#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */ -#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */ -#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */ -#define SRAM3_BB_BASE ((uint32_t)0x22400000) /*!< SRAM3(64 KB) base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ -#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */ - -/* Legacy defines */ -#define SRAM_BASE SRAM1_BASE -#define SRAM_BB_BASE SRAM1_BB_BASE - - -/*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) -#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) - -/*!< APB1 peripherals */ -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) -#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) -#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) -#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) -#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) -#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) -#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) -#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400) -#define UART7_BASE (APB1PERIPH_BASE + 0x7800) -#define UART8_BASE (APB1PERIPH_BASE + 0x7C00) - -/*!< APB2 peripherals */ -#define TIM1_BASE (APB2PERIPH_BASE + 0x0000) -#define TIM8_BASE (APB2PERIPH_BASE + 0x0400) -#define USART1_BASE (APB2PERIPH_BASE + 0x1000) -#define USART6_BASE (APB2PERIPH_BASE + 0x1400) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2000) -#define ADC2_BASE (APB2PERIPH_BASE + 0x2100) -#define ADC3_BASE (APB2PERIPH_BASE + 0x2200) -#define ADC_BASE (APB2PERIPH_BASE + 0x2300) -#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) -#define SPI4_BASE (APB2PERIPH_BASE + 0x3400) -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) -#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) -#define TIM9_BASE (APB2PERIPH_BASE + 0x4000) -#define TIM10_BASE (APB2PERIPH_BASE + 0x4400) -#define TIM11_BASE (APB2PERIPH_BASE + 0x4800) -#define SPI5_BASE (APB2PERIPH_BASE + 0x5000) -#define SPI6_BASE (APB2PERIPH_BASE + 0x5400) -#define SAI1_BASE (APB2PERIPH_BASE + 0x5800) -#define SAI1_Block_A_BASE (SAI1_BASE + 0x004) -#define SAI1_Block_B_BASE (SAI1_BASE + 0x024) -#define LTDC_BASE (APB2PERIPH_BASE + 0x6800) -#define LTDC_Layer1_BASE (LTDC_BASE + 0x84) -#define LTDC_Layer2_BASE (LTDC_BASE + 0x104) - -/*!< AHB1 peripherals */ -#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) -#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) -#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) -#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) -#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) -#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) -#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) -#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) -#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) -#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400) -#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800) -#define CRC_BASE (AHB1PERIPH_BASE + 0x3000) -#define RCC_BASE (AHB1PERIPH_BASE + 0x3800) -#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) -#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) -#define DMA1_Stream0_BASE (DMA1_BASE + 0x010) -#define DMA1_Stream1_BASE (DMA1_BASE + 0x028) -#define DMA1_Stream2_BASE (DMA1_BASE + 0x040) -#define DMA1_Stream3_BASE (DMA1_BASE + 0x058) -#define DMA1_Stream4_BASE (DMA1_BASE + 0x070) -#define DMA1_Stream5_BASE (DMA1_BASE + 0x088) -#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) -#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) -#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) -#define DMA2_Stream0_BASE (DMA2_BASE + 0x010) -#define DMA2_Stream1_BASE (DMA2_BASE + 0x028) -#define DMA2_Stream2_BASE (DMA2_BASE + 0x040) -#define DMA2_Stream3_BASE (DMA2_BASE + 0x058) -#define DMA2_Stream4_BASE (DMA2_BASE + 0x070) -#define DMA2_Stream5_BASE (DMA2_BASE + 0x088) -#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) -#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) -#define ETH_BASE (AHB1PERIPH_BASE + 0x8000) -#define ETH_MAC_BASE (ETH_BASE) -#define ETH_MMC_BASE (ETH_BASE + 0x0100) -#define ETH_PTP_BASE (ETH_BASE + 0x0700) -#define ETH_DMA_BASE (ETH_BASE + 0x1000) -#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000) - -/*!< AHB2 peripherals */ -#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) -#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000) -#define HASH_BASE (AHB2PERIPH_BASE + 0x60400) -#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710) -#define RNG_BASE (AHB2PERIPH_BASE + 0x60800) - -#if defined (STM32F40_41xxx) -/*!< FSMC Bankx registers base address */ -#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) -#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) -#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) -#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) -#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) -#endif /* STM32F40_41xxx */ - -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) -/*!< FMC Bankx registers base address */ -#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) -#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) -#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060) -#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080) -#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0) -#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140) -#endif /* STM32F427_437xx || STM32F429_439xx */ - -/* Debug MCU registers base address */ -#define DBGMCU_BASE ((uint32_t )0xE0042000) - -/** - * @} - */ - -/** @addtogroup Peripheral_declaration - * @{ - */ -#define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#define TIM3 ((TIM_TypeDef *) TIM3_BASE) -#define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#define TIM5 ((TIM_TypeDef *) TIM5_BASE) -#define TIM6 ((TIM_TypeDef *) TIM6_BASE) -#define TIM7 ((TIM_TypeDef *) TIM7_BASE) -#define TIM12 ((TIM_TypeDef *) TIM12_BASE) -#define TIM13 ((TIM_TypeDef *) TIM13_BASE) -#define TIM14 ((TIM_TypeDef *) TIM14_BASE) -#define RTC ((RTC_TypeDef *) RTC_BASE) -#define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) -#define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#define SPI3 ((SPI_TypeDef *) SPI3_BASE) -#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) -#define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define UART4 ((USART_TypeDef *) UART4_BASE) -#define UART5 ((USART_TypeDef *) UART5_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define I2C3 ((I2C_TypeDef *) I2C3_BASE) -#define CAN1 ((CAN_TypeDef *) CAN1_BASE) -#define CAN2 ((CAN_TypeDef *) CAN2_BASE) -#define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) -#define UART7 ((USART_TypeDef *) UART7_BASE) -#define UART8 ((USART_TypeDef *) UART8_BASE) -#define TIM1 ((TIM_TypeDef *) TIM1_BASE) -#define TIM8 ((TIM_TypeDef *) TIM8_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define USART6 ((USART_TypeDef *) USART6_BASE) -#define ADC ((ADC_Common_TypeDef *) ADC_BASE) -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC2 ((ADC_TypeDef *) ADC2_BASE) -#define ADC3 ((ADC_TypeDef *) ADC3_BASE) -#define SDIO ((SDIO_TypeDef *) SDIO_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define SPI4 ((SPI_TypeDef *) SPI4_BASE) -#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) -#define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#define TIM9 ((TIM_TypeDef *) TIM9_BASE) -#define TIM10 ((TIM_TypeDef *) TIM10_BASE) -#define TIM11 ((TIM_TypeDef *) TIM11_BASE) -#define SPI5 ((SPI_TypeDef *) SPI5_BASE) -#define SPI6 ((SPI_TypeDef *) SPI6_BASE) -#define SAI1 ((SAI_TypeDef *) SAI1_BASE) -#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) -#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) -#define LTDC ((LTDC_TypeDef *)LTDC_BASE) -#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) -#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) -#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) -#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) -#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) -#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) -#define CRC ((CRC_TypeDef *) CRC_BASE) -#define RCC ((RCC_TypeDef *) RCC_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) -#define DMA1 ((DMA_TypeDef *) DMA1_BASE) -#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) -#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) -#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) -#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) -#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) -#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) -#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) -#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) -#define DMA2 ((DMA_TypeDef *) DMA2_BASE) -#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) -#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) -#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) -#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) -#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) -#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) -#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) -#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) -#define ETH ((ETH_TypeDef *) ETH_BASE) -#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE) -#define DCMI ((DCMI_TypeDef *) DCMI_BASE) -#define CRYP ((CRYP_TypeDef *) CRYP_BASE) -#define HASH ((HASH_TypeDef *) HASH_BASE) -#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE) -#define RNG ((RNG_TypeDef *) RNG_BASE) - -#if defined (STM32F40_41xxx) -#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) -#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) -#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) -#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) -#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) -#endif /* STM32F40_41xxx */ - -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) -#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) -#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) -#define FMC_Bank2 ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE) -#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) -#define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE) -#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) -#endif /* STM32F427_437xx || STM32F429_439xx */ - -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) - -/** - * @} - */ - -/** @addtogroup Exported_constants - * @{ - */ - - /** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ - -/******************************************************************************/ -/* Peripheral Registers_Bits_Definition */ -/******************************************************************************/ - -/******************************************************************************/ -/* */ -/* Analog to Digital Converter */ -/* */ -/******************************************************************************/ -/******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD ((uint8_t)0x01) /*!
© COPYRIGHT 2013 STMicroelectronics
- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_adc.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup ADC - * @brief ADC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* ADC DISCNUM mask */ -#define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF) - -/* ADC AWDCH mask */ -#define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0) - -/* ADC Analog watchdog enable mode mask */ -#define CR1_AWDMode_RESET ((uint32_t)0xFF3FFDFF) - -/* CR1 register Mask */ -#define CR1_CLEAR_MASK ((uint32_t)0xFCFFFEFF) - -/* ADC EXTEN mask */ -#define CR2_EXTEN_RESET ((uint32_t)0xCFFFFFFF) - -/* ADC JEXTEN mask */ -#define CR2_JEXTEN_RESET ((uint32_t)0xFFCFFFFF) - -/* ADC JEXTSEL mask */ -#define CR2_JEXTSEL_RESET ((uint32_t)0xFFF0FFFF) - -/* CR2 register Mask */ -#define CR2_CLEAR_MASK ((uint32_t)0xC0FFF7FD) - -/* ADC SQx mask */ -#define SQR3_SQ_SET ((uint32_t)0x0000001F) -#define SQR2_SQ_SET ((uint32_t)0x0000001F) -#define SQR1_SQ_SET ((uint32_t)0x0000001F) - -/* ADC L Mask */ -#define SQR1_L_RESET ((uint32_t)0xFF0FFFFF) - -/* ADC JSQx mask */ -#define JSQR_JSQ_SET ((uint32_t)0x0000001F) - -/* ADC JL mask */ -#define JSQR_JL_SET ((uint32_t)0x00300000) -#define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF) - -/* ADC SMPx mask */ -#define SMPR1_SMP_SET ((uint32_t)0x00000007) -#define SMPR2_SMP_SET ((uint32_t)0x00000007) - -/* ADC JDRx registers offset */ -#define JDR_OFFSET ((uint8_t)0x28) - -/* ADC CDR register base address */ -#define CDR_ADDRESS ((uint32_t)0x40012308) - -/* ADC CCR register Mask */ -#define CR_CLEAR_MASK ((uint32_t)0xFFFC30E0) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup ADC_Private_Functions - * @{ - */ - -/** @defgroup ADC_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize and configure the ADC Prescaler - (+) ADC Conversion Resolution (12bit..6bit) - (+) Scan Conversion Mode (multichannel or one channel) for regular group - (+) ADC Continuous Conversion Mode (Continuous or Single conversion) for - regular group - (+) External trigger Edge and source of regular group, - (+) Converted data alignment (left or right) - (+) The number of ADC conversions that will be done using the sequencer for - regular channel group - (+) Multi ADC mode selection - (+) Direct memory access mode selection for multi ADC mode - (+) Delay between 2 sampling phases (used in dual or triple interleaved modes) - (+) Enable or disable the ADC peripheral -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes all ADCs peripherals registers to their default reset - * values. - * @param None - * @retval None - */ -void ADC_DeInit(void) -{ - /* Enable all ADCs reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, ENABLE); - - /* Release all ADCs from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, DISABLE); -} - -/** - * @brief Initializes the ADCx peripheral according to the specified parameters - * in the ADC_InitStruct. - * @note This function is used to configure the global features of the ADC ( - * Resolution and Data Alignment), however, the rest of the configuration - * parameters are specific to the regular channels group (scan mode - * activation, continuous mode activation, External trigger source and - * edge, number of conversion in the regular channels group sequencer). - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains - * the configuration information for the specified ADC peripheral. - * @retval None - */ -void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) -{ - uint32_t tmpreg1 = 0; - uint8_t tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution)); - assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode)); - assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); - assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge)); - assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); - assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); - assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfConversion)); - - /*---------------------------- ADCx CR1 Configuration -----------------*/ - /* Get the ADCx CR1 value */ - tmpreg1 = ADCx->CR1; - - /* Clear RES and SCAN bits */ - tmpreg1 &= CR1_CLEAR_MASK; - - /* Configure ADCx: scan conversion mode and resolution */ - /* Set SCAN bit according to ADC_ScanConvMode value */ - /* Set RES bit according to ADC_Resolution value */ - tmpreg1 |= (uint32_t)(((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8) | \ - ADC_InitStruct->ADC_Resolution); - /* Write to ADCx CR1 */ - ADCx->CR1 = tmpreg1; - /*---------------------------- ADCx CR2 Configuration -----------------*/ - /* Get the ADCx CR2 value */ - tmpreg1 = ADCx->CR2; - - /* Clear CONT, ALIGN, EXTEN and EXTSEL bits */ - tmpreg1 &= CR2_CLEAR_MASK; - - /* Configure ADCx: external trigger event and edge, data alignment and - continuous conversion mode */ - /* Set ALIGN bit according to ADC_DataAlign value */ - /* Set EXTEN bits according to ADC_ExternalTrigConvEdge value */ - /* Set EXTSEL bits according to ADC_ExternalTrigConv value */ - /* Set CONT bit according to ADC_ContinuousConvMode value */ - tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | \ - ADC_InitStruct->ADC_ExternalTrigConv | - ADC_InitStruct->ADC_ExternalTrigConvEdge | \ - ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); - - /* Write to ADCx CR2 */ - ADCx->CR2 = tmpreg1; - /*---------------------------- ADCx SQR1 Configuration -----------------*/ - /* Get the ADCx SQR1 value */ - tmpreg1 = ADCx->SQR1; - - /* Clear L bits */ - tmpreg1 &= SQR1_L_RESET; - - /* Configure ADCx: regular channel sequence length */ - /* Set L bits according to ADC_NbrOfConversion value */ - tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfConversion - (uint8_t)1); - tmpreg1 |= ((uint32_t)tmpreg2 << 20); - - /* Write to ADCx SQR1 */ - ADCx->SQR1 = tmpreg1; -} - -/** - * @brief Fills each ADC_InitStruct member with its default value. - * @note This function is used to initialize the global features of the ADC ( - * Resolution and Data Alignment), however, the rest of the configuration - * parameters are specific to the regular channels group (scan mode - * activation, continuous mode activation, External trigger source and - * edge, number of conversion in the regular channels group sequencer). - * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) -{ - /* Initialize the ADC_Mode member */ - ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b; - - /* initialize the ADC_ScanConvMode member */ - ADC_InitStruct->ADC_ScanConvMode = DISABLE; - - /* Initialize the ADC_ContinuousConvMode member */ - ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; - - /* Initialize the ADC_ExternalTrigConvEdge member */ - ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None; - - /* Initialize the ADC_ExternalTrigConv member */ - ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; - - /* Initialize the ADC_DataAlign member */ - ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; - - /* Initialize the ADC_NbrOfConversion member */ - ADC_InitStruct->ADC_NbrOfConversion = 1; -} - -/** - * @brief Initializes the ADCs peripherals according to the specified parameters - * in the ADC_CommonInitStruct. - * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure - * that contains the configuration information for All ADCs peripherals. - * @retval None - */ -void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) -{ - uint32_t tmpreg1 = 0; - /* Check the parameters */ - assert_param(IS_ADC_MODE(ADC_CommonInitStruct->ADC_Mode)); - assert_param(IS_ADC_PRESCALER(ADC_CommonInitStruct->ADC_Prescaler)); - assert_param(IS_ADC_DMA_ACCESS_MODE(ADC_CommonInitStruct->ADC_DMAAccessMode)); - assert_param(IS_ADC_SAMPLING_DELAY(ADC_CommonInitStruct->ADC_TwoSamplingDelay)); - /*---------------------------- ADC CCR Configuration -----------------*/ - /* Get the ADC CCR value */ - tmpreg1 = ADC->CCR; - - /* Clear MULTI, DELAY, DMA and ADCPRE bits */ - tmpreg1 &= CR_CLEAR_MASK; - - /* Configure ADCx: Multi mode, Delay between two sampling time, ADC prescaler, - and DMA access mode for multimode */ - /* Set MULTI bits according to ADC_Mode value */ - /* Set ADCPRE bits according to ADC_Prescaler value */ - /* Set DMA bits according to ADC_DMAAccessMode value */ - /* Set DELAY bits according to ADC_TwoSamplingDelay value */ - tmpreg1 |= (uint32_t)(ADC_CommonInitStruct->ADC_Mode | - ADC_CommonInitStruct->ADC_Prescaler | - ADC_CommonInitStruct->ADC_DMAAccessMode | - ADC_CommonInitStruct->ADC_TwoSamplingDelay); - - /* Write to ADC CCR */ - ADC->CCR = tmpreg1; -} - -/** - * @brief Fills each ADC_CommonInitStruct member with its default value. - * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure - * which will be initialized. - * @retval None - */ -void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) -{ - /* Initialize the ADC_Mode member */ - ADC_CommonInitStruct->ADC_Mode = ADC_Mode_Independent; - - /* initialize the ADC_Prescaler member */ - ADC_CommonInitStruct->ADC_Prescaler = ADC_Prescaler_Div2; - - /* Initialize the ADC_DMAAccessMode member */ - ADC_CommonInitStruct->ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled; - - /* Initialize the ADC_TwoSamplingDelay member */ - ADC_CommonInitStruct->ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles; -} - -/** - * @brief Enables or disables the specified ADC peripheral. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the ADCx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the ADON bit to wake up the ADC from power down mode */ - ADCx->CR2 |= (uint32_t)ADC_CR2_ADON; - } - else - { - /* Disable the selected ADC peripheral */ - ADCx->CR2 &= (uint32_t)(~ADC_CR2_ADON); - } -} -/** - * @} - */ - -/** @defgroup ADC_Group2 Analog Watchdog configuration functions - * @brief Analog Watchdog configuration functions - * -@verbatim - =============================================================================== - ##### Analog Watchdog configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to configure the Analog Watchdog - (AWD) feature in the ADC. - - [..] A typical configuration Analog Watchdog is done following these steps : - (#) the ADC guarded channel(s) is (are) selected using the - ADC_AnalogWatchdogSingleChannelConfig() function. - (#) The Analog watchdog lower and higher threshold are configured using the - ADC_AnalogWatchdogThresholdsConfig() function. - (#) The Analog watchdog is enabled and configured to enable the check, on one - or more channels, using the ADC_AnalogWatchdogCmd() function. -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the analog watchdog on single/all regular or - * injected channels - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration. - * This parameter can be one of the following values: - * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel - * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel - * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel - * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel - * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel - * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels - * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog - * @retval None - */ -void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog)); - - /* Get the old register value */ - tmpreg = ADCx->CR1; - - /* Clear AWDEN, JAWDEN and AWDSGL bits */ - tmpreg &= CR1_AWDMode_RESET; - - /* Set the analog watchdog enable mode */ - tmpreg |= ADC_AnalogWatchdog; - - /* Store the new register value */ - ADCx->CR1 = tmpreg; -} - -/** - * @brief Configures the high and low thresholds of the analog watchdog. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param HighThreshold: the ADC analog watchdog High threshold value. - * This parameter must be a 12-bit value. - * @param LowThreshold: the ADC analog watchdog Low threshold value. - * This parameter must be a 12-bit value. - * @retval None - */ -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, - uint16_t LowThreshold) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_THRESHOLD(HighThreshold)); - assert_param(IS_ADC_THRESHOLD(LowThreshold)); - - /* Set the ADCx high threshold */ - ADCx->HTR = HighThreshold; - - /* Set the ADCx low threshold */ - ADCx->LTR = LowThreshold; -} - -/** - * @brief Configures the analog watchdog guarded single channel - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure for the analog watchdog. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @arg ADC_Channel_18: ADC Channel18 selected - * @retval None - */ -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - - /* Get the old register value */ - tmpreg = ADCx->CR1; - - /* Clear the Analog watchdog channel select bits */ - tmpreg &= CR1_AWDCH_RESET; - - /* Set the Analog watchdog channel */ - tmpreg |= ADC_Channel; - - /* Store the new register value */ - ADCx->CR1 = tmpreg; -} -/** - * @} - */ - -/** @defgroup ADC_Group3 Temperature Sensor, Vrefint (Voltage Reference internal) - * and VBAT (Voltage BATtery) management functions - * @brief Temperature Sensor, Vrefint and VBAT management functions - * -@verbatim - =============================================================================== - ##### Temperature Sensor, Vrefint and VBAT management functions ##### - =============================================================================== - [..] This section provides functions allowing to enable/ disable the internal - connections between the ADC and the Temperature Sensor, the Vrefint and - the Vbat sources. - - [..] A typical configuration to get the Temperature sensor and Vrefint channels - voltages is done following these steps : - (#) Enable the internal connection of Temperature sensor and Vrefint sources - with the ADC channels using ADC_TempSensorVrefintCmd() function. - (#) Select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using - ADC_RegularChannelConfig() or ADC_InjectedChannelConfig() functions - (#) Get the voltage values, using ADC_GetConversionValue() or - ADC_GetInjectedConversionValue(). - - [..] A typical configuration to get the VBAT channel voltage is done following - these steps : - (#) Enable the internal connection of VBAT source with the ADC channel using - ADC_VBATCmd() function. - (#) Select the ADC_Channel_Vbat using ADC_RegularChannelConfig() or - ADC_InjectedChannelConfig() functions - (#) Get the voltage value, using ADC_GetConversionValue() or - ADC_GetInjectedConversionValue(). - -@endverbatim - * @{ - */ - - -/** - * @brief Enables or disables the temperature sensor and Vrefint channels. - * @param NewState: new state of the temperature sensor and Vrefint channels. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_TempSensorVrefintCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the temperature sensor and Vrefint channel*/ - ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE; - } - else - { - /* Disable the temperature sensor and Vrefint channel*/ - ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE); - } -} - -/** - * @brief Enables or disables the VBAT (Voltage Battery) channel. - * - * @note the Battery voltage measured is equal to VBAT/2 on STM32F40xx and - * STM32F41xx devices and equal to VBAT/4 on STM32F42xx and STM32F43xx devices - * - * @param NewState: new state of the VBAT channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_VBATCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the VBAT channel*/ - ADC->CCR |= (uint32_t)ADC_CCR_VBATE; - } - else - { - /* Disable the VBAT channel*/ - ADC->CCR &= (uint32_t)(~ADC_CCR_VBATE); - } -} - -/** - * @} - */ - -/** @defgroup ADC_Group4 Regular Channels Configuration functions - * @brief Regular Channels Configuration functions - * -@verbatim - =============================================================================== - ##### Regular Channels Configuration functions ##### - =============================================================================== - - [..] This section provides functions allowing to manage the ADC's regular channels, - it is composed of 2 sub sections : - - (#) Configuration and management functions for regular channels: This subsection - provides functions allowing to configure the ADC regular channels : - (++) Configure the rank in the regular group sequencer for each channel - (++) Configure the sampling time for each channel - (++) select the conversion Trigger for regular channels - (++) select the desired EOC event behavior configuration - (++) Activate the continuous Mode (*) - (++) Activate the Discontinuous Mode - -@@- Please Note that the following features for regular channels - are configurated using the ADC_Init() function : - (+@@) scan mode activation - (+@@) continuous mode activation (**) - (+@@) External trigger source - (+@@) External trigger edge - (+@@) number of conversion in the regular channels group sequencer. - - -@@- (*) and (**) are performing the same configuration - - (#) Get the conversion data: This subsection provides an important function in - the ADC peripheral since it returns the converted data of the current - regular channel. When the Conversion value is read, the EOC Flag is - automatically cleared. - - -@- For multi ADC mode, the last ADC1, ADC2 and ADC3 regular conversions - results data (in the selected multi mode) can be returned in the same - time using ADC_GetMultiModeConversionValue() function. - -@endverbatim - * @{ - */ -/** - * @brief Configures for the selected ADC regular channel its corresponding - * rank in the sequencer and its sample time. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @arg ADC_Channel_18: ADC Channel18 selected - * @param Rank: The rank in the regular group sequencer. - * This parameter must be between 1 to 16. - * @param ADC_SampleTime: The sample time value to be set for the selected channel. - * This parameter can be one of the following values: - * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles - * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles - * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles - * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles - * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles - * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles - * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles - * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles - * @retval None - */ -void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - assert_param(IS_ADC_REGULAR_RANK(Rank)); - assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); - - /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ - if (ADC_Channel > ADC_Channel_9) - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR1; - - /* Calculate the mask to clear */ - tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 10)); - - /* Clear the old sample time */ - tmpreg1 &= ~tmpreg2; - - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); - - /* Set the new sample time */ - tmpreg1 |= tmpreg2; - - /* Store the new register value */ - ADCx->SMPR1 = tmpreg1; - } - else /* ADC_Channel include in ADC_Channel_[0..9] */ - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR2; - - /* Calculate the mask to clear */ - tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel); - - /* Clear the old sample time */ - tmpreg1 &= ~tmpreg2; - - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - - /* Set the new sample time */ - tmpreg1 |= tmpreg2; - - /* Store the new register value */ - ADCx->SMPR2 = tmpreg1; - } - /* For Rank 1 to 6 */ - if (Rank < 7) - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR3; - - /* Calculate the mask to clear */ - tmpreg2 = SQR3_SQ_SET << (5 * (Rank - 1)); - - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); - - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - - /* Store the new register value */ - ADCx->SQR3 = tmpreg1; - } - /* For Rank 7 to 12 */ - else if (Rank < 13) - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR2; - - /* Calculate the mask to clear */ - tmpreg2 = SQR2_SQ_SET << (5 * (Rank - 7)); - - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); - - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - - /* Store the new register value */ - ADCx->SQR2 = tmpreg1; - } - /* For Rank 13 to 16 */ - else - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR1; - - /* Calculate the mask to clear */ - tmpreg2 = SQR1_SQ_SET << (5 * (Rank - 13)); - - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); - - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - - /* Store the new register value */ - ADCx->SQR1 = tmpreg1; - } -} - -/** - * @brief Enables the selected ADC software start conversion of the regular channels. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval None - */ -void ADC_SoftwareStartConv(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Enable the selected ADC conversion for regular group */ - ADCx->CR2 |= (uint32_t)ADC_CR2_SWSTART; -} - -/** - * @brief Gets the selected ADC Software start regular conversion Status. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The new state of ADC software start conversion (SET or RESET). - */ -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Check the status of SWSTART bit */ - if ((ADCx->CR2 & ADC_CR2_SWSTART) != (uint32_t)RESET) - { - /* SWSTART bit is set */ - bitstatus = SET; - } - else - { - /* SWSTART bit is reset */ - bitstatus = RESET; - } - - /* Return the SWSTART bit status */ - return bitstatus; -} - - -/** - * @brief Enables or disables the EOC on each regular channel conversion - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC EOC flag rising - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected ADC EOC rising on each regular channel conversion */ - ADCx->CR2 |= (uint32_t)ADC_CR2_EOCS; - } - else - { - /* Disable the selected ADC EOC rising on each regular channel conversion */ - ADCx->CR2 &= (uint32_t)(~ADC_CR2_EOCS); - } -} - -/** - * @brief Enables or disables the ADC continuous conversion mode - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC continuous conversion mode - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected ADC continuous conversion mode */ - ADCx->CR2 |= (uint32_t)ADC_CR2_CONT; - } - else - { - /* Disable the selected ADC continuous conversion mode */ - ADCx->CR2 &= (uint32_t)(~ADC_CR2_CONT); - } -} - -/** - * @brief Configures the discontinuous mode for the selected ADC regular group - * channel. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param Number: specifies the discontinuous mode regular channel count value. - * This number must be between 1 and 8. - * @retval None - */ -void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number)); - - /* Get the old register value */ - tmpreg1 = ADCx->CR1; - - /* Clear the old discontinuous mode channel count */ - tmpreg1 &= CR1_DISCNUM_RESET; - - /* Set the discontinuous mode channel count */ - tmpreg2 = Number - 1; - tmpreg1 |= tmpreg2 << 13; - - /* Store the new register value */ - ADCx->CR1 = tmpreg1; -} - -/** - * @brief Enables or disables the discontinuous mode on regular group channel - * for the specified ADC - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC discontinuous mode on - * regular group channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected ADC regular discontinuous mode */ - ADCx->CR1 |= (uint32_t)ADC_CR1_DISCEN; - } - else - { - /* Disable the selected ADC regular discontinuous mode */ - ADCx->CR1 &= (uint32_t)(~ADC_CR1_DISCEN); - } -} - -/** - * @brief Returns the last ADCx conversion result data for regular channel. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The Data conversion value. - */ -uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Return the selected ADC conversion value */ - return (uint16_t) ADCx->DR; -} - -/** - * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results - * data in the selected multi mode. - * @param None - * @retval The Data conversion value. - * @note In dual mode, the value returned by this function is as following - * Data[15:0] : these bits contain the regular data of ADC1. - * Data[31:16]: these bits contain the regular data of ADC2. - * @note In triple mode, the value returned by this function is as following - * Data[15:0] : these bits contain alternatively the regular data of ADC1, ADC3 and ADC2. - * Data[31:16]: these bits contain alternatively the regular data of ADC2, ADC1 and ADC3. - */ -uint32_t ADC_GetMultiModeConversionValue(void) -{ - /* Return the multi mode conversion value */ - return (*(__IO uint32_t *) CDR_ADDRESS); -} -/** - * @} - */ - -/** @defgroup ADC_Group5 Regular Channels DMA Configuration functions - * @brief Regular Channels DMA Configuration functions - * -@verbatim - =============================================================================== - ##### Regular Channels DMA Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to configure the DMA for ADC - regular channels. - Since converted regular channel values are stored into a unique data - register, it is useful to use DMA for conversion of more than one regular - channel. This avoids the loss of the data already stored in the ADC - Data register. - When the DMA mode is enabled (using the ADC_DMACmd() function), after each - conversion of a regular channel, a DMA request is generated. - [..] Depending on the "DMA disable selection for Independent ADC mode" - configuration (using the ADC_DMARequestAfterLastTransferCmd() function), - at the end of the last DMA transfer, two possibilities are allowed: - (+) No new DMA request is issued to the DMA controller (feature DISABLED) - (+) Requests can continue to be generated (feature ENABLED). - [..] Depending on the "DMA disable selection for multi ADC mode" configuration - (using the void ADC_MultiModeDMARequestAfterLastTransferCmd() function), - at the end of the last DMA transfer, two possibilities are allowed: - (+) No new DMA request is issued to the DMA controller (feature DISABLED) - (+) Requests can continue to be generated (feature ENABLED). - -@endverbatim - * @{ - */ - - /** - * @brief Enables or disables the specified ADC DMA request. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC DMA transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC DMA request */ - ADCx->CR2 |= (uint32_t)ADC_CR2_DMA; - } - else - { - /* Disable the selected ADC DMA request */ - ADCx->CR2 &= (uint32_t)(~ADC_CR2_DMA); - } -} - -/** - * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode) - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC DMA request after last transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC DMA request after last transfer */ - ADCx->CR2 |= (uint32_t)ADC_CR2_DDS; - } - else - { - /* Disable the selected ADC DMA request after last transfer */ - ADCx->CR2 &= (uint32_t)(~ADC_CR2_DDS); - } -} - -/** - * @brief Enables or disables the ADC DMA request after last transfer in multi ADC mode - * @param NewState: new state of the selected ADC DMA request after last transfer. - * This parameter can be: ENABLE or DISABLE. - * @note if Enabled, DMA requests are issued as long as data are converted and - * DMA mode for multi ADC mode (selected using ADC_CommonInit() function - * by ADC_CommonInitStruct.ADC_DMAAccessMode structure member) is - * ADC_DMAAccessMode_1, ADC_DMAAccessMode_2 or ADC_DMAAccessMode_3. - * @retval None - */ -void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC DMA request after last transfer */ - ADC->CCR |= (uint32_t)ADC_CCR_DDS; - } - else - { - /* Disable the selected ADC DMA request after last transfer */ - ADC->CCR &= (uint32_t)(~ADC_CCR_DDS); - } -} -/** - * @} - */ - -/** @defgroup ADC_Group6 Injected channels Configuration functions - * @brief Injected channels Configuration functions - * -@verbatim - =============================================================================== - ##### Injected channels Configuration functions ##### - =============================================================================== - - [..] This section provide functions allowing to configure the ADC Injected channels, - it is composed of 2 sub sections : - - (#) Configuration functions for Injected channels: This subsection provides - functions allowing to configure the ADC injected channels : - (++) Configure the rank in the injected group sequencer for each channel - (++) Configure the sampling time for each channel - (++) Activate the Auto injected Mode - (++) Activate the Discontinuous Mode - (++) scan mode activation - (++) External/software trigger source - (++) External trigger edge - (++) injected channels sequencer. - - (#) Get the Specified Injected channel conversion data: This subsection - provides an important function in the ADC peripheral since it returns the - converted data of the specific injected channel. - -@endverbatim - * @{ - */ -/** - * @brief Configures for the selected ADC injected channel its corresponding - * rank in the sequencer and its sample time. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @arg ADC_Channel_18: ADC Channel18 selected - * @param Rank: The rank in the injected group sequencer. - * This parameter must be between 1 to 4. - * @param ADC_SampleTime: The sample time value to be set for the selected channel. - * This parameter can be one of the following values: - * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles - * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles - * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles - * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles - * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles - * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles - * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles - * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles - * @retval None - */ -void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - assert_param(IS_ADC_INJECTED_RANK(Rank)); - assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); - /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ - if (ADC_Channel > ADC_Channel_9) - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR1; - /* Calculate the mask to clear */ - tmpreg2 = SMPR1_SMP_SET << (3*(ADC_Channel - 10)); - /* Clear the old sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10)); - /* Set the new sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR1 = tmpreg1; - } - else /* ADC_Channel include in ADC_Channel_[0..9] */ - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR2; - /* Calculate the mask to clear */ - tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel); - /* Clear the old sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - /* Set the new sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR2 = tmpreg1; - } - /* Rank configuration */ - /* Get the old register value */ - tmpreg1 = ADCx->JSQR; - /* Get JL value: Number = JL+1 */ - tmpreg3 = (tmpreg1 & JSQR_JL_SET)>> 20; - /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */ - tmpreg2 = JSQR_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - /* Clear the old JSQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - /* Set the JSQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->JSQR = tmpreg1; -} - -/** - * @brief Configures the sequencer length for injected channels - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param Length: The sequencer length. - * This parameter must be a number between 1 to 4. - * @retval None - */ -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_LENGTH(Length)); - - /* Get the old register value */ - tmpreg1 = ADCx->JSQR; - - /* Clear the old injected sequence length JL bits */ - tmpreg1 &= JSQR_JL_RESET; - - /* Set the injected sequence length JL bits */ - tmpreg2 = Length - 1; - tmpreg1 |= tmpreg2 << 20; - - /* Store the new register value */ - ADCx->JSQR = tmpreg1; -} - -/** - * @brief Set the injected channels conversion value offset - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_InjectedChannel: the ADC injected channel to set its offset. - * This parameter can be one of the following values: - * @arg ADC_InjectedChannel_1: Injected Channel1 selected - * @arg ADC_InjectedChannel_2: Injected Channel2 selected - * @arg ADC_InjectedChannel_3: Injected Channel3 selected - * @arg ADC_InjectedChannel_4: Injected Channel4 selected - * @param Offset: the offset value for the selected ADC injected channel - * This parameter must be a 12bit value. - * @retval None - */ -void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) -{ - __IO uint32_t tmp = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); - assert_param(IS_ADC_OFFSET(Offset)); - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel; - - /* Set the selected injected channel data offset */ - *(__IO uint32_t *) tmp = (uint32_t)Offset; -} - - /** - * @brief Configures the ADCx external trigger for injected channels conversion. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion. - * This parameter can be one of the following values: - * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected - * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected - * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected - * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected - * @arg ADC_ExternalTrigInjecConv_T3_CC2: Timer3 capture compare2 selected - * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected - * @arg ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected - * @arg ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected - * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected - * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected - * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected - * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected - * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected - * @arg ADC_ExternalTrigInjecConv_T8_CC3: Timer8 capture compare3 selected - * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected - * @arg ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected - * @retval None - */ -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv)); - - /* Get the old register value */ - tmpreg = ADCx->CR2; - - /* Clear the old external event selection for injected group */ - tmpreg &= CR2_JEXTSEL_RESET; - - /* Set the external event selection for injected group */ - tmpreg |= ADC_ExternalTrigInjecConv; - - /* Store the new register value */ - ADCx->CR2 = tmpreg; -} - -/** - * @brief Configures the ADCx external trigger edge for injected channels conversion. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_ExternalTrigInjecConvEdge: specifies the ADC external trigger edge - * to start injected conversion. - * This parameter can be one of the following values: - * @arg ADC_ExternalTrigInjecConvEdge_None: external trigger disabled for - * injected conversion - * @arg ADC_ExternalTrigInjecConvEdge_Rising: detection on rising edge - * @arg ADC_ExternalTrigInjecConvEdge_Falling: detection on falling edge - * @arg ADC_ExternalTrigInjecConvEdge_RisingFalling: detection on both rising - * and falling edge - * @retval None - */ -void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(ADC_ExternalTrigInjecConvEdge)); - /* Get the old register value */ - tmpreg = ADCx->CR2; - /* Clear the old external trigger edge for injected group */ - tmpreg &= CR2_JEXTEN_RESET; - /* Set the new external trigger edge for injected group */ - tmpreg |= ADC_ExternalTrigInjecConvEdge; - /* Store the new register value */ - ADCx->CR2 = tmpreg; -} - -/** - * @brief Enables the selected ADC software start conversion of the injected channels. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval None - */ -void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Enable the selected ADC conversion for injected group */ - ADCx->CR2 |= (uint32_t)ADC_CR2_JSWSTART; -} - -/** - * @brief Gets the selected ADC Software start injected conversion Status. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The new state of ADC software start injected conversion (SET or RESET). - */ -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Check the status of JSWSTART bit */ - if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET) - { - /* JSWSTART bit is set */ - bitstatus = SET; - } - else - { - /* JSWSTART bit is reset */ - bitstatus = RESET; - } - /* Return the JSWSTART bit status */ - return bitstatus; -} - -/** - * @brief Enables or disables the selected ADC automatic injected group - * conversion after regular one. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC auto injected conversion - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC automatic injected group conversion */ - ADCx->CR1 |= (uint32_t)ADC_CR1_JAUTO; - } - else - { - /* Disable the selected ADC automatic injected group conversion */ - ADCx->CR1 &= (uint32_t)(~ADC_CR1_JAUTO); - } -} - -/** - * @brief Enables or disables the discontinuous mode for injected group - * channel for the specified ADC - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC discontinuous mode on injected - * group channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC injected discontinuous mode */ - ADCx->CR1 |= (uint32_t)ADC_CR1_JDISCEN; - } - else - { - /* Disable the selected ADC injected discontinuous mode */ - ADCx->CR1 &= (uint32_t)(~ADC_CR1_JDISCEN); - } -} - -/** - * @brief Returns the ADC injected channel conversion result - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_InjectedChannel: the converted ADC injected channel. - * This parameter can be one of the following values: - * @arg ADC_InjectedChannel_1: Injected Channel1 selected - * @arg ADC_InjectedChannel_2: Injected Channel2 selected - * @arg ADC_InjectedChannel_3: Injected Channel3 selected - * @arg ADC_InjectedChannel_4: Injected Channel4 selected - * @retval The Data conversion value. - */ -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel + JDR_OFFSET; - - /* Returns the selected injected channel conversion data value */ - return (uint16_t) (*(__IO uint32_t*) tmp); -} -/** - * @} - */ - -/** @defgroup ADC_Group7 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure the ADC Interrupts - and to get the status and clear flags and Interrupts pending bits. - - [..] Each ADC provides 4 Interrupts sources and 6 Flags which can be divided - into 3 groups: - - *** Flags and Interrupts for ADC regular channels *** - ===================================================== - [..] - (+) Flags : - (##) ADC_FLAG_OVR : Overrun detection when regular converted data are lost - - (##) ADC_FLAG_EOC : Regular channel end of conversion ==> to indicate - (depending on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() ) - the end of: - (+++) a regular CHANNEL conversion - (+++) sequence of regular GROUP conversions . - - (##) ADC_FLAG_STRT: Regular channel start ==> to indicate when regular - CHANNEL conversion starts. - [..] - (+) Interrupts : - (##) ADC_IT_OVR : specifies the interrupt source for Overrun detection - event. - (##) ADC_IT_EOC : specifies the interrupt source for Regular channel end - of conversion event. - - - *** Flags and Interrupts for ADC Injected channels *** - ====================================================== - [..] - (+) Flags : - (##) ADC_FLAG_JEOC : Injected channel end of conversion ==> to indicate - at the end of injected GROUP conversion - - (##) ADC_FLAG_JSTRT: Injected channel start ==> to indicate hardware when - injected GROUP conversion starts. - [..] - (+) Interrupts : - (##) ADC_IT_JEOC : specifies the interrupt source for Injected channel - end of conversion event. - - *** General Flags and Interrupts for the ADC *** - ================================================ - [..] - (+)Flags : - (##) ADC_FLAG_AWD: Analog watchdog ==> to indicate if the converted voltage - crosses the programmed thresholds values. - [..] - (+) Interrupts : - (##) ADC_IT_AWD : specifies the interrupt source for Analog watchdog event. - - - [..] The user should identify which mode will be used in his application to - manage the ADC controller events: Polling mode or Interrupt mode. - - [..] In the Polling Mode it is advised to use the following functions: - (+) ADC_GetFlagStatus() : to check if flags events occur. - (+) ADC_ClearFlag() : to clear the flags events. - - [..] In the Interrupt Mode it is advised to use the following functions: - (+) ADC_ITConfig() : to enable or disable the interrupt source. - (+) ADC_GetITStatus() : to check if Interrupt occurs. - (+) ADC_ClearITPendingBit() : to clear the Interrupt pending Bit - (corresponding Flag). -@endverbatim - * @{ - */ -/** - * @brief Enables or disables the specified ADC interrupts. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt mask - * @arg ADC_IT_AWD: Analog watchdog interrupt mask - * @arg ADC_IT_JEOC: End of injected conversion interrupt mask - * @arg ADC_IT_OVR: Overrun interrupt enable - * @param NewState: new state of the specified ADC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) -{ - uint32_t itmask = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_ADC_IT(ADC_IT)); - - /* Get the ADC IT index */ - itmask = (uint8_t)ADC_IT; - itmask = (uint32_t)0x01 << itmask; - - if (NewState != DISABLE) - { - /* Enable the selected ADC interrupts */ - ADCx->CR1 |= itmask; - } - else - { - /* Disable the selected ADC interrupts */ - ADCx->CR1 &= (~(uint32_t)itmask); - } -} - -/** - * @brief Checks whether the specified ADC flag is set or not. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg ADC_FLAG_AWD: Analog watchdog flag - * @arg ADC_FLAG_EOC: End of conversion flag - * @arg ADC_FLAG_JEOC: End of injected group conversion flag - * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag - * @arg ADC_FLAG_STRT: Start of regular group conversion flag - * @arg ADC_FLAG_OVR: Overrun flag - * @retval The new state of ADC_FLAG (SET or RESET). - */ -FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); - - /* Check the status of the specified ADC flag */ - if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET) - { - /* ADC_FLAG is set */ - bitstatus = SET; - } - else - { - /* ADC_FLAG is reset */ - bitstatus = RESET; - } - /* Return the ADC_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the ADCx's pending flags. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg ADC_FLAG_AWD: Analog watchdog flag - * @arg ADC_FLAG_EOC: End of conversion flag - * @arg ADC_FLAG_JEOC: End of injected group conversion flag - * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag - * @arg ADC_FLAG_STRT: Start of regular group conversion flag - * @arg ADC_FLAG_OVR: Overrun flag - * @retval None - */ -void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG)); - - /* Clear the selected ADC flags */ - ADCx->SR = ~(uint32_t)ADC_FLAG; -} - -/** - * @brief Checks whether the specified ADC interrupt has occurred or not. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt source to check. - * This parameter can be one of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt mask - * @arg ADC_IT_AWD: Analog watchdog interrupt mask - * @arg ADC_IT_JEOC: End of injected conversion interrupt mask - * @arg ADC_IT_OVR: Overrun interrupt mask - * @retval The new state of ADC_IT (SET or RESET). - */ -ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t itmask = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_IT(ADC_IT)); - - /* Get the ADC IT index */ - itmask = ADC_IT >> 8; - - /* Get the ADC_IT enable bit status */ - enablestatus = (ADCx->CR1 & ((uint32_t)0x01 << (uint8_t)ADC_IT)) ; - - /* Check the status of the specified ADC interrupt */ - if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus) - { - /* ADC_IT is set */ - bitstatus = SET; - } - else - { - /* ADC_IT is reset */ - bitstatus = RESET; - } - /* Return the ADC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the ADCx's interrupt pending bits. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt mask - * @arg ADC_IT_AWD: Analog watchdog interrupt mask - * @arg ADC_IT_JEOC: End of injected conversion interrupt mask - * @arg ADC_IT_OVR: Overrun interrupt mask - * @retval None - */ -void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT) -{ - uint8_t itmask = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_IT(ADC_IT)); - /* Get the ADC IT index */ - itmask = (uint8_t)(ADC_IT >> 8); - /* Clear the selected ADC interrupt pending bits */ - ADCx->SR = ~(uint32_t)itmask; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm32f4xx_adc.h b/stm/stmperiph/stm32f4xx_adc.h deleted file mode 100644 index 9f5fe7acc..000000000 --- a/stm/stmperiph/stm32f4xx_adc.h +++ /dev/null @@ -1,656 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_adc.h - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief This file contains all the functions prototypes for the ADC firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_ADC_H -#define __STM32F4xx_ADC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup ADC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief ADC Init structure definition - */ -typedef struct -{ - uint32_t ADC_Resolution; /*!< Configures the ADC resolution dual mode. - This parameter can be a value of @ref ADC_resolution */ - FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion - is performed in Scan (multichannels) - or Single (one channel) mode. - This parameter can be set to ENABLE or DISABLE */ - FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion - is performed in Continuous or Single mode. - This parameter can be set to ENABLE or DISABLE. */ - uint32_t ADC_ExternalTrigConvEdge; /*!< Select the external trigger edge and - enable the trigger of a regular group. - This parameter can be a value of - @ref ADC_external_trigger_edge_for_regular_channels_conversion */ - uint32_t ADC_ExternalTrigConv; /*!< Select the external event used to trigger - the start of conversion of a regular group. - This parameter can be a value of - @ref ADC_extrenal_trigger_sources_for_regular_channels_conversion */ - uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment - is left or right. This parameter can be - a value of @ref ADC_data_align */ - uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions - that will be done using the sequencer for - regular channel group. - This parameter must range from 1 to 16. */ -}ADC_InitTypeDef; - -/** - * @brief ADC Common Init structure definition - */ -typedef struct -{ - uint32_t ADC_Mode; /*!< Configures the ADC to operate in - independent or multi mode. - This parameter can be a value of @ref ADC_Common_mode */ - uint32_t ADC_Prescaler; /*!< Select the frequency of the clock - to the ADC. The clock is common for all the ADCs. - This parameter can be a value of @ref ADC_Prescaler */ - uint32_t ADC_DMAAccessMode; /*!< Configures the Direct memory access - mode for multi ADC mode. - This parameter can be a value of - @ref ADC_Direct_memory_access_mode_for_multi_mode */ - uint32_t ADC_TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. - This parameter can be a value of - @ref ADC_delay_between_2_sampling_phases */ - -}ADC_CommonInitTypeDef; - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup ADC_Exported_Constants - * @{ - */ -#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ - ((PERIPH) == ADC2) || \ - ((PERIPH) == ADC3)) - -/** @defgroup ADC_Common_mode - * @{ - */ -#define ADC_Mode_Independent ((uint32_t)0x00000000) -#define ADC_DualMode_RegSimult_InjecSimult ((uint32_t)0x00000001) -#define ADC_DualMode_RegSimult_AlterTrig ((uint32_t)0x00000002) -#define ADC_DualMode_InjecSimult ((uint32_t)0x00000005) -#define ADC_DualMode_RegSimult ((uint32_t)0x00000006) -#define ADC_DualMode_Interl ((uint32_t)0x00000007) -#define ADC_DualMode_AlterTrig ((uint32_t)0x00000009) -#define ADC_TripleMode_RegSimult_InjecSimult ((uint32_t)0x00000011) -#define ADC_TripleMode_RegSimult_AlterTrig ((uint32_t)0x00000012) -#define ADC_TripleMode_InjecSimult ((uint32_t)0x00000015) -#define ADC_TripleMode_RegSimult ((uint32_t)0x00000016) -#define ADC_TripleMode_Interl ((uint32_t)0x00000017) -#define ADC_TripleMode_AlterTrig ((uint32_t)0x00000019) -#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \ - ((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \ - ((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \ - ((MODE) == ADC_DualMode_InjecSimult) || \ - ((MODE) == ADC_DualMode_RegSimult) || \ - ((MODE) == ADC_DualMode_Interl) || \ - ((MODE) == ADC_DualMode_AlterTrig) || \ - ((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \ - ((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \ - ((MODE) == ADC_TripleMode_InjecSimult) || \ - ((MODE) == ADC_TripleMode_RegSimult) || \ - ((MODE) == ADC_TripleMode_Interl) || \ - ((MODE) == ADC_TripleMode_AlterTrig)) -/** - * @} - */ - - -/** @defgroup ADC_Prescaler - * @{ - */ -#define ADC_Prescaler_Div2 ((uint32_t)0x00000000) -#define ADC_Prescaler_Div4 ((uint32_t)0x00010000) -#define ADC_Prescaler_Div6 ((uint32_t)0x00020000) -#define ADC_Prescaler_Div8 ((uint32_t)0x00030000) -#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || \ - ((PRESCALER) == ADC_Prescaler_Div4) || \ - ((PRESCALER) == ADC_Prescaler_Div6) || \ - ((PRESCALER) == ADC_Prescaler_Div8)) -/** - * @} - */ - - -/** @defgroup ADC_Direct_memory_access_mode_for_multi_mode - * @{ - */ -#define ADC_DMAAccessMode_Disabled ((uint32_t)0x00000000) /* DMA mode disabled */ -#define ADC_DMAAccessMode_1 ((uint32_t)0x00004000) /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/ -#define ADC_DMAAccessMode_2 ((uint32_t)0x00008000) /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/ -#define ADC_DMAAccessMode_3 ((uint32_t)0x0000C000) /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */ -#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \ - ((MODE) == ADC_DMAAccessMode_1) || \ - ((MODE) == ADC_DMAAccessMode_2) || \ - ((MODE) == ADC_DMAAccessMode_3)) - -/** - * @} - */ - - -/** @defgroup ADC_delay_between_2_sampling_phases - * @{ - */ -#define ADC_TwoSamplingDelay_5Cycles ((uint32_t)0x00000000) -#define ADC_TwoSamplingDelay_6Cycles ((uint32_t)0x00000100) -#define ADC_TwoSamplingDelay_7Cycles ((uint32_t)0x00000200) -#define ADC_TwoSamplingDelay_8Cycles ((uint32_t)0x00000300) -#define ADC_TwoSamplingDelay_9Cycles ((uint32_t)0x00000400) -#define ADC_TwoSamplingDelay_10Cycles ((uint32_t)0x00000500) -#define ADC_TwoSamplingDelay_11Cycles ((uint32_t)0x00000600) -#define ADC_TwoSamplingDelay_12Cycles ((uint32_t)0x00000700) -#define ADC_TwoSamplingDelay_13Cycles ((uint32_t)0x00000800) -#define ADC_TwoSamplingDelay_14Cycles ((uint32_t)0x00000900) -#define ADC_TwoSamplingDelay_15Cycles ((uint32_t)0x00000A00) -#define ADC_TwoSamplingDelay_16Cycles ((uint32_t)0x00000B00) -#define ADC_TwoSamplingDelay_17Cycles ((uint32_t)0x00000C00) -#define ADC_TwoSamplingDelay_18Cycles ((uint32_t)0x00000D00) -#define ADC_TwoSamplingDelay_19Cycles ((uint32_t)0x00000E00) -#define ADC_TwoSamplingDelay_20Cycles ((uint32_t)0x00000F00) -#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_6Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_7Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_8Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_9Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_10Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_11Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_12Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_13Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_14Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_15Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_16Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_17Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_18Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_19Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_20Cycles)) - -/** - * @} - */ - - -/** @defgroup ADC_resolution - * @{ - */ -#define ADC_Resolution_12b ((uint32_t)0x00000000) -#define ADC_Resolution_10b ((uint32_t)0x01000000) -#define ADC_Resolution_8b ((uint32_t)0x02000000) -#define ADC_Resolution_6b ((uint32_t)0x03000000) -#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \ - ((RESOLUTION) == ADC_Resolution_10b) || \ - ((RESOLUTION) == ADC_Resolution_8b) || \ - ((RESOLUTION) == ADC_Resolution_6b)) - -/** - * @} - */ - - -/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion - * @{ - */ -#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000) -#define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000) -#define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000) -#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000) -#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \ - ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \ - ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \ - ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling)) -/** - * @} - */ - - -/** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion - * @{ - */ -#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) -#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x01000000) -#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x02000000) -#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000) -#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x04000000) -#define ADC_ExternalTrigConv_T2_CC4 ((uint32_t)0x05000000) -#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000) -#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000) -#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x08000000) -#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x09000000) -#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x0A000000) -#define ADC_ExternalTrigConv_T5_CC2 ((uint32_t)0x0B000000) -#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x0C000000) -#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x0D000000) -#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x0E000000) -#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000) -#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_CC4) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T5_CC2) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11)) -/** - * @} - */ - - -/** @defgroup ADC_data_align - * @{ - */ -#define ADC_DataAlign_Right ((uint32_t)0x00000000) -#define ADC_DataAlign_Left ((uint32_t)0x00000800) -#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ - ((ALIGN) == ADC_DataAlign_Left)) -/** - * @} - */ - - -/** @defgroup ADC_channels - * @{ - */ -#define ADC_Channel_0 ((uint8_t)0x00) -#define ADC_Channel_1 ((uint8_t)0x01) -#define ADC_Channel_2 ((uint8_t)0x02) -#define ADC_Channel_3 ((uint8_t)0x03) -#define ADC_Channel_4 ((uint8_t)0x04) -#define ADC_Channel_5 ((uint8_t)0x05) -#define ADC_Channel_6 ((uint8_t)0x06) -#define ADC_Channel_7 ((uint8_t)0x07) -#define ADC_Channel_8 ((uint8_t)0x08) -#define ADC_Channel_9 ((uint8_t)0x09) -#define ADC_Channel_10 ((uint8_t)0x0A) -#define ADC_Channel_11 ((uint8_t)0x0B) -#define ADC_Channel_12 ((uint8_t)0x0C) -#define ADC_Channel_13 ((uint8_t)0x0D) -#define ADC_Channel_14 ((uint8_t)0x0E) -#define ADC_Channel_15 ((uint8_t)0x0F) -#define ADC_Channel_16 ((uint8_t)0x10) -#define ADC_Channel_17 ((uint8_t)0x11) -#define ADC_Channel_18 ((uint8_t)0x12) - -#if defined (STM32F40_41xxx) -#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) -#endif /* STM32F40_41xxx */ - -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx) -#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_18) -#endif /* STM32F427_437xx || STM32F429_439xx || STM32F401xx */ - -#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) -#define ADC_Channel_Vbat ((uint8_t)ADC_Channel_18) - -#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || \ - ((CHANNEL) == ADC_Channel_1) || \ - ((CHANNEL) == ADC_Channel_2) || \ - ((CHANNEL) == ADC_Channel_3) || \ - ((CHANNEL) == ADC_Channel_4) || \ - ((CHANNEL) == ADC_Channel_5) || \ - ((CHANNEL) == ADC_Channel_6) || \ - ((CHANNEL) == ADC_Channel_7) || \ - ((CHANNEL) == ADC_Channel_8) || \ - ((CHANNEL) == ADC_Channel_9) || \ - ((CHANNEL) == ADC_Channel_10) || \ - ((CHANNEL) == ADC_Channel_11) || \ - ((CHANNEL) == ADC_Channel_12) || \ - ((CHANNEL) == ADC_Channel_13) || \ - ((CHANNEL) == ADC_Channel_14) || \ - ((CHANNEL) == ADC_Channel_15) || \ - ((CHANNEL) == ADC_Channel_16) || \ - ((CHANNEL) == ADC_Channel_17) || \ - ((CHANNEL) == ADC_Channel_18)) -/** - * @} - */ - - -/** @defgroup ADC_sampling_times - * @{ - */ -#define ADC_SampleTime_3Cycles ((uint8_t)0x00) -#define ADC_SampleTime_15Cycles ((uint8_t)0x01) -#define ADC_SampleTime_28Cycles ((uint8_t)0x02) -#define ADC_SampleTime_56Cycles ((uint8_t)0x03) -#define ADC_SampleTime_84Cycles ((uint8_t)0x04) -#define ADC_SampleTime_112Cycles ((uint8_t)0x05) -#define ADC_SampleTime_144Cycles ((uint8_t)0x06) -#define ADC_SampleTime_480Cycles ((uint8_t)0x07) -#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_3Cycles) || \ - ((TIME) == ADC_SampleTime_15Cycles) || \ - ((TIME) == ADC_SampleTime_28Cycles) || \ - ((TIME) == ADC_SampleTime_56Cycles) || \ - ((TIME) == ADC_SampleTime_84Cycles) || \ - ((TIME) == ADC_SampleTime_112Cycles) || \ - ((TIME) == ADC_SampleTime_144Cycles) || \ - ((TIME) == ADC_SampleTime_480Cycles)) -/** - * @} - */ - - -/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion - * @{ - */ -#define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000) -#define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000) -#define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000) -#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000) -#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \ - ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \ - ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \ - ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling)) - -/** - * @} - */ - - -/** @defgroup ADC_extrenal_trigger_sources_for_injected_channels_conversion - * @{ - */ -#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00000000) -#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00010000) -#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00020000) -#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00030000) -#define ADC_ExternalTrigInjecConv_T3_CC2 ((uint32_t)0x00040000) -#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00050000) -#define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000) -#define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000) -#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000) -#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00090000) -#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x000A0000) -#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x000B0000) -#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x000C0000) -#define ADC_ExternalTrigInjecConv_T8_CC3 ((uint32_t)0x000D0000) -#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x000E0000) -#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000) -#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC2) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC3) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15)) -/** - * @} - */ - - -/** @defgroup ADC_injected_channel_selection - * @{ - */ -#define ADC_InjectedChannel_1 ((uint8_t)0x14) -#define ADC_InjectedChannel_2 ((uint8_t)0x18) -#define ADC_InjectedChannel_3 ((uint8_t)0x1C) -#define ADC_InjectedChannel_4 ((uint8_t)0x20) -#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ - ((CHANNEL) == ADC_InjectedChannel_2) || \ - ((CHANNEL) == ADC_InjectedChannel_3) || \ - ((CHANNEL) == ADC_InjectedChannel_4)) -/** - * @} - */ - - -/** @defgroup ADC_analog_watchdog_selection - * @{ - */ -#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) -#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) -#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) -#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) -#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) -#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) -#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) -#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_None)) -/** - * @} - */ - - -/** @defgroup ADC_interrupts_definition - * @{ - */ -#define ADC_IT_EOC ((uint16_t)0x0205) -#define ADC_IT_AWD ((uint16_t)0x0106) -#define ADC_IT_JEOC ((uint16_t)0x0407) -#define ADC_IT_OVR ((uint16_t)0x201A) -#define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \ - ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR)) -/** - * @} - */ - - -/** @defgroup ADC_flags_definition - * @{ - */ -#define ADC_FLAG_AWD ((uint8_t)0x01) -#define ADC_FLAG_EOC ((uint8_t)0x02) -#define ADC_FLAG_JEOC ((uint8_t)0x04) -#define ADC_FLAG_JSTRT ((uint8_t)0x08) -#define ADC_FLAG_STRT ((uint8_t)0x10) -#define ADC_FLAG_OVR ((uint8_t)0x20) - -#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00)) -#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || \ - ((FLAG) == ADC_FLAG_EOC) || \ - ((FLAG) == ADC_FLAG_JEOC) || \ - ((FLAG)== ADC_FLAG_JSTRT) || \ - ((FLAG) == ADC_FLAG_STRT) || \ - ((FLAG)== ADC_FLAG_OVR)) -/** - * @} - */ - - -/** @defgroup ADC_thresholds - * @{ - */ -#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) -/** - * @} - */ - - -/** @defgroup ADC_injected_offset - * @{ - */ -#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) -/** - * @} - */ - - -/** @defgroup ADC_injected_length - * @{ - */ -#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) -/** - * @} - */ - - -/** @defgroup ADC_injected_rank - * @{ - */ -#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) -/** - * @} - */ - - -/** @defgroup ADC_regular_length - * @{ - */ -#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) -/** - * @} - */ - - -/** @defgroup ADC_regular_rank - * @{ - */ -#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) -/** - * @} - */ - - -/** @defgroup ADC_regular_discontinuous_mode_number - * @{ - */ -#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) -/** - * @} - */ - - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the ADC configuration to the default reset state *****/ -void ADC_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); -void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); -void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct); -void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct); -void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); - -/* Analog Watchdog configuration functions ************************************/ -void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold); -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); - -/* Temperature Sensor, Vrefint and VBAT management functions ******************/ -void ADC_TempSensorVrefintCmd(FunctionalState NewState); -void ADC_VBATCmd(FunctionalState NewState); - -/* Regular Channels Configuration functions ***********************************/ -void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_SoftwareStartConv(ADC_TypeDef* ADCx); -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); -void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); -void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); -uint32_t ADC_GetMultiModeConversionValue(void); - -/* Regular Channels DMA Configuration functions *******************************/ -void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState); - -/* Injected channels Configuration functions **********************************/ -void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); -void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); -void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge); -void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx); -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); -void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); - -/* Interrupts and flags management functions **********************************/ -void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); -FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); -void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); -ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); -void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_ADC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm32f4xx_conf.h b/stm/stmperiph/stm32f4xx_conf.h deleted file mode 100644 index 515a93c6e..000000000 --- a/stm/stmperiph/stm32f4xx_conf.h +++ /dev/null @@ -1,122 +0,0 @@ -/** - ****************************************************************************** - * @file Project/STM32F4xx_StdPeriph_Templates/stm32f4xx_conf.h - * @author MCD Application Team - * @version V1.3.0 - * @date 13-November-2013 - * @brief Library configuration file. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_CONF_H -#define __STM32F4xx_CONF_H - -/* Includes ------------------------------------------------------------------*/ -/* Uncomment the line below to enable peripheral header file inclusion */ -#include "stm32f4xx_adc.h" -//#include "stm32f4xx_crc.h" -//#include "stm32f4xx_dbgmcu.h" -#include "stm32f4xx_dma.h" -#include "stm32f4xx_exti.h" -#include "stm32f4xx_flash.h" -#include "stm32f4xx_gpio.h" -#include "stm32f4xx_i2c.h" -//#include "stm32f4xx_iwdg.h" -#include "stm32f4xx_pwr.h" -#include "stm32f4xx_rcc.h" -#include "stm32f4xx_rtc.h" -#include "stm32f4xx_sdio.h" -#include "stm32f4xx_spi.h" -#include "stm32f4xx_syscfg.h" -#include "stm32f4xx_tim.h" -#include "stm32f4xx_usart.h" -//#include "stm32f4xx_wwdg.h" -#include "stm_misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ - -#if defined (STM32F429_439xx) -#include "stm32f4xx_cryp.h" -#include "stm32f4xx_hash.h" -#include "stm32f4xx_rng.h" -#include "stm32f4xx_can.h" -#include "stm32f4xx_dac.h" -#include "stm32f4xx_dcmi.h" -#include "stm32f4xx_dma2d.h" -#include "stm32f4xx_fmc.h" -#include "stm32f4xx_ltdc.h" -#include "stm32f4xx_sai.h" -#endif /* STM32F429_439xx */ - -#if defined (STM32F427_437xx) -#include "stm32f4xx_cryp.h" -#include "stm32f4xx_hash.h" -#include "stm32f4xx_rng.h" -#include "stm32f4xx_can.h" -#include "stm32f4xx_dac.h" -#include "stm32f4xx_dcmi.h" -#include "stm32f4xx_dma2d.h" -#include "stm32f4xx_fmc.h" -#include "stm32f4xx_sai.h" -#endif /* STM32F427_437xx */ - -#if defined (STM32F40_41xxx) -//#include "stm32f4xx_cryp.h" -//#include "stm32f4xx_hash.h" -#include "stm32f4xx_rng.h" -//#include "stm32f4xx_can.h" -#include "stm32f4xx_dac.h" -//#include "stm32f4xx_dcmi.h" -//#include "stm32f4xx_fsmc.h" -#endif /* STM32F40_41xxx */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* If an external clock source is used, then the value of the following define - should be set to the value of the external clock source, else, if no external - clock is used, keep this define commented */ -/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ - - -/* Uncomment the line below to expanse the "assert_param" macro in the - Standard Peripheral Library drivers code */ -/* #define USE_FULL_ASSERT 1 */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT - -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0) -#endif /* USE_FULL_ASSERT */ - -#endif /* __STM32F4xx_CONF_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm32f4xx_dac.c b/stm/stmperiph/stm32f4xx_dac.c deleted file mode 100644 index daff78d88..000000000 --- a/stm/stmperiph/stm32f4xx_dac.c +++ /dev/null @@ -1,714 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_dac.c - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief This file provides firmware functions to manage the following - * functionalities of the Digital-to-Analog Converter (DAC) peripheral: - * + DAC channels configuration: trigger, output buffer, data format - * + DMA management - * + Interrupts and flags management - * - @verbatim - =============================================================================== - ##### DAC Peripheral features ##### - =============================================================================== - [..] - *** DAC Channels *** - ==================== - [..] - The device integrates two 12-bit Digital Analog Converters that can - be used independently or simultaneously (dual mode): - (#) DAC channel1 with DAC_OUT1 (PA4) as output - (#) DAC channel2 with DAC_OUT2 (PA5) as output - - *** DAC Triggers *** - ==================== - [..] - Digital to Analog conversion can be non-triggered using DAC_Trigger_None - and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register - using DAC_SetChannel1Data() / DAC_SetChannel2Data() functions. - [..] - Digital to Analog conversion can be triggered by: - (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9. - The used pin (GPIOx_Pin9) must be configured in input mode. - - (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8 - (DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...) - The timer TRGO event should be selected using TIM_SelectOutputTrigger() - - (#) Software using DAC_Trigger_Software - - *** DAC Buffer mode feature *** - =============================== - [..] - Each DAC channel integrates an output buffer that can be used to - reduce the output impedance, and to drive external loads directly - without having to add an external operational amplifier. - To enable, the output buffer use - DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable; - [..] - (@) Refer to the device datasheet for more details about output - impedance value with and without output buffer. - - *** DAC wave generation feature *** - =================================== - [..] - Both DAC channels can be used to generate - (#) Noise wave using DAC_WaveGeneration_Noise - (#) Triangle wave using DAC_WaveGeneration_Triangle - - -@- Wave generation can be disabled using DAC_WaveGeneration_None - - *** DAC data format *** - ======================= - [..] - The DAC data format can be: - (#) 8-bit right alignment using DAC_Align_8b_R - (#) 12-bit left alignment using DAC_Align_12b_L - (#) 12-bit right alignment using DAC_Align_12b_R - - *** DAC data value to voltage correspondence *** - ================================================ - [..] - The analog output voltage on each DAC channel pin is determined - by the following equation: - DAC_OUTx = VREF+ * DOR / 4095 - with DOR is the Data Output Register - VEF+ is the input voltage reference (refer to the device datasheet) - e.g. To set DAC_OUT1 to 0.7V, use - DAC_SetChannel1Data(DAC_Align_12b_R, 868); - Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V - - *** DMA requests *** - ===================== - [..] - A DMA1 request can be generated when an external trigger (but not - a software trigger) occurs if DMA1 requests are enabled using - DAC_DMACmd() - [..] - DMA1 requests are mapped as following: - (#) DAC channel1 : mapped on DMA1 Stream5 channel7 which must be - already configured - (#) DAC channel2 : mapped on DMA1 Stream6 channel7 which must be - already configured - - - ##### How to use this driver ##### - =============================================================================== - [..] - (+) DAC APB clock must be enabled to get write access to DAC - registers using - RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE) - (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode. - (+) Configure the DAC channel using DAC_Init() function - (+) Enable the DAC channel using DAC_Cmd() function - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_dac.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup DAC - * @brief DAC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* CR register Mask */ -#define CR_CLEAR_MASK ((uint32_t)0x00000FFE) - -/* DAC Dual Channels SWTRIG masks */ -#define DUAL_SWTRIG_SET ((uint32_t)0x00000003) -#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC) - -/* DHR registers offsets */ -#define DHR12R1_OFFSET ((uint32_t)0x00000008) -#define DHR12R2_OFFSET ((uint32_t)0x00000014) -#define DHR12RD_OFFSET ((uint32_t)0x00000020) - -/* DOR register offset */ -#define DOR_OFFSET ((uint32_t)0x0000002C) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup DAC_Private_Functions - * @{ - */ - -/** @defgroup DAC_Group1 DAC channels configuration - * @brief DAC channels configuration: trigger, output buffer, data format - * -@verbatim - =============================================================================== - ##### DAC channels configuration: trigger, output buffer, data format ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the DAC peripheral registers to their default reset values. - * @param None - * @retval None - */ -void DAC_DeInit(void) -{ - /* Enable DAC reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); - /* Release DAC from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); -} - -/** - * @brief Initializes the DAC peripheral according to the specified parameters - * in the DAC_InitStruct. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that contains - * the configuration information for the specified DAC channel. - * @retval None - */ -void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - - /* Check the DAC parameters */ - assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger)); - assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration)); - assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude)); - assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer)); - -/*---------------------------- DAC CR Configuration --------------------------*/ - /* Get the DAC CR value */ - tmpreg1 = DAC->CR; - /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ - tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel); - /* Configure for the selected DAC channel: buffer output, trigger, - wave generation, mask/amplitude for wave generation */ - /* Set TSELx and TENx bits according to DAC_Trigger value */ - /* Set WAVEx bits according to DAC_WaveGeneration value */ - /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ - /* Set BOFFx bit according to DAC_OutputBuffer value */ - tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | - DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | \ - DAC_InitStruct->DAC_OutputBuffer); - /* Calculate CR register value depending on DAC_Channel */ - tmpreg1 |= tmpreg2 << DAC_Channel; - /* Write to DAC CR */ - DAC->CR = tmpreg1; -} - -/** - * @brief Fills each DAC_InitStruct member with its default value. - * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct) -{ -/*--------------- Reset DAC init structure parameters values -----------------*/ - /* Initialize the DAC_Trigger member */ - DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; - /* Initialize the DAC_WaveGeneration member */ - DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; - /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ - DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; - /* Initialize the DAC_OutputBuffer member */ - DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; -} - -/** - * @brief Enables or disables the specified DAC channel. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the DAC channel. - * This parameter can be: ENABLE or DISABLE. - * @note When the DAC channel is enabled the trigger source can no more be modified. - * @retval None - */ -void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DAC channel */ - DAC->CR |= (DAC_CR_EN1 << DAC_Channel); - } - else - { - /* Disable the selected DAC channel */ - DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel)); - } -} - -/** - * @brief Enables or disables the selected DAC channel software trigger. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the selected DAC channel software trigger. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable software trigger for the selected DAC channel */ - DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4); - } - else - { - /* Disable software trigger for the selected DAC channel */ - DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4)); - } -} - -/** - * @brief Enables or disables simultaneously the two DAC channels software triggers. - * @param NewState: new state of the DAC channels software triggers. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable software trigger for both DAC channels */ - DAC->SWTRIGR |= DUAL_SWTRIG_SET; - } - else - { - /* Disable software trigger for both DAC channels */ - DAC->SWTRIGR &= DUAL_SWTRIG_RESET; - } -} - -/** - * @brief Enables or disables the selected DAC channel wave generation. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_Wave: specifies the wave type to enable or disable. - * This parameter can be one of the following values: - * @arg DAC_Wave_Noise: noise wave generation - * @arg DAC_Wave_Triangle: triangle wave generation - * @param NewState: new state of the selected DAC channel wave generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_WAVE(DAC_Wave)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected wave generation for the selected DAC channel */ - DAC->CR |= DAC_Wave << DAC_Channel; - } - else - { - /* Disable the selected wave generation for the selected DAC channel */ - DAC->CR &= ~(DAC_Wave << DAC_Channel); - } -} - -/** - * @brief Set the specified data holding register value for DAC channel1. - * @param DAC_Align: Specifies the data alignment for DAC channel1. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data: Data to be loaded in the selected data holding register. - * @retval None - */ -void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data)); - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12R1_OFFSET + DAC_Align; - - /* Set the DAC channel1 selected data holding register */ - *(__IO uint32_t *) tmp = Data; -} - -/** - * @brief Set the specified data holding register value for DAC channel2. - * @param DAC_Align: Specifies the data alignment for DAC channel2. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data: Data to be loaded in the selected data holding register. - * @retval None - */ -void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data)); - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12R2_OFFSET + DAC_Align; - - /* Set the DAC channel2 selected data holding register */ - *(__IO uint32_t *)tmp = Data; -} - -/** - * @brief Set the specified data holding register value for dual channel DAC. - * @param DAC_Align: Specifies the data alignment for dual channel DAC. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data2: Data for DAC Channel2 to be loaded in the selected data holding register. - * @param Data1: Data for DAC Channel1 to be loaded in the selected data holding register. - * @note In dual mode, a unique register access is required to write in both - * DAC channels at the same time. - * @retval None - */ -void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) -{ - uint32_t data = 0, tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data1)); - assert_param(IS_DAC_DATA(Data2)); - - /* Calculate and set dual DAC data holding register value */ - if (DAC_Align == DAC_Align_8b_R) - { - data = ((uint32_t)Data2 << 8) | Data1; - } - else - { - data = ((uint32_t)Data2 << 16) | Data1; - } - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12RD_OFFSET + DAC_Align; - - /* Set the dual DAC selected data holding register */ - *(__IO uint32_t *)tmp = data; -} - -/** - * @brief Returns the last data output value of the selected DAC channel. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @retval The selected DAC channel data output value. - */ -uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - - tmp = (uint32_t) DAC_BASE ; - tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2); - - /* Returns the DAC channel data output register value */ - return (uint16_t) (*(__IO uint32_t*) tmp); -} -/** - * @} - */ - -/** @defgroup DAC_Group2 DMA management functions - * @brief DMA management functions - * -@verbatim - =============================================================================== - ##### DMA management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified DAC channel DMA request. - * @note When enabled DMA1 is generated when an external trigger (EXTI Line9, - * TIM2, TIM4, TIM5, TIM6, TIM7 or TIM8 but not a software trigger) occurs. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the selected DAC channel DMA request. - * This parameter can be: ENABLE or DISABLE. - * @note The DAC channel1 is mapped on DMA1 Stream 5 channel7 which must be - * already configured. - * @note The DAC channel2 is mapped on DMA1 Stream 6 channel7 which must be - * already configured. - * @retval None - */ -void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DAC channel DMA request */ - DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel); - } - else - { - /* Disable the selected DAC channel DMA request */ - DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel)); - } -} -/** - * @} - */ - -/** @defgroup DAC_Group3 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified DAC interrupts. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @note The DMA underrun occurs when a second external trigger arrives before the - * acknowledgement for the first external trigger is received (first request). - * @param NewState: new state of the specified DAC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_DAC_IT(DAC_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected DAC interrupts */ - DAC->CR |= (DAC_IT << DAC_Channel); - } - else - { - /* Disable the selected DAC interrupts */ - DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel)); - } -} - -/** - * @brief Checks whether the specified DAC flag is set or not. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_FLAG: specifies the flag to check. - * This parameter can be only of the following value: - * @arg DAC_FLAG_DMAUDR: DMA underrun flag - * @note The DMA underrun occurs when a second external trigger arrives before the - * acknowledgement for the first external trigger is received (first request). - * @retval The new state of DAC_FLAG (SET or RESET). - */ -FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_FLAG(DAC_FLAG)); - - /* Check the status of the specified DAC flag */ - if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET) - { - /* DAC_FLAG is set */ - bitstatus = SET; - } - else - { - /* DAC_FLAG is reset */ - bitstatus = RESET; - } - /* Return the DAC_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the DAC channel's pending flags. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_FLAG: specifies the flag to clear. - * This parameter can be of the following value: - * @arg DAC_FLAG_DMAUDR: DMA underrun flag - * @note The DMA underrun occurs when a second external trigger arrives before the - * acknowledgement for the first external trigger is received (first request). - * @retval None - */ -void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_FLAG(DAC_FLAG)); - - /* Clear the selected DAC flags */ - DAC->SR = (DAC_FLAG << DAC_Channel); -} - -/** - * @brief Checks whether the specified DAC interrupt has occurred or not. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt source to check. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @note The DMA underrun occurs when a second external trigger arrives before the - * acknowledgement for the first external trigger is received (first request). - * @retval The new state of DAC_IT (SET or RESET). - */ -ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_IT(DAC_IT)); - - /* Get the DAC_IT enable bit status */ - enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ; - - /* Check the status of the specified DAC interrupt */ - if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus) - { - /* DAC_IT is set */ - bitstatus = SET; - } - else - { - /* DAC_IT is reset */ - bitstatus = RESET; - } - /* Return the DAC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the DAC channel's interrupt pending bits. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt pending bit to clear. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @note The DMA underrun occurs when a second external trigger arrives before the - * acknowledgement for the first external trigger is received (first request). - * @retval None - */ -void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_IT(DAC_IT)); - - /* Clear the selected DAC interrupt pending bits */ - DAC->SR = (DAC_IT << DAC_Channel); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm32f4xx_dac.h b/stm/stmperiph/stm32f4xx_dac.h deleted file mode 100644 index 224bec1a1..000000000 --- a/stm/stmperiph/stm32f4xx_dac.h +++ /dev/null @@ -1,304 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_dac.h - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief This file contains all the functions prototypes for the DAC firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_DAC_H -#define __STM32F4xx_DAC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DAC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief DAC Init structure definition - */ - -typedef struct -{ - uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. - This parameter can be a value of @ref DAC_trigger_selection */ - - uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves - are generated, or whether no wave is generated. - This parameter can be a value of @ref DAC_wave_generation */ - - uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or - the maximum amplitude triangle generation for the DAC channel. - This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ - - uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. - This parameter can be a value of @ref DAC_output_buffer */ -}DAC_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DAC_Exported_Constants - * @{ - */ - -/** @defgroup DAC_trigger_selection - * @{ - */ - -#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register - has been loaded, and not by external trigger */ -#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ - -#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */ - -#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ - ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T8_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T5_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T4_TRGO) || \ - ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ - ((TRIGGER) == DAC_Trigger_Software)) - -/** - * @} - */ - -/** @defgroup DAC_wave_generation - * @{ - */ - -#define DAC_WaveGeneration_None ((uint32_t)0x00000000) -#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) -#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) -#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ - ((WAVE) == DAC_WaveGeneration_Noise) || \ - ((WAVE) == DAC_WaveGeneration_Triangle)) -/** - * @} - */ - -/** @defgroup DAC_lfsrunmask_triangleamplitude - * @{ - */ - -#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ -#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ -#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ -#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ -#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ -#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ -#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ -#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ -#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ -#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ -#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ -#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ -#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ -#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ - -#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ - ((VALUE) == DAC_TriangleAmplitude_1) || \ - ((VALUE) == DAC_TriangleAmplitude_3) || \ - ((VALUE) == DAC_TriangleAmplitude_7) || \ - ((VALUE) == DAC_TriangleAmplitude_15) || \ - ((VALUE) == DAC_TriangleAmplitude_31) || \ - ((VALUE) == DAC_TriangleAmplitude_63) || \ - ((VALUE) == DAC_TriangleAmplitude_127) || \ - ((VALUE) == DAC_TriangleAmplitude_255) || \ - ((VALUE) == DAC_TriangleAmplitude_511) || \ - ((VALUE) == DAC_TriangleAmplitude_1023) || \ - ((VALUE) == DAC_TriangleAmplitude_2047) || \ - ((VALUE) == DAC_TriangleAmplitude_4095)) -/** - * @} - */ - -/** @defgroup DAC_output_buffer - * @{ - */ - -#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) -#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) -#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ - ((STATE) == DAC_OutputBuffer_Disable)) -/** - * @} - */ - -/** @defgroup DAC_Channel_selection - * @{ - */ - -#define DAC_Channel_1 ((uint32_t)0x00000000) -#define DAC_Channel_2 ((uint32_t)0x00000010) -#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ - ((CHANNEL) == DAC_Channel_2)) -/** - * @} - */ - -/** @defgroup DAC_data_alignement - * @{ - */ - -#define DAC_Align_12b_R ((uint32_t)0x00000000) -#define DAC_Align_12b_L ((uint32_t)0x00000004) -#define DAC_Align_8b_R ((uint32_t)0x00000008) -#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ - ((ALIGN) == DAC_Align_12b_L) || \ - ((ALIGN) == DAC_Align_8b_R)) -/** - * @} - */ - -/** @defgroup DAC_wave_generation - * @{ - */ - -#define DAC_Wave_Noise ((uint32_t)0x00000040) -#define DAC_Wave_Triangle ((uint32_t)0x00000080) -#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ - ((WAVE) == DAC_Wave_Triangle)) -/** - * @} - */ - -/** @defgroup DAC_data - * @{ - */ - -#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) -/** - * @} - */ - -/** @defgroup DAC_interrupts_definition - * @{ - */ -#define DAC_IT_DMAUDR ((uint32_t)0x00002000) -#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) - -/** - * @} - */ - -/** @defgroup DAC_flags_definition - * @{ - */ - -#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) -#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the DAC configuration to the default reset state *****/ -void DAC_DeInit(void); - -/* DAC channels configuration: trigger, output buffer, data format functions */ -void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); -void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); -void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); -void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); -void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); -void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); -void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); -void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); -void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); -uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); - -/* DMA management functions ***************************************************/ -void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState); -FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG); -void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG); -ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT); -void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_DAC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm32f4xx_dma.c b/stm/stmperiph/stm32f4xx_dma.c deleted file mode 100644 index ef86764ea..000000000 --- a/stm/stmperiph/stm32f4xx_dma.c +++ /dev/null @@ -1,1301 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_dma.c - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief This file provides firmware functions to manage the following - * functionalities of the Direct Memory Access controller (DMA): - * + Initialization and Configuration - * + Data Counter - * + Double Buffer mode configuration and command - * + Interrupts and flags management - * - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - (#) Enable The DMA controller clock using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA1, ENABLE) - function for DMA1 or using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2, ENABLE) - function for DMA2. - - (#) Enable and configure the peripheral to be connected to the DMA Stream - (except for internal SRAM / FLASH memories: no initialization is - necessary). - - (#) For a given Stream, program the required configuration through following parameters: - Source and Destination addresses, Transfer Direction, Transfer size, Source and Destination - data formats, Circular or Normal mode, Stream Priority level, Source and Destination - Incrementation mode, FIFO mode and its Threshold (if needed), Burst - mode for Source and/or Destination (if needed) using the DMA_Init() function. - To avoid filling unneccessary fields, you can call DMA_StructInit() function - to initialize a given structure with default values (reset values), the modify - only necessary fields - (ie. Source and Destination addresses, Transfer size and Data Formats). - - (#) Enable the NVIC and the corresponding interrupt(s) using the function - DMA_ITConfig() if you need to use DMA interrupts. - - (#) Optionally, if the Circular mode is enabled, you can use the Double buffer mode by configuring - the second Memory address and the first Memory to be used through the function - DMA_DoubleBufferModeConfig(). Then enable the Double buffer mode through the function - DMA_DoubleBufferModeCmd(). These operations must be done before step 6. - - (#) Enable the DMA stream using the DMA_Cmd() function. - - (#) Activate the needed Stream Request using PPP_DMACmd() function for - any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...) - The function allowing this operation is provided in each PPP peripheral - driver (ie. SPI_DMACmd for SPI peripheral). - Once the Stream is enabled, it is not possible to modify its configuration - unless the stream is stopped and disabled. - After enabling the Stream, it is advised to monitor the EN bit status using - the function DMA_GetCmdStatus(). In case of configuration errors or bus errors - this bit will remain reset and all transfers on this Stream will remain on hold. - - (#) Optionally, you can configure the number of data to be transferred - when the Stream is disabled (ie. after each Transfer Complete event - or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter(). - And you can get the number of remaining data to be transferred using - the function DMA_GetCurrDataCounter() at run time (when the DMA Stream is - enabled and running). - - (#) To control DMA events you can use one of the following two methods: - (##) Check on DMA Stream flags using the function DMA_GetFlagStatus(). - (##) Use DMA interrupts through the function DMA_ITConfig() at initialization - phase and DMA_GetITStatus() function into interrupt routines in - communication phase. - [..] - After checking on a flag you should clear it using DMA_ClearFlag() - function. And after checking on an interrupt event you should - clear it using DMA_ClearITPendingBit() function. - - (#) Optionally, if Circular mode and Double Buffer mode are enabled, you can modify - the Memory Addresses using the function DMA_MemoryTargetConfig(). Make sure that - the Memory Address to be modified is not the one currently in use by DMA Stream. - This condition can be monitored using the function DMA_GetCurrentMemoryTarget(). - - (#) Optionally, Pause-Resume operations may be performed: - The DMA_Cmd() function may be used to perform Pause-Resume operation. - When a transfer is ongoing, calling this function to disable the - Stream will cause the transfer to be paused. All configuration registers - and the number of remaining data will be preserved. When calling again - this function to re-enable the Stream, the transfer will be resumed from - the point where it was paused. - - -@- Memory-to-Memory transfer is possible by setting the address of the memory into - the Peripheral registers. In this mode, Circular mode and Double Buffer mode - are not allowed. - - -@- The FIFO is used mainly to reduce bus usage and to allow data - packing/unpacking: it is possible to set different Data Sizes for - the Peripheral and the Memory (ie. you can set Half-Word data size - for the peripheral to access its data register and set Word data size - for the Memory to gain in access time. Each two Half-words will be - packed and written in a single access to a Word in the Memory). - - -@- When FIFO is disabled, it is not allowed to configure different - Data Sizes for Source and Destination. In this case the Peripheral - Data Size will be applied to both Source and Destination. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_dma.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup DMA - * @brief DMA driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* Masks Definition */ -#define TRANSFER_IT_ENABLE_MASK (uint32_t)(DMA_SxCR_TCIE | DMA_SxCR_HTIE | \ - DMA_SxCR_TEIE | DMA_SxCR_DMEIE) - -#define DMA_Stream0_IT_MASK (uint32_t)(DMA_LISR_FEIF0 | DMA_LISR_DMEIF0 | \ - DMA_LISR_TEIF0 | DMA_LISR_HTIF0 | \ - DMA_LISR_TCIF0) - -#define DMA_Stream1_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 6) -#define DMA_Stream2_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 16) -#define DMA_Stream3_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 22) -#define DMA_Stream4_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK | (uint32_t)0x20000000) -#define DMA_Stream5_IT_MASK (uint32_t)(DMA_Stream1_IT_MASK | (uint32_t)0x20000000) -#define DMA_Stream6_IT_MASK (uint32_t)(DMA_Stream2_IT_MASK | (uint32_t)0x20000000) -#define DMA_Stream7_IT_MASK (uint32_t)(DMA_Stream3_IT_MASK | (uint32_t)0x20000000) -#define TRANSFER_IT_MASK (uint32_t)0x0F3C0F3C -#define HIGH_ISR_MASK (uint32_t)0x20000000 -#define RESERVED_MASK (uint32_t)0x0F7D0F7D - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - - -/** @defgroup DMA_Private_Functions - * @{ - */ - -/** @defgroup DMA_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to initialize the DMA Stream source - and destination addresses, incrementation and data sizes, transfer direction, - buffer size, circular/normal mode selection, memory-to-memory mode selection - and Stream priority value. - [..] - The DMA_Init() function follows the DMA configuration procedures as described in - reference manual (RM0090) except the first point: waiting on EN bit to be reset. - This condition should be checked by user application using the function DMA_GetCmdStatus() - before calling the DMA_Init() function. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitialize the DMAy Streamx registers to their default reset values. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @retval None - */ -void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - - /* Disable the selected DMAy Streamx */ - DMAy_Streamx->CR &= ~((uint32_t)DMA_SxCR_EN); - - /* Reset DMAy Streamx control register */ - DMAy_Streamx->CR = 0; - - /* Reset DMAy Streamx Number of Data to Transfer register */ - DMAy_Streamx->NDTR = 0; - - /* Reset DMAy Streamx peripheral address register */ - DMAy_Streamx->PAR = 0; - - /* Reset DMAy Streamx memory 0 address register */ - DMAy_Streamx->M0AR = 0; - - /* Reset DMAy Streamx memory 1 address register */ - DMAy_Streamx->M1AR = 0; - - /* Reset DMAy Streamx FIFO control register */ - DMAy_Streamx->FCR = (uint32_t)0x00000021; - - /* Reset interrupt pending bits for the selected stream */ - if (DMAy_Streamx == DMA1_Stream0) - { - /* Reset interrupt pending bits for DMA1 Stream0 */ - DMA1->LIFCR = DMA_Stream0_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream1) - { - /* Reset interrupt pending bits for DMA1 Stream1 */ - DMA1->LIFCR = DMA_Stream1_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream2) - { - /* Reset interrupt pending bits for DMA1 Stream2 */ - DMA1->LIFCR = DMA_Stream2_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream3) - { - /* Reset interrupt pending bits for DMA1 Stream3 */ - DMA1->LIFCR = DMA_Stream3_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream4) - { - /* Reset interrupt pending bits for DMA1 Stream4 */ - DMA1->HIFCR = DMA_Stream4_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream5) - { - /* Reset interrupt pending bits for DMA1 Stream5 */ - DMA1->HIFCR = DMA_Stream5_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream6) - { - /* Reset interrupt pending bits for DMA1 Stream6 */ - DMA1->HIFCR = (uint32_t)DMA_Stream6_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream7) - { - /* Reset interrupt pending bits for DMA1 Stream7 */ - DMA1->HIFCR = DMA_Stream7_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream0) - { - /* Reset interrupt pending bits for DMA2 Stream0 */ - DMA2->LIFCR = DMA_Stream0_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream1) - { - /* Reset interrupt pending bits for DMA2 Stream1 */ - DMA2->LIFCR = DMA_Stream1_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream2) - { - /* Reset interrupt pending bits for DMA2 Stream2 */ - DMA2->LIFCR = DMA_Stream2_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream3) - { - /* Reset interrupt pending bits for DMA2 Stream3 */ - DMA2->LIFCR = DMA_Stream3_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream4) - { - /* Reset interrupt pending bits for DMA2 Stream4 */ - DMA2->HIFCR = DMA_Stream4_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream5) - { - /* Reset interrupt pending bits for DMA2 Stream5 */ - DMA2->HIFCR = DMA_Stream5_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream6) - { - /* Reset interrupt pending bits for DMA2 Stream6 */ - DMA2->HIFCR = DMA_Stream6_IT_MASK; - } - else - { - if (DMAy_Streamx == DMA2_Stream7) - { - /* Reset interrupt pending bits for DMA2 Stream7 */ - DMA2->HIFCR = DMA_Stream7_IT_MASK; - } - } -} - -/** - * @brief Initializes the DMAy Streamx according to the specified parameters in - * the DMA_InitStruct structure. - * @note Before calling this function, it is recommended to check that the Stream - * is actually disabled using the function DMA_GetCmdStatus(). - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval None - */ -void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_CHANNEL(DMA_InitStruct->DMA_Channel)); - assert_param(IS_DMA_DIRECTION(DMA_InitStruct->DMA_DIR)); - assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); - assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); - assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); - assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); - assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); - assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); - assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); - assert_param(IS_DMA_FIFO_MODE_STATE(DMA_InitStruct->DMA_FIFOMode)); - assert_param(IS_DMA_FIFO_THRESHOLD(DMA_InitStruct->DMA_FIFOThreshold)); - assert_param(IS_DMA_MEMORY_BURST(DMA_InitStruct->DMA_MemoryBurst)); - assert_param(IS_DMA_PERIPHERAL_BURST(DMA_InitStruct->DMA_PeripheralBurst)); - - /*------------------------- DMAy Streamx CR Configuration ------------------*/ - /* Get the DMAy_Streamx CR value */ - tmpreg = DMAy_Streamx->CR; - - /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ - tmpreg &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ - DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ - DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ - DMA_SxCR_DIR)); - - /* Configure DMAy Streamx: */ - /* Set CHSEL bits according to DMA_CHSEL value */ - /* Set DIR bits according to DMA_DIR value */ - /* Set PINC bit according to DMA_PeripheralInc value */ - /* Set MINC bit according to DMA_MemoryInc value */ - /* Set PSIZE bits according to DMA_PeripheralDataSize value */ - /* Set MSIZE bits according to DMA_MemoryDataSize value */ - /* Set CIRC bit according to DMA_Mode value */ - /* Set PL bits according to DMA_Priority value */ - /* Set MBURST bits according to DMA_MemoryBurst value */ - /* Set PBURST bits according to DMA_PeripheralBurst value */ - tmpreg |= DMA_InitStruct->DMA_Channel | DMA_InitStruct->DMA_DIR | - DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | - DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | - DMA_InitStruct->DMA_Mode | DMA_InitStruct->DMA_Priority | - DMA_InitStruct->DMA_MemoryBurst | DMA_InitStruct->DMA_PeripheralBurst; - - /* Write to DMAy Streamx CR register */ - DMAy_Streamx->CR = tmpreg; - - /*------------------------- DMAy Streamx FCR Configuration -----------------*/ - /* Get the DMAy_Streamx FCR value */ - tmpreg = DMAy_Streamx->FCR; - - /* Clear DMDIS and FTH bits */ - tmpreg &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); - - /* Configure DMAy Streamx FIFO: - Set DMDIS bits according to DMA_FIFOMode value - Set FTH bits according to DMA_FIFOThreshold value */ - tmpreg |= DMA_InitStruct->DMA_FIFOMode | DMA_InitStruct->DMA_FIFOThreshold; - - /* Write to DMAy Streamx CR */ - DMAy_Streamx->FCR = tmpreg; - - /*------------------------- DMAy Streamx NDTR Configuration ----------------*/ - /* Write to DMAy Streamx NDTR register */ - DMAy_Streamx->NDTR = DMA_InitStruct->DMA_BufferSize; - - /*------------------------- DMAy Streamx PAR Configuration -----------------*/ - /* Write to DMAy Streamx PAR */ - DMAy_Streamx->PAR = DMA_InitStruct->DMA_PeripheralBaseAddr; - - /*------------------------- DMAy Streamx M0AR Configuration ----------------*/ - /* Write to DMAy Streamx M0AR */ - DMAy_Streamx->M0AR = DMA_InitStruct->DMA_Memory0BaseAddr; -} - -/** - * @brief Fills each DMA_InitStruct member with its default value. - * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) -{ - /*-------------- Reset DMA init structure parameters values ----------------*/ - /* Initialize the DMA_Channel member */ - DMA_InitStruct->DMA_Channel = 0; - - /* Initialize the DMA_PeripheralBaseAddr member */ - DMA_InitStruct->DMA_PeripheralBaseAddr = 0; - - /* Initialize the DMA_Memory0BaseAddr member */ - DMA_InitStruct->DMA_Memory0BaseAddr = 0; - - /* Initialize the DMA_DIR member */ - DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralToMemory; - - /* Initialize the DMA_BufferSize member */ - DMA_InitStruct->DMA_BufferSize = 0; - - /* Initialize the DMA_PeripheralInc member */ - DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; - - /* Initialize the DMA_MemoryInc member */ - DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; - - /* Initialize the DMA_PeripheralDataSize member */ - DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - - /* Initialize the DMA_MemoryDataSize member */ - DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - - /* Initialize the DMA_Mode member */ - DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; - - /* Initialize the DMA_Priority member */ - DMA_InitStruct->DMA_Priority = DMA_Priority_Low; - - /* Initialize the DMA_FIFOMode member */ - DMA_InitStruct->DMA_FIFOMode = DMA_FIFOMode_Disable; - - /* Initialize the DMA_FIFOThreshold member */ - DMA_InitStruct->DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull; - - /* Initialize the DMA_MemoryBurst member */ - DMA_InitStruct->DMA_MemoryBurst = DMA_MemoryBurst_Single; - - /* Initialize the DMA_PeripheralBurst member */ - DMA_InitStruct->DMA_PeripheralBurst = DMA_PeripheralBurst_Single; -} - -/** - * @brief Enables or disables the specified DMAy Streamx. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param NewState: new state of the DMAy Streamx. - * This parameter can be: ENABLE or DISABLE. - * - * @note This function may be used to perform Pause-Resume operation. When a - * transfer is ongoing, calling this function to disable the Stream will - * cause the transfer to be paused. All configuration registers and the - * number of remaining data will be preserved. When calling again this - * function to re-enable the Stream, the transfer will be resumed from - * the point where it was paused. - * - * @note After configuring the DMA Stream (DMA_Init() function) and enabling the - * stream, it is recommended to check (or wait until) the DMA Stream is - * effectively enabled. A Stream may remain disabled if a configuration - * parameter is wrong. - * After disabling a DMA Stream, it is also recommended to check (or wait - * until) the DMA Stream is effectively disabled. If a Stream is disabled - * while a data transfer is ongoing, the current data will be transferred - * and the Stream will be effectively disabled only after the transfer of - * this single data is finished. - * - * @retval None - */ -void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DMAy Streamx by setting EN bit */ - DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_EN; - } - else - { - /* Disable the selected DMAy Streamx by clearing EN bit */ - DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_EN; - } -} - -/** - * @brief Configures, when the PINC (Peripheral Increment address mode) bit is - * set, if the peripheral address should be incremented with the data - * size (configured with PSIZE bits) or by a fixed offset equal to 4 - * (32-bit aligned addresses). - * - * @note This function has no effect if the Peripheral Increment mode is disabled. - * - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_Pincos: specifies the Peripheral increment offset size. - * This parameter can be one of the following values: - * @arg DMA_PINCOS_Psize: Peripheral address increment is done - * accordingly to PSIZE parameter. - * @arg DMA_PINCOS_WordAligned: Peripheral address increment offset is - * fixed to 4 (32-bit aligned addresses). - * @retval None - */ -void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_PINCOS_SIZE(DMA_Pincos)); - - /* Check the needed Peripheral increment offset */ - if(DMA_Pincos != DMA_PINCOS_Psize) - { - /* Configure DMA_SxCR_PINCOS bit with the input parameter */ - DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PINCOS; - } - else - { - /* Clear the PINCOS bit: Peripheral address incremented according to PSIZE */ - DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PINCOS; - } -} - -/** - * @brief Configures, when the DMAy Streamx is disabled, the flow controller for - * the next transactions (Peripheral or Memory). - * - * @note Before enabling this feature, check if the used peripheral supports - * the Flow Controller mode or not. - * - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_FlowCtrl: specifies the DMA flow controller. - * This parameter can be one of the following values: - * @arg DMA_FlowCtrl_Memory: DMAy_Streamx transactions flow controller is - * the DMA controller. - * @arg DMA_FlowCtrl_Peripheral: DMAy_Streamx transactions flow controller - * is the peripheral. - * @retval None - */ -void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_FLOW_CTRL(DMA_FlowCtrl)); - - /* Check the needed flow controller */ - if(DMA_FlowCtrl != DMA_FlowCtrl_Memory) - { - /* Configure DMA_SxCR_PFCTRL bit with the input parameter */ - DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PFCTRL; - } - else - { - /* Clear the PFCTRL bit: Memory is the flow controller */ - DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PFCTRL; - } -} -/** - * @} - */ - -/** @defgroup DMA_Group2 Data Counter functions - * @brief Data Counter functions - * -@verbatim - =============================================================================== - ##### Data Counter functions ##### - =============================================================================== - [..] - This subsection provides function allowing to configure and read the buffer size - (number of data to be transferred). - [..] - The DMA data counter can be written only when the DMA Stream is disabled - (ie. after transfer complete event). - [..] - The following function can be used to write the Stream data counter value: - (+) void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter); - -@- It is advised to use this function rather than DMA_Init() in situations - where only the Data buffer needs to be reloaded. - -@- If the Source and Destination Data Sizes are different, then the value - written in data counter, expressing the number of transfers, is relative - to the number of transfers from the Peripheral point of view. - ie. If Memory data size is Word, Peripheral data size is Half-Words, - then the value to be configured in the data counter is the number - of Half-Words to be transferred from/to the peripheral. - [..] - The DMA data counter can be read to indicate the number of remaining transfers for - the relative DMA Stream. This counter is decremented at the end of each data - transfer and when the transfer is complete: - (+) If Normal mode is selected: the counter is set to 0. - (+) If Circular mode is selected: the counter is reloaded with the initial value - (configured before enabling the DMA Stream) - [..] - The following function can be used to read the Stream data counter value: - (+) uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx); - -@endverbatim - * @{ - */ - -/** - * @brief Writes the number of data units to be transferred on the DMAy Streamx. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param Counter: Number of data units to be transferred (from 0 to 65535) - * Number of data items depends only on the Peripheral data format. - * - * @note If Peripheral data format is Bytes: number of data units is equal - * to total number of bytes to be transferred. - * - * @note If Peripheral data format is Half-Word: number of data units is - * equal to total number of bytes to be transferred / 2. - * - * @note If Peripheral data format is Word: number of data units is equal - * to total number of bytes to be transferred / 4. - * - * @note In Memory-to-Memory transfer mode, the memory buffer pointed by - * DMAy_SxPAR register is considered as Peripheral. - * - * @retval The number of remaining data units in the current DMAy Streamx transfer. - */ -void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - - /* Write the number of data units to be transferred */ - DMAy_Streamx->NDTR = (uint16_t)Counter; -} - -/** - * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @retval The number of remaining data units in the current DMAy Streamx transfer. - */ -uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - - /* Return the number of remaining data units for DMAy Streamx */ - return ((uint16_t)(DMAy_Streamx->NDTR)); -} -/** - * @} - */ - -/** @defgroup DMA_Group3 Double Buffer mode functions - * @brief Double Buffer mode functions - * -@verbatim - =============================================================================== - ##### Double Buffer mode functions ##### - =============================================================================== - [..] - This subsection provides function allowing to configure and control the double - buffer mode parameters. - - [..] - The Double Buffer mode can be used only when Circular mode is enabled. - The Double Buffer mode cannot be used when transferring data from Memory to Memory. - - [..] - The Double Buffer mode allows to set two different Memory addresses from/to which - the DMA controller will access alternatively (after completing transfer to/from - target memory 0, it will start transfer to/from target memory 1). - This allows to reduce software overhead for double buffering and reduce the CPU - access time. - - [..] - Two functions must be called before calling the DMA_Init() function: - (+) void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, - uint32_t Memory1BaseAddr, uint32_t DMA_CurrentMemory); - (+) void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState); - - [..] - DMA_DoubleBufferModeConfig() is called to configure the Memory 1 base address - and the first Memory target from/to which the transfer will start after - enabling the DMA Stream. Then DMA_DoubleBufferModeCmd() must be called - to enable the Double Buffer mode (or disable it when it should not be used). - - [..] - Two functions can be called dynamically when the transfer is ongoing (or when the DMA Stream is - stopped) to modify on of the target Memories addresses or to check wich Memory target is currently - used: - (+) void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, - uint32_t MemoryBaseAddr, uint32_t DMA_MemoryTarget); - (+) uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx); - - [..] - DMA_MemoryTargetConfig() can be called to modify the base address of one of - the two target Memories. - The Memory of which the base address will be modified must not be currently - be used by the DMA Stream (ie. if the DMA Stream is currently transferring - from Memory 1 then you can only modify base address of target Memory 0 and vice versa). - To check this condition, it is recommended to use the function DMA_GetCurrentMemoryTarget() which - returns the index of the Memory target currently in use by the DMA Stream. - -@endverbatim - * @{ - */ - -/** - * @brief Configures, when the DMAy Streamx is disabled, the double buffer mode - * and the current memory target. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param Memory1BaseAddr: the base address of the second buffer (Memory 1) - * @param DMA_CurrentMemory: specifies which memory will be first buffer for - * the transactions when the Stream will be enabled. - * This parameter can be one of the following values: - * @arg DMA_Memory_0: Memory 0 is the current buffer. - * @arg DMA_Memory_1: Memory 1 is the current buffer. - * - * @note Memory0BaseAddr is set by the DMA structure configuration in DMA_Init(). - * - * @retval None - */ -void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr, - uint32_t DMA_CurrentMemory) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_CURRENT_MEM(DMA_CurrentMemory)); - - if (DMA_CurrentMemory != DMA_Memory_0) - { - /* Set Memory 1 as current memory address */ - DMAy_Streamx->CR |= (uint32_t)(DMA_SxCR_CT); - } - else - { - /* Set Memory 0 as current memory address */ - DMAy_Streamx->CR &= ~(uint32_t)(DMA_SxCR_CT); - } - - /* Write to DMAy Streamx M1AR */ - DMAy_Streamx->M1AR = Memory1BaseAddr; -} - -/** - * @brief Enables or disables the double buffer mode for the selected DMA stream. - * @note This function can be called only when the DMA Stream is disabled. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param NewState: new state of the DMAy Streamx double buffer mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Configure the Double Buffer mode */ - if (NewState != DISABLE) - { - /* Enable the Double buffer mode */ - DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_DBM; - } - else - { - /* Disable the Double buffer mode */ - DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_DBM; - } -} - -/** - * @brief Configures the Memory address for the next buffer transfer in double - * buffer mode (for dynamic use). This function can be called when the - * DMA Stream is enabled and when the transfer is ongoing. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param MemoryBaseAddr: The base address of the target memory buffer - * @param DMA_MemoryTarget: Next memory target to be used. - * This parameter can be one of the following values: - * @arg DMA_Memory_0: To use the memory address 0 - * @arg DMA_Memory_1: To use the memory address 1 - * - * @note It is not allowed to modify the Base Address of a target Memory when - * this target is involved in the current transfer. ie. If the DMA Stream - * is currently transferring to/from Memory 1, then it not possible to - * modify Base address of Memory 1, but it is possible to modify Base - * address of Memory 0. - * To know which Memory is currently used, you can use the function - * DMA_GetCurrentMemoryTarget(). - * - * @retval None - */ -void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr, - uint32_t DMA_MemoryTarget) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_CURRENT_MEM(DMA_MemoryTarget)); - - /* Check the Memory target to be configured */ - if (DMA_MemoryTarget != DMA_Memory_0) - { - /* Write to DMAy Streamx M1AR */ - DMAy_Streamx->M1AR = MemoryBaseAddr; - } - else - { - /* Write to DMAy Streamx M0AR */ - DMAy_Streamx->M0AR = MemoryBaseAddr; - } -} - -/** - * @brief Returns the current memory target used by double buffer transfer. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @retval The memory target number: 0 for Memory0 or 1 for Memory1. - */ -uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - - /* Get the current memory target */ - if ((DMAy_Streamx->CR & DMA_SxCR_CT) != 0) - { - /* Current memory buffer used is Memory 1 */ - tmp = 1; - } - else - { - /* Current memory buffer used is Memory 0 */ - tmp = 0; - } - return tmp; -} -/** - * @} - */ - -/** @defgroup DMA_Group4 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Check the DMA enable status - (+) Check the FIFO status - (+) Configure the DMA Interrupts sources and check or clear the flags or - pending bits status. - - [..] - (#) DMA Enable status: - After configuring the DMA Stream (DMA_Init() function) and enabling - the stream, it is recommended to check (or wait until) the DMA Stream - is effectively enabled. A Stream may remain disabled if a configuration - parameter is wrong. After disabling a DMA Stream, it is also recommended - to check (or wait until) the DMA Stream is effectively disabled. - If a Stream is disabled while a data transfer is ongoing, the current - data will be transferred and the Stream will be effectively disabled - only after this data transfer completion. - To monitor this state it is possible to use the following function: - (++) FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx); - - (#) FIFO Status: - It is possible to monitor the FIFO status when a transfer is ongoing - using the following function: - (++) uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx); - - (#) DMA Interrupts and Flags: - The user should identify which mode will be used in his application - to manage the DMA controller events: Polling mode or Interrupt mode. - - *** Polling Mode *** - ==================== - [..] - Each DMA stream can be managed through 4 event Flags: - (x : DMA Stream number ) - (#) DMA_FLAG_FEIFx : to indicate that a FIFO Mode Transfer Error event occurred. - (#) DMA_FLAG_DMEIFx : to indicate that a Direct Mode Transfer Error event occurred. - (#) DMA_FLAG_TEIFx : to indicate that a Transfer Error event occurred. - (#) DMA_FLAG_HTIFx : to indicate that a Half-Transfer Complete event occurred. - (#) DMA_FLAG_TCIFx : to indicate that a Transfer Complete event occurred . - [..] - In this Mode it is advised to use the following functions: - (+) FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); - (+) void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); - - *** Interrupt Mode *** - ====================== - [..] - Each DMA Stream can be managed through 4 Interrupts: - - *** Interrupt Source *** - ======================== - [..] - (#) DMA_IT_FEIFx : specifies the interrupt source for the FIFO Mode Transfer Error event. - (#) DMA_IT_DMEIFx : specifies the interrupt source for the Direct Mode Transfer Error event. - (#) DMA_IT_TEIFx : specifies the interrupt source for the Transfer Error event. - (#) DMA_IT_HTIFx : specifies the interrupt source for the Half-Transfer Complete event. - (#) DMA_IT_TCIFx : specifies the interrupt source for the a Transfer Complete event. - [..] - In this Mode it is advised to use the following functions: - (+) void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState); - (+) ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); - (+) void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); - -@endverbatim - * @{ - */ - -/** - * @brief Returns the status of EN bit for the specified DMAy Streamx. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * - * @note After configuring the DMA Stream (DMA_Init() function) and enabling - * the stream, it is recommended to check (or wait until) the DMA Stream - * is effectively enabled. A Stream may remain disabled if a configuration - * parameter is wrong. - * After disabling a DMA Stream, it is also recommended to check (or wait - * until) the DMA Stream is effectively disabled. If a Stream is disabled - * while a data transfer is ongoing, the current data will be transferred - * and the Stream will be effectively disabled only after the transfer - * of this single data is finished. - * - * @retval Current state of the DMAy Streamx (ENABLE or DISABLE). - */ -FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx) -{ - FunctionalState state = DISABLE; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - - if ((DMAy_Streamx->CR & (uint32_t)DMA_SxCR_EN) != 0) - { - /* The selected DMAy Streamx EN bit is set (DMA is still transferring) */ - state = ENABLE; - } - else - { - /* The selected DMAy Streamx EN bit is cleared (DMA is disabled and - all transfers are complete) */ - state = DISABLE; - } - return state; -} - -/** - * @brief Returns the current DMAy Streamx FIFO filled level. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @retval The FIFO filling state. - * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full - * and not empty. - * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. - * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. - * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. - * - DMA_FIFOStatus_Empty: when FIFO is empty - * - DMA_FIFOStatus_Full: when FIFO is full - */ -uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - - /* Get the FIFO level bits */ - tmpreg = (uint32_t)((DMAy_Streamx->FCR & DMA_SxFCR_FS)); - - return tmpreg; -} - -/** - * @brief Checks whether the specified DMAy Streamx flag is set or not. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg DMA_FLAG_TCIFx: Streamx transfer complete flag - * @arg DMA_FLAG_HTIFx: Streamx half transfer complete flag - * @arg DMA_FLAG_TEIFx: Streamx transfer error flag - * @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag - * @arg DMA_FLAG_FEIFx: Streamx FIFO error flag - * Where x can be 0 to 7 to select the DMA Stream. - * @retval The new state of DMA_FLAG (SET or RESET). - */ -FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG) -{ - FlagStatus bitstatus = RESET; - DMA_TypeDef* DMAy; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_GET_FLAG(DMA_FLAG)); - - /* Determine the DMA to which belongs the stream */ - if (DMAy_Streamx < DMA2_Stream0) - { - /* DMAy_Streamx belongs to DMA1 */ - DMAy = DMA1; - } - else - { - /* DMAy_Streamx belongs to DMA2 */ - DMAy = DMA2; - } - - /* Check if the flag is in HISR or LISR */ - if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET) - { - /* Get DMAy HISR register value */ - tmpreg = DMAy->HISR; - } - else - { - /* Get DMAy LISR register value */ - tmpreg = DMAy->LISR; - } - - /* Mask the reserved bits */ - tmpreg &= (uint32_t)RESERVED_MASK; - - /* Check the status of the specified DMA flag */ - if ((tmpreg & DMA_FLAG) != (uint32_t)RESET) - { - /* DMA_FLAG is set */ - bitstatus = SET; - } - else - { - /* DMA_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the DMA_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the DMAy Streamx's pending flags. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCIFx: Streamx transfer complete flag - * @arg DMA_FLAG_HTIFx: Streamx half transfer complete flag - * @arg DMA_FLAG_TEIFx: Streamx transfer error flag - * @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag - * @arg DMA_FLAG_FEIFx: Streamx FIFO error flag - * Where x can be 0 to 7 to select the DMA Stream. - * @retval None - */ -void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG) -{ - DMA_TypeDef* DMAy; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG)); - - /* Determine the DMA to which belongs the stream */ - if (DMAy_Streamx < DMA2_Stream0) - { - /* DMAy_Streamx belongs to DMA1 */ - DMAy = DMA1; - } - else - { - /* DMAy_Streamx belongs to DMA2 */ - DMAy = DMA2; - } - - /* Check if LIFCR or HIFCR register is targeted */ - if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET) - { - /* Set DMAy HIFCR register clear flag bits */ - DMAy->HIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK); - } - else - { - /* Set DMAy LIFCR register clear flag bits */ - DMAy->LIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK); - } -} - -/** - * @brief Enables or disables the specified DMAy Streamx interrupts. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_IT: specifies the DMA interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask - * @arg DMA_IT_HT: Half transfer complete interrupt mask - * @arg DMA_IT_TE: Transfer error interrupt mask - * @arg DMA_IT_FE: FIFO error interrupt mask - * @param NewState: new state of the specified DMA interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_CONFIG_IT(DMA_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Check if the DMA_IT parameter contains a FIFO interrupt */ - if ((DMA_IT & DMA_IT_FE) != 0) - { - if (NewState != DISABLE) - { - /* Enable the selected DMA FIFO interrupts */ - DMAy_Streamx->FCR |= (uint32_t)DMA_IT_FE; - } - else - { - /* Disable the selected DMA FIFO interrupts */ - DMAy_Streamx->FCR &= ~(uint32_t)DMA_IT_FE; - } - } - - /* Check if the DMA_IT parameter contains a Transfer interrupt */ - if (DMA_IT != DMA_IT_FE) - { - if (NewState != DISABLE) - { - /* Enable the selected DMA transfer interrupts */ - DMAy_Streamx->CR |= (uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK); - } - else - { - /* Disable the selected DMA transfer interrupts */ - DMAy_Streamx->CR &= ~(uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK); - } - } -} - -/** - * @brief Checks whether the specified DMAy Streamx interrupt has occurred or not. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_IT: specifies the DMA interrupt source to check. - * This parameter can be one of the following values: - * @arg DMA_IT_TCIFx: Streamx transfer complete interrupt - * @arg DMA_IT_HTIFx: Streamx half transfer complete interrupt - * @arg DMA_IT_TEIFx: Streamx transfer error interrupt - * @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt - * @arg DMA_IT_FEIFx: Streamx FIFO error interrupt - * Where x can be 0 to 7 to select the DMA Stream. - * @retval The new state of DMA_IT (SET or RESET). - */ -ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT) -{ - ITStatus bitstatus = RESET; - DMA_TypeDef* DMAy; - uint32_t tmpreg = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_GET_IT(DMA_IT)); - - /* Determine the DMA to which belongs the stream */ - if (DMAy_Streamx < DMA2_Stream0) - { - /* DMAy_Streamx belongs to DMA1 */ - DMAy = DMA1; - } - else - { - /* DMAy_Streamx belongs to DMA2 */ - DMAy = DMA2; - } - - /* Check if the interrupt enable bit is in the CR or FCR register */ - if ((DMA_IT & TRANSFER_IT_MASK) != (uint32_t)RESET) - { - /* Get the interrupt enable position mask in CR register */ - tmpreg = (uint32_t)((DMA_IT >> 11) & TRANSFER_IT_ENABLE_MASK); - - /* Check the enable bit in CR register */ - enablestatus = (uint32_t)(DMAy_Streamx->CR & tmpreg); - } - else - { - /* Check the enable bit in FCR register */ - enablestatus = (uint32_t)(DMAy_Streamx->FCR & DMA_IT_FE); - } - - /* Check if the interrupt pending flag is in LISR or HISR */ - if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET) - { - /* Get DMAy HISR register value */ - tmpreg = DMAy->HISR ; - } - else - { - /* Get DMAy LISR register value */ - tmpreg = DMAy->LISR ; - } - - /* mask all reserved bits */ - tmpreg &= (uint32_t)RESERVED_MASK; - - /* Check the status of the specified DMA interrupt */ - if (((tmpreg & DMA_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) - { - /* DMA_IT is set */ - bitstatus = SET; - } - else - { - /* DMA_IT is reset */ - bitstatus = RESET; - } - - /* Return the DMA_IT status */ - return bitstatus; -} - -/** - * @brief Clears the DMAy Streamx's interrupt pending bits. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_IT: specifies the DMA interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TCIFx: Streamx transfer complete interrupt - * @arg DMA_IT_HTIFx: Streamx half transfer complete interrupt - * @arg DMA_IT_TEIFx: Streamx transfer error interrupt - * @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt - * @arg DMA_IT_FEIFx: Streamx FIFO error interrupt - * Where x can be 0 to 7 to select the DMA Stream. - * @retval None - */ -void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT) -{ - DMA_TypeDef* DMAy; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_CLEAR_IT(DMA_IT)); - - /* Determine the DMA to which belongs the stream */ - if (DMAy_Streamx < DMA2_Stream0) - { - /* DMAy_Streamx belongs to DMA1 */ - DMAy = DMA1; - } - else - { - /* DMAy_Streamx belongs to DMA2 */ - DMAy = DMA2; - } - - /* Check if LIFCR or HIFCR register is targeted */ - if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET) - { - /* Set DMAy HIFCR register clear interrupt bits */ - DMAy->HIFCR = (uint32_t)(DMA_IT & RESERVED_MASK); - } - else - { - /* Set DMAy LIFCR register clear interrupt bits */ - DMAy->LIFCR = (uint32_t)(DMA_IT & RESERVED_MASK); - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm32f4xx_dma.h b/stm/stmperiph/stm32f4xx_dma.h deleted file mode 100644 index 3a105d1b4..000000000 --- a/stm/stmperiph/stm32f4xx_dma.h +++ /dev/null @@ -1,609 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_dma.h - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief This file contains all the functions prototypes for the DMA firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_DMA_H -#define __STM32F4xx_DMA_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DMA - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief DMA Init structure definition - */ - -typedef struct -{ - uint32_t DMA_Channel; /*!< Specifies the channel used for the specified stream. - This parameter can be a value of @ref DMA_channel */ - - uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Streamx. */ - - uint32_t DMA_Memory0BaseAddr; /*!< Specifies the memory 0 base address for DMAy Streamx. - This memory is the default memory used when double buffer mode is - not enabled. */ - - uint32_t DMA_DIR; /*!< Specifies if the data will be transferred from memory to peripheral, - from memory to memory or from peripheral to memory. - This parameter can be a value of @ref DMA_data_transfer_direction */ - - uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Stream. - The data unit is equal to the configuration set in DMA_PeripheralDataSize - or DMA_MemoryDataSize members depending in the transfer direction. */ - - uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register should be incremented or not. - This parameter can be a value of @ref DMA_peripheral_incremented_mode */ - - uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register should be incremented or not. - This parameter can be a value of @ref DMA_memory_incremented_mode */ - - uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. - This parameter can be a value of @ref DMA_peripheral_data_size */ - - uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. - This parameter can be a value of @ref DMA_memory_data_size */ - - uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Streamx. - This parameter can be a value of @ref DMA_circular_normal_mode - @note The circular buffer mode cannot be used if the memory-to-memory - data transfer is configured on the selected Stream */ - - uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Streamx. - This parameter can be a value of @ref DMA_priority_level */ - - uint32_t DMA_FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified Stream. - This parameter can be a value of @ref DMA_fifo_direct_mode - @note The Direct mode (FIFO mode disabled) cannot be used if the - memory-to-memory data transfer is configured on the selected Stream */ - - uint32_t DMA_FIFOThreshold; /*!< Specifies the FIFO threshold level. - This parameter can be a value of @ref DMA_fifo_threshold_level */ - - uint32_t DMA_MemoryBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. - It specifies the amount of data to be transferred in a single non interruptable - transaction. This parameter can be a value of @ref DMA_memory_burst - @note The burst mode is possible only if the address Increment mode is enabled. */ - - uint32_t DMA_PeripheralBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. - It specifies the amount of data to be transferred in a single non interruptable - transaction. This parameter can be a value of @ref DMA_peripheral_burst - @note The burst mode is possible only if the address Increment mode is enabled. */ -}DMA_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Constants - * @{ - */ - -#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Stream0) || \ - ((PERIPH) == DMA1_Stream1) || \ - ((PERIPH) == DMA1_Stream2) || \ - ((PERIPH) == DMA1_Stream3) || \ - ((PERIPH) == DMA1_Stream4) || \ - ((PERIPH) == DMA1_Stream5) || \ - ((PERIPH) == DMA1_Stream6) || \ - ((PERIPH) == DMA1_Stream7) || \ - ((PERIPH) == DMA2_Stream0) || \ - ((PERIPH) == DMA2_Stream1) || \ - ((PERIPH) == DMA2_Stream2) || \ - ((PERIPH) == DMA2_Stream3) || \ - ((PERIPH) == DMA2_Stream4) || \ - ((PERIPH) == DMA2_Stream5) || \ - ((PERIPH) == DMA2_Stream6) || \ - ((PERIPH) == DMA2_Stream7)) - -#define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1) || \ - ((CONTROLLER) == DMA2)) - -/** @defgroup DMA_channel - * @{ - */ -#define DMA_Channel_0 ((uint32_t)0x00000000) -#define DMA_Channel_1 ((uint32_t)0x02000000) -#define DMA_Channel_2 ((uint32_t)0x04000000) -#define DMA_Channel_3 ((uint32_t)0x06000000) -#define DMA_Channel_4 ((uint32_t)0x08000000) -#define DMA_Channel_5 ((uint32_t)0x0A000000) -#define DMA_Channel_6 ((uint32_t)0x0C000000) -#define DMA_Channel_7 ((uint32_t)0x0E000000) - -#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_Channel_0) || \ - ((CHANNEL) == DMA_Channel_1) || \ - ((CHANNEL) == DMA_Channel_2) || \ - ((CHANNEL) == DMA_Channel_3) || \ - ((CHANNEL) == DMA_Channel_4) || \ - ((CHANNEL) == DMA_Channel_5) || \ - ((CHANNEL) == DMA_Channel_6) || \ - ((CHANNEL) == DMA_Channel_7)) -/** - * @} - */ - - -/** @defgroup DMA_data_transfer_direction - * @{ - */ -#define DMA_DIR_PeripheralToMemory ((uint32_t)0x00000000) -#define DMA_DIR_MemoryToPeripheral ((uint32_t)0x00000040) -#define DMA_DIR_MemoryToMemory ((uint32_t)0x00000080) - -#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_DIR_PeripheralToMemory ) || \ - ((DIRECTION) == DMA_DIR_MemoryToPeripheral) || \ - ((DIRECTION) == DMA_DIR_MemoryToMemory)) -/** - * @} - */ - - -/** @defgroup DMA_data_buffer_size - * @{ - */ -#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) -/** - * @} - */ - - -/** @defgroup DMA_peripheral_incremented_mode - * @{ - */ -#define DMA_PeripheralInc_Enable ((uint32_t)0x00000200) -#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) - -#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ - ((STATE) == DMA_PeripheralInc_Disable)) -/** - * @} - */ - - -/** @defgroup DMA_memory_incremented_mode - * @{ - */ -#define DMA_MemoryInc_Enable ((uint32_t)0x00000400) -#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) - -#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ - ((STATE) == DMA_MemoryInc_Disable)) -/** - * @} - */ - - -/** @defgroup DMA_peripheral_data_size - * @{ - */ -#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) -#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000800) -#define DMA_PeripheralDataSize_Word ((uint32_t)0x00001000) - -#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ - ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ - ((SIZE) == DMA_PeripheralDataSize_Word)) -/** - * @} - */ - - -/** @defgroup DMA_memory_data_size - * @{ - */ -#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) -#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00002000) -#define DMA_MemoryDataSize_Word ((uint32_t)0x00004000) - -#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ - ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ - ((SIZE) == DMA_MemoryDataSize_Word )) -/** - * @} - */ - - -/** @defgroup DMA_circular_normal_mode - * @{ - */ -#define DMA_Mode_Normal ((uint32_t)0x00000000) -#define DMA_Mode_Circular ((uint32_t)0x00000100) - -#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal ) || \ - ((MODE) == DMA_Mode_Circular)) -/** - * @} - */ - - -/** @defgroup DMA_priority_level - * @{ - */ -#define DMA_Priority_Low ((uint32_t)0x00000000) -#define DMA_Priority_Medium ((uint32_t)0x00010000) -#define DMA_Priority_High ((uint32_t)0x00020000) -#define DMA_Priority_VeryHigh ((uint32_t)0x00030000) - -#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_Low ) || \ - ((PRIORITY) == DMA_Priority_Medium) || \ - ((PRIORITY) == DMA_Priority_High) || \ - ((PRIORITY) == DMA_Priority_VeryHigh)) -/** - * @} - */ - - -/** @defgroup DMA_fifo_direct_mode - * @{ - */ -#define DMA_FIFOMode_Disable ((uint32_t)0x00000000) -#define DMA_FIFOMode_Enable ((uint32_t)0x00000004) - -#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMode_Disable ) || \ - ((STATE) == DMA_FIFOMode_Enable)) -/** - * @} - */ - - -/** @defgroup DMA_fifo_threshold_level - * @{ - */ -#define DMA_FIFOThreshold_1QuarterFull ((uint32_t)0x00000000) -#define DMA_FIFOThreshold_HalfFull ((uint32_t)0x00000001) -#define DMA_FIFOThreshold_3QuartersFull ((uint32_t)0x00000002) -#define DMA_FIFOThreshold_Full ((uint32_t)0x00000003) - -#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFOThreshold_1QuarterFull ) || \ - ((THRESHOLD) == DMA_FIFOThreshold_HalfFull) || \ - ((THRESHOLD) == DMA_FIFOThreshold_3QuartersFull) || \ - ((THRESHOLD) == DMA_FIFOThreshold_Full)) -/** - * @} - */ - - -/** @defgroup DMA_memory_burst - * @{ - */ -#define DMA_MemoryBurst_Single ((uint32_t)0x00000000) -#define DMA_MemoryBurst_INC4 ((uint32_t)0x00800000) -#define DMA_MemoryBurst_INC8 ((uint32_t)0x01000000) -#define DMA_MemoryBurst_INC16 ((uint32_t)0x01800000) - -#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MemoryBurst_Single) || \ - ((BURST) == DMA_MemoryBurst_INC4) || \ - ((BURST) == DMA_MemoryBurst_INC8) || \ - ((BURST) == DMA_MemoryBurst_INC16)) -/** - * @} - */ - - -/** @defgroup DMA_peripheral_burst - * @{ - */ -#define DMA_PeripheralBurst_Single ((uint32_t)0x00000000) -#define DMA_PeripheralBurst_INC4 ((uint32_t)0x00200000) -#define DMA_PeripheralBurst_INC8 ((uint32_t)0x00400000) -#define DMA_PeripheralBurst_INC16 ((uint32_t)0x00600000) - -#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PeripheralBurst_Single) || \ - ((BURST) == DMA_PeripheralBurst_INC4) || \ - ((BURST) == DMA_PeripheralBurst_INC8) || \ - ((BURST) == DMA_PeripheralBurst_INC16)) -/** - * @} - */ - - -/** @defgroup DMA_fifo_status_level - * @{ - */ -#define DMA_FIFOStatus_Less1QuarterFull ((uint32_t)0x00000000 << 3) -#define DMA_FIFOStatus_1QuarterFull ((uint32_t)0x00000001 << 3) -#define DMA_FIFOStatus_HalfFull ((uint32_t)0x00000002 << 3) -#define DMA_FIFOStatus_3QuartersFull ((uint32_t)0x00000003 << 3) -#define DMA_FIFOStatus_Empty ((uint32_t)0x00000004 << 3) -#define DMA_FIFOStatus_Full ((uint32_t)0x00000005 << 3) - -#define IS_DMA_FIFO_STATUS(STATUS) (((STATUS) == DMA_FIFOStatus_Less1QuarterFull ) || \ - ((STATUS) == DMA_FIFOStatus_HalfFull) || \ - ((STATUS) == DMA_FIFOStatus_1QuarterFull) || \ - ((STATUS) == DMA_FIFOStatus_3QuartersFull) || \ - ((STATUS) == DMA_FIFOStatus_Full) || \ - ((STATUS) == DMA_FIFOStatus_Empty)) -/** - * @} - */ - -/** @defgroup DMA_flags_definition - * @{ - */ -#define DMA_FLAG_FEIF0 ((uint32_t)0x10800001) -#define DMA_FLAG_DMEIF0 ((uint32_t)0x10800004) -#define DMA_FLAG_TEIF0 ((uint32_t)0x10000008) -#define DMA_FLAG_HTIF0 ((uint32_t)0x10000010) -#define DMA_FLAG_TCIF0 ((uint32_t)0x10000020) -#define DMA_FLAG_FEIF1 ((uint32_t)0x10000040) -#define DMA_FLAG_DMEIF1 ((uint32_t)0x10000100) -#define DMA_FLAG_TEIF1 ((uint32_t)0x10000200) -#define DMA_FLAG_HTIF1 ((uint32_t)0x10000400) -#define DMA_FLAG_TCIF1 ((uint32_t)0x10000800) -#define DMA_FLAG_FEIF2 ((uint32_t)0x10010000) -#define DMA_FLAG_DMEIF2 ((uint32_t)0x10040000) -#define DMA_FLAG_TEIF2 ((uint32_t)0x10080000) -#define DMA_FLAG_HTIF2 ((uint32_t)0x10100000) -#define DMA_FLAG_TCIF2 ((uint32_t)0x10200000) -#define DMA_FLAG_FEIF3 ((uint32_t)0x10400000) -#define DMA_FLAG_DMEIF3 ((uint32_t)0x11000000) -#define DMA_FLAG_TEIF3 ((uint32_t)0x12000000) -#define DMA_FLAG_HTIF3 ((uint32_t)0x14000000) -#define DMA_FLAG_TCIF3 ((uint32_t)0x18000000) -#define DMA_FLAG_FEIF4 ((uint32_t)0x20000001) -#define DMA_FLAG_DMEIF4 ((uint32_t)0x20000004) -#define DMA_FLAG_TEIF4 ((uint32_t)0x20000008) -#define DMA_FLAG_HTIF4 ((uint32_t)0x20000010) -#define DMA_FLAG_TCIF4 ((uint32_t)0x20000020) -#define DMA_FLAG_FEIF5 ((uint32_t)0x20000040) -#define DMA_FLAG_DMEIF5 ((uint32_t)0x20000100) -#define DMA_FLAG_TEIF5 ((uint32_t)0x20000200) -#define DMA_FLAG_HTIF5 ((uint32_t)0x20000400) -#define DMA_FLAG_TCIF5 ((uint32_t)0x20000800) -#define DMA_FLAG_FEIF6 ((uint32_t)0x20010000) -#define DMA_FLAG_DMEIF6 ((uint32_t)0x20040000) -#define DMA_FLAG_TEIF6 ((uint32_t)0x20080000) -#define DMA_FLAG_HTIF6 ((uint32_t)0x20100000) -#define DMA_FLAG_TCIF6 ((uint32_t)0x20200000) -#define DMA_FLAG_FEIF7 ((uint32_t)0x20400000) -#define DMA_FLAG_DMEIF7 ((uint32_t)0x21000000) -#define DMA_FLAG_TEIF7 ((uint32_t)0x22000000) -#define DMA_FLAG_HTIF7 ((uint32_t)0x24000000) -#define DMA_FLAG_TCIF7 ((uint32_t)0x28000000) - -#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \ - (((FLAG) & 0xC002F082) == 0x00) && ((FLAG) != 0x00)) - -#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0) || ((FLAG) == DMA_FLAG_HTIF0) || \ - ((FLAG) == DMA_FLAG_TEIF0) || ((FLAG) == DMA_FLAG_DMEIF0) || \ - ((FLAG) == DMA_FLAG_FEIF0) || ((FLAG) == DMA_FLAG_TCIF1) || \ - ((FLAG) == DMA_FLAG_HTIF1) || ((FLAG) == DMA_FLAG_TEIF1) || \ - ((FLAG) == DMA_FLAG_DMEIF1) || ((FLAG) == DMA_FLAG_FEIF1) || \ - ((FLAG) == DMA_FLAG_TCIF2) || ((FLAG) == DMA_FLAG_HTIF2) || \ - ((FLAG) == DMA_FLAG_TEIF2) || ((FLAG) == DMA_FLAG_DMEIF2) || \ - ((FLAG) == DMA_FLAG_FEIF2) || ((FLAG) == DMA_FLAG_TCIF3) || \ - ((FLAG) == DMA_FLAG_HTIF3) || ((FLAG) == DMA_FLAG_TEIF3) || \ - ((FLAG) == DMA_FLAG_DMEIF3) || ((FLAG) == DMA_FLAG_FEIF3) || \ - ((FLAG) == DMA_FLAG_TCIF4) || ((FLAG) == DMA_FLAG_HTIF4) || \ - ((FLAG) == DMA_FLAG_TEIF4) || ((FLAG) == DMA_FLAG_DMEIF4) || \ - ((FLAG) == DMA_FLAG_FEIF4) || ((FLAG) == DMA_FLAG_TCIF5) || \ - ((FLAG) == DMA_FLAG_HTIF5) || ((FLAG) == DMA_FLAG_TEIF5) || \ - ((FLAG) == DMA_FLAG_DMEIF5) || ((FLAG) == DMA_FLAG_FEIF5) || \ - ((FLAG) == DMA_FLAG_TCIF6) || ((FLAG) == DMA_FLAG_HTIF6) || \ - ((FLAG) == DMA_FLAG_TEIF6) || ((FLAG) == DMA_FLAG_DMEIF6) || \ - ((FLAG) == DMA_FLAG_FEIF6) || ((FLAG) == DMA_FLAG_TCIF7) || \ - ((FLAG) == DMA_FLAG_HTIF7) || ((FLAG) == DMA_FLAG_TEIF7) || \ - ((FLAG) == DMA_FLAG_DMEIF7) || ((FLAG) == DMA_FLAG_FEIF7)) -/** - * @} - */ - - -/** @defgroup DMA_interrupt_enable_definitions - * @{ - */ -#define DMA_IT_TC ((uint32_t)0x00000010) -#define DMA_IT_HT ((uint32_t)0x00000008) -#define DMA_IT_TE ((uint32_t)0x00000004) -#define DMA_IT_DME ((uint32_t)0x00000002) -#define DMA_IT_FE ((uint32_t)0x00000080) - -#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFF61) == 0x00) && ((IT) != 0x00)) -/** - * @} - */ - - -/** @defgroup DMA_interrupts_definitions - * @{ - */ -#define DMA_IT_FEIF0 ((uint32_t)0x90000001) -#define DMA_IT_DMEIF0 ((uint32_t)0x10001004) -#define DMA_IT_TEIF0 ((uint32_t)0x10002008) -#define DMA_IT_HTIF0 ((uint32_t)0x10004010) -#define DMA_IT_TCIF0 ((uint32_t)0x10008020) -#define DMA_IT_FEIF1 ((uint32_t)0x90000040) -#define DMA_IT_DMEIF1 ((uint32_t)0x10001100) -#define DMA_IT_TEIF1 ((uint32_t)0x10002200) -#define DMA_IT_HTIF1 ((uint32_t)0x10004400) -#define DMA_IT_TCIF1 ((uint32_t)0x10008800) -#define DMA_IT_FEIF2 ((uint32_t)0x90010000) -#define DMA_IT_DMEIF2 ((uint32_t)0x10041000) -#define DMA_IT_TEIF2 ((uint32_t)0x10082000) -#define DMA_IT_HTIF2 ((uint32_t)0x10104000) -#define DMA_IT_TCIF2 ((uint32_t)0x10208000) -#define DMA_IT_FEIF3 ((uint32_t)0x90400000) -#define DMA_IT_DMEIF3 ((uint32_t)0x11001000) -#define DMA_IT_TEIF3 ((uint32_t)0x12002000) -#define DMA_IT_HTIF3 ((uint32_t)0x14004000) -#define DMA_IT_TCIF3 ((uint32_t)0x18008000) -#define DMA_IT_FEIF4 ((uint32_t)0xA0000001) -#define DMA_IT_DMEIF4 ((uint32_t)0x20001004) -#define DMA_IT_TEIF4 ((uint32_t)0x20002008) -#define DMA_IT_HTIF4 ((uint32_t)0x20004010) -#define DMA_IT_TCIF4 ((uint32_t)0x20008020) -#define DMA_IT_FEIF5 ((uint32_t)0xA0000040) -#define DMA_IT_DMEIF5 ((uint32_t)0x20001100) -#define DMA_IT_TEIF5 ((uint32_t)0x20002200) -#define DMA_IT_HTIF5 ((uint32_t)0x20004400) -#define DMA_IT_TCIF5 ((uint32_t)0x20008800) -#define DMA_IT_FEIF6 ((uint32_t)0xA0010000) -#define DMA_IT_DMEIF6 ((uint32_t)0x20041000) -#define DMA_IT_TEIF6 ((uint32_t)0x20082000) -#define DMA_IT_HTIF6 ((uint32_t)0x20104000) -#define DMA_IT_TCIF6 ((uint32_t)0x20208000) -#define DMA_IT_FEIF7 ((uint32_t)0xA0400000) -#define DMA_IT_DMEIF7 ((uint32_t)0x21001000) -#define DMA_IT_TEIF7 ((uint32_t)0x22002000) -#define DMA_IT_HTIF7 ((uint32_t)0x24004000) -#define DMA_IT_TCIF7 ((uint32_t)0x28008000) - -#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0x30000000) != 0x30000000) && \ - (((IT) & 0x30000000) != 0) && ((IT) != 0x00) && \ - (((IT) & 0x40820082) == 0x00)) - -#define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TCIF0) || ((IT) == DMA_IT_HTIF0) || \ - ((IT) == DMA_IT_TEIF0) || ((IT) == DMA_IT_DMEIF0) || \ - ((IT) == DMA_IT_FEIF0) || ((IT) == DMA_IT_TCIF1) || \ - ((IT) == DMA_IT_HTIF1) || ((IT) == DMA_IT_TEIF1) || \ - ((IT) == DMA_IT_DMEIF1)|| ((IT) == DMA_IT_FEIF1) || \ - ((IT) == DMA_IT_TCIF2) || ((IT) == DMA_IT_HTIF2) || \ - ((IT) == DMA_IT_TEIF2) || ((IT) == DMA_IT_DMEIF2) || \ - ((IT) == DMA_IT_FEIF2) || ((IT) == DMA_IT_TCIF3) || \ - ((IT) == DMA_IT_HTIF3) || ((IT) == DMA_IT_TEIF3) || \ - ((IT) == DMA_IT_DMEIF3)|| ((IT) == DMA_IT_FEIF3) || \ - ((IT) == DMA_IT_TCIF4) || ((IT) == DMA_IT_HTIF4) || \ - ((IT) == DMA_IT_TEIF4) || ((IT) == DMA_IT_DMEIF4) || \ - ((IT) == DMA_IT_FEIF4) || ((IT) == DMA_IT_TCIF5) || \ - ((IT) == DMA_IT_HTIF5) || ((IT) == DMA_IT_TEIF5) || \ - ((IT) == DMA_IT_DMEIF5)|| ((IT) == DMA_IT_FEIF5) || \ - ((IT) == DMA_IT_TCIF6) || ((IT) == DMA_IT_HTIF6) || \ - ((IT) == DMA_IT_TEIF6) || ((IT) == DMA_IT_DMEIF6) || \ - ((IT) == DMA_IT_FEIF6) || ((IT) == DMA_IT_TCIF7) || \ - ((IT) == DMA_IT_HTIF7) || ((IT) == DMA_IT_TEIF7) || \ - ((IT) == DMA_IT_DMEIF7)|| ((IT) == DMA_IT_FEIF7)) -/** - * @} - */ - - -/** @defgroup DMA_peripheral_increment_offset - * @{ - */ -#define DMA_PINCOS_Psize ((uint32_t)0x00000000) -#define DMA_PINCOS_WordAligned ((uint32_t)0x00008000) - -#define IS_DMA_PINCOS_SIZE(SIZE) (((SIZE) == DMA_PINCOS_Psize) || \ - ((SIZE) == DMA_PINCOS_WordAligned)) -/** - * @} - */ - - -/** @defgroup DMA_flow_controller_definitions - * @{ - */ -#define DMA_FlowCtrl_Memory ((uint32_t)0x00000000) -#define DMA_FlowCtrl_Peripheral ((uint32_t)0x00000020) - -#define IS_DMA_FLOW_CTRL(CTRL) (((CTRL) == DMA_FlowCtrl_Memory) || \ - ((CTRL) == DMA_FlowCtrl_Peripheral)) -/** - * @} - */ - - -/** @defgroup DMA_memory_targets_definitions - * @{ - */ -#define DMA_Memory_0 ((uint32_t)0x00000000) -#define DMA_Memory_1 ((uint32_t)0x00080000) - -#define IS_DMA_CURRENT_MEM(MEM) (((MEM) == DMA_Memory_0) || ((MEM) == DMA_Memory_1)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the DMA configuration to the default reset state *****/ -void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx); - -/* Initialization and Configuration functions *********************************/ -void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct); -void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); -void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState); - -/* Optional Configuration functions *******************************************/ -void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos); -void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl); - -/* Data Counter functions *****************************************************/ -void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter); -uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx); - -/* Double Buffer mode functions ***********************************************/ -void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr, - uint32_t DMA_CurrentMemory); -void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState); -void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr, - uint32_t DMA_MemoryTarget); -uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx); - -/* Interrupts and flags management functions **********************************/ -FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx); -uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx); -FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); -void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); -void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState); -ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); -void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_DMA_H */ - -/** - * @} - */ - -/** - * @} - */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm32f4xx_exti.c b/stm/stmperiph/stm32f4xx_exti.c deleted file mode 100644 index 4eb676417..000000000 --- a/stm/stmperiph/stm32f4xx_exti.c +++ /dev/null @@ -1,312 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_exti.c - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief This file provides firmware functions to manage the following - * functionalities of the EXTI peripheral: - * + Initialization and Configuration - * + Interrupts and flags management - * -@verbatim - - =================================================================== - ##### EXTI features ##### - =================================================================== - - [..] External interrupt/event lines are mapped as following: - (#) All available GPIO pins are connected to the 16 external - interrupt/event lines from EXTI0 to EXTI15. - (#) EXTI line 16 is connected to the PVD Output - (#) EXTI line 17 is connected to the RTC Alarm event - (#) EXTI line 18 is connected to the USB OTG FS Wakeup from suspend event - (#) EXTI line 19 is connected to the Ethernet Wakeup event - (#) EXTI line 20 is connected to the USB OTG HS (configured in FS) Wakeup event - (#) EXTI line 21 is connected to the RTC Tamper and Time Stamp events - (#) EXTI line 22 is connected to the RTC Wakeup event - - - ##### How to use this driver ##### - =================================================================== - - [..] In order to use an I/O pin as an external interrupt source, follow steps - below: - (#) Configure the I/O in input mode using GPIO_Init() - (#) Select the input source pin for the EXTI line using SYSCFG_EXTILineConfig() - (#) Select the mode(interrupt, event) and configure the trigger - selection (Rising, falling or both) using EXTI_Init() - (#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init() - - [..] - (@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx - registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); - -@endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_exti.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup EXTI - * @brief EXTI driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup EXTI_Private_Functions - * @{ - */ - -/** @defgroup EXTI_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the EXTI peripheral registers to their default reset values. - * @param None - * @retval None - */ -void EXTI_DeInit(void) -{ - EXTI->IMR = 0x00000000; - EXTI->EMR = 0x00000000; - EXTI->RTSR = 0x00000000; - EXTI->FTSR = 0x00000000; - EXTI->PR = 0x007FFFFF; -} - -/** - * @brief Initializes the EXTI peripheral according to the specified - * parameters in the EXTI_InitStruct. - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure - * that contains the configuration information for the EXTI peripheral. - * @retval None - */ -void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); - assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); - assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); - assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); - - tmp = (uint32_t)EXTI_BASE; - - if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) - { - /* Clear EXTI line configuration */ - EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; - - tmp += EXTI_InitStruct->EXTI_Mode; - - *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; - - /* Clear Rising Falling edge configuration */ - EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; - - /* Select the trigger for the selected external interrupts */ - if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) - { - /* Rising Falling edge */ - EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; - EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; - } - else - { - tmp = (uint32_t)EXTI_BASE; - tmp += EXTI_InitStruct->EXTI_Trigger; - - *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; - } - } - else - { - tmp += EXTI_InitStruct->EXTI_Mode; - - /* Disable the selected external lines */ - *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; - } -} - -/** - * @brief Fills each EXTI_InitStruct member with its reset value. - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) -{ - EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; - EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; - EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; - EXTI_InitStruct->EXTI_LineCmd = DISABLE; -} - -/** - * @brief Generates a Software interrupt on selected EXTI line. - * @param EXTI_Line: specifies the EXTI line on which the software interrupt - * will be generated. - * This parameter can be any combination of EXTI_Linex where x can be (0..22) - * @retval None - */ -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->SWIER |= EXTI_Line; -} - -/** - * @} - */ - -/** @defgroup EXTI_Group2 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the specified EXTI line flag is set or not. - * @param EXTI_Line: specifies the EXTI line flag to check. - * This parameter can be EXTI_Linex where x can be(0..22) - * @retval The new state of EXTI_Line (SET or RESET). - */ -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_GET_EXTI_LINE(EXTI_Line)); - - if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the EXTI's line pending flags. - * @param EXTI_Line: specifies the EXTI lines flags to clear. - * This parameter can be any combination of EXTI_Linex where x can be (0..22) - * @retval None - */ -void EXTI_ClearFlag(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->PR = EXTI_Line; -} - -/** - * @brief Checks whether the specified EXTI line is asserted or not. - * @param EXTI_Line: specifies the EXTI line to check. - * This parameter can be EXTI_Linex where x can be(0..22) - * @retval The new state of EXTI_Line (SET or RESET). - */ -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_GET_EXTI_LINE(EXTI_Line)); - - if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; - -} - -/** - * @brief Clears the EXTI's line pending bits. - * @param EXTI_Line: specifies the EXTI lines to clear. - * This parameter can be any combination of EXTI_Linex where x can be (0..22) - * @retval None - */ -void EXTI_ClearITPendingBit(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->PR = EXTI_Line; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm32f4xx_exti.h b/stm/stmperiph/stm32f4xx_exti.h deleted file mode 100644 index 39105e3b7..000000000 --- a/stm/stmperiph/stm32f4xx_exti.h +++ /dev/null @@ -1,183 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_exti.h - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief This file contains all the functions prototypes for the EXTI firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_EXTI_H -#define __STM32F4xx_EXTI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup EXTI - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief EXTI mode enumeration - */ - -typedef enum -{ - EXTI_Mode_Interrupt = 0x00, - EXTI_Mode_Event = 0x04 -}EXTIMode_TypeDef; - -#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) - -/** - * @brief EXTI Trigger enumeration - */ - -typedef enum -{ - EXTI_Trigger_Rising = 0x08, - EXTI_Trigger_Falling = 0x0C, - EXTI_Trigger_Rising_Falling = 0x10 -}EXTITrigger_TypeDef; - -#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ - ((TRIGGER) == EXTI_Trigger_Falling) || \ - ((TRIGGER) == EXTI_Trigger_Rising_Falling)) -/** - * @brief EXTI Init Structure definition - */ - -typedef struct -{ - uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. - This parameter can be any combination value of @ref EXTI_Lines */ - - EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. - This parameter can be a value of @ref EXTITrigger_TypeDef */ - - FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. - This parameter can be set either to ENABLE or DISABLE */ -}EXTI_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup EXTI_Exported_Constants - * @{ - */ - -/** @defgroup EXTI_Lines - * @{ - */ - -#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ -#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ -#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ -#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ -#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ -#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ -#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ -#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ -#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ -#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ -#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ -#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ -#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ -#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ -#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ -#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ -#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ -#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ -#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */ -#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ -#define EXTI_Line20 ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */ -#define EXTI_Line21 ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ -#define EXTI_Line22 ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to the RTC Wakeup event */ - -#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00)) - -#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ - ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ - ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ - ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ - ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ - ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ - ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ - ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ - ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ - ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \ - ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) ||\ - ((LINE) == EXTI_Line22)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the EXTI configuration to the default reset state *****/ -void EXTI_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); -void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); - -/* Interrupts and flags management functions **********************************/ -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); -void EXTI_ClearFlag(uint32_t EXTI_Line); -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); -void EXTI_ClearITPendingBit(uint32_t EXTI_Line); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_EXTI_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm32f4xx_flash.c b/stm/stmperiph/stm32f4xx_flash.c deleted file mode 100644 index f3551b116..000000000 --- a/stm/stmperiph/stm32f4xx_flash.c +++ /dev/null @@ -1,1580 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_flash.c - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief This file provides firmware functions to manage the following - * functionalities of the FLASH peripheral: - * + FLASH Interface configuration - * + FLASH Memory Programming - * + Option Bytes Programming - * + Interrupts and flags management - * - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - This driver provides functions to configure and program the FLASH memory - of all STM32F4xx devices. These functions are split in 4 groups: - - (#) FLASH Interface configuration functions: this group includes the - management of the following features: - (++) Set the latency - (++) Enable/Disable the prefetch buffer - (++) Enable/Disable the Instruction cache and the Data cache - (++) Reset the Instruction cache and the Data cache - - (#) FLASH Memory Programming functions: this group includes all needed - functions to erase and program the main memory: - (++) Lock and Unlock the FLASH interface - (++) Erase function: Erase sector, erase all sectors - (++) Program functions: byte, half word, word and double word - - (#) Option Bytes Programming functions: this group includes all needed - functions to manage the Option Bytes: - (++) Set/Reset the write protection - (++) Set the Read protection Level - (++) Set the BOR level - (++) Program the user Option Bytes - (++) Launch the Option Bytes loader - - (#) Interrupts and flags management functions: this group - includes all needed functions to: - (++) Enable/Disable the FLASH interrupt sources - (++) Get flags status - (++) Clear flags - (++) Get FLASH operation status - (++) Wait for last FLASH operation - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_flash.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup FLASH - * @brief FLASH driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define SECTOR_MASK ((uint32_t)0xFFFFFF07) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup FLASH_Private_Functions - * @{ - */ - -/** @defgroup FLASH_Group1 FLASH Interface configuration functions - * @brief FLASH Interface configuration functions - * - -@verbatim - =============================================================================== - ##### FLASH Interface configuration functions ##### - =============================================================================== - [..] - This group includes the following functions: - (+) void FLASH_SetLatency(uint32_t FLASH_Latency) - To correctly read data from FLASH memory, the number of wait states (LATENCY) - must be correctly programmed according to the frequency of the CPU clock - (HCLK) and the supply voltage of the device. - [..] - For STM32F405xx/07xx and STM32F415xx/17xx devices - +-------------------------------------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |---------------------------------------------------------------------| - | | voltage range | voltage range | voltage range | voltage range | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | - |---------------|----------------|----------------|-----------------|-----------------| - |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | - |---------------|----------------|----------------|-----------------|-----------------| - |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | - |---------------|----------------|----------------|-----------------|-----------------| - |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | - |---------------|----------------|----------------|-----------------|-----------------| - |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 | - |---------------|----------------|----------------|-----------------|-----------------| - |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 | - |---------------|----------------|----------------|-----------------|-----------------| - |5WS(6CPU cycle)|150< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120| - |---------------|----------------|----------------|-----------------|-----------------| - |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140| - |---------------|----------------|----------------|-----------------|-----------------| - |7WS(8CPU cycle)| NA | NA |154 < HCLK <= 168|140 < HCLK <= 160| - +---------------|----------------|----------------|-----------------|-----------------+ - - [..] - For STM32F42xxx/43xxx devices - +-------------------------------------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |---------------------------------------------------------------------| - | | voltage range | voltage range | voltage range | voltage range | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | - |---------------|----------------|----------------|-----------------|-----------------| - |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | - |---------------|----------------|----------------|-----------------|-----------------| - |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | - |---------------|----------------|----------------|-----------------|-----------------| - |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | - |---------------|----------------|----------------|-----------------|-----------------| - |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 | - |---------------|----------------|----------------|-----------------|-----------------| - |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 | - |---------------|----------------|----------------|-----------------|-----------------| - |5WS(6CPU cycle)|120< HCLK <= 180|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120| - |---------------|----------------|----------------|-----------------|-----------------| - |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140| - |---------------|----------------|----------------|-----------------|-----------------| - |7WS(8CPU cycle)| NA |168< HCLK <= 180|154 < HCLK <= 176|140 < HCLK <= 160| - |---------------|----------------|----------------|-----------------|-----------------| - |8WS(9CPU cycle)| NA | NA |176 < HCLK <= 180|160 < HCLK <= 168| - +-------------------------------------------------------------------------------------+ - - [..] - For STM32F401x devices - +-------------------------------------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |---------------------------------------------------------------------| - | | voltage range | voltage range | voltage range | voltage range | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | - |---------------|----------------|----------------|-----------------|-----------------| - |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | - |---------------|----------------|----------------|-----------------|-----------------| - |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | - |---------------|----------------|----------------|-----------------|-----------------| - |2WS(3CPU cycle)|60 < HCLK <= 84 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | - |---------------|----------------|----------------|-----------------|-----------------| - |3WS(4CPU cycle)| NA |72 < HCLK <= 84 |66 < HCLK <= 84 |60 < HCLK <= 80 | - |---------------|----------------|----------------|-----------------|-----------------| - |4WS(5CPU cycle)| NA | NA | NA |80 < HCLK <= 84 | - +-------------------------------------------------------------------------------------+ - - [..] - +-------------------------------------------------------------------------------------------------------------------+ - | | voltage range | voltage range | voltage range | voltage range | voltage range 2.7 V - 3.6 V | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | with External Vpp = 9V | - |---------------|----------------|----------------|-----------------|-----------------|-----------------------------| - |Max Parallelism| x32 | x16 | x8 | x64 | - |---------------|----------------|----------------|-----------------|-----------------|-----------------------------| - |PSIZE[1:0] | 10 | 01 | 00 | 11 | - +-------------------------------------------------------------------------------------------------------------------+ - - -@- On STM32F405xx/407xx and STM32F415xx/417xx devices: - (++) when VOS = '0' Scale 2 mode, the maximum value of fHCLK = 144MHz. - (++) when VOS = '1' Scale 1 mode, the maximum value of fHCLK = 168MHz. - [..] - On STM32F42xxx/43xxx devices: - (++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 120MHz. - (++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 144MHz if OverDrive OFF and 168MHz if OverDrive ON. - (++) when VOS[1:0] = '0x11' Scale 1 mode, the maximum value of fHCLK is 168MHz if OverDrive OFF and 180MHz if OverDrive ON. - [..] - On STM32F401x devices: - (++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 60MHz. - (++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 84MHz. - For more details please refer product DataSheet - You can use PWR_MainRegulatorModeConfig() function to control VOS bits. - - (+) void FLASH_PrefetchBufferCmd(FunctionalState NewState) - (+) void FLASH_InstructionCacheCmd(FunctionalState NewState) - (+) void FLASH_DataCacheCmd(FunctionalState NewState) - (+) void FLASH_InstructionCacheReset(void) - (+) void FLASH_DataCacheReset(void) - - [..] - The unlock sequence is not needed for these functions. - -@endverbatim - * @{ - */ - -/** - * @brief Sets the code latency value. - * @param FLASH_Latency: specifies the FLASH Latency value. - * This parameter can be one of the following values: - * @arg FLASH_Latency_0: FLASH Zero Latency cycle - * @arg FLASH_Latency_1: FLASH One Latency cycle - * @arg FLASH_Latency_2: FLASH Two Latency cycles - * @arg FLASH_Latency_3: FLASH Three Latency cycles - * @arg FLASH_Latency_4: FLASH Four Latency cycles - * @arg FLASH_Latency_5: FLASH Five Latency cycles - * @arg FLASH_Latency_6: FLASH Six Latency cycles - * @arg FLASH_Latency_7: FLASH Seven Latency cycles - * @arg FLASH_Latency_8: FLASH Eight Latency cycles - * @arg FLASH_Latency_9: FLASH Nine Latency cycles - * @arg FLASH_Latency_10: FLASH Teen Latency cycles - * @arg FLASH_Latency_11: FLASH Eleven Latency cycles - * @arg FLASH_Latency_12: FLASH Twelve Latency cycles - * @arg FLASH_Latency_13: FLASH Thirteen Latency cycles - * @arg FLASH_Latency_14: FLASH Fourteen Latency cycles - * @arg FLASH_Latency_15: FLASH Fifteen Latency cycles - * - * @note For STM32F405xx/407xx, STM32F415xx/417xx and STM32F401xx devices this parameter - * can be a value between FLASH_Latency_0 and FLASH_Latency_7. - * - * @note For STM32F42xxx/43xxx devices this parameter can be a value between - * FLASH_Latency_0 and FLASH_Latency_15. - * - * @retval None - */ -void FLASH_SetLatency(uint32_t FLASH_Latency) -{ - /* Check the parameters */ - assert_param(IS_FLASH_LATENCY(FLASH_Latency)); - - /* Perform Byte access to FLASH_ACR[8:0] to set the Latency value */ - *(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)FLASH_Latency; -} - -/** - * @brief Enables or disables the Prefetch Buffer. - * @param NewState: new state of the Prefetch Buffer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_PrefetchBufferCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Enable or disable the Prefetch Buffer */ - if(NewState != DISABLE) - { - FLASH->ACR |= FLASH_ACR_PRFTEN; - } - else - { - FLASH->ACR &= (~FLASH_ACR_PRFTEN); - } -} - -/** - * @brief Enables or disables the Instruction Cache feature. - * @param NewState: new state of the Instruction Cache. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_InstructionCacheCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if(NewState != DISABLE) - { - FLASH->ACR |= FLASH_ACR_ICEN; - } - else - { - FLASH->ACR &= (~FLASH_ACR_ICEN); - } -} - -/** - * @brief Enables or disables the Data Cache feature. - * @param NewState: new state of the Data Cache. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_DataCacheCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if(NewState != DISABLE) - { - FLASH->ACR |= FLASH_ACR_DCEN; - } - else - { - FLASH->ACR &= (~FLASH_ACR_DCEN); - } -} - -/** - * @brief Resets the Instruction Cache. - * @note This function must be used only when the Instruction Cache is disabled. - * @param None - * @retval None - */ -void FLASH_InstructionCacheReset(void) -{ - FLASH->ACR |= FLASH_ACR_ICRST; -} - -/** - * @brief Resets the Data Cache. - * @note This function must be used only when the Data Cache is disabled. - * @param None - * @retval None - */ -void FLASH_DataCacheReset(void) -{ - FLASH->ACR |= FLASH_ACR_DCRST; -} - -/** - * @} - */ - -/** @defgroup FLASH_Group2 FLASH Memory Programming functions - * @brief FLASH Memory Programming functions - * -@verbatim - =============================================================================== - ##### FLASH Memory Programming functions ##### - =============================================================================== - [..] - This group includes the following functions: - (+) void FLASH_Unlock(void) - (+) void FLASH_Lock(void) - (+) FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange) - (+) FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange) - (+) FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data) - (+) FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) - (+) FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) - (+) FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data) - The following functions can be used only for STM32F42xxx/43xxx devices. - (+) FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange) - (+) FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange) - [..] - Any operation of erase or program should follow these steps: - (#) Call the FLASH_Unlock() function to enable the FLASH control register access - - (#) Call the desired function to erase sector(s) or program data - - (#) Call the FLASH_Lock() function to disable the FLASH control register access - (recommended to protect the FLASH memory against possible unwanted operation) - -@endverbatim - * @{ - */ - -/** - * @brief Unlocks the FLASH control register access - * @param None - * @retval None - */ -void FLASH_Unlock(void) -{ - if((FLASH->CR & FLASH_CR_LOCK) != RESET) - { - /* Authorize the FLASH Registers access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; - } -} - -/** - * @brief Locks the FLASH control register access - * @param None - * @retval None - */ -void FLASH_Lock(void) -{ - /* Set the LOCK Bit to lock the FLASH Registers access */ - FLASH->CR |= FLASH_CR_LOCK; -} - -/** - * @brief Erases a specified FLASH Sector. - * - * @note If an erase and a program operations are requested simustaneously, - * the erase operation is performed before the program one. - * - * @param FLASH_Sector: The Sector number to be erased. - * - * @note For STM32F405xx/407xx and STM32F415xx/417xx devices this parameter can - * be a value between FLASH_Sector_0 and FLASH_Sector_11. - * - * For STM32F42xxx/43xxx devices this parameter can be a value between - * FLASH_Sector_0 and FLASH_Sector_23. - * - * For STM32F401xx devices this parameter can be a value between - * FLASH_Sector_0 and FLASH_Sector_5. - * - * @param VoltageRange: The device voltage range which defines the erase parallelism. - * This parameter can be one of the following values: - * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, - * the operation will be done by byte (8-bit) - * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V, - * the operation will be done by half word (16-bit) - * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V, - * the operation will be done by word (32-bit) - * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, - * the operation will be done by double word (64-bit) - * - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange) -{ - uint32_t tmp_psize = 0x0; - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_SECTOR(FLASH_Sector)); - assert_param(IS_VOLTAGERANGE(VoltageRange)); - - if(VoltageRange == VoltageRange_1) - { - tmp_psize = FLASH_PSIZE_BYTE; - } - else if(VoltageRange == VoltageRange_2) - { - tmp_psize = FLASH_PSIZE_HALF_WORD; - } - else if(VoltageRange == VoltageRange_3) - { - tmp_psize = FLASH_PSIZE_WORD; - } - else - { - tmp_psize = FLASH_PSIZE_DOUBLE_WORD; - } - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase the sector */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= tmp_psize; - FLASH->CR &= SECTOR_MASK; - FLASH->CR |= FLASH_CR_SER | FLASH_Sector; - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the erase operation is completed, disable the SER Bit */ - FLASH->CR &= (~FLASH_CR_SER); - FLASH->CR &= SECTOR_MASK; - } - /* Return the Erase Status */ - return status; -} - -/** - * @brief Erases all FLASH Sectors. - * - * @note If an erase and a program operations are requested simustaneously, - * the erase operation is performed before the program one. - * - * @param VoltageRange: The device voltage range which defines the erase parallelism. - * This parameter can be one of the following values: - * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, - * the operation will be done by byte (8-bit) - * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V, - * the operation will be done by half word (16-bit) - * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V, - * the operation will be done by word (32-bit) - * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, - * the operation will be done by double word (64-bit) - * - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange) -{ - uint32_t tmp_psize = 0x0; - FLASH_Status status = FLASH_COMPLETE; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - assert_param(IS_VOLTAGERANGE(VoltageRange)); - - if(VoltageRange == VoltageRange_1) - { - tmp_psize = FLASH_PSIZE_BYTE; - } - else if(VoltageRange == VoltageRange_2) - { - tmp_psize = FLASH_PSIZE_HALF_WORD; - } - else if(VoltageRange == VoltageRange_3) - { - tmp_psize = FLASH_PSIZE_WORD; - } - else - { - tmp_psize = FLASH_PSIZE_DOUBLE_WORD; - } - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase all sectors */ -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= tmp_psize; - FLASH->CR |= (FLASH_CR_MER1 | FLASH_CR_MER2); - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the erase operation is completed, disable the MER Bit */ - FLASH->CR &= ~(FLASH_CR_MER1 | FLASH_CR_MER2); -#endif /* STM32F427_437xx || STM32F429_439xx */ - -#if defined (STM32F40_41xxx) || defined (STM32F401xx) - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= tmp_psize; - FLASH->CR |= FLASH_CR_MER; - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the erase operation is completed, disable the MER Bit */ - FLASH->CR &= (~FLASH_CR_MER); -#endif /* STM32F40_41xxx || STM32F401xx */ - - } - /* Return the Erase Status */ - return status; -} - -/** - * @brief Erases all FLASH Sectors in Bank 1. - * - * @note This function can be used only for STM32F42xxx/43xxx devices. - * - * @note If an erase and a program operations are requested simultaneously, - * the erase operation is performed before the program one. - * - * @param VoltageRange: The device voltage range which defines the erase parallelism. - * This parameter can be one of the following values: - * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, - * the operation will be done by byte (8-bit) - * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V, - * the operation will be done by half word (16-bit) - * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V, - * the operation will be done by word (32-bit) - * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, - * the operation will be done by double word (64-bit) - * - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange) -{ - uint32_t tmp_psize = 0x0; - FLASH_Status status = FLASH_COMPLETE; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - assert_param(IS_VOLTAGERANGE(VoltageRange)); - - if(VoltageRange == VoltageRange_1) - { - tmp_psize = FLASH_PSIZE_BYTE; - } - else if(VoltageRange == VoltageRange_2) - { - tmp_psize = FLASH_PSIZE_HALF_WORD; - } - else if(VoltageRange == VoltageRange_3) - { - tmp_psize = FLASH_PSIZE_WORD; - } - else - { - tmp_psize = FLASH_PSIZE_DOUBLE_WORD; - } - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase all sectors */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= tmp_psize; - FLASH->CR |= FLASH_CR_MER1; - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the erase operation is completed, disable the MER Bit */ - FLASH->CR &= (~FLASH_CR_MER1); - - } - /* Return the Erase Status */ - return status; -} - - -/** - * @brief Erases all FLASH Sectors in Bank 2. - * - * @note This function can be used only for STM32F42xxx/43xxx devices. - * - * @note If an erase and a program operations are requested simultaneously, - * the erase operation is performed before the program one. - * - * @param VoltageRange: The device voltage range which defines the erase parallelism. - * This parameter can be one of the following values: - * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, - * the operation will be done by byte (8-bit) - * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V, - * the operation will be done by half word (16-bit) - * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V, - * the operation will be done by word (32-bit) - * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, - * the operation will be done by double word (64-bit) - * - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange) -{ - uint32_t tmp_psize = 0x0; - FLASH_Status status = FLASH_COMPLETE; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - assert_param(IS_VOLTAGERANGE(VoltageRange)); - - if(VoltageRange == VoltageRange_1) - { - tmp_psize = FLASH_PSIZE_BYTE; - } - else if(VoltageRange == VoltageRange_2) - { - tmp_psize = FLASH_PSIZE_HALF_WORD; - } - else if(VoltageRange == VoltageRange_3) - { - tmp_psize = FLASH_PSIZE_WORD; - } - else - { - tmp_psize = FLASH_PSIZE_DOUBLE_WORD; - } - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase all sectors */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= tmp_psize; - FLASH->CR |= FLASH_CR_MER2; - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the erase operation is completed, disable the MER Bit */ - FLASH->CR &= (~FLASH_CR_MER2); - - } - /* Return the Erase Status */ - return status; -} - -/** - * @brief Programs a double word (64-bit) at a specified address. - * @note This function must be used when the device voltage range is from - * 2.7V to 3.6V and an External Vpp is present. - * - * @note If an erase and a program operations are requested simustaneously, - * the erase operation is performed before the program one. - * - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD; - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint64_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the program operation is completed, disable the PG Bit */ - FLASH->CR &= (~FLASH_CR_PG); - } - /* Return the Program Status */ - return status; -} - -/** - * @brief Programs a word (32-bit) at a specified address. - * - * @note This function must be used when the device voltage range is from 2.7V to 3.6V. - * - * @note If an erase and a program operations are requested simustaneously, - * the erase operation is performed before the program one. - * - * @param Address: specifies the address to be programmed. - * This parameter can be any address in Program memory zone or in OTP zone. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= FLASH_PSIZE_WORD; - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint32_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the program operation is completed, disable the PG Bit */ - FLASH->CR &= (~FLASH_CR_PG); - } - /* Return the Program Status */ - return status; -} - -/** - * @brief Programs a half word (16-bit) at a specified address. - * @note This function must be used when the device voltage range is from 2.1V to 3.6V. - * - * @note If an erase and a program operations are requested simustaneously, - * the erase operation is performed before the program one. - * - * @param Address: specifies the address to be programmed. - * This parameter can be any address in Program memory zone or in OTP zone. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= FLASH_PSIZE_HALF_WORD; - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint16_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the program operation is completed, disable the PG Bit */ - FLASH->CR &= (~FLASH_CR_PG); - } - /* Return the Program Status */ - return status; -} - -/** - * @brief Programs a byte (8-bit) at a specified address. - * @note This function can be used within all the device supply voltage ranges. - * - * @note If an erase and a program operations are requested simustaneously, - * the erase operation is performed before the program one. - * - * @param Address: specifies the address to be programmed. - * This parameter can be any address in Program memory zone or in OTP zone. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= FLASH_PSIZE_BYTE; - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint8_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the program operation is completed, disable the PG Bit */ - FLASH->CR &= (~FLASH_CR_PG); - } - - /* Return the Program Status */ - return status; -} - -/** - * @} - */ - -/** @defgroup FLASH_Group3 Option Bytes Programming functions - * @brief Option Bytes Programming functions - * -@verbatim - =============================================================================== - ##### Option Bytes Programming functions ##### - =============================================================================== - [..] - This group includes the following functions: - (+) void FLASH_OB_Unlock(void) - (+) void FLASH_OB_Lock(void) - (+) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) - (+) void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState) - (+) void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PCROPSelect) - (+) void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState) - (+) void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState) - (+) void FLASH_OB_RDPConfig(uint8_t OB_RDP) - (+) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) - (+) void FLASH_OB_BORConfig(uint8_t OB_BOR) - (+) FLASH_Status FLASH_ProgramOTP(uint32_t Address, uint32_t Data) - (+) FLASH_Status FLASH_OB_Launch(void) - (+) uint32_t FLASH_OB_GetUser(void) - (+) uint8_t FLASH_OB_GetWRP(void) - (+) uint8_t FLASH_OB_GetWRP1(void) - (+) uint8_t FLASH_OB_GetPCROP(void) - (+) uint8_t FLASH_OB_GetPCROP1(void) - (+) uint8_t FLASH_OB_GetRDP(void) - (+) uint8_t FLASH_OB_GetBOR(void) - [..] - The following function can be used only for STM32F42xxx/43xxx devices. - (+) void FLASH_OB_BootConfig(uint8_t OB_BOOT) - [..] - Any operation of erase or program should follow these steps: - (#) Call the FLASH_OB_Unlock() function to enable the FLASH option control - register access - - (#) Call one or several functions to program the desired Option Bytes: - (++) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) - => to Enable/Disable the desired sector write protection - (++) void FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read - Protection Level - (++) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) - => to configure the user Option Bytes. - (++) void FLASH_OB_BORConfig(uint8_t OB_BOR) => to set the BOR Level - - (#) Once all needed Option Bytes to be programmed are correctly written, - call the FLASH_OB_Launch() function to launch the Option Bytes - programming process. - - -@- When changing the IWDG mode from HW to SW or from SW to HW, a system - reset is needed to make the change effective. - - (#) Call the FLASH_OB_Lock() function to disable the FLASH option control - register access (recommended to protect the Option Bytes against - possible unwanted operations) - -@endverbatim - * @{ - */ - -/** - * @brief Unlocks the FLASH Option Control Registers access. - * @param None - * @retval None - */ -void FLASH_OB_Unlock(void) -{ - if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET) - { - /* Authorizes the Option Byte register programming */ - FLASH->OPTKEYR = FLASH_OPT_KEY1; - FLASH->OPTKEYR = FLASH_OPT_KEY2; - } -} - -/** - * @brief Locks the FLASH Option Control Registers access. - * @param None - * @retval None - */ -void FLASH_OB_Lock(void) -{ - /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ - FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK; -} - -/** - * @brief Enables or disables the write protection of the desired sectors, for the first - * 1 Mb of the Flash - * - * @note When the memory read protection level is selected (RDP level = 1), - * it is not possible to program or erase the flash sector i if CortexM4 - * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 - * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). - * - * @param OB_WRP: specifies the sector(s) to be write protected or unprotected. - * This parameter can be one of the following values: - * @arg OB_WRP: A value between OB_WRP_Sector0 and OB_WRP_Sector11 - * @arg OB_WRP_Sector_All - * @param Newstate: new state of the Write Protection. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_WRP(OB_WRP)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - if(NewState != DISABLE) - { - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_WRP); - } - else - { - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)OB_WRP; - } - } -} - -/** - * @brief Enables or disables the write protection of the desired sectors, for the second - * 1 Mb of the Flash - * - * @note This function can be used only for STM32F42xxx/43xxx devices. - * - * @note When the memory read out protection is selected (RDP level = 1), - * it is not possible to program or erase the flash sector i if CortexM4 - * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 - * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). - * - * @param OB_WRP: specifies the sector(s) to be write protected or unprotected. - * This parameter can be one of the following values: - * @arg OB_WRP: A value between OB_WRP_Sector12 and OB_WRP_Sector23 - * @arg OB_WRP_Sector_All - * @param Newstate: new state of the Write Protection. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_WRP(OB_WRP)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - if(NewState != DISABLE) - { - *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~OB_WRP); - } - else - { - *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)OB_WRP; - } - } -} - -/** - * @brief Select the Protection Mode (SPRMOD). - * - * @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx devices. - * - * @note After PCROP activation, Option Byte modification is not possible. - * Exception made for the global Read Out Protection modification level (level1 to level0) - * @note Once SPRMOD bit is active unprotection of a protected sector is not possible - * - * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag - * - * @note Some Precautions should be taken when activating the PCROP feature : - * The active value of nWRPi bits is inverted when PCROP mode is active, this means if SPRMOD = 1 - * and WRPi = 1 (default value), then the user sector i is read/write protected. - * In order to avoid activation of PCROP Mode for undesired sectors, please follow the - * below safety sequence : - * - Disable PCROP for all Sectors using FLASH_OB_PCROPConfig(OB_PCROP_Sector_All, DISABLE) function - * for Bank1 or FLASH_OB_PCROP1Config(OB_PCROP_Sector_All, DISABLE) function for Bank2 - * - Enable PCROP for the desired Sector i using FLASH_OB_PCROPConfig(Sector i, ENABLE) function - * - Activate the PCROP Mode FLASH_OB_PCROPSelectionConfig() function. - * - * @param OB_PCROP: Select the Protection Mode of nWPRi bits - * This parameter can be one of the following values: - * @arg OB_PcROP_Disable: nWRPi control the write protection of respective user sectors. - * @arg OB_PcROP_Enable: nWRPi control the read&write protection (PCROP) of respective user sectors. - * @retval None - */ -void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PcROP) -{ - uint8_t optiontmp = 0xFF; - - /* Check the parameters */ - assert_param(IS_OB_PCROP_SELECT(OB_PcROP)); - - /* Mask SPRMOD bit */ - optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F); - /* Update Option Byte */ - *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PcROP | optiontmp); - -} - -/** - * @brief Enables or disables the read/write protection (PCROP) of the desired - * sectors, for the first 1 MB of the Flash. - * - * @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx devices. - * - * @param OB_PCROP: specifies the sector(s) to be read/write protected or unprotected. - * This parameter can be one of the following values: - * @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector11 for - * STM32F42xxx/43xxx devices and between OB_PCROP_Sector0 and - * OB_PCROP_Sector5 for STM32F401xx devices. - * @arg OB_PCROP_Sector_All - * @param Newstate: new state of the Write Protection. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_PCROP(OB_PCROP)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - if(NewState != DISABLE) - { - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)OB_PCROP; - } - else - { - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_PCROP); - } - } -} - -/** - * @brief Enables or disables the read/write protection (PCROP) of the desired - * sectors - * - * @note This function can be used only for STM32F42xxx/43xxx devices. - * - * @param OB_PCROP: specifies the sector(s) to be read/write protected or unprotected. - * This parameter can be one of the following values: - * @arg OB_PCROP: A value between OB_PCROP_Sector12 and OB_PCROP_Sector23 - * @arg OB_PCROP_Sector_All - * @param Newstate: new state of the Write Protection. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_PCROP(OB_PCROP)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - if(NewState != DISABLE) - { - *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)OB_PCROP; - } - else - { - *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~OB_PCROP); - } - } -} - - -/** - * @brief Sets the read protection level. - * @param OB_RDP: specifies the read protection level. - * This parameter can be one of the following values: - * @arg OB_RDP_Level_0: No protection - * @arg OB_RDP_Level_1: Read protection of the memory - * @arg OB_RDP_Level_2: Full chip protection - * - * /!\ Warning /!\ When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 - * - * @retval None - */ -void FLASH_OB_RDPConfig(uint8_t OB_RDP) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_RDP(OB_RDP)); - - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = OB_RDP; - - } -} - -/** - * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. - * @param OB_IWDG: Selects the IWDG mode - * This parameter can be one of the following values: - * @arg OB_IWDG_SW: Software IWDG selected - * @arg OB_IWDG_HW: Hardware IWDG selected - * @param OB_STOP: Reset event when entering STOP mode. - * This parameter can be one of the following values: - * @arg OB_STOP_NoRST: No reset generated when entering in STOP - * @arg OB_STOP_RST: Reset generated when entering in STOP - * @param OB_STDBY: Reset event when entering Standby mode. - * This parameter can be one of the following values: - * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY - * @arg OB_STDBY_RST: Reset generated when entering in STANDBY - * @retval None - */ -void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) -{ - uint8_t optiontmp = 0xFF; - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); - assert_param(IS_OB_STOP_SOURCE(OB_STOP)); - assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) - /* Mask OPTLOCK, OPTSTRT, BOR_LEV and BFB2 bits */ - optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1F); -#endif /* STM32F427_437xx || STM32F429_439xx */ - -#if defined (STM32F40_41xxx) || defined (STM32F401xx) - /* Mask OPTLOCK, OPTSTRT and BOR_LEV bits */ - optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0F); -#endif /* STM32F40_41xxx || STM32F401xx */ - - /* Update User Option Byte */ - *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = OB_IWDG | (uint8_t)(OB_STDBY | (uint8_t)(OB_STOP | ((uint8_t)optiontmp))); - } -} - -/** - * @brief Configure the Dual Bank Boot. - * - * @note This function can be used only for STM32F42xxx/43xxx devices. - * - * @param OB_BOOT: specifies the Dual Bank Boot Option byte. - * This parameter can be one of the following values: - * @arg OB_Dual_BootEnabled: Dual Bank Boot Enable - * @arg OB_Dual_BootDisabled: Dual Bank Boot Disabled - * @retval None - */ -void FLASH_OB_BootConfig(uint8_t OB_BOOT) -{ - /* Check the parameters */ - assert_param(IS_OB_BOOT(OB_BOOT)); - - /* Set Dual Bank Boot */ - *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BFB2); - *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOOT; - -} - -/** - * @brief Sets the BOR Level. - * @param OB_BOR: specifies the Option Bytes BOR Reset Level. - * This parameter can be one of the following values: - * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V - * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V - * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V - * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V - * @retval None - */ -void FLASH_OB_BORConfig(uint8_t OB_BOR) -{ - /* Check the parameters */ - assert_param(IS_OB_BOR(OB_BOR)); - - /* Set the BOR Level */ - *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV); - *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOR; - -} - -/** - * @brief Launch the option byte loading. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_OB_Launch(void) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Set the OPTSTRT bit in OPTCR register */ - *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - return status; -} - -/** - * @brief Returns the FLASH User Option Bytes values. - * @param None - * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1) - * and RST_STDBY(Bit2). - */ -uint8_t FLASH_OB_GetUser(void) -{ - /* Return the User Option Byte */ - return (uint8_t)(FLASH->OPTCR >> 5); -} - -/** - * @brief Returns the FLASH Write Protection Option Bytes value. - * @param None - * @retval The FLASH Write Protection Option Bytes value - */ -uint16_t FLASH_OB_GetWRP(void) -{ - /* Return the FLASH write protection Register value */ - return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS)); -} - -/** - * @brief Returns the FLASH Write Protection Option Bytes value. - * - * @note This function can be used only for STM32F42xxx/43xxx devices. - * - * @param None - * @retval The FLASH Write Protection Option Bytes value - */ -uint16_t FLASH_OB_GetWRP1(void) -{ - /* Return the FLASH write protection Register value */ - return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS)); -} - -/** - * @brief Returns the FLASH PC Read/Write Protection Option Bytes value. - * - * @note This function can be used only for STM32F42xxx/43xxx devices and STM32F401xx devices. - * - * @param None - * @retval The FLASH PC Read/Write Protection Option Bytes value - */ -uint16_t FLASH_OB_GetPCROP(void) -{ - /* Return the FLASH PC Read/write protection Register value */ - return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS)); -} - -/** - * @brief Returns the FLASH PC Read/Write Protection Option Bytes value. - * - * @note This function can be used only for STM32F42xxx/43xxx devices. - * - * @param None - * @retval The FLASH PC Read/Write Protection Option Bytes value - */ -uint16_t FLASH_OB_GetPCROP1(void) -{ - /* Return the FLASH write protection Register value */ - return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS)); -} - -/** - * @brief Returns the FLASH Read Protection level. - * @param None - * @retval FLASH ReadOut Protection Status: - * - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set - * - RESET, when OB_RDP_Level_0 is set - */ -FlagStatus FLASH_OB_GetRDP(void) -{ - FlagStatus readstatus = RESET; - - if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) != (uint8_t)OB_RDP_Level_0)) - { - readstatus = SET; - } - else - { - readstatus = RESET; - } - return readstatus; -} - -/** - * @brief Returns the FLASH BOR level. - * @param None - * @retval The FLASH BOR level: - * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V - * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V - * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V - * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V - */ -uint8_t FLASH_OB_GetBOR(void) -{ - /* Return the FLASH BOR level */ - return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0C); -} - -/** - * @} - */ - -/** @defgroup FLASH_Group4 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified FLASH interrupts. - * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg FLASH_IT_ERR: FLASH Error Interrupt - * @arg FLASH_IT_EOP: FLASH end of operation Interrupt - * @retval None - */ -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FLASH_IT(FLASH_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if(NewState != DISABLE) - { - /* Enable the interrupt sources */ - FLASH->CR |= FLASH_IT; - } - else - { - /* Disable the interrupt sources */ - FLASH->CR &= ~(uint32_t)FLASH_IT; - } -} - -/** - * @brief Checks whether the specified FLASH flag is set or not. - * @param FLASH_FLAG: specifies the FLASH flag to check. - * This parameter can be one of the following values: - * @arg FLASH_FLAG_EOP: FLASH End of Operation flag - * @arg FLASH_FLAG_OPERR: FLASH operation Error flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag - * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag - * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag - * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag - * @arg FLASH_FLAG_RDERR: FLASH (PCROP) Read Protection error flag (STM32F42/43xxx and STM32F401xx devices) - * @arg FLASH_FLAG_BSY: FLASH Busy flag - * @retval The new state of FLASH_FLAG (SET or RESET). - */ -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)); - - if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the new state of FLASH_FLAG (SET or RESET) */ - return bitstatus; -} - -/** - * @brief Clears the FLASH's pending flags. - * @param FLASH_FLAG: specifies the FLASH flags to clear. - * This parameter can be any combination of the following values: - * @arg FLASH_FLAG_EOP: FLASH End of Operation flag - * @arg FLASH_FLAG_OPERR: FLASH operation Error flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag - * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag - * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag - * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag - * @arg FLASH_FLAG_RDERR: FLASH Read Protection error flag (STM32F42/43xxx and STM32F401xx devices) - * @retval None - */ -void FLASH_ClearFlag(uint32_t FLASH_FLAG) -{ - /* Check the parameters */ - assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)); - - /* Clear the flags */ - FLASH->SR = FLASH_FLAG; -} - -/** - * @brief Returns the FLASH Status. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_RD, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_GetStatus(void) -{ - FLASH_Status flashstatus = FLASH_COMPLETE; - - if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) - { - flashstatus = FLASH_BUSY; - } - else - { - if((FLASH->SR & FLASH_FLAG_WRPERR) != (uint32_t)0x00) - { - flashstatus = FLASH_ERROR_WRP; - } - else - { - if((FLASH->SR & FLASH_FLAG_RDERR) != (uint32_t)0x00) - { - flashstatus = FLASH_ERROR_RD; - } - else - { - if((FLASH->SR & (uint32_t)0xEF) != (uint32_t)0x00) - { - flashstatus = FLASH_ERROR_PROGRAM; - } - else - { - if((FLASH->SR & FLASH_FLAG_OPERR) != (uint32_t)0x00) - { - flashstatus = FLASH_ERROR_OPERATION; - } - else - { - flashstatus = FLASH_COMPLETE; - } - } - } - } - } - /* Return the FLASH Status */ - return flashstatus; -} - -/** - * @brief Waits for a FLASH operation to complete. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_WaitForLastOperation(void) -{ - __IO FLASH_Status status = FLASH_COMPLETE; - - /* Check for the FLASH Status */ - status = FLASH_GetStatus(); - - /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. - Even if the FLASH operation fails, the BUSY flag will be reset and an error - flag will be set */ - while(status == FLASH_BUSY) - { - status = FLASH_GetStatus(); - } - /* Return the operation status */ - return status; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm32f4xx_flash.h b/stm/stmperiph/stm32f4xx_flash.h deleted file mode 100644 index ee3e9a9fe..000000000 --- a/stm/stmperiph/stm32f4xx_flash.h +++ /dev/null @@ -1,482 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_flash.h - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief This file contains all the functions prototypes for the FLASH - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_FLASH_H -#define __STM32F4xx_FLASH_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup FLASH - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** - * @brief FLASH Status - */ -typedef enum -{ - FLASH_BUSY = 1, - FLASH_ERROR_RD, - FLASH_ERROR_PGS, - FLASH_ERROR_PGP, - FLASH_ERROR_PGA, - FLASH_ERROR_WRP, - FLASH_ERROR_PROGRAM, - FLASH_ERROR_OPERATION, - FLASH_COMPLETE -}FLASH_Status; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup FLASH_Exported_Constants - * @{ - */ - -/** @defgroup Flash_Latency - * @{ - */ -#define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */ -#define FLASH_Latency_1 ((uint8_t)0x0001) /*!< FLASH One Latency cycle */ -#define FLASH_Latency_2 ((uint8_t)0x0002) /*!< FLASH Two Latency cycles */ -#define FLASH_Latency_3 ((uint8_t)0x0003) /*!< FLASH Three Latency cycles */ -#define FLASH_Latency_4 ((uint8_t)0x0004) /*!< FLASH Four Latency cycles */ -#define FLASH_Latency_5 ((uint8_t)0x0005) /*!< FLASH Five Latency cycles */ -#define FLASH_Latency_6 ((uint8_t)0x0006) /*!< FLASH Six Latency cycles */ -#define FLASH_Latency_7 ((uint8_t)0x0007) /*!< FLASH Seven Latency cycles */ -#define FLASH_Latency_8 ((uint8_t)0x0008) /*!< FLASH Eight Latency cycles */ -#define FLASH_Latency_9 ((uint8_t)0x0009) /*!< FLASH Nine Latency cycles */ -#define FLASH_Latency_10 ((uint8_t)0x000A) /*!< FLASH Ten Latency cycles */ -#define FLASH_Latency_11 ((uint8_t)0x000B) /*!< FLASH Eleven Latency cycles */ -#define FLASH_Latency_12 ((uint8_t)0x000C) /*!< FLASH Twelve Latency cycles */ -#define FLASH_Latency_13 ((uint8_t)0x000D) /*!< FLASH Thirteen Latency cycles */ -#define FLASH_Latency_14 ((uint8_t)0x000E) /*!< FLASH Fourteen Latency cycles */ -#define FLASH_Latency_15 ((uint8_t)0x000F) /*!< FLASH Fifteen Latency cycles */ - - -#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ - ((LATENCY) == FLASH_Latency_1) || \ - ((LATENCY) == FLASH_Latency_2) || \ - ((LATENCY) == FLASH_Latency_3) || \ - ((LATENCY) == FLASH_Latency_4) || \ - ((LATENCY) == FLASH_Latency_5) || \ - ((LATENCY) == FLASH_Latency_6) || \ - ((LATENCY) == FLASH_Latency_7) || \ - ((LATENCY) == FLASH_Latency_8) || \ - ((LATENCY) == FLASH_Latency_9) || \ - ((LATENCY) == FLASH_Latency_10) || \ - ((LATENCY) == FLASH_Latency_11) || \ - ((LATENCY) == FLASH_Latency_12) || \ - ((LATENCY) == FLASH_Latency_13) || \ - ((LATENCY) == FLASH_Latency_14) || \ - ((LATENCY) == FLASH_Latency_15)) -/** - * @} - */ - -/** @defgroup FLASH_Voltage_Range - * @{ - */ -#define VoltageRange_1 ((uint8_t)0x00) /*!< Device operating range: 1.8V to 2.1V */ -#define VoltageRange_2 ((uint8_t)0x01) /*!= 0x08000000) && ((ADDRESS) < 0x081FFFFF)) ||\ - (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F))) -#endif /* STM32F427_437xx || STM32F429_439xx */ - -#if defined (STM32F40_41xxx) -#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) ||\ - (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F))) -#endif /* STM32F40_41xxx */ - -#if defined (STM32F401xx) -#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0803FFFF)) ||\ - (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F))) -#endif /* STM32F401xx */ -/** - * @} - */ - -/** @defgroup Option_Bytes_Write_Protection - * @{ - */ -#define OB_WRP_Sector_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */ -#define OB_WRP_Sector_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */ -#define OB_WRP_Sector_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */ -#define OB_WRP_Sector_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */ -#define OB_WRP_Sector_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */ -#define OB_WRP_Sector_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */ -#define OB_WRP_Sector_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */ -#define OB_WRP_Sector_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */ -#define OB_WRP_Sector_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */ -#define OB_WRP_Sector_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */ -#define OB_WRP_Sector_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */ -#define OB_WRP_Sector_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */ -#define OB_WRP_Sector_12 ((uint32_t)0x00000001) /*!< Write protection of Sector12 */ -#define OB_WRP_Sector_13 ((uint32_t)0x00000002) /*!< Write protection of Sector13 */ -#define OB_WRP_Sector_14 ((uint32_t)0x00000004) /*!< Write protection of Sector14 */ -#define OB_WRP_Sector_15 ((uint32_t)0x00000008) /*!< Write protection of Sector15 */ -#define OB_WRP_Sector_16 ((uint32_t)0x00000010) /*!< Write protection of Sector16 */ -#define OB_WRP_Sector_17 ((uint32_t)0x00000020) /*!< Write protection of Sector17 */ -#define OB_WRP_Sector_18 ((uint32_t)0x00000040) /*!< Write protection of Sector18 */ -#define OB_WRP_Sector_19 ((uint32_t)0x00000080) /*!< Write protection of Sector19 */ -#define OB_WRP_Sector_20 ((uint32_t)0x00000100) /*!< Write protection of Sector20 */ -#define OB_WRP_Sector_21 ((uint32_t)0x00000200) /*!< Write protection of Sector21 */ -#define OB_WRP_Sector_22 ((uint32_t)0x00000400) /*!< Write protection of Sector22 */ -#define OB_WRP_Sector_23 ((uint32_t)0x00000800) /*!< Write protection of Sector23 */ -#define OB_WRP_Sector_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */ - -#define IS_OB_WRP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) -/** - * @} - */ - -/** @defgroup Selection_Protection_Mode - * @{ - */ -#define OB_PcROP_Disable ((uint8_t)0x00) /*!< Disabled PcROP, nWPRi bits used for Write Protection on sector i */ -#define OB_PcROP_Enable ((uint8_t)0x80) /*!< Enable PcROP, nWPRi bits used for PCRoP Protection on sector i */ -#define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PcROP_Disable) || ((PCROP) == OB_PcROP_Enable)) -/** - * @} - */ - -/** @defgroup Option_Bytes_PC_ReadWrite_Protection - * @{ - */ -#define OB_PCROP_Sector_0 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0 */ -#define OB_PCROP_Sector_1 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1 */ -#define OB_PCROP_Sector_2 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2 */ -#define OB_PCROP_Sector_3 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector3 */ -#define OB_PCROP_Sector_4 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector4 */ -#define OB_PCROP_Sector_5 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector5 */ -#define OB_PCROP_Sector_6 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector6 */ -#define OB_PCROP_Sector_7 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector7 */ -#define OB_PCROP_Sector_8 ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector8 */ -#define OB_PCROP_Sector_9 ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector9 */ -#define OB_PCROP_Sector_10 ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector10 */ -#define OB_PCROP_Sector_11 ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector11 */ -#define OB_PCROP_Sector_12 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector12 */ -#define OB_PCROP_Sector_13 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector13 */ -#define OB_PCROP_Sector_14 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector14 */ -#define OB_PCROP_Sector_15 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector15 */ -#define OB_PCROP_Sector_16 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector16 */ -#define OB_PCROP_Sector_17 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector17 */ -#define OB_PCROP_Sector_18 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector18 */ -#define OB_PCROP_Sector_19 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector19 */ -#define OB_PCROP_Sector_20 ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector20 */ -#define OB_PCROP_Sector_21 ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector21 */ -#define OB_PCROP_Sector_22 ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector22 */ -#define OB_PCROP_Sector_23 ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector23 */ -#define OB_PCROP_Sector_All ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors */ - -#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_Read_Protection - * @{ - */ -#define OB_RDP_Level_0 ((uint8_t)0xAA) -#define OB_RDP_Level_1 ((uint8_t)0x55) -/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /*!< Warning: When enabling read protection level 2 - it's no more possible to go back to level 1 or 0 */ -#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\ - ((LEVEL) == OB_RDP_Level_1))/*||\ - ((LEVEL) == OB_RDP_Level_2))*/ -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_IWatchdog - * @{ - */ -#define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */ -#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */ -#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_nRST_STOP - * @{ - */ -#define OB_STOP_NoRST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */ -#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */ -#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) -/** - * @} - */ - - -/** @defgroup FLASH_Option_Bytes_nRST_STDBY - * @{ - */ -#define OB_STDBY_NoRST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */ -#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */ -#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) -/** - * @} - */ - -/** @defgroup FLASH_BOR_Reset_Level - * @{ - */ -#define OB_BOR_LEVEL3 ((uint8_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */ -#define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */ -#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */ -#define OB_BOR_OFF ((uint8_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */ -#define IS_OB_BOR(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\ - ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF)) -/** - * @} - */ - -/** @defgroup FLASH_Dual_Boot - * @{ - */ -#define OB_Dual_BootEnabled ((uint8_t)0x10) /*!< Dual Bank Boot Enable */ -#define OB_Dual_BootDisabled ((uint8_t)0x00) /*!< Dual Bank Boot Disable, always boot on User Flash */ -#define IS_OB_BOOT(BOOT) (((BOOT) == OB_Dual_BootEnabled) || ((BOOT) == OB_Dual_BootDisabled)) -/** - * @} - */ - -/** @defgroup FLASH_Interrupts - * @{ - */ -#define FLASH_IT_EOP ((uint32_t)0x01000000) /*!< End of FLASH Operation Interrupt source */ -#define FLASH_IT_ERR ((uint32_t)0x02000000) /*!< Error Interrupt source */ -#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFCFFFFFF) == 0x00000000) && ((IT) != 0x00000000)) -/** - * @} - */ - -/** @defgroup FLASH_Flags - * @{ - */ -#define FLASH_FLAG_EOP ((uint32_t)0x00000001) /*!< FLASH End of Operation flag */ -#define FLASH_FLAG_OPERR ((uint32_t)0x00000002) /*!< FLASH operation Error flag */ -#define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ -#define FLASH_FLAG_PGAERR ((uint32_t)0x00000020) /*!< FLASH Programming Alignment error flag */ -#define FLASH_FLAG_PGPERR ((uint32_t)0x00000040) /*!< FLASH Programming Parallelism error flag */ -#define FLASH_FLAG_PGSERR ((uint32_t)0x00000080) /*!< FLASH Programming Sequence error flag */ -#define FLASH_FLAG_RDERR ((uint32_t)0x00000100) /*!< Read Protection error flag (PCROP) */ -#define FLASH_FLAG_BSY ((uint32_t)0x00010000) /*!< FLASH Busy flag */ -#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFE0C) == 0x00000000) && ((FLAG) != 0x00000000)) -#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_OPERR) || \ - ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) || \ - ((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_PGSERR) || \ - ((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_RDERR)) -/** - * @} - */ - -/** @defgroup FLASH_Program_Parallelism - * @{ - */ -#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000) -#define FLASH_PSIZE_HALF_WORD ((uint32_t)0x00000100) -#define FLASH_PSIZE_WORD ((uint32_t)0x00000200) -#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)0x00000300) -#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFF) -/** - * @} - */ - -/** @defgroup FLASH_Keys - * @{ - */ -#define RDP_KEY ((uint16_t)0x00A5) -#define FLASH_KEY1 ((uint32_t)0x45670123) -#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) -#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3B) -#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7F) -/** - * @} - */ - -/** - * @brief ACR register byte 0 (Bits[7:0]) base address - */ -#define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00) -/** - * @brief OPTCR register byte 0 (Bits[7:0]) base address - */ -#define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14) -/** - * @brief OPTCR register byte 1 (Bits[15:8]) base address - */ -#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15) -/** - * @brief OPTCR register byte 2 (Bits[23:16]) base address - */ -#define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16) -/** - * @brief OPTCR register byte 3 (Bits[31:24]) base address - */ -#define OPTCR_BYTE3_ADDRESS ((uint32_t)0x40023C17) - -/** - * @brief OPTCR1 register byte 0 (Bits[7:0]) base address - */ -#define OPTCR1_BYTE2_ADDRESS ((uint32_t)0x40023C1A) - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* FLASH Interface configuration functions ************************************/ -void FLASH_SetLatency(uint32_t FLASH_Latency); -void FLASH_PrefetchBufferCmd(FunctionalState NewState); -void FLASH_InstructionCacheCmd(FunctionalState NewState); -void FLASH_DataCacheCmd(FunctionalState NewState); -void FLASH_InstructionCacheReset(void); -void FLASH_DataCacheReset(void); - -/* FLASH Memory Programming functions *****************************************/ -void FLASH_Unlock(void); -void FLASH_Lock(void); -FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange); -FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange); -FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange); -FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange); -FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data); -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); -FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data); - -/* Option Bytes Programming functions *****************************************/ -void FLASH_OB_Unlock(void); -void FLASH_OB_Lock(void); -void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState); -void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState); -void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PcROP); -void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState); -void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState); -void FLASH_OB_RDPConfig(uint8_t OB_RDP); -void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); -void FLASH_OB_BORConfig(uint8_t OB_BOR); -void FLASH_OB_BootConfig(uint8_t OB_BOOT); -FLASH_Status FLASH_OB_Launch(void); -uint8_t FLASH_OB_GetUser(void); -uint16_t FLASH_OB_GetWRP(void); -uint16_t FLASH_OB_GetWRP1(void); -uint16_t FLASH_OB_GetPCROP(void); -uint16_t FLASH_OB_GetPCROP1(void); -FlagStatus FLASH_OB_GetRDP(void); -uint8_t FLASH_OB_GetBOR(void); - -/* Interrupts and flags management functions **********************************/ -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); -void FLASH_ClearFlag(uint32_t FLASH_FLAG); -FLASH_Status FLASH_GetStatus(void); -FLASH_Status FLASH_WaitForLastOperation(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_FLASH_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm32f4xx_gpio.c b/stm/stmperiph/stm32f4xx_gpio.c deleted file mode 100644 index c099e948e..000000000 --- a/stm/stmperiph/stm32f4xx_gpio.c +++ /dev/null @@ -1,611 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_gpio.c - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief This file provides firmware functions to manage the following - * functionalities of the GPIO peripheral: - * + Initialization and Configuration - * + GPIO Read and Write - * + GPIO Alternate functions configuration - * -@verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - (#) Enable the GPIO AHB clock using the following function - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - - (#) Configure the GPIO pin(s) using GPIO_Init() - Four possible configuration are available for each pin: - (++) Input: Floating, Pull-up, Pull-down. - (++) Output: Push-Pull (Pull-up, Pull-down or no Pull) - Open Drain (Pull-up, Pull-down or no Pull). In output mode, the speed - is configurable: 2 MHz, 25 MHz, 50 MHz or 100 MHz. - (++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull) Open - Drain (Pull-up, Pull-down or no Pull). - (++) Analog: required mode when a pin is to be used as ADC channel or DAC - output. - - (#) Peripherals alternate function: - (++) For ADC and DAC, configure the desired pin in analog mode using - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN; - (+++) For other peripherals (TIM, USART...): - (+++) Connect the pin to the desired peripherals' Alternate - Function (AF) using GPIO_PinAFConfig() function - (+++) Configure the desired pin in alternate function mode using - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - (+++) Select the type, pull-up/pull-down and output speed via - GPIO_PuPd, GPIO_OType and GPIO_Speed members - (+++) Call GPIO_Init() function - - (#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit() - - (#) To set/reset the level of a pin configured in output mode use - GPIO_SetBits()/GPIO_ResetBits() - - (#) During and just after reset, the alternate functions are not - active and the GPIO pins are configured in input floating mode (except JTAG - pins). - - (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose - (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has - priority over the GPIO function. - - (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as - general purpose PH0 and PH1, respectively, when the HSE oscillator is off. - The HSE has priority over the GPIO function. - -@endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_gpio.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup GPIO - * @brief GPIO driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup GPIO_Private_Functions - * @{ - */ - -/** @defgroup GPIO_Group1 Initialization and Configuration - * @brief Initialization and Configuration - * -@verbatim - =============================================================================== - ##### Initialization and Configuration ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief De-initializes the GPIOx peripheral registers to their default reset values. - * @note By default, The GPIO pins are configured in input floating mode (except JTAG pins). - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @retval None - */ -void GPIO_DeInit(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - if (GPIOx == GPIOA) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, DISABLE); - } - else if (GPIOx == GPIOB) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, DISABLE); - } - else if (GPIOx == GPIOC) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, DISABLE); - } - else if (GPIOx == GPIOD) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, DISABLE); - } - else if (GPIOx == GPIOE) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, DISABLE); - } - else if (GPIOx == GPIOF) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, DISABLE); - } - else if (GPIOx == GPIOG) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, DISABLE); - } - else if (GPIOx == GPIOH) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, DISABLE); - } - - else if (GPIOx == GPIOI) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE); - } - else if (GPIOx == GPIOJ) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOJ, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOJ, DISABLE); - } - else - { - if (GPIOx == GPIOK) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOK, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOK, DISABLE); - } - } -} - -/** - * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains - * the configuration information for the specified GPIO peripheral. - * @retval None - */ -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) -{ - uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); - assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); - assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd)); - - /* ------------------------- Configure the port pins ---------------- */ - /*-- GPIO Mode Configuration --*/ - for (pinpos = 0x00; pinpos < 0x10; pinpos++) - { - pos = ((uint32_t)0x01) << pinpos; - /* Get the port pins position */ - currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; - - if (currentpin == pos) - { - GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2)); - GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2)); - - if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF)) - { - /* Check Speed mode parameters */ - assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); - - /* Speed mode configuration */ - GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2)); - GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2)); - - /* Check Output mode parameters */ - assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType)); - - /* Output mode configuration*/ - GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ; - GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos)); - } - - /* Pull-up Pull down resistor configuration*/ - GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2)); - GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2)); - } - } -} - -/** - * @brief Fills each GPIO_InitStruct member with its default value. - * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized. - * @retval None - */ -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) -{ - /* Reset GPIO init structure parameters values */ - GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStruct->GPIO_OType = GPIO_OType_PP; - GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL; -} - -/** - * @brief Locks GPIO Pins configuration registers. - * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, - * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. - * @note The configuration of the locked GPIO pins can no longer be modified - * until the next reset. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @param GPIO_Pin: specifies the port bit to be locked. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - __IO uint32_t tmp = 0x00010000; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - tmp |= GPIO_Pin; - /* Set LCKK bit */ - GPIOx->LCKR = tmp; - /* Reset LCKK bit */ - GPIOx->LCKR = GPIO_Pin; - /* Set LCKK bit */ - GPIOx->LCKR = tmp; - /* Read LCKK bit*/ - tmp = GPIOx->LCKR; - /* Read LCKK bit*/ - tmp = GPIOx->LCKR; -} - -/** - * @} - */ - -/** @defgroup GPIO_Group2 GPIO Read and Write - * @brief GPIO Read and Write - * -@verbatim - =============================================================================== - ##### GPIO Read and Write ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Reads the specified input port pin. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @param GPIO_Pin: specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * @retval The input port pin value. - */ -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - return bitstatus; -} - -/** - * @brief Reads the specified GPIO input data port. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @retval GPIO input data port value. - */ -uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - return ((uint16_t)GPIOx->IDR); -} - -/** - * @brief Reads the specified output data port bit. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @param GPIO_Pin: specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * @retval The output port pin value. - */ -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - - if (((GPIOx->ODR) & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - return bitstatus; -} - -/** - * @brief Reads the specified GPIO output data port. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @retval GPIO output data port value. - */ -uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - return ((uint16_t)GPIOx->ODR); -} - -/** - * @brief Sets the selected data port bits. - * @note This functions uses GPIOx_BSRR register to allow atomic read/modify - * accesses. In this way, there is no risk of an IRQ occurring between - * the read and the modify access. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @param GPIO_Pin: specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->BSRRL = GPIO_Pin; -} - -/** - * @brief Clears the selected data port bits. - * @note This functions uses GPIOx_BSRR register to allow atomic read/modify - * accesses. In this way, there is no risk of an IRQ occurring between - * the read and the modify access. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @param GPIO_Pin: specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->BSRRH = GPIO_Pin; -} - -/** - * @brief Sets or clears the selected data port bit. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be one of GPIO_Pin_x where x can be (0..15). - * @param BitVal: specifies the value to be written to the selected bit. - * This parameter can be one of the BitAction enum values: - * @arg Bit_RESET: to clear the port pin - * @arg Bit_SET: to set the port pin - * @retval None - */ -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - assert_param(IS_GPIO_BIT_ACTION(BitVal)); - - if (BitVal != Bit_RESET) - { - GPIOx->BSRRL = GPIO_Pin; - } - else - { - GPIOx->BSRRH = GPIO_Pin ; - } -} - -/** - * @brief Writes data to the specified GPIO data port. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @param PortVal: specifies the value to be written to the port output data register. - * @retval None - */ -void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - GPIOx->ODR = PortVal; -} - -/** - * @brief Toggles the specified GPIO pins.. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @param GPIO_Pin: Specifies the pins to be toggled. - * @retval None - */ -void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - GPIOx->ODR ^= GPIO_Pin; -} - -/** - * @} - */ - -/** @defgroup GPIO_Group3 GPIO Alternate functions configuration function - * @brief GPIO Alternate functions configuration function - * -@verbatim - =============================================================================== - ##### GPIO Alternate functions configuration function ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Changes the mapping of the specified pin. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @param GPIO_PinSource: specifies the pin for the Alternate function. - * This parameter can be GPIO_PinSourcex where x can be (0..15). - * @param GPIO_AFSelection: selects the pin to used as Alternate function. - * This parameter can be one of the following values: - * @arg GPIO_AF_RTC_50Hz: Connect RTC_50Hz pin to AF0 (default after reset) - * @arg GPIO_AF_MCO: Connect MCO pin (MCO1 and MCO2) to AF0 (default after reset) - * @arg GPIO_AF_TAMPER: Connect TAMPER pins (TAMPER_1 and TAMPER_2) to AF0 (default after reset) - * @arg GPIO_AF_SWJ: Connect SWJ pins (SWD and JTAG)to AF0 (default after reset) - * @arg GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset) - * @arg GPIO_AF_TIM1: Connect TIM1 pins to AF1 - * @arg GPIO_AF_TIM2: Connect TIM2 pins to AF1 - * @arg GPIO_AF_TIM3: Connect TIM3 pins to AF2 - * @arg GPIO_AF_TIM4: Connect TIM4 pins to AF2 - * @arg GPIO_AF_TIM5: Connect TIM5 pins to AF2 - * @arg GPIO_AF_TIM8: Connect TIM8 pins to AF3 - * @arg GPIO_AF_TIM9: Connect TIM9 pins to AF3 - * @arg GPIO_AF_TIM10: Connect TIM10 pins to AF3 - * @arg GPIO_AF_TIM11: Connect TIM11 pins to AF3 - * @arg GPIO_AF_I2C1: Connect I2C1 pins to AF4 - * @arg GPIO_AF_I2C2: Connect I2C2 pins to AF4 - * @arg GPIO_AF_I2C3: Connect I2C3 pins to AF4 - * @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5 - * @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5 - * @arg GPIO_AF_SPI4: Connect SPI4 pins to AF5 - * @arg GPIO_AF_SPI5: Connect SPI5 pins to AF5 - * @arg GPIO_AF_SPI6: Connect SPI6 pins to AF5 - * @arg GPIO_AF_SAI1: Connect SAI1 pins to AF6 for STM32F42xxx/43xxx devices. - * @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6 - * @arg GPIO_AF_I2S3ext: Connect I2S3ext pins to AF7 - * @arg GPIO_AF_USART1: Connect USART1 pins to AF7 - * @arg GPIO_AF_USART2: Connect USART2 pins to AF7 - * @arg GPIO_AF_USART3: Connect USART3 pins to AF7 - * @arg GPIO_AF_UART4: Connect UART4 pins to AF8 - * @arg GPIO_AF_UART5: Connect UART5 pins to AF8 - * @arg GPIO_AF_USART6: Connect USART6 pins to AF8 - * @arg GPIO_AF_UART7: Connect UART7 pins to AF8 - * @arg GPIO_AF_UART8: Connect UART8 pins to AF8 - * @arg GPIO_AF_CAN1: Connect CAN1 pins to AF9 - * @arg GPIO_AF_CAN2: Connect CAN2 pins to AF9 - * @arg GPIO_AF_TIM12: Connect TIM12 pins to AF9 - * @arg GPIO_AF_TIM13: Connect TIM13 pins to AF9 - * @arg GPIO_AF_TIM14: Connect TIM14 pins to AF9 - * @arg GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10 - * @arg GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10 - * @arg GPIO_AF_ETH: Connect ETHERNET pins to AF11 - * @arg GPIO_AF_FSMC: Connect FSMC pins to AF12 - * @arg GPIO_AF_FMC: Connect FMC pins to AF12 for STM32F42xxx/43xxx devices. - * @arg GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12 - * @arg GPIO_AF_SDIO: Connect SDIO pins to AF12 - * @arg GPIO_AF_DCMI: Connect DCMI pins to AF13 - * @arg GPIO_AF_LTDC: Connect LTDC pins to AF14 for STM32F429xx/439xx devices. - * @arg GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15 - * @retval None - */ -void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF) -{ - uint32_t temp = 0x00; - uint32_t temp_2 = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); - assert_param(IS_GPIO_AF(GPIO_AF)); - - temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ; - GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ; - temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp; - GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm32f4xx_gpio.h b/stm/stmperiph/stm32f4xx_gpio.h deleted file mode 100644 index d93b14197..000000000 --- a/stm/stmperiph/stm32f4xx_gpio.h +++ /dev/null @@ -1,489 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_gpio.h - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief This file contains all the functions prototypes for the GPIO firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_GPIO_H -#define __STM32F4xx_GPIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup GPIO - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ - ((PERIPH) == GPIOB) || \ - ((PERIPH) == GPIOC) || \ - ((PERIPH) == GPIOD) || \ - ((PERIPH) == GPIOE) || \ - ((PERIPH) == GPIOF) || \ - ((PERIPH) == GPIOG) || \ - ((PERIPH) == GPIOH) || \ - ((PERIPH) == GPIOI) || \ - ((PERIPH) == GPIOJ) || \ - ((PERIPH) == GPIOK)) - -/** - * @brief GPIO Configuration Mode enumeration - */ -typedef enum -{ - GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */ - GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */ - GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */ - GPIO_Mode_AN = 0x03 /*!< GPIO Analog Mode */ -}GPIOMode_TypeDef; -#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || \ - ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN)) - -/** - * @brief GPIO Output type enumeration - */ -typedef enum -{ - GPIO_OType_PP = 0x00, - GPIO_OType_OD = 0x01 -}GPIOOType_TypeDef; -#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD)) - - -/** - * @brief GPIO Output Maximum frequency enumeration - */ -typedef enum -{ - GPIO_Low_Speed = 0x00, /*!< Low speed */ - GPIO_Medium_Speed = 0x01, /*!< Medium speed */ - GPIO_Fast_Speed = 0x02, /*!< Fast speed */ - GPIO_High_Speed = 0x03 /*!< High speed */ -}GPIOSpeed_TypeDef; - -/* Add legacy definition */ -#define GPIO_Speed_2MHz GPIO_Low_Speed -#define GPIO_Speed_25MHz GPIO_Medium_Speed -#define GPIO_Speed_50MHz GPIO_Fast_Speed -#define GPIO_Speed_100MHz GPIO_High_Speed - -#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Low_Speed) || ((SPEED) == GPIO_Medium_Speed) || \ - ((SPEED) == GPIO_Fast_Speed)|| ((SPEED) == GPIO_High_Speed)) - -/** - * @brief GPIO Configuration PullUp PullDown enumeration - */ -typedef enum -{ - GPIO_PuPd_NOPULL = 0x00, - GPIO_PuPd_UP = 0x01, - GPIO_PuPd_DOWN = 0x02 -}GPIOPuPd_TypeDef; -#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \ - ((PUPD) == GPIO_PuPd_DOWN)) - -/** - * @brief GPIO Bit SET and Bit RESET enumeration - */ -typedef enum -{ - Bit_RESET = 0, - Bit_SET -}BitAction; -#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) - - -/** - * @brief GPIO Init structure definition - */ -typedef struct -{ - uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins_define */ - - GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIOMode_TypeDef */ - - GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIOSpeed_TypeDef */ - - GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins. - This parameter can be a value of @ref GPIOOType_TypeDef */ - - GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins. - This parameter can be a value of @ref GPIOPuPd_TypeDef */ -}GPIO_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup GPIO_Exported_Constants - * @{ - */ - -/** @defgroup GPIO_pins_define - * @{ - */ -#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ -#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ -#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ -#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ -#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ -#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ -#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ -#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ -#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ -#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ -#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ -#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ -#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ -#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ -#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ -#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ -#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ - -#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) -#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ - ((PIN) == GPIO_Pin_1) || \ - ((PIN) == GPIO_Pin_2) || \ - ((PIN) == GPIO_Pin_3) || \ - ((PIN) == GPIO_Pin_4) || \ - ((PIN) == GPIO_Pin_5) || \ - ((PIN) == GPIO_Pin_6) || \ - ((PIN) == GPIO_Pin_7) || \ - ((PIN) == GPIO_Pin_8) || \ - ((PIN) == GPIO_Pin_9) || \ - ((PIN) == GPIO_Pin_10) || \ - ((PIN) == GPIO_Pin_11) || \ - ((PIN) == GPIO_Pin_12) || \ - ((PIN) == GPIO_Pin_13) || \ - ((PIN) == GPIO_Pin_14) || \ - ((PIN) == GPIO_Pin_15)) -/** - * @} - */ - - -/** @defgroup GPIO_Pin_sources - * @{ - */ -#define GPIO_PinSource0 ((uint8_t)0x00) -#define GPIO_PinSource1 ((uint8_t)0x01) -#define GPIO_PinSource2 ((uint8_t)0x02) -#define GPIO_PinSource3 ((uint8_t)0x03) -#define GPIO_PinSource4 ((uint8_t)0x04) -#define GPIO_PinSource5 ((uint8_t)0x05) -#define GPIO_PinSource6 ((uint8_t)0x06) -#define GPIO_PinSource7 ((uint8_t)0x07) -#define GPIO_PinSource8 ((uint8_t)0x08) -#define GPIO_PinSource9 ((uint8_t)0x09) -#define GPIO_PinSource10 ((uint8_t)0x0A) -#define GPIO_PinSource11 ((uint8_t)0x0B) -#define GPIO_PinSource12 ((uint8_t)0x0C) -#define GPIO_PinSource13 ((uint8_t)0x0D) -#define GPIO_PinSource14 ((uint8_t)0x0E) -#define GPIO_PinSource15 ((uint8_t)0x0F) - -#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ - ((PINSOURCE) == GPIO_PinSource1) || \ - ((PINSOURCE) == GPIO_PinSource2) || \ - ((PINSOURCE) == GPIO_PinSource3) || \ - ((PINSOURCE) == GPIO_PinSource4) || \ - ((PINSOURCE) == GPIO_PinSource5) || \ - ((PINSOURCE) == GPIO_PinSource6) || \ - ((PINSOURCE) == GPIO_PinSource7) || \ - ((PINSOURCE) == GPIO_PinSource8) || \ - ((PINSOURCE) == GPIO_PinSource9) || \ - ((PINSOURCE) == GPIO_PinSource10) || \ - ((PINSOURCE) == GPIO_PinSource11) || \ - ((PINSOURCE) == GPIO_PinSource12) || \ - ((PINSOURCE) == GPIO_PinSource13) || \ - ((PINSOURCE) == GPIO_PinSource14) || \ - ((PINSOURCE) == GPIO_PinSource15)) -/** - * @} - */ - -/** @defgroup GPIO_Alternat_function_selection_define - * @{ - */ -/** - * @brief AF 0 selection - */ -#define GPIO_AF_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ -#define GPIO_AF_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ -#define GPIO_AF_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ -#define GPIO_AF_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#define GPIO_AF_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ - -/** - * @brief AF 1 selection - */ -#define GPIO_AF_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ -#define GPIO_AF_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ - -/** - * @brief AF 2 selection - */ -#define GPIO_AF_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ -#define GPIO_AF_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ -#define GPIO_AF_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ - -/** - * @brief AF 3 selection - */ -#define GPIO_AF_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ -#define GPIO_AF_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ -#define GPIO_AF_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ -#define GPIO_AF_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ - -/** - * @brief AF 4 selection - */ -#define GPIO_AF_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ -#define GPIO_AF_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ -#define GPIO_AF_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ -#define GPIO_AF_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ -#define GPIO_AF_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */ -#define GPIO_AF_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */ - -/** - * @brief AF 6 selection - */ -#define GPIO_AF_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ - -#define GPIO_AF_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ - -/** - * @brief AF 7 selection - */ -#define GPIO_AF_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ -#define GPIO_AF_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ -#define GPIO_AF_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ -#define GPIO_AF_I2S3ext ((uint8_t)0x07) /* I2S3ext Alternate Function mapping */ - -/** - * @brief AF 8 selection - */ -#define GPIO_AF_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ -#define GPIO_AF_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ -#define GPIO_AF_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ -#define GPIO_AF_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */ -#define GPIO_AF_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ - -/** - * @brief AF 9 selection - */ -#define GPIO_AF_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ -#define GPIO_AF_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ -#define GPIO_AF_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ -#define GPIO_AF_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ -#define GPIO_AF_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ - -#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping (Only for STM32F401xx Devices) */ -#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping (Only for STM32F401xx Devices) */ - -/** - * @brief AF 10 selection - */ -#define GPIO_AF_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */ -#define GPIO_AF_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */ - -/** - * @brief AF 11 selection - */ -#define GPIO_AF_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ - -/** - * @brief AF 12 selection - */ -#if defined (STM32F40_41xxx) -#define GPIO_AF_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */ -#endif /* STM32F40_41xxx */ - -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) -#define GPIO_AF_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */ -#endif /* STM32F427_437xx || STM32F429_439xx */ - -#define GPIO_AF_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */ -#define GPIO_AF_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */ - -/** - * @brief AF 13 selection - */ -#define GPIO_AF_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ - -/** - * @brief AF 14 selection - */ - -#define GPIO_AF_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */ - -/** - * @brief AF 15 selection - */ -#define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ - -#if defined (STM32F40_41xxx) -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \ - ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \ - ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \ - ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \ - ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \ - ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \ - ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \ - ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \ - ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \ - ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \ - ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \ - ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \ - ((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \ - ((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \ - ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \ - ((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_OTG_HS_FS) || \ - ((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_DCMI) || \ - ((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_FSMC)) -#endif /* STM32F40_41xxx */ - -#if defined (STM32F401xx) -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \ - ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \ - ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \ - ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \ - ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \ - ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \ - ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \ - ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \ - ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \ - ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \ - ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \ - ((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_USART6) || \ - ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \ - ((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_SPI4)) -#endif /* STM32F401xx */ - -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \ - ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \ - ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \ - ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \ - ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \ - ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \ - ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \ - ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \ - ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \ - ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \ - ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \ - ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \ - ((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \ - ((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \ - ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \ - ((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_OTG_HS_FS) || \ - ((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_DCMI) || \ - ((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_SPI4) || \ - ((AF) == GPIO_AF_SPI5) || ((AF) == GPIO_AF_SPI6) || \ - ((AF) == GPIO_AF_UART7) || ((AF) == GPIO_AF_UART8) || \ - ((AF) == GPIO_AF_FMC) || ((AF) == GPIO_AF_SAI1) || \ - ((AF) == GPIO_AF_LTDC)) -#endif /* STM32F427_437xx || STM32F429_439xx */ - -/** - * @} - */ - -/** @defgroup GPIO_Legacy - * @{ - */ - -#define GPIO_Mode_AIN GPIO_Mode_AN - -#define GPIO_AF_OTG1_FS GPIO_AF_OTG_FS -#define GPIO_AF_OTG2_HS GPIO_AF_OTG_HS -#define GPIO_AF_OTG2_FS GPIO_AF_OTG_HS_FS - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the GPIO configuration to the default reset state ****/ -void GPIO_DeInit(GPIO_TypeDef* GPIOx); - -/* Initialization and Configuration functions *********************************/ -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); -void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); - -/* GPIO Read and Write functions **********************************************/ -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); -void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); -void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); -void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); - -/* GPIO Alternate functions configuration function ****************************/ -void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_GPIO_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm32f4xx_i2c.c b/stm/stmperiph/stm32f4xx_i2c.c deleted file mode 100644 index 4580c0dd7..000000000 --- a/stm/stmperiph/stm32f4xx_i2c.c +++ /dev/null @@ -1,1462 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_i2c.c - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief This file provides firmware functions to manage the following - * functionalities of the Inter-integrated circuit (I2C) - * + Initialization and Configuration - * + Data transfers - * + PEC management - * + DMA transfers management - * + Interrupts, events and flags management - * - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - (#) Enable peripheral clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2Cx, ENABLE) - function for I2C1, I2C2 or I2C3. - - (#) Enable SDA, SCL and SMBA (when used) GPIO clocks using - RCC_AHBPeriphClockCmd() function. - - (#) Peripherals alternate function: - (++) Connect the pin to the desired peripherals' Alternate - Function (AF) using GPIO_PinAFConfig() function - (++) Configure the desired pin in alternate function by: - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - (++) Select the type, pull-up/pull-down and output speed via - GPIO_PuPd, GPIO_OType and GPIO_Speed members - (++) Call GPIO_Init() function - Recommended configuration is Push-Pull, Pull-up, Open-Drain. - Add an external pull up if necessary (typically 4.7 KOhm). - - (#) Program the Mode, duty cycle , Own address, Ack, Speed and Acknowledged - Address using the I2C_Init() function. - - (#) Optionally you can enable/configure the following parameters without - re-initialization (i.e there is no need to call again I2C_Init() function): - (++) Enable the acknowledge feature using I2C_AcknowledgeConfig() function - (++) Enable the dual addressing mode using I2C_DualAddressCmd() function - (++) Enable the general call using the I2C_GeneralCallCmd() function - (++) Enable the clock stretching using I2C_StretchClockCmd() function - (++) Enable the fast mode duty cycle using the I2C_FastModeDutyCycleConfig() - function. - (++) Configure the NACK position for Master Receiver mode in case of - 2 bytes reception using the function I2C_NACKPositionConfig(). - (++) Enable the PEC Calculation using I2C_CalculatePEC() function - (++) For SMBus Mode: - (+++) Enable the Address Resolution Protocol (ARP) using I2C_ARPCmd() function - (+++) Configure the SMBusAlert pin using I2C_SMBusAlertConfig() function - - (#) Enable the NVIC and the corresponding interrupt using the function - I2C_ITConfig() if you need to use interrupt mode. - - (#) When using the DMA mode - (++) Configure the DMA using DMA_Init() function - (++) Active the needed channel Request using I2C_DMACmd() or - I2C_DMALastTransferCmd() function. - -@@- When using DMA mode, I2C interrupts may be used at the same time to - control the communication flow (Start/Stop/Ack... events and errors). - - (#) Enable the I2C using the I2C_Cmd() function. - - (#) Enable the DMA using the DMA_Cmd() function when using DMA mode in the - transfers. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_i2c.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup I2C - * @brief I2C driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -#define CR1_CLEAR_MASK ((uint16_t)0xFBF5) /*I2C_ClockSpeed)); - assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode)); - assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle)); - assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1)); - assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack)); - assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress)); - -/*---------------------------- I2Cx CR2 Configuration ------------------------*/ - /* Get the I2Cx CR2 value */ - tmpreg = I2Cx->CR2; - /* Clear frequency FREQ[5:0] bits */ - tmpreg &= (uint16_t)~((uint16_t)I2C_CR2_FREQ); - /* Get pclk1 frequency value */ - RCC_GetClocksFreq(&rcc_clocks); - pclk1 = rcc_clocks.PCLK1_Frequency; - /* Set frequency bits depending on pclk1 value */ - freqrange = (uint16_t)(pclk1 / 1000000); - tmpreg |= freqrange; - /* Write to I2Cx CR2 */ - I2Cx->CR2 = tmpreg; - -/*---------------------------- I2Cx CCR Configuration ------------------------*/ - /* Disable the selected I2C peripheral to configure TRISE */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE); - /* Reset tmpreg value */ - /* Clear F/S, DUTY and CCR[11:0] bits */ - tmpreg = 0; - - /* Configure speed in standard mode */ - if (I2C_InitStruct->I2C_ClockSpeed <= 100000) - { - /* Standard mode speed calculate */ - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); - /* Test if CCR value is under 0x4*/ - if (result < 0x04) - { - /* Set minimum allowed value */ - result = 0x04; - } - /* Set speed value for standard mode */ - tmpreg |= result; - /* Set Maximum Rise Time for standard mode */ - I2Cx->TRISE = freqrange + 1; - } - /* Configure speed in fast mode */ - /* To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency (I2C peripheral - input clock) must be a multiple of 10 MHz */ - else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/ - { - if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) - { - /* Fast mode speed calculate: Tlow/Thigh = 2 */ - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); - } - else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/ - { - /* Fast mode speed calculate: Tlow/Thigh = 16/9 */ - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); - /* Set DUTY bit */ - result |= I2C_DutyCycle_16_9; - } - - /* Test if CCR value is under 0x1*/ - if ((result & I2C_CCR_CCR) == 0) - { - /* Set minimum allowed value */ - result |= (uint16_t)0x0001; - } - /* Set speed value and set F/S bit for fast mode */ - tmpreg |= (uint16_t)(result | I2C_CCR_FS); - /* Set Maximum Rise Time for fast mode */ - I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); - } - - /* Write to I2Cx CCR */ - I2Cx->CCR = tmpreg; - /* Enable the selected I2C peripheral */ - I2Cx->CR1 |= I2C_CR1_PE; - -/*---------------------------- I2Cx CR1 Configuration ------------------------*/ - /* Get the I2Cx CR1 value */ - tmpreg = I2Cx->CR1; - /* Clear ACK, SMBTYPE and SMBUS bits */ - tmpreg &= CR1_CLEAR_MASK; - /* Configure I2Cx: mode and acknowledgement */ - /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */ - /* Set ACK bit according to I2C_Ack value */ - tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); - /* Write to I2Cx CR1 */ - I2Cx->CR1 = tmpreg; - -/*---------------------------- I2Cx OAR1 Configuration -----------------------*/ - /* Set I2Cx Own Address1 and acknowledged address */ - I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); -} - -/** - * @brief Fills each I2C_InitStruct member with its default value. - * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized. - * @retval None - */ -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) -{ -/*---------------- Reset I2C init structure parameters values ----------------*/ - /* initialize the I2C_ClockSpeed member */ - I2C_InitStruct->I2C_ClockSpeed = 5000; - /* Initialize the I2C_Mode member */ - I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; - /* Initialize the I2C_DutyCycle member */ - I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; - /* Initialize the I2C_OwnAddress1 member */ - I2C_InitStruct->I2C_OwnAddress1 = 0; - /* Initialize the I2C_Ack member */ - I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; - /* Initialize the I2C_AcknowledgedAddress member */ - I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; -} - -/** - * @brief Enables or disables the specified I2C peripheral. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2Cx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C peripheral */ - I2Cx->CR1 |= I2C_CR1_PE; - } - else - { - /* Disable the selected I2C peripheral */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE); - } -} - -/** - * @brief Enables or disables the Analog filter of I2C peripheral. - * - * @note This function can be used only for STM32F42xxx/STM3243xxx and STM32F401xx devices. - * - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the Analog filter. - * This parameter can be: ENABLE or DISABLE. - * @note This function should be called before initializing and enabling - the I2C Peripheral. - * @retval None - */ -void I2C_AnalogFilterCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the analog filter */ - I2Cx->FLTR &= (uint16_t)~((uint16_t)I2C_FLTR_ANOFF); - } - else - { - /* Disable the analog filter */ - I2Cx->FLTR |= I2C_FLTR_ANOFF; - } -} - -/** - * @brief Configures the Digital noise filter of I2C peripheral. - * - * @note This function can be used only for STM32F42xxx/STM3243xxx and STM32F401xx devices. - * - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_DigitalFilter: Coefficient of digital noise filter. - * This parameter can be a number between 0x00 and 0x0F. - * @note This function should be called before initializing and enabling - the I2C Peripheral. - * @retval None - */ -void I2C_DigitalFilterConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DigitalFilter) -{ - uint16_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_DIGITAL_FILTER(I2C_DigitalFilter)); - - /* Get the old register value */ - tmpreg = I2Cx->FLTR; - - /* Reset I2Cx DNF bit [3:0] */ - tmpreg &= (uint16_t)~((uint16_t)I2C_FLTR_DNF); - - /* Set I2Cx DNF coefficient */ - tmpreg |= (uint16_t)((uint16_t)I2C_DigitalFilter & I2C_FLTR_DNF); - - /* Store the new register value */ - I2Cx->FLTR = tmpreg; -} - -/** - * @brief Generates I2Cx communication START condition. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C START condition generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Generate a START condition */ - I2Cx->CR1 |= I2C_CR1_START; - } - else - { - /* Disable the START condition generation */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_START); - } -} - -/** - * @brief Generates I2Cx communication STOP condition. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C STOP condition generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Generate a STOP condition */ - I2Cx->CR1 |= I2C_CR1_STOP; - } - else - { - /* Disable the STOP condition generation */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_STOP); - } -} - -/** - * @brief Transmits the address byte to select the slave device. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param Address: specifies the slave address which will be transmitted - * @param I2C_Direction: specifies whether the I2C device will be a Transmitter - * or a Receiver. - * This parameter can be one of the following values - * @arg I2C_Direction_Transmitter: Transmitter mode - * @arg I2C_Direction_Receiver: Receiver mode - * @retval None. - */ -void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_DIRECTION(I2C_Direction)); - /* Test on the direction to set/reset the read/write bit */ - if (I2C_Direction != I2C_Direction_Transmitter) - { - /* Set the address bit0 for read */ - Address |= I2C_OAR1_ADD0; - } - else - { - /* Reset the address bit0 for write */ - Address &= (uint8_t)~((uint8_t)I2C_OAR1_ADD0); - } - /* Send the address */ - I2Cx->DR = Address; -} - -/** - * @brief Enables or disables the specified I2C acknowledge feature. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C Acknowledgement. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the acknowledgement */ - I2Cx->CR1 |= I2C_CR1_ACK; - } - else - { - /* Disable the acknowledgement */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ACK); - } -} - -/** - * @brief Configures the specified I2C own address2. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param Address: specifies the 7bit I2C own address2. - * @retval None. - */ -void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address) -{ - uint16_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Get the old register value */ - tmpreg = I2Cx->OAR2; - - /* Reset I2Cx Own address2 bit [7:1] */ - tmpreg &= (uint16_t)~((uint16_t)I2C_OAR2_ADD2); - - /* Set I2Cx Own address2 */ - tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); - - /* Store the new register value */ - I2Cx->OAR2 = tmpreg; -} - -/** - * @brief Enables or disables the specified I2C dual addressing mode. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C dual addressing mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable dual addressing mode */ - I2Cx->OAR2 |= I2C_OAR2_ENDUAL; - } - else - { - /* Disable dual addressing mode */ - I2Cx->OAR2 &= (uint16_t)~((uint16_t)I2C_OAR2_ENDUAL); - } -} - -/** - * @brief Enables or disables the specified I2C general call feature. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C General call. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable generall call */ - I2Cx->CR1 |= I2C_CR1_ENGC; - } - else - { - /* Disable generall call */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENGC); - } -} - -/** - * @brief Enables or disables the specified I2C software reset. - * @note When software reset is enabled, the I2C IOs are released (this can - * be useful to recover from bus errors). - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C software reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Peripheral under reset */ - I2Cx->CR1 |= I2C_CR1_SWRST; - } - else - { - /* Peripheral not under reset */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_SWRST); - } -} - -/** - * @brief Enables or disables the specified I2C Clock stretching. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2Cx Clock stretching. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState == DISABLE) - { - /* Enable the selected I2C Clock stretching */ - I2Cx->CR1 |= I2C_CR1_NOSTRETCH; - } - else - { - /* Disable the selected I2C Clock stretching */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_NOSTRETCH); - } -} - -/** - * @brief Selects the specified I2C fast mode duty cycle. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_DutyCycle: specifies the fast mode duty cycle. - * This parameter can be one of the following values: - * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2 - * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9 - * @retval None - */ -void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle)); - if (I2C_DutyCycle != I2C_DutyCycle_16_9) - { - /* I2C fast mode Tlow/Thigh=2 */ - I2Cx->CCR &= I2C_DutyCycle_2; - } - else - { - /* I2C fast mode Tlow/Thigh=16/9 */ - I2Cx->CCR |= I2C_DutyCycle_16_9; - } -} - -/** - * @brief Selects the specified I2C NACK position in master receiver mode. - * @note This function is useful in I2C Master Receiver mode when the number - * of data to be received is equal to 2. In this case, this function - * should be called (with parameter I2C_NACKPosition_Next) before data - * reception starts,as described in the 2-byte reception procedure - * recommended in Reference Manual in Section: Master receiver. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_NACKPosition: specifies the NACK position. - * This parameter can be one of the following values: - * @arg I2C_NACKPosition_Next: indicates that the next byte will be the last - * received byte. - * @arg I2C_NACKPosition_Current: indicates that current byte is the last - * received byte. - * - * @note This function configures the same bit (POS) as I2C_PECPositionConfig() - * but is intended to be used in I2C mode while I2C_PECPositionConfig() - * is intended to used in SMBUS mode. - * - * @retval None - */ -void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition)); - - /* Check the input parameter */ - if (I2C_NACKPosition == I2C_NACKPosition_Next) - { - /* Next byte in shift register is the last received byte */ - I2Cx->CR1 |= I2C_NACKPosition_Next; - } - else - { - /* Current byte in shift register is the last received byte */ - I2Cx->CR1 &= I2C_NACKPosition_Current; - } -} - -/** - * @brief Drives the SMBusAlert pin high or low for the specified I2C. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_SMBusAlert: specifies SMBAlert pin level. - * This parameter can be one of the following values: - * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low - * @arg I2C_SMBusAlert_High: SMBAlert pin driven high - * @retval None - */ -void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert)); - if (I2C_SMBusAlert == I2C_SMBusAlert_Low) - { - /* Drive the SMBusAlert pin Low */ - I2Cx->CR1 |= I2C_SMBusAlert_Low; - } - else - { - /* Drive the SMBusAlert pin High */ - I2Cx->CR1 &= I2C_SMBusAlert_High; - } -} - -/** - * @brief Enables or disables the specified I2C ARP. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2Cx ARP. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C ARP */ - I2Cx->CR1 |= I2C_CR1_ENARP; - } - else - { - /* Disable the selected I2C ARP */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENARP); - } -} -/** - * @} - */ - -/** @defgroup I2C_Group2 Data transfers functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### Data transfers functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Sends a data byte through the I2Cx peripheral. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param Data: Byte to be transmitted.. - * @retval None - */ -void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - /* Write in the DR register the data to be sent */ - I2Cx->DR = Data; -} - -/** - * @brief Returns the most recent received data by the I2Cx peripheral. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @retval The value of the received data. - */ -uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - /* Return the data in the DR register */ - return (uint8_t)I2Cx->DR; -} - -/** - * @} - */ - -/** @defgroup I2C_Group3 PEC management functions - * @brief PEC management functions - * -@verbatim - =============================================================================== - ##### PEC management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified I2C PEC transfer. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C PEC transmission. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C PEC transmission */ - I2Cx->CR1 |= I2C_CR1_PEC; - } - else - { - /* Disable the selected I2C PEC transmission */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PEC); - } -} - -/** - * @brief Selects the specified I2C PEC position. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_PECPosition: specifies the PEC position. - * This parameter can be one of the following values: - * @arg I2C_PECPosition_Next: indicates that the next byte is PEC - * @arg I2C_PECPosition_Current: indicates that current byte is PEC - * - * @note This function configures the same bit (POS) as I2C_NACKPositionConfig() - * but is intended to be used in SMBUS mode while I2C_NACKPositionConfig() - * is intended to used in I2C mode. - * - * @retval None - */ -void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition)); - if (I2C_PECPosition == I2C_PECPosition_Next) - { - /* Next byte in shift register is PEC */ - I2Cx->CR1 |= I2C_PECPosition_Next; - } - else - { - /* Current byte in shift register is PEC */ - I2Cx->CR1 &= I2C_PECPosition_Current; - } -} - -/** - * @brief Enables or disables the PEC value calculation of the transferred bytes. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2Cx PEC value calculation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C PEC calculation */ - I2Cx->CR1 |= I2C_CR1_ENPEC; - } - else - { - /* Disable the selected I2C PEC calculation */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENPEC); - } -} - -/** - * @brief Returns the PEC value for the specified I2C. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @retval The PEC value. - */ -uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - /* Return the selected I2C PEC value */ - return ((I2Cx->SR2) >> 8); -} - -/** - * @} - */ - -/** @defgroup I2C_Group4 DMA transfers management functions - * @brief DMA transfers management functions - * -@verbatim - =============================================================================== - ##### DMA transfers management functions ##### - =============================================================================== - This section provides functions allowing to configure the I2C DMA channels - requests. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified I2C DMA requests. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C DMA transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C DMA requests */ - I2Cx->CR2 |= I2C_CR2_DMAEN; - } - else - { - /* Disable the selected I2C DMA requests */ - I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_DMAEN); - } -} - -/** - * @brief Specifies that the next DMA transfer is the last one. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C DMA last transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Next DMA transfer is the last transfer */ - I2Cx->CR2 |= I2C_CR2_LAST; - } - else - { - /* Next DMA transfer is not the last transfer */ - I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_LAST); - } -} - -/** - * @} - */ - -/** @defgroup I2C_Group5 Interrupts events and flags management functions - * @brief Interrupts, events and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts, events and flags management functions ##### - =============================================================================== - [..] - This section provides functions allowing to configure the I2C Interrupts - sources and check or clear the flags or pending bits status. - The user should identify which mode will be used in his application to manage - the communication: Polling mode, Interrupt mode or DMA mode. - - - ##### I2C State Monitoring Functions ##### - =============================================================================== - [..] - This I2C driver provides three different ways for I2C state monitoring - depending on the application requirements and constraints: - - - (#) Basic state monitoring (Using I2C_CheckEvent() function) - - It compares the status registers (SR1 and SR2) content to a given event - (can be the combination of one or more flags). - It returns SUCCESS if the current status includes the given flags - and returns ERROR if one or more flags are missing in the current status. - - (++) When to use - (+++) This function is suitable for most applications as well as for startup - activity since the events are fully described in the product reference - manual (RM0090). - (+++) It is also suitable for users who need to define their own events. - - (++) Limitations - If an error occurs (ie. error flags are set besides to the monitored - flags), the I2C_CheckEvent() function may return SUCCESS despite - the communication hold or corrupted real state. - In this case, it is advised to use error interrupts to monitor - the error events and handle them in the interrupt IRQ handler. - - -@@- For error management, it is advised to use the following functions: - (+@@) I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). - (+@@) I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. - Where x is the peripheral instance (I2C1, I2C2 ...) - (+@@) I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the - I2Cx_ER_IRQHandler() function in order to determine which error occurred. - (+@@) I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() - and/or I2C_GenerateStop() in order to clear the error flag and source - and return to correct communication status. - - - (#) Advanced state monitoring (Using the function I2C_GetLastEvent()) - - Using the function I2C_GetLastEvent() which returns the image of both status - registers in a single word (uint32_t) (Status Register 2 value is shifted left - by 16 bits and concatenated to Status Register 1). - - (++) When to use - (+++) This function is suitable for the same applications above but it - allows to overcome the mentioned limitation of I2C_GetFlagStatus() - function. - (+++) The returned value could be compared to events already defined in - the library (stm32f4xx_i2c.h) or to custom values defined by user. - This function is suitable when multiple flags are monitored at the - same time. - (+++) At the opposite of I2C_CheckEvent() function, this function allows - user to choose when an event is accepted (when all events flags are - set and no other flags are set or just when the needed flags are set - like I2C_CheckEvent() function. - - (++) Limitations - (+++) User may need to define his own events. - (+++) Same remark concerning the error management is applicable for this - function if user decides to check only regular communication flags - (and ignores error flags). - - - (#) Flag-based state monitoring (Using the function I2C_GetFlagStatus()) - - Using the function I2C_GetFlagStatus() which simply returns the status of - one single flag (ie. I2C_FLAG_RXNE ...). - - (++) When to use - (+++) This function could be used for specific applications or in debug - phase. - (+++) It is suitable when only one flag checking is needed (most I2C - events are monitored through multiple flags). - (++) Limitations: - (+++) When calling this function, the Status register is accessed. - Some flags are cleared when the status register is accessed. - So checking the status of one Flag, may clear other ones. - (+++) Function may need to be called twice or more in order to monitor - one single event. - - For detailed description of Events, please refer to section I2C_Events in - stm32f4xx_i2c.h file. - -@endverbatim - * @{ - */ - -/** - * @brief Reads the specified I2C register and returns its value. - * @param I2C_Register: specifies the register to read. - * This parameter can be one of the following values: - * @arg I2C_Register_CR1: CR1 register. - * @arg I2C_Register_CR2: CR2 register. - * @arg I2C_Register_OAR1: OAR1 register. - * @arg I2C_Register_OAR2: OAR2 register. - * @arg I2C_Register_DR: DR register. - * @arg I2C_Register_SR1: SR1 register. - * @arg I2C_Register_SR2: SR2 register. - * @arg I2C_Register_CCR: CCR register. - * @arg I2C_Register_TRISE: TRISE register. - * @retval The value of the read register. - */ -uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_REGISTER(I2C_Register)); - - tmp = (uint32_t) I2Cx; - tmp += I2C_Register; - - /* Return the selected register value */ - return (*(__IO uint16_t *) tmp); -} - -/** - * @brief Enables or disables the specified I2C interrupts. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg I2C_IT_BUF: Buffer interrupt mask - * @arg I2C_IT_EVT: Event interrupt mask - * @arg I2C_IT_ERR: Error interrupt mask - * @param NewState: new state of the specified I2C interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_I2C_CONFIG_IT(I2C_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected I2C interrupts */ - I2Cx->CR2 |= I2C_IT; - } - else - { - /* Disable the selected I2C interrupts */ - I2Cx->CR2 &= (uint16_t)~I2C_IT; - } -} - -/* - =============================================================================== - 1. Basic state monitoring - =============================================================================== - */ - -/** - * @brief Checks whether the last I2Cx Event is equal to the one passed - * as parameter. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_EVENT: specifies the event to be checked. - * This parameter can be one of the following values: - * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED: EV1 - * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED: EV1 - * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED: EV1 - * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED: EV1 - * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED: EV1 - * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED: EV2 - * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF): EV2 - * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL): EV2 - * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED: EV3 - * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF): EV3 - * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL): EV3 - * @arg I2C_EVENT_SLAVE_ACK_FAILURE: EV3_2 - * @arg I2C_EVENT_SLAVE_STOP_DETECTED: EV4 - * @arg I2C_EVENT_MASTER_MODE_SELECT: EV5 - * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED: EV6 - * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED: EV6 - * @arg I2C_EVENT_MASTER_BYTE_RECEIVED: EV7 - * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING: EV8 - * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED: EV8_2 - * @arg I2C_EVENT_MASTER_MODE_ADDRESS10: EV9 - * - * @note For detailed description of Events, please refer to section I2C_Events - * in stm32f4xx_i2c.h file. - * - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Last event is equal to the I2C_EVENT - * - ERROR: Last event is different from the I2C_EVENT - */ -ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_EVENT(I2C_EVENT)); - - /* Read the I2Cx status register */ - flag1 = I2Cx->SR1; - flag2 = I2Cx->SR2; - flag2 = flag2 << 16; - - /* Get the last event value from I2C status register */ - lastevent = (flag1 | flag2) & FLAG_MASK; - - /* Check whether the last event contains the I2C_EVENT */ - if ((lastevent & I2C_EVENT) == I2C_EVENT) - { - /* SUCCESS: last event is equal to I2C_EVENT */ - status = SUCCESS; - } - else - { - /* ERROR: last event is different from I2C_EVENT */ - status = ERROR; - } - /* Return status */ - return status; -} - -/* - =============================================================================== - 2. Advanced state monitoring - =============================================================================== - */ - -/** - * @brief Returns the last I2Cx Event. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * - * @note For detailed description of Events, please refer to section I2C_Events - * in stm32f4xx_i2c.h file. - * - * @retval The last event - */ -uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Read the I2Cx status register */ - flag1 = I2Cx->SR1; - flag2 = I2Cx->SR2; - flag2 = flag2 << 16; - - /* Get the last event value from I2C status register */ - lastevent = (flag1 | flag2) & FLAG_MASK; - - /* Return status */ - return lastevent; -} - -/* - =============================================================================== - 3. Flag-based state monitoring - =============================================================================== - */ - -/** - * @brief Checks whether the specified I2C flag is set or not. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg I2C_FLAG_DUALF: Dual flag (Slave mode) - * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode) - * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode) - * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode) - * @arg I2C_FLAG_TRA: Transmitter/Receiver flag - * @arg I2C_FLAG_BUSY: Bus busy flag - * @arg I2C_FLAG_MSL: Master/Slave flag - * @arg I2C_FLAG_SMBALERT: SMBus Alert flag - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_FLAG_PECERR: PEC error in reception flag - * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_FLAG_AF: Acknowledge failure flag - * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_FLAG_BERR: Bus error flag - * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter) - * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag - * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode) - * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode) - * @arg I2C_FLAG_BTF: Byte transfer finished flag - * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL" - * Address matched flag (Slave mode)"ENDAD" - * @arg I2C_FLAG_SB: Start bit flag (Master mode) - * @retval The new state of I2C_FLAG (SET or RESET). - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) -{ - FlagStatus bitstatus = RESET; - __IO uint32_t i2creg = 0, i2cxbase = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); - - /* Get the I2Cx peripheral base address */ - i2cxbase = (uint32_t)I2Cx; - - /* Read flag register index */ - i2creg = I2C_FLAG >> 28; - - /* Get bit[23:0] of the flag */ - I2C_FLAG &= FLAG_MASK; - - if(i2creg != 0) - { - /* Get the I2Cx SR1 register address */ - i2cxbase += 0x14; - } - else - { - /* Flag in I2Cx SR2 Register */ - I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); - /* Get the I2Cx SR2 register address */ - i2cxbase += 0x18; - } - - if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) - { - /* I2C_FLAG is set */ - bitstatus = SET; - } - else - { - /* I2C_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the I2C_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the I2Cx's pending flags. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg I2C_FLAG_SMBALERT: SMBus Alert flag - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_FLAG_PECERR: PEC error in reception flag - * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_FLAG_AF: Acknowledge failure flag - * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_FLAG_BERR: Bus error flag - * - * @note STOPF (STOP detection) is cleared by software sequence: a read operation - * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation - * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). - * @note ADD10 (10-bit header sent) is cleared by software sequence: a read - * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the - * second byte of the address in DR register. - * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read - * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a - * read/write to I2C_DR register (I2C_SendData()). - * @note ADDR (Address sent) is cleared by software sequence: a read operation to - * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to - * I2C_SR2 register ((void)(I2Cx->SR2)). - * @note SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1 - * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR - * register (I2C_SendData()). - * - * @retval None - */ -void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) -{ - uint32_t flagpos = 0; - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG)); - /* Get the I2C flag position */ - flagpos = I2C_FLAG & FLAG_MASK; - /* Clear the selected I2C flag */ - I2Cx->SR1 = (uint16_t)~flagpos; -} - -/** - * @brief Checks whether the specified I2C interrupt has occurred or not. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_IT: specifies the interrupt source to check. - * This parameter can be one of the following values: - * @arg I2C_IT_SMBALERT: SMBus Alert flag - * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_IT_PECERR: PEC error in reception flag - * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_IT_AF: Acknowledge failure flag - * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_IT_BERR: Bus error flag - * @arg I2C_IT_TXE: Data register empty flag (Transmitter) - * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag - * @arg I2C_IT_STOPF: Stop detection flag (Slave mode) - * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode) - * @arg I2C_IT_BTF: Byte transfer finished flag - * @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL" - * Address matched flag (Slave mode)"ENDAD" - * @arg I2C_IT_SB: Start bit flag (Master mode) - * @retval The new state of I2C_IT (SET or RESET). - */ -ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_GET_IT(I2C_IT)); - - /* Check if the interrupt source is enabled or not */ - enablestatus = (uint32_t)(((I2C_IT & ITEN_MASK) >> 16) & (I2Cx->CR2)) ; - - /* Get bit[23:0] of the flag */ - I2C_IT &= FLAG_MASK; - - /* Check the status of the specified I2C flag */ - if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) - { - /* I2C_IT is set */ - bitstatus = SET; - } - else - { - /* I2C_IT is reset */ - bitstatus = RESET; - } - /* Return the I2C_IT status */ - return bitstatus; -} - -/** - * @brief Clears the I2Cx's interrupt pending bits. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg I2C_IT_SMBALERT: SMBus Alert interrupt - * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt - * @arg I2C_IT_PECERR: PEC error in reception interrupt - * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode) - * @arg I2C_IT_AF: Acknowledge failure interrupt - * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode) - * @arg I2C_IT_BERR: Bus error interrupt - * - * @note STOPF (STOP detection) is cleared by software sequence: a read operation - * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to - * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). - * @note ADD10 (10-bit header sent) is cleared by software sequence: a read - * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second - * byte of the address in I2C_DR register. - * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read - * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a - * read/write to I2C_DR register (I2C_SendData()). - * @note ADDR (Address sent) is cleared by software sequence: a read operation to - * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to - * I2C_SR2 register ((void)(I2Cx->SR2)). - * @note SB (Start Bit) is cleared by software sequence: a read operation to - * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to - * I2C_DR register (I2C_SendData()). - * @retval None - */ -void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT) -{ - uint32_t flagpos = 0; - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_CLEAR_IT(I2C_IT)); - - /* Get the I2C flag position */ - flagpos = I2C_IT & FLAG_MASK; - - /* Clear the selected I2C flag */ - I2Cx->SR1 = (uint16_t)~flagpos; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm32f4xx_i2c.h b/stm/stmperiph/stm32f4xx_i2c.h deleted file mode 100644 index 87ca21284..000000000 --- a/stm/stmperiph/stm32f4xx_i2c.h +++ /dev/null @@ -1,711 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_i2c.h - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief This file contains all the functions prototypes for the I2C firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_I2C_H -#define __STM32F4xx_I2C_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup I2C - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief I2C Init structure definition - */ - -typedef struct -{ - uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency. - This parameter must be set to a value lower than 400kHz */ - - uint16_t I2C_Mode; /*!< Specifies the I2C mode. - This parameter can be a value of @ref I2C_mode */ - - uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle. - This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ - - uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ - - uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement. - This parameter can be a value of @ref I2C_acknowledgement */ - - uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged. - This parameter can be a value of @ref I2C_acknowledged_address */ -}I2C_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - - -/** @defgroup I2C_Exported_Constants - * @{ - */ - -#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ - ((PERIPH) == I2C2) || \ - ((PERIPH) == I2C3)) - -/** @defgroup I2C_Digital_Filter - * @{ - */ - -#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F) -/** - * @} - */ - - -/** @defgroup I2C_mode - * @{ - */ - -#define I2C_Mode_I2C ((uint16_t)0x0000) -#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) -#define I2C_Mode_SMBusHost ((uint16_t)0x000A) -#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ - ((MODE) == I2C_Mode_SMBusDevice) || \ - ((MODE) == I2C_Mode_SMBusHost)) -/** - * @} - */ - -/** @defgroup I2C_duty_cycle_in_fast_mode - * @{ - */ - -#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */ -#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */ -#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \ - ((CYCLE) == I2C_DutyCycle_2)) -/** - * @} - */ - -/** @defgroup I2C_acknowledgement - * @{ - */ - -#define I2C_Ack_Enable ((uint16_t)0x0400) -#define I2C_Ack_Disable ((uint16_t)0x0000) -#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \ - ((STATE) == I2C_Ack_Disable)) -/** - * @} - */ - -/** @defgroup I2C_transfer_direction - * @{ - */ - -#define I2C_Direction_Transmitter ((uint8_t)0x00) -#define I2C_Direction_Receiver ((uint8_t)0x01) -#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ - ((DIRECTION) == I2C_Direction_Receiver)) -/** - * @} - */ - -/** @defgroup I2C_acknowledged_address - * @{ - */ - -#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) -#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) -#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ - ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) -/** - * @} - */ - -/** @defgroup I2C_registers - * @{ - */ - -#define I2C_Register_CR1 ((uint8_t)0x00) -#define I2C_Register_CR2 ((uint8_t)0x04) -#define I2C_Register_OAR1 ((uint8_t)0x08) -#define I2C_Register_OAR2 ((uint8_t)0x0C) -#define I2C_Register_DR ((uint8_t)0x10) -#define I2C_Register_SR1 ((uint8_t)0x14) -#define I2C_Register_SR2 ((uint8_t)0x18) -#define I2C_Register_CCR ((uint8_t)0x1C) -#define I2C_Register_TRISE ((uint8_t)0x20) -#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ - ((REGISTER) == I2C_Register_CR2) || \ - ((REGISTER) == I2C_Register_OAR1) || \ - ((REGISTER) == I2C_Register_OAR2) || \ - ((REGISTER) == I2C_Register_DR) || \ - ((REGISTER) == I2C_Register_SR1) || \ - ((REGISTER) == I2C_Register_SR2) || \ - ((REGISTER) == I2C_Register_CCR) || \ - ((REGISTER) == I2C_Register_TRISE)) -/** - * @} - */ - -/** @defgroup I2C_NACK_position - * @{ - */ - -#define I2C_NACKPosition_Next ((uint16_t)0x0800) -#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) -#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \ - ((POSITION) == I2C_NACKPosition_Current)) -/** - * @} - */ - -/** @defgroup I2C_SMBus_alert_pin_level - * @{ - */ - -#define I2C_SMBusAlert_Low ((uint16_t)0x2000) -#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) -#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \ - ((ALERT) == I2C_SMBusAlert_High)) -/** - * @} - */ - -/** @defgroup I2C_PEC_position - * @{ - */ - -#define I2C_PECPosition_Next ((uint16_t)0x0800) -#define I2C_PECPosition_Current ((uint16_t)0xF7FF) -#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \ - ((POSITION) == I2C_PECPosition_Current)) -/** - * @} - */ - -/** @defgroup I2C_interrupts_definition - * @{ - */ - -#define I2C_IT_BUF ((uint16_t)0x0400) -#define I2C_IT_EVT ((uint16_t)0x0200) -#define I2C_IT_ERR ((uint16_t)0x0100) -#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) -/** - * @} - */ - -/** @defgroup I2C_interrupts_definition - * @{ - */ - -#define I2C_IT_SMBALERT ((uint32_t)0x01008000) -#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) -#define I2C_IT_PECERR ((uint32_t)0x01001000) -#define I2C_IT_OVR ((uint32_t)0x01000800) -#define I2C_IT_AF ((uint32_t)0x01000400) -#define I2C_IT_ARLO ((uint32_t)0x01000200) -#define I2C_IT_BERR ((uint32_t)0x01000100) -#define I2C_IT_TXE ((uint32_t)0x06000080) -#define I2C_IT_RXNE ((uint32_t)0x06000040) -#define I2C_IT_STOPF ((uint32_t)0x02000010) -#define I2C_IT_ADD10 ((uint32_t)0x02000008) -#define I2C_IT_BTF ((uint32_t)0x02000004) -#define I2C_IT_ADDR ((uint32_t)0x02000002) -#define I2C_IT_SB ((uint32_t)0x02000001) - -#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00)) - -#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \ - ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \ - ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \ - ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \ - ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \ - ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \ - ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB)) -/** - * @} - */ - -/** @defgroup I2C_flags_definition - * @{ - */ - -/** - * @brief SR2 register flags - */ - -#define I2C_FLAG_DUALF ((uint32_t)0x00800000) -#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) -#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) -#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) -#define I2C_FLAG_TRA ((uint32_t)0x00040000) -#define I2C_FLAG_BUSY ((uint32_t)0x00020000) -#define I2C_FLAG_MSL ((uint32_t)0x00010000) - -/** - * @brief SR1 register flags - */ - -#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) -#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) -#define I2C_FLAG_PECERR ((uint32_t)0x10001000) -#define I2C_FLAG_OVR ((uint32_t)0x10000800) -#define I2C_FLAG_AF ((uint32_t)0x10000400) -#define I2C_FLAG_ARLO ((uint32_t)0x10000200) -#define I2C_FLAG_BERR ((uint32_t)0x10000100) -#define I2C_FLAG_TXE ((uint32_t)0x10000080) -#define I2C_FLAG_RXNE ((uint32_t)0x10000040) -#define I2C_FLAG_STOPF ((uint32_t)0x10000010) -#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) -#define I2C_FLAG_BTF ((uint32_t)0x10000004) -#define I2C_FLAG_ADDR ((uint32_t)0x10000002) -#define I2C_FLAG_SB ((uint32_t)0x10000001) - -#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) - -#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \ - ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \ - ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \ - ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \ - ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \ - ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \ - ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \ - ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \ - ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \ - ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \ - ((FLAG) == I2C_FLAG_SB)) -/** - * @} - */ - -/** @defgroup I2C_Events - * @{ - */ - -/** - =============================================================================== - I2C Master Events (Events grouped in order of communication) - =============================================================================== - */ - -/** - * @brief Communication start - * - * After sending the START condition (I2C_GenerateSTART() function) the master - * has to wait for this event. It means that the Start condition has been correctly - * released on the I2C bus (the bus is free, no other devices is communicating). - * - */ -/* --EV5 */ -#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ - -/** - * @brief Address Acknowledge - * - * After checking on EV5 (start condition correctly released on the bus), the - * master sends the address of the slave(s) with which it will communicate - * (I2C_Send7bitAddress() function, it also determines the direction of the communication: - * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges - * his address. If an acknowledge is sent on the bus, one of the following events will - * be set: - * - * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - * event is set. - * - * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - * is set - * - * 3) In case of 10-Bit addressing mode, the master (just after generating the START - * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() - * function). Then master should wait on EV9. It means that the 10-bit addressing - * header has been correctly sent on the bus. Then master should send the second part of - * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master - * should wait for event EV6. - * - */ - -/* --EV6 */ -#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ -#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ -/* --EV9 */ -#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ - -/** - * @brief Communication events - * - * If a communication is established (START condition generated and slave address - * acknowledged) then the master has to check on one of the following events for - * communication procedures: - * - * 1) Master Receiver mode: The master has to wait on the event EV7 then to read - * the data received from the slave (I2C_ReceiveData() function). - * - * 2) Master Transmitter mode: The master has to send data (I2C_SendData() - * function) then to wait on event EV8 or EV8_2. - * These two events are similar: - * - EV8 means that the data has been written in the data register and is - * being shifted out. - * - EV8_2 means that the data has been physically shifted out and output - * on the bus. - * In most cases, using EV8 is sufficient for the application. - * Using EV8_2 leads to a slower communication but ensure more reliable test. - * EV8_2 is also more suitable than EV8 for testing on the last data transmission - * (before Stop condition generation). - * - * @note In case the user software does not guarantee that this event EV7 is - * managed before the current byte end of transfer, then user may check on EV7 - * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)). - * In this case the communication may be slower. - * - */ - -/* Master RECEIVER mode -----------------------------*/ -/* --EV7 */ -#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ - -/* Master TRANSMITTER mode --------------------------*/ -/* --EV8 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ -/* --EV8_2 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ - - -/** - =============================================================================== - I2C Slave Events (Events grouped in order of communication) - =============================================================================== - */ - - -/** - * @brief Communication start events - * - * Wait on one of these events at the start of the communication. It means that - * the I2C peripheral detected a Start condition on the bus (generated by master - * device) followed by the peripheral address. The peripheral generates an ACK - * condition on the bus (if the acknowledge feature is enabled through function - * I2C_AcknowledgeConfig()) and the events listed above are set : - * - * 1) In normal case (only one address managed by the slave), when the address - * sent by the master matches the own address of the peripheral (configured by - * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set - * (where XXX could be TRANSMITTER or RECEIVER). - * - * 2) In case the address sent by the master matches the second address of the - * peripheral (configured by the function I2C_OwnAddress2Config() and enabled - * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED - * (where XXX could be TRANSMITTER or RECEIVER) are set. - * - * 3) In case the address sent by the master is General Call (address 0x00) and - * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) - * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. - * - */ - -/* --EV1 (all the events below are variants of EV1) */ -/* 1) Case of One Single Address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ - -/* 2) Case of Dual address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ - -/* 3) Case of General Call enabled for the slave */ -#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ - -/** - * @brief Communication events - * - * Wait on one of these events when EV1 has already been checked and: - * - * - Slave RECEIVER mode: - * - EV2: When the application is expecting a data byte to be received. - * - EV4: When the application is expecting the end of the communication: master - * sends a stop condition and data transmission is stopped. - * - * - Slave Transmitter mode: - * - EV3: When a byte has been transmitted by the slave and the application is expecting - * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and - * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be - * used when the user software doesn't guarantee the EV3 is managed before the - * current byte end of transfer. - * - EV3_2: When the master sends a NACK in order to tell slave that data transmission - * shall end (before sending the STOP condition). In this case slave has to stop sending - * data bytes and expect a Stop condition on the bus. - * - * @note In case the user software does not guarantee that the event EV2 is - * managed before the current byte end of transfer, then user may check on EV2 - * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)). - * In this case the communication may be slower. - * - */ - -/* Slave RECEIVER mode --------------------------*/ -/* --EV2 */ -#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ -/* --EV4 */ -#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ - -/* Slave TRANSMITTER mode -----------------------*/ -/* --EV3 */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ -/* --EV3_2 */ -#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ - -/* - =============================================================================== - End of Events Description - =============================================================================== - */ - -#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \ - ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \ - ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \ - ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \ - ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \ - ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE)) -/** - * @} - */ - -/** @defgroup I2C_own_address1 - * @{ - */ - -#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF) -/** - * @} - */ - -/** @defgroup I2C_clock_speed - * @{ - */ - -#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the I2C configuration to the default reset state *****/ -void I2C_DeInit(I2C_TypeDef* I2Cx); - -/* Initialization and Configuration functions *********************************/ -void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); -void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_DigitalFilterConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DigitalFilter); -void I2C_AnalogFilterCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); -void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); -void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); -void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition); -void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); -void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); - -/* Data transfers functions ***************************************************/ -void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); -uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); - -/* PEC management functions ***************************************************/ -void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); -void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); -uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); - -/* DMA transfers management functions *****************************************/ -void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); - -/* Interrupts, events and flags management functions **************************/ -uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); -void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); - -/* - =============================================================================== - I2C State Monitoring Functions - =============================================================================== - This I2C driver provides three different ways for I2C state monitoring - depending on the application requirements and constraints: - - - 1. Basic state monitoring (Using I2C_CheckEvent() function) - ----------------------------------------------------------- - It compares the status registers (SR1 and SR2) content to a given event - (can be the combination of one or more flags). - It returns SUCCESS if the current status includes the given flags - and returns ERROR if one or more flags are missing in the current status. - - - When to use - - This function is suitable for most applications as well as for startup - activity since the events are fully described in the product reference - manual (RM0090). - - It is also suitable for users who need to define their own events. - - - Limitations - - If an error occurs (ie. error flags are set besides to the monitored - flags), the I2C_CheckEvent() function may return SUCCESS despite - the communication hold or corrupted real state. - In this case, it is advised to use error interrupts to monitor - the error events and handle them in the interrupt IRQ handler. - - Note - For error management, it is advised to use the following functions: - - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). - - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. - Where x is the peripheral instance (I2C1, I2C2 ...) - - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the - I2Cx_ER_IRQHandler() function in order to determine which error occurred. - - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() - and/or I2C_GenerateStop() in order to clear the error flag and source - and return to correct communication status. - - - 2. Advanced state monitoring (Using the function I2C_GetLastEvent()) - -------------------------------------------------------------------- - Using the function I2C_GetLastEvent() which returns the image of both status - registers in a single word (uint32_t) (Status Register 2 value is shifted left - by 16 bits and concatenated to Status Register 1). - - - When to use - - This function is suitable for the same applications above but it - allows to overcome the mentioned limitation of I2C_GetFlagStatus() - function. - - The returned value could be compared to events already defined in - this file or to custom values defined by user. - This function is suitable when multiple flags are monitored at the - same time. - - At the opposite of I2C_CheckEvent() function, this function allows - user to choose when an event is accepted (when all events flags are - set and no other flags are set or just when the needed flags are set - like I2C_CheckEvent() function. - - - Limitations - - User may need to define his own events. - - Same remark concerning the error management is applicable for this - function if user decides to check only regular communication flags - (and ignores error flags). - - - 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus()) - ----------------------------------------------------------------------- - - Using the function I2C_GetFlagStatus() which simply returns the status of - one single flag (ie. I2C_FLAG_RXNE ...). - - - When to use - - This function could be used for specific applications or in debug - phase. - - It is suitable when only one flag checking is needed (most I2C - events are monitored through multiple flags). - - Limitations: - - When calling this function, the Status register is accessed. - Some flags are cleared when the status register is accessed. - So checking the status of one Flag, may clear other ones. - - Function may need to be called twice or more in order to monitor - one single event. - */ - -/* - =============================================================================== - 1. Basic state monitoring - =============================================================================== - */ -ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); -/* - =============================================================================== - 2. Advanced state monitoring - =============================================================================== - */ -uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); -/* - =============================================================================== - 3. Flag-based state monitoring - =============================================================================== - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); - - -void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); -ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); -void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_I2C_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm32f4xx_pwr.c b/stm/stmperiph/stm32f4xx_pwr.c deleted file mode 100644 index 61b8515e1..000000000 --- a/stm/stmperiph/stm32f4xx_pwr.c +++ /dev/null @@ -1,885 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_pwr.c - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief This file provides firmware functions to manage the following - * functionalities of the Power Controller (PWR) peripheral: - * + Backup Domain Access - * + PVD configuration - * + WakeUp pin configuration - * + Main and Backup Regulators configuration - * + FLASH Power Down configuration - * + Low Power modes configuration - * + Flags management - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_pwr.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup PWR - * @brief PWR driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* --------- PWR registers bit address in the alias region ---------- */ -#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) - -/* --- CR Register ---*/ - -/* Alias word address of DBP bit */ -#define CR_OFFSET (PWR_OFFSET + 0x00) -#define DBP_BitNumber 0x08 -#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) - -/* Alias word address of PVDE bit */ -#define PVDE_BitNumber 0x04 -#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) - -/* Alias word address of FPDS bit */ -#define FPDS_BitNumber 0x09 -#define CR_FPDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4)) - -/* Alias word address of PMODE bit */ -#define PMODE_BitNumber 0x0E -#define CR_PMODE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4)) - -/* Alias word address of ODEN bit */ -#define ODEN_BitNumber 0x10 -#define CR_ODEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODEN_BitNumber * 4)) - -/* Alias word address of ODSWEN bit */ -#define ODSWEN_BitNumber 0x11 -#define CR_ODSWEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODSWEN_BitNumber * 4)) - -/* --- CSR Register ---*/ - -/* Alias word address of EWUP bit */ -#define CSR_OFFSET (PWR_OFFSET + 0x04) -#define EWUP_BitNumber 0x08 -#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) - -/* Alias word address of BRE bit */ -#define BRE_BitNumber 0x09 -#define CSR_BRE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4)) - -/* ------------------ PWR registers bit mask ------------------------ */ - -/* CR register bit mask */ -#define CR_DS_MASK ((uint32_t)0xFFFFF3FC) -#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F) -#define CR_VOS_MASK ((uint32_t)0xFFFF3FFF) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup PWR_Private_Functions - * @{ - */ - -/** @defgroup PWR_Group1 Backup Domain Access function - * @brief Backup Domain Access function - * -@verbatim - =============================================================================== - ##### Backup Domain Access function ##### - =============================================================================== - [..] - After reset, the backup domain (RTC registers, RTC backup data - registers and backup SRAM) is protected against possible unwanted - write accesses. - To enable access to the RTC Domain and RTC registers, proceed as follows: - (+) Enable the Power Controller (PWR) APB1 interface clock using the - RCC_APB1PeriphClockCmd() function. - (+) Enable access to RTC domain using the PWR_BackupAccessCmd() function. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the PWR peripheral registers to their default reset values. - * @param None - * @retval None - */ -void PWR_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); -} - -/** - * @brief Enables or disables access to the backup domain (RTC registers, RTC - * backup data registers and backup SRAM). - * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the - * Backup Domain Access should be kept enabled. - * @param NewState: new state of the access to the backup domain. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_BackupAccessCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup PWR_Group2 PVD configuration functions - * @brief PVD configuration functions - * -@verbatim - =============================================================================== - ##### PVD configuration functions ##### - =============================================================================== - [..] - (+) The PVD is used to monitor the VDD power supply by comparing it to a - threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). - (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower - than the PVD threshold. This event is internally connected to the EXTI - line16 and can generate an interrupt if enabled through the EXTI registers. - (+) The PVD is stopped in Standby mode. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). - * @param PWR_PVDLevel: specifies the PVD detection level - * This parameter can be one of the following values: - * @arg PWR_PVDLevel_0 - * @arg PWR_PVDLevel_1 - * @arg PWR_PVDLevel_2 - * @arg PWR_PVDLevel_3 - * @arg PWR_PVDLevel_4 - * @arg PWR_PVDLevel_5 - * @arg PWR_PVDLevel_6 - * @arg PWR_PVDLevel_7 - * @note Refer to the electrical characteristics of your device datasheet for - * more details about the voltage threshold corresponding to each - * detection level. - * @retval None - */ -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); - - tmpreg = PWR->CR; - - /* Clear PLS[7:5] bits */ - tmpreg &= CR_PLS_MASK; - - /* Set PLS[7:5] bits according to PWR_PVDLevel value */ - tmpreg |= PWR_PVDLevel; - - /* Store the new value */ - PWR->CR = tmpreg; -} - -/** - * @brief Enables or disables the Power Voltage Detector(PVD). - * @param NewState: new state of the PVD. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_PVDCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup PWR_Group3 WakeUp pin configuration functions - * @brief WakeUp pin configuration functions - * -@verbatim - =============================================================================== - ##### WakeUp pin configuration functions ##### - =============================================================================== - [..] - (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is - forced in input pull down configuration and is active on rising edges. - (+) There is only one WakeUp pin: WakeUp Pin 1 on PA.00. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the WakeUp Pin functionality. - * @param NewState: new state of the WakeUp Pin functionality. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_WakeUpPinCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup PWR_Group4 Main and Backup Regulators configuration functions - * @brief Main and Backup Regulators configuration functions - * -@verbatim - =============================================================================== - ##### Main and Backup Regulators configuration functions ##### - =============================================================================== - [..] - (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from - the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is - retained even in Standby or VBAT mode when the low power backup regulator - is enabled. It can be considered as an internal EEPROM when VBAT is - always present. You can use the PWR_BackupRegulatorCmd() function to - enable the low power backup regulator and use the PWR_GetFlagStatus - (PWR_FLAG_BRR) to check if it is ready or not. - - (+) When the backup domain is supplied by VDD (analog switch connected to VDD) - the backup SRAM is powered from VDD which replaces the VBAT power supply to - save battery life. - - (+) The backup SRAM is not mass erased by an tamper event. It is read - protected to prevent confidential data, such as cryptographic private - key, from being accessed. The backup SRAM can be erased only through - the Flash interface when a protection level change from level 1 to - level 0 is requested. - -@- Refer to the description of Read protection (RDP) in the reference manual. - - (+) The main internal regulator can be configured to have a tradeoff between - performance and power consumption when the device does not operate at - the maximum frequency. - (+) For STM32F405xx/407xx and STM32F415xx/417xx Devices, the regulator can be - configured on the fly through PWR_MainRegulatorModeConfig() function which - configure VOS bit in PWR_CR register: - (++) When this bit is set (Regulator voltage output Scale 1 mode selected) - the System frequency can go up to 168 MHz. - (++) When this bit is reset (Regulator voltage output Scale 2 mode selected) - the System frequency can go up to 144 MHz. - - (+) For STM32F42xxx/43xxx Devices, the regulator can be configured through - PWR_MainRegulatorModeConfig() function which configure VOS[1:0] bits in - PWR_CR register: - which configure VOS[1:0] bits in PWR_CR register: - (++) When VOS[1:0] = 11 (Regulator voltage output Scale 1 mode selected) - the System frequency can go up to 168 MHz. - (++) When VOS[1:0] = 10 (Regulator voltage output Scale 2 mode selected) - the System frequency can go up to 144 MHz. - (++) When VOS[1:0] = 01 (Regulator voltage output Scale 3 mode selected) - the System frequency can go up to 120 MHz. - - (+) For STM32F42xxx/43xxx Devices, the scale can be modified only when the PLL - is OFF and the HSI or HSE clock source is selected as system clock. - The new value programmed is active only when the PLL is ON. - When the PLL is OFF, the voltage scale 3 is automatically selected. - Refer to the datasheets for more details. - - (+) For STM32F42xxx/43xxx Devices, in Run mode: the main regulator has - 2 operating modes available: - (++) Normal mode: The CPU and core logic operate at maximum frequency at a given - voltage scaling (scale 1, scale 2 or scale 3) - (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a - higher frequency than the normal mode for a given voltage scaling (scale 1, - scale 2 or scale 3). This mode is enabled through PWR_OverDriveCmd() function and - PWR_OverDriveSWCmd() function, to enter or exit from Over-drive mode please follow - the sequence described in Reference manual. - - (+) For STM32F42xxx/43xxx Devices, in Stop mode: the main regulator or low power regulator - supplies a low power voltage to the 1.2V domain, thus preserving the content of registers - and internal SRAM. 2 operating modes are available: - (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only - available when the main regulator or the low power regulator is used in Scale 3 or - low voltage mode. - (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only - available when the main regulator or the low power regulator is in low voltage mode. - This mode is enabled through PWR_UnderDriveCmd() function. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the Backup Regulator. - * @param NewState: new state of the Backup Regulator. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_BackupRegulatorCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the main internal regulator output voltage. - * @param PWR_Regulator_Voltage: specifies the regulator output voltage to achieve - * a tradeoff between performance and power consumption when the device does - * not operate at the maximum frequency (refer to the datasheets for more details). - * This parameter can be one of the following values: - * @arg PWR_Regulator_Voltage_Scale1: Regulator voltage output Scale 1 mode, - * System frequency up to 168 MHz. - * @arg PWR_Regulator_Voltage_Scale2: Regulator voltage output Scale 2 mode, - * System frequency up to 144 MHz. - * @arg PWR_Regulator_Voltage_Scale3: Regulator voltage output Scale 3 mode, - * System frequency up to 120 MHz (only for STM32F42xxx/43xxx devices) - * @retval None - */ -void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR_VOLTAGE(PWR_Regulator_Voltage)); - - tmpreg = PWR->CR; - - /* Clear VOS[15:14] bits */ - tmpreg &= CR_VOS_MASK; - - /* Set VOS[15:14] bits according to PWR_Regulator_Voltage value */ - tmpreg |= PWR_Regulator_Voltage; - - /* Store the new value */ - PWR->CR = tmpreg; -} - -/** - * @brief Enables or disables the Over-Drive. - * - * @note This function can be used only for STM32F42xxx/STM3243xxx devices. - * This mode allows the CPU and the core logic to operate at a higher frequency - * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). - * - * @note It is recommended to enter or exit Over-drive mode when the application is not running - * critical tasks and when the system clock source is either HSI or HSE. - * During the Over-drive switch activation, no peripheral clocks should be enabled. - * The peripheral clocks must be enabled once the Over-drive mode is activated. - * - * @param NewState: new state of the Over Drive mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_OverDriveCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Set/Reset the ODEN bit to enable/disable the Over Drive mode */ - *(__IO uint32_t *) CR_ODEN_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the Over-Drive switching. - * - * @note This function can be used only for STM32F42xxx/STM3243xxx devices. - * - * @param NewState: new state of the Over Drive switching mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_OverDriveSWCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Set/Reset the ODSWEN bit to enable/disable the Over Drive switching mode */ - *(__IO uint32_t *) CR_ODSWEN_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the Under-Drive mode. - * - * @note This function can be used only for STM32F42xxx/STM3243xxx devices. - * @note This mode is enabled only with STOP low power mode. - * In this mode, the 1.2V domain is preserved in reduced leakage mode. This - * mode is only available when the main regulator or the low power regulator - * is in low voltage mode - * - * @note If the Under-drive mode was enabled, it is automatically disabled after - * exiting Stop mode. - * When the voltage regulator operates in Under-drive mode, an additional - * startup delay is induced when waking up from Stop mode. - * - * @param NewState: new state of the Under Drive mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_UnderDriveCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the UDEN[1:0] bits to enable the Under Drive mode */ - PWR->CR |= (uint32_t)PWR_CR_UDEN; - } - else - { - /* Reset the UDEN[1:0] bits to disable the Under Drive mode */ - PWR->CR &= (uint32_t)(~PWR_CR_UDEN); - } -} - -/** - * @} - */ - -/** @defgroup PWR_Group5 FLASH Power Down configuration functions - * @brief FLASH Power Down configuration functions - * -@verbatim - =============================================================================== - ##### FLASH Power Down configuration functions ##### - =============================================================================== - [..] - (+) By setting the FPDS bit in the PWR_CR register by using the - PWR_FlashPowerDownCmd() function, the Flash memory also enters power - down mode when the device enters Stop mode. When the Flash memory - is in power down mode, an additional startup delay is incurred when - waking up from Stop mode. -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the Flash Power Down in STOP mode. - * @param NewState: new state of the Flash power mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_FlashPowerDownCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup PWR_Group6 Low Power modes configuration functions - * @brief Low Power modes configuration functions - * -@verbatim - =============================================================================== - ##### Low Power modes configuration functions ##### - =============================================================================== - [..] - The devices feature 3 low-power modes: - (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running. - (+) Stop mode: all clocks are stopped, regulator running, regulator - in low power mode - (+) Standby mode: 1.2V domain powered off. - - *** Sleep mode *** - ================== - [..] - (+) Entry: - (++) The Sleep mode is entered by using the __WFI() or __WFE() functions. - (+) Exit: - (++) Any peripheral interrupt acknowledged by the nested vectored interrupt - controller (NVIC) can wake up the device from Sleep mode. - - *** Stop mode *** - ================= - [..] - In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI, - and the HSE RC oscillators are disabled. Internal SRAM and register contents - are preserved. - The voltage regulator can be configured either in normal or low-power mode. - To minimize the consumption In Stop mode, FLASH can be powered off before - entering the Stop mode. It can be switched on again by software after exiting - the Stop mode using the PWR_FlashPowerDownCmd() function. - - (+) Entry: - (++) The Stop mode is entered using the PWR_EnterSTOPMode(PWR_MainRegulator_ON) - function with: - (+++) Main regulator ON. - (+++) Low Power regulator ON. - (+) Exit: - (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode. - - *** Standby mode *** - ==================== - [..] - The Standby mode allows to achieve the lowest power consumption. It is based - on the Cortex-M4 deepsleep mode, with the voltage regulator disabled. - The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and - the HSE oscillator are also switched off. SRAM and register contents are lost - except for the RTC registers, RTC backup registers, backup SRAM and Standby - circuitry. - - The voltage regulator is OFF. - - (+) Entry: - (++) The Standby mode is entered using the PWR_EnterSTANDBYMode() function. - (+) Exit: - (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, - tamper event, time-stamp event, external reset in NRST pin, IWDG reset. - - *** Auto-wakeup (AWU) from low-power mode *** - ============================================= - [..] - The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC - Wakeup event, a tamper event, a time-stamp event, or a comparator event, - without depending on an external interrupt (Auto-wakeup mode). - - (#) RTC auto-wakeup (AWU) from the Stop mode - - (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to: - (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt - or Event modes) using the EXTI_Init() function. - (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function - (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() - and RTC_AlarmCmd() functions. - (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it - is necessary to: - (+++) Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt - or Event modes) using the EXTI_Init() function. - (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() - function - (+++) Configure the RTC to detect the tamper or time stamp event using the - RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() - functions. - (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to: - (+++) Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt - or Event modes) using the EXTI_Init() function. - (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function - (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), - RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. - - (#) RTC auto-wakeup (AWU) from the Standby mode - - (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to: - (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function - (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() - and RTC_AlarmCmd() functions. - (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it - is necessary to: - (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() - function - (+++) Configure the RTC to detect the tamper or time stamp event using the - RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() - functions. - (++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to: - (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function - (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), - RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. - -@endverbatim - * @{ - */ - -/** - * @brief Enters STOP mode. - * - * @note In Stop mode, all I/O pins keep the same state as in Run mode. - * @note When exiting Stop mode by issuing an interrupt or a wakeup event, - * the HSI RC oscillator is selected as system clock. - * @note When the voltage regulator operates in low power mode, an additional - * startup delay is incurred when waking up from Stop mode. - * By keeping the internal regulator ON during Stop mode, the consumption - * is higher although the startup time is reduced. - * - * @param PWR_Regulator: specifies the regulator state in STOP mode. - * This parameter can be one of the following values: - * @arg PWR_MainRegulator_ON: STOP mode with regulator ON - * @arg PWR_LowPowerRegulator_ON: STOP mode with low power regulator ON - * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction - * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction - * @retval None - */ -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(PWR_Regulator)); - assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); - - /* Select the regulator state in STOP mode ---------------------------------*/ - tmpreg = PWR->CR; - /* Clear PDDS and LPDS bits */ - tmpreg &= CR_DS_MASK; - - /* Set LPDS, MRLVDS and LPLVDS bits according to PWR_Regulator value */ - tmpreg |= PWR_Regulator; - - /* Store the new value */ - PWR->CR = tmpreg; - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* Select STOP mode entry --------------------------------------------------*/ - if(PWR_STOPEntry == PWR_STOPEntry_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __WFE(); - } - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); -} - -/** - * @brief Enters in Under-Drive STOP mode. - * - * @note This mode is only available for STM32F42xxx/STM3243xxx devices. - * - * @note This mode can be selected only when the Under-Drive is already active - * - * @note In Stop mode, all I/O pins keep the same state as in Run mode. - * @note When exiting Stop mode by issuing an interrupt or a wakeup event, - * the HSI RC oscillator is selected as system clock. - * @note When the voltage regulator operates in low power mode, an additional - * startup delay is incurred when waking up from Stop mode. - * By keeping the internal regulator ON during Stop mode, the consumption - * is higher although the startup time is reduced. - * - * @param PWR_Regulator: specifies the regulator state in STOP mode. - * This parameter can be one of the following values: - * @arg PWR_MainRegulator_UnderDrive_ON: Main Regulator in under-drive mode - * and Flash memory in power-down when the device is in Stop under-drive mode - * @arg PWR_LowPowerRegulator_UnderDrive_ON: Low Power Regulator in under-drive mode - * and Flash memory in power-down when the device is in Stop under-drive mode - * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction - * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction - * @retval None - */ -void PWR_EnterUnderDriveSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR_UNDERDRIVE(PWR_Regulator)); - assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); - - /* Select the regulator state in STOP mode ---------------------------------*/ - tmpreg = PWR->CR; - /* Clear PDDS and LPDS bits */ - tmpreg &= CR_DS_MASK; - - /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */ - tmpreg |= PWR_Regulator; - - /* Store the new value */ - PWR->CR = tmpreg; - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* Select STOP mode entry --------------------------------------------------*/ - if(PWR_STOPEntry == PWR_STOPEntry_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __WFE(); - } - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); -} - -/** - * @brief Enters STANDBY mode. - * @note In Standby mode, all I/O pins are high impedance except for: - * - Reset pad (still available) - * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC - * Alarm out, or RTC clock calibration out. - * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp. - * - WKUP pin 1 (PA0) if enabled. - * @param None - * @retval None - */ -void PWR_EnterSTANDBYMode(void) -{ - /* Clear Wakeup flag */ - PWR->CR |= PWR_CR_CWUF; - - /* Select STANDBY mode */ - PWR->CR |= PWR_CR_PDDS; - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - -/* This option is used to ensure that store operations are completed */ -#if defined ( __CC_ARM ) - __force_stores(); -#endif - /* Request Wait For Interrupt */ - __WFI(); -} - -/** - * @} - */ - -/** @defgroup PWR_Group7 Flags management functions - * @brief Flags management functions - * -@verbatim - =============================================================================== - ##### Flags management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the specified PWR flag is set or not. - * @param PWR_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event - * was received from the WKUP pin or from the RTC alarm (Alarm A - * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup. - * An additional wakeup event is detected if the WKUP pin is enabled - * (by setting the EWUP bit) when the WKUP pin level is already high. - * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was - * resumed from StandBy mode. - * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled - * by the PWR_PVDCmd() function. The PVD is stopped by Standby mode - * For this reason, this bit is equal to 0 after Standby or reset - * until the PVDE bit is set. - * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset - * when the device wakes up from Standby mode or by a system reset - * or power reset. - * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage - * scaling output selection is ready. - * @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode - * is ready (STM32F42xxx/43xxx devices) - * @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode - * switcching is ready (STM32F42xxx/43xxx devices) - * @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode - * is enabled in Stop mode (STM32F42xxx/43xxx devices) - * @retval The new state of PWR_FLAG (SET or RESET). - */ -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); - - if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the PWR's pending flags. - * @param PWR_FLAG: specifies the flag to clear. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag - * @arg PWR_FLAG_SB: StandBy flag - * @arg PWR_FLAG_UDRDY: Under-drive ready flag (STM32F42xxx/43xxx devices) - * @retval None - */ -void PWR_ClearFlag(uint32_t PWR_FLAG) -{ - /* Check the parameters */ - assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); - -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) - if (PWR_FLAG != PWR_FLAG_UDRDY) - { - PWR->CR |= PWR_FLAG << 2; - } - else - { - PWR->CSR |= PWR_FLAG_UDRDY; - } -#endif /* STM32F427_437xx || STM32F429_439xx */ - -#if defined (STM32F40_41xxx) || defined (STM32F401xx) - PWR->CR |= PWR_FLAG << 2; -#endif /* STM32F40_41xxx */ -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm32f4xx_pwr.h b/stm/stmperiph/stm32f4xx_pwr.h deleted file mode 100644 index 4ce588db6..000000000 --- a/stm/stmperiph/stm32f4xx_pwr.h +++ /dev/null @@ -1,210 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_pwr.h - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief This file contains all the functions prototypes for the PWR firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_PWR_H -#define __STM32F4xx_PWR_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup PWR - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Constants - * @{ - */ - -/** @defgroup PWR_PVD_detection_level - * @{ - */ -#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0 -#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1 -#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2 -#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3 -#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4 -#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5 -#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6 -#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7 - -#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \ - ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \ - ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \ - ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7)) -/** - * @} - */ - - -/** @defgroup PWR_Regulator_state_in_STOP_mode - * @{ - */ -#define PWR_MainRegulator_ON ((uint32_t)0x00000000) -#define PWR_LowPowerRegulator_ON PWR_CR_LPDS - -/* --- PWR_Legacy ---*/ -#define PWR_Regulator_ON PWR_MainRegulator_ON -#define PWR_Regulator_LowPower PWR_LowPowerRegulator_ON - -#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MainRegulator_ON) || \ - ((REGULATOR) == PWR_LowPowerRegulator_ON)) - -/** - * @} - */ - -/** @defgroup PWR_Regulator_state_in_UnderDrive_mode - * @{ - */ -#define PWR_MainRegulator_UnderDrive_ON PWR_CR_MRUDS -#define PWR_LowPowerRegulator_UnderDrive_ON ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS)) - -#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MainRegulator_UnderDrive_ON) || \ - ((REGULATOR) == PWR_LowPowerRegulator_UnderDrive_ON)) - -/** - * @} - */ - -/** @defgroup PWR_STOP_mode_entry - * @{ - */ -#define PWR_STOPEntry_WFI ((uint8_t)0x01) -#define PWR_STOPEntry_WFE ((uint8_t)0x02) -#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) -/** - * @} - */ - -/** @defgroup PWR_Regulator_Voltage_Scale - * @{ - */ -#define PWR_Regulator_Voltage_Scale1 ((uint32_t)0x0000C000) -#define PWR_Regulator_Voltage_Scale2 ((uint32_t)0x00008000) -#define PWR_Regulator_Voltage_Scale3 ((uint32_t)0x00004000) -#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_Regulator_Voltage_Scale1) || \ - ((VOLTAGE) == PWR_Regulator_Voltage_Scale2) || \ - ((VOLTAGE) == PWR_Regulator_Voltage_Scale3)) -/** - * @} - */ - -/** @defgroup PWR_Flag - * @{ - */ -#define PWR_FLAG_WU PWR_CSR_WUF -#define PWR_FLAG_SB PWR_CSR_SBF -#define PWR_FLAG_PVDO PWR_CSR_PVDO -#define PWR_FLAG_BRR PWR_CSR_BRR -#define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY -#define PWR_FLAG_ODRDY PWR_CSR_ODRDY -#define PWR_FLAG_ODSWRDY PWR_CSR_ODSWRDY -#define PWR_FLAG_UDRDY PWR_CSR_UDSWRDY - -/* --- FLAG Legacy ---*/ -#define PWR_FLAG_REGRDY PWR_FLAG_VOSRDY - -#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ - ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_BRR) || \ - ((FLAG) == PWR_FLAG_VOSRDY) || ((FLAG) == PWR_FLAG_ODRDY) || \ - ((FLAG) == PWR_FLAG_ODSWRDY) || ((FLAG) == PWR_FLAG_UDRDY)) - - -#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ - ((FLAG) == PWR_FLAG_UDRDY)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the PWR configuration to the default reset state ******/ -void PWR_DeInit(void); - -/* Backup Domain Access function **********************************************/ -void PWR_BackupAccessCmd(FunctionalState NewState); - -/* PVD configuration functions ************************************************/ -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); -void PWR_PVDCmd(FunctionalState NewState); - -/* WakeUp pins configuration functions ****************************************/ -void PWR_WakeUpPinCmd(FunctionalState NewState); - -/* Main and Backup Regulators configuration functions *************************/ -void PWR_BackupRegulatorCmd(FunctionalState NewState); -void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage); -void PWR_OverDriveCmd(FunctionalState NewState); -void PWR_OverDriveSWCmd(FunctionalState NewState); -void PWR_UnderDriveCmd(FunctionalState NewState); - -/* FLASH Power Down configuration functions ***********************************/ -void PWR_FlashPowerDownCmd(FunctionalState NewState); - -/* Low Power modes configuration functions ************************************/ -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); -void PWR_EnterUnderDriveSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); -void PWR_EnterSTANDBYMode(void); - -/* Flags management functions *************************************************/ -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); -void PWR_ClearFlag(uint32_t PWR_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_PWR_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm32f4xx_rcc.c b/stm/stmperiph/stm32f4xx_rcc.c deleted file mode 100644 index 4c5b47b3f..000000000 --- a/stm/stmperiph/stm32f4xx_rcc.c +++ /dev/null @@ -1,2217 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_rcc.c - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief This file provides firmware functions to manage the following - * functionalities of the Reset and clock control (RCC) peripheral: - * + Internal/external clocks, PLL, CSS and MCO configuration - * + System, AHB and APB busses clocks configuration - * + Peripheral clocks configuration - * + Interrupts and flags management - * - @verbatim - =============================================================================== - ##### RCC specific features ##### - =============================================================================== - [..] - After reset the device is running from Internal High Speed oscillator - (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache - and I-Cache are disabled, and all peripherals are off except internal - SRAM, Flash and JTAG. - (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses; - all peripherals mapped on these busses are running at HSI speed. - (+) The clock for all peripherals is switched off, except the SRAM and FLASH. - (+) All GPIOs are in input floating state, except the JTAG pins which - are assigned to be used for debug purpose. - [..] - Once the device started from reset, the user application has to: - (+) Configure the clock source to be used to drive the System clock - (if the application needs higher frequency/performance) - (+) Configure the System clock frequency and Flash settings - (+) Configure the AHB and APB busses prescalers - (+) Enable the clock for the peripheral(s) to be used - (+) Configure the clock source(s) for peripherals which clocks are not - derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup RCC - * @brief RCC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* ------------ RCC registers bit address in the alias region ----------- */ -#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) -/* --- CR Register ---*/ -/* Alias word address of HSION bit */ -#define CR_OFFSET (RCC_OFFSET + 0x00) -#define HSION_BitNumber 0x00 -#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) -/* Alias word address of CSSON bit */ -#define CSSON_BitNumber 0x13 -#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) -/* Alias word address of PLLON bit */ -#define PLLON_BitNumber 0x18 -#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) -/* Alias word address of PLLI2SON bit */ -#define PLLI2SON_BitNumber 0x1A -#define CR_PLLI2SON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4)) - -/* Alias word address of PLLSAION bit */ -#define PLLSAION_BitNumber 0x1C -#define CR_PLLSAION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLSAION_BitNumber * 4)) - -/* --- CFGR Register ---*/ -/* Alias word address of I2SSRC bit */ -#define CFGR_OFFSET (RCC_OFFSET + 0x08) -#define I2SSRC_BitNumber 0x17 -#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4)) - -/* --- BDCR Register ---*/ -/* Alias word address of RTCEN bit */ -#define BDCR_OFFSET (RCC_OFFSET + 0x70) -#define RTCEN_BitNumber 0x0F -#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) -/* Alias word address of BDRST bit */ -#define BDRST_BitNumber 0x10 -#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) - -/* --- CSR Register ---*/ -/* Alias word address of LSION bit */ -#define CSR_OFFSET (RCC_OFFSET + 0x74) -#define LSION_BitNumber 0x00 -#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) - -/* --- DCKCFGR Register ---*/ -/* Alias word address of TIMPRE bit */ -#define DCKCFGR_OFFSET (RCC_OFFSET + 0x8C) -#define TIMPRE_BitNumber 0x18 -#define DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4)) -/* ---------------------- RCC registers bit mask ------------------------ */ -/* CFGR register bit mask */ -#define CFGR_MCO2_RESET_MASK ((uint32_t)0x07FFFFFF) -#define CFGR_MCO1_RESET_MASK ((uint32_t)0xF89FFFFF) - -/* RCC Flag Mask */ -#define FLAG_MASK ((uint8_t)0x1F) - -/* CR register byte 3 (Bits[23:16]) base address */ -#define CR_BYTE3_ADDRESS ((uint32_t)0x40023802) - -/* CIR register byte 2 (Bits[15:8]) base address */ -#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01)) - -/* CIR register byte 3 (Bits[23:16]) base address */ -#define CIR_BYTE3_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02)) - -/* BDCR register base address */ -#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; - -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RCC_Private_Functions - * @{ - */ - -/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions - * @brief Internal and external clocks, PLL, CSS and MCO configuration functions - * -@verbatim - =================================================================================== - ##### Internal and external clocks, PLL, CSS and MCO configuration functions ##### - =================================================================================== - [..] - This section provide functions allowing to configure the internal/external clocks, - PLLs, CSS and MCO pins. - - (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through - the PLL as System clock source. - - (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC - clock source. - - (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or - through the PLL as System clock source. Can be used also as RTC clock source. - - (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. - - (#) PLL (clocked by HSI or HSE), featuring two different output clocks: - (++) The first output is used to generate the high speed system clock (up to 168 MHz) - (++) The second output is used to generate the clock for the USB OTG FS (48 MHz), - the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz). - - (#) PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve - high-quality audio performance on the I2S interface or SAI interface in case - of STM32F429x/439x devices. - - (#) PLLSAI clocked by (HSI or HSE), used to generate an accurate clock to SAI - interface and LCD TFT controller available only for STM32F42xxx/43xxx devices. - - (#) CSS (Clock security system), once enable and if a HSE clock failure occurs - (HSE used directly or through PLL as System clock source), the System clock - is automatically switched to HSI and an interrupt is generated if enabled. - The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) - exception vector. - - (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL - clock (through a configurable prescaler) on PA8 pin. - - (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S - clock (through a configurable prescaler) on PC9 pin. - @endverbatim - * @{ - */ - -/** - * @brief Resets the RCC clock configuration to the default reset state. - * @note The default reset state of the clock configuration is given below: - * - HSI ON and used as system clock source - * - HSE, PLL and PLLI2S OFF - * - AHB, APB1 and APB2 prescaler set to 1. - * - CSS, MCO1 and MCO2 OFF - * - All interrupts disabled - * @note This function doesn't modify the configuration of the - * - Peripheral clocks - * - LSI, LSE and RTC clocks - * @param None - * @retval None - */ -void RCC_DeInit(void) -{ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON, PLLON, PLLI2S and PLLSAI(STM32F42/43xxx devices) bits */ - RCC->CR &= (uint32_t)0xEAF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x24003010; - - /* Reset PLLI2SCFGR register */ - RCC->PLLI2SCFGR = 0x20003000; - - /* Reset PLLSAICFGR register, only available for STM32F42/43xxx devices */ - RCC->PLLSAICFGR = 0x24003000; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000; - - /* Disable Timers clock prescalers selection, only available for STM32F42/43xxx devices */ - RCC->DCKCFGR = 0x00000000; - -} - -/** - * @brief Configures the External High Speed oscillator (HSE). - * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application - * software should wait on HSERDY flag to be set indicating that HSE clock - * is stable and can be used to clock the PLL and/or system clock. - * @note HSE state can not be changed if it is used directly or through the - * PLL as system clock. In this case, you have to select another source - * of the system clock then change the HSE state (ex. disable it). - * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. - * @note This function reset the CSSON bit, so if the Clock security system(CSS) - * was previously enabled you have to enable it again after calling this - * function. - * @param RCC_HSE: specifies the new state of the HSE. - * This parameter can be one of the following values: - * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after - * 6 HSE oscillator clock cycles. - * @arg RCC_HSE_ON: turn ON the HSE oscillator - * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock - * @retval None - */ -void RCC_HSEConfig(uint8_t RCC_HSE) -{ - /* Check the parameters */ - assert_param(IS_RCC_HSE(RCC_HSE)); - - /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ - *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF; - - /* Set the new HSE configuration -------------------------------------------*/ - *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE; -} - -/** - * @brief Waits for HSE start-up. - * @note This functions waits on HSERDY flag to be set and return SUCCESS if - * this flag is set, otherwise returns ERROR if the timeout is reached - * and this flag is not set. The timeout value is defined by the constant - * HSE_STARTUP_TIMEOUT in stm32f4xx.h file. You can tailor it depending - * on the HSE crystal used in your application. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: HSE oscillator is stable and ready to use - * - ERROR: HSE oscillator not yet ready - */ -ErrorStatus RCC_WaitForHSEStartUp(void) -{ - __IO uint32_t startupcounter = 0; - ErrorStatus status = ERROR; - FlagStatus hsestatus = RESET; - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - hsestatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); - startupcounter++; - } while((startupcounter != HSE_STARTUP_TIMEOUT) && (hsestatus == RESET)); - - if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - return (status); -} - -/** - * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. - * @note The calibration is used to compensate for the variations in voltage - * and temperature that influence the frequency of the internal HSI RC. - * @param HSICalibrationValue: specifies the calibration trimming value. - * This parameter must be a number between 0 and 0x1F. - * @retval None - */ -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue)); - - tmpreg = RCC->CR; - - /* Clear HSITRIM[4:0] bits */ - tmpreg &= ~RCC_CR_HSITRIM; - - /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ - tmpreg |= (uint32_t)HSICalibrationValue << 3; - - /* Store the new value */ - RCC->CR = tmpreg; -} - -/** - * @brief Enables or disables the Internal High Speed oscillator (HSI). - * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. - * It is used (enabled by hardware) as system clock source after startup - * from Reset, wakeup from STOP and STANDBY mode, or in case of failure - * of the HSE used directly or indirectly as system clock (if the Clock - * Security System CSS is enabled). - * @note HSI can not be stopped if it is used as system clock source. In this case, - * you have to select another source of the system clock then stop the HSI. - * @note After enabling the HSI, the application software should wait on HSIRDY - * flag to be set indicating that HSI clock is stable and can be used as - * system clock source. - * @param NewState: new state of the HSI. - * This parameter can be: ENABLE or DISABLE. - * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator - * clock cycles. - * @retval None - */ -void RCC_HSICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the External Low Speed oscillator (LSE). - * @note As the LSE is in the Backup domain and write access is denied to - * this domain after reset, you have to enable write access using - * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE - * (to be done once after reset). - * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application - * software should wait on LSERDY flag to be set indicating that LSE clock - * is stable and can be used to clock the RTC. - * @param RCC_LSE: specifies the new state of the LSE. - * This parameter can be one of the following values: - * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after - * 6 LSE oscillator clock cycles. - * @arg RCC_LSE_ON: turn ON the LSE oscillator - * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock - * @retval None - */ -void RCC_LSEConfig(uint8_t RCC_LSE) -{ - /* Check the parameters */ - assert_param(IS_RCC_LSE(RCC_LSE)); - - /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ - /* Reset LSEON bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; - - /* Reset LSEBYP bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; - - /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */ - switch (RCC_LSE) - { - case RCC_LSE_ON: - /* Set LSEON bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON; - break; - case RCC_LSE_Bypass: - /* Set LSEBYP and LSEON bits */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; - break; - default: - break; - } -} - -/** - * @brief Enables or disables the Internal Low Speed oscillator (LSI). - * @note After enabling the LSI, the application software should wait on - * LSIRDY flag to be set indicating that LSI clock is stable and can - * be used to clock the IWDG and/or the RTC. - * @note LSI can not be disabled if the IWDG is running. - * @param NewState: new state of the LSI. - * This parameter can be: ENABLE or DISABLE. - * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator - * clock cycles. - * @retval None - */ -void RCC_LSICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the main PLL clock source, multiplication and division factors. - * @note This function must be used only when the main PLL is disabled. - * - * @param RCC_PLLSource: specifies the PLL entry clock source. - * This parameter can be one of the following values: - * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry - * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry - * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. - * - * @param PLLM: specifies the division factor for PLL VCO input clock - * This parameter must be a number between 0 and 63. - * @note You have to set the PLLM parameter correctly to ensure that the VCO input - * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency - * of 2 MHz to limit PLL jitter. - * - * @param PLLN: specifies the multiplication factor for PLL VCO output clock - * This parameter must be a number between 192 and 432. - * @note You have to set the PLLN parameter correctly to ensure that the VCO - * output frequency is between 192 and 432 MHz. - * - * @param PLLP: specifies the division factor for main system clock (SYSCLK) - * This parameter must be a number in the range {2, 4, 6, or 8}. - * @note You have to set the PLLP parameter correctly to not exceed 168 MHz on - * the System clock frequency. - * - * @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks - * This parameter must be a number between 4 and 15. - * @note If the USB OTG FS is used in your application, you have to set the - * PLLQ parameter correctly to have 48 MHz clock for the USB. However, - * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work - * correctly. - * - * @retval None - */ -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ) -{ - /* Check the parameters */ - assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); - assert_param(IS_RCC_PLLM_VALUE(PLLM)); - assert_param(IS_RCC_PLLN_VALUE(PLLN)); - assert_param(IS_RCC_PLLP_VALUE(PLLP)); - assert_param(IS_RCC_PLLQ_VALUE(PLLQ)); - - RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) | - (PLLQ << 24); -} - -/** - * @brief Enables or disables the main PLL. - * @note After enabling the main PLL, the application software should wait on - * PLLRDY flag to be set indicating that PLL clock is stable and can - * be used as system clock source. - * @note The main PLL can not be disabled if it is used as system clock source - * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. - * @param NewState: new state of the main PLL. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLLCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState; -} - -#if defined (STM32F40_41xxx) || defined (STM32F401xx) -/** - * @brief Configures the PLLI2S clock multiplication and division factors. - * - * @note This function can be used only for STM32F405xx/407xx, STM32F415xx/417xx - * or STM32F401xx devices. - * - * @note This function must be used only when the PLLI2S is disabled. - * @note PLLI2S clock source is common with the main PLL (configured in - * RCC_PLLConfig function ) - * - * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock - * This parameter must be a number between 192 and 432. - * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO - * output frequency is between 192 and 432 MHz. - * - * @param PLLI2SR: specifies the division factor for I2S clock - * This parameter must be a number between 2 and 7. - * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz - * on the I2S clock frequency. - * - * @retval None - */ -void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR) -{ - /* Check the parameters */ - assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN)); - assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR)); - - RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28); -} -#endif /* STM32F40_41xxx || STM32F401xx */ - -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) -/** - * @brief Configures the PLLI2S clock multiplication and division factors. - * - * @note This function can be used only for STM32F42xxx/43xxx devices - * - * @note This function must be used only when the PLLI2S is disabled. - * @note PLLI2S clock source is common with the main PLL (configured in - * RCC_PLLConfig function ) - * - * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock - * This parameter must be a number between 192 and 432. - * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO - * output frequency is between 192 and 432 MHz. - * - * @param PLLI2SQ: specifies the division factor for SAI1 clock - * This parameter must be a number between 2 and 15. - * - * @param PLLI2SR: specifies the division factor for I2S clock - * This parameter must be a number between 2 and 7. - * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz - * on the I2S clock frequency. - * @note the PLLI2SR parameter is only available with STM32F42xxx/43xxx devices. - * - * @retval None - */ -void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR) -{ - /* Check the parameters */ - assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN)); - assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SQ)); - assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR)); - - RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SQ << 24) | (PLLI2SR << 28); -} -#endif /* STM32F427_437xx || STM32F429_439xx */ - -/** - * @brief Enables or disables the PLLI2S. - * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. - * @param NewState: new state of the PLLI2S. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLLI2SCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_PLLI2SON_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the PLLSAI clock multiplication and division factors. - * - * @note This function can be used only for STM32F42xxx/43xxx devices - * - * @note This function must be used only when the PLLSAI is disabled. - * @note PLLSAI clock source is common with the main PLL (configured in - * RCC_PLLConfig function ) - * - * @param PLLSAIN: specifies the multiplication factor for PLLSAI VCO output clock - * This parameter must be a number between 192 and 432. - * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO - * output frequency is between 192 and 432 MHz. - * - * @param PLLSAIQ: specifies the division factor for SAI1 clock - * This parameter must be a number between 2 and 15. - * - * @param PLLSAIR: specifies the division factor for LTDC clock - * This parameter must be a number between 2 and 7. - * - * @retval None - */ -void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR) -{ - /* Check the parameters */ - assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIN)); - assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIR)); - - RCC->PLLSAICFGR = (PLLSAIN << 6) | (PLLSAIQ << 24) | (PLLSAIR << 28); -} - -/** - * @brief Enables or disables the PLLSAI. - * - * @note This function can be used only for STM32F42xxx/43xxx devices - * - * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. - * @param NewState: new state of the PLLSAI. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLLSAICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_PLLSAION_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the Clock Security System. - * @note If a failure is detected on the HSE oscillator clock, this oscillator - * is automatically disabled and an interrupt is generated to inform the - * software about the failure (Clock Security System Interrupt, CSSI), - * allowing the MCU to perform rescue operations. The CSSI is linked to - * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. - * @param NewState: new state of the Clock Security System. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_ClockSecuritySystemCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState; -} - -/** - * @brief Selects the clock source to output on MCO1 pin(PA8). - * @note PA8 should be configured in alternate function mode. - * @param RCC_MCO1Source: specifies the clock source to output. - * This parameter can be one of the following values: - * @arg RCC_MCO1Source_HSI: HSI clock selected as MCO1 source - * @arg RCC_MCO1Source_LSE: LSE clock selected as MCO1 source - * @arg RCC_MCO1Source_HSE: HSE clock selected as MCO1 source - * @arg RCC_MCO1Source_PLLCLK: main PLL clock selected as MCO1 source - * @param RCC_MCO1Div: specifies the MCO1 prescaler. - * This parameter can be one of the following values: - * @arg RCC_MCO1Div_1: no division applied to MCO1 clock - * @arg RCC_MCO1Div_2: division by 2 applied to MCO1 clock - * @arg RCC_MCO1Div_3: division by 3 applied to MCO1 clock - * @arg RCC_MCO1Div_4: division by 4 applied to MCO1 clock - * @arg RCC_MCO1Div_5: division by 5 applied to MCO1 clock - * @retval None - */ -void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_MCO1SOURCE(RCC_MCO1Source)); - assert_param(IS_RCC_MCO1DIV(RCC_MCO1Div)); - - tmpreg = RCC->CFGR; - - /* Clear MCO1[1:0] and MCO1PRE[2:0] bits */ - tmpreg &= CFGR_MCO1_RESET_MASK; - - /* Select MCO1 clock source and prescaler */ - tmpreg |= RCC_MCO1Source | RCC_MCO1Div; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Selects the clock source to output on MCO2 pin(PC9). - * @note PC9 should be configured in alternate function mode. - * @param RCC_MCO2Source: specifies the clock source to output. - * This parameter can be one of the following values: - * @arg RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source - * @arg RCC_MCO2Source_PLLI2SCLK: PLLI2S clock selected as MCO2 source - * @arg RCC_MCO2Source_HSE: HSE clock selected as MCO2 source - * @arg RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source - * @param RCC_MCO2Div: specifies the MCO2 prescaler. - * This parameter can be one of the following values: - * @arg RCC_MCO2Div_1: no division applied to MCO2 clock - * @arg RCC_MCO2Div_2: division by 2 applied to MCO2 clock - * @arg RCC_MCO2Div_3: division by 3 applied to MCO2 clock - * @arg RCC_MCO2Div_4: division by 4 applied to MCO2 clock - * @arg RCC_MCO2Div_5: division by 5 applied to MCO2 clock - * @retval None - */ -void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_MCO2SOURCE(RCC_MCO2Source)); - assert_param(IS_RCC_MCO2DIV(RCC_MCO2Div)); - - tmpreg = RCC->CFGR; - - /* Clear MCO2 and MCO2PRE[2:0] bits */ - tmpreg &= CFGR_MCO2_RESET_MASK; - - /* Select MCO2 clock source and prescaler */ - tmpreg |= RCC_MCO2Source | RCC_MCO2Div; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @} - */ - -/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions - * @brief System, AHB and APB busses clocks configuration functions - * -@verbatim - =============================================================================== - ##### System, AHB and APB busses clocks configuration functions ##### - =============================================================================== - [..] - This section provide functions allowing to configure the System, AHB, APB1 and - APB2 busses clocks. - - (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, - HSE and PLL. - The AHB clock (HCLK) is derived from System clock through configurable - prescaler and used to clock the CPU, memory and peripherals mapped - on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived - from AHB clock through configurable prescalers and used to clock - the peripherals mapped on these busses. You can use - "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks. - - -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: - (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or - from an external clock mapped on the I2S_CKIN pin. - You have to use RCC_I2SCLKConfig() function to configure this clock. - (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock - divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd() - functions to configure this clock. - (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz - to work correctly, while the SDIO require a frequency equal or lower than - to 48. This clock is derived of the main PLL through PLLQ divider. - (+@) IWDG clock which is always the LSI clock. - - (#) For STM32F405xx/407xx and STM32F415xx/417xx devices, the maximum frequency - of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz. Depending - on the device voltage range, the maximum frequency should be adapted accordingly: - +-------------------------------------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |---------------------------------------------------------------------| - | | voltage range | voltage range | voltage range | voltage range | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | - |---------------|----------------|----------------|-----------------|-----------------| - |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | - |---------------|----------------|----------------|-----------------|-----------------| - |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | - |---------------|----------------|----------------|-----------------|-----------------| - |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | - |---------------|----------------|----------------|-----------------|-----------------| - |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 | - |---------------|----------------|----------------|-----------------|-----------------| - |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 | - |---------------|----------------|----------------|-----------------|-----------------| - |5WS(6CPU cycle)|150< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120| - |---------------|----------------|----------------|-----------------|-----------------| - |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140| - |---------------|----------------|----------------|-----------------|-----------------| - |7WS(8CPU cycle)| NA | NA |154 < HCLK <= 168|140 < HCLK <= 160| - +---------------|----------------|----------------|-----------------|-----------------+ - (#) For STM32F42xxx/43xxx devices, the maximum frequency of the SYSCLK and HCLK is 180 MHz, - PCLK2 90 MHz and PCLK1 45 MHz. Depending on the device voltage range, the maximum - frequency should be adapted accordingly: - +-------------------------------------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |---------------------------------------------------------------------| - | | voltage range | voltage range | voltage range | voltage range | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | - |---------------|----------------|----------------|-----------------|-----------------| - |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | - |---------------|----------------|----------------|-----------------|-----------------| - |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | - |---------------|----------------|----------------|-----------------|-----------------| - |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | - |---------------|----------------|----------------|-----------------|-----------------| - |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 | - |---------------|----------------|----------------|-----------------|-----------------| - |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 | - |---------------|----------------|----------------|-----------------|-----------------| - |5WS(6CPU cycle)|120< HCLK <= 180|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120| - |---------------|----------------|----------------|-----------------|-----------------| - |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140| - |---------------|----------------|----------------|-----------------|-----------------| - |7WS(8CPU cycle)| NA |168< HCLK <= 180|154 < HCLK <= 176|140 < HCLK <= 160| - |---------------|----------------|----------------|-----------------|-----------------| - |8WS(9CPU cycle)| NA | NA |176 < HCLK <= 180|160 < HCLK <= 168| - +-------------------------------------------------------------------------------------+ - - (#) For STM32F401xx devices, the maximum frequency of the SYSCLK and HCLK is 84 MHz, - PCLK2 84 MHz and PCLK1 42 MHz. Depending on the device voltage range, the maximum - frequency should be adapted accordingly: - +-------------------------------------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |---------------------------------------------------------------------| - | | voltage range | voltage range | voltage range | voltage range | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | - |---------------|----------------|----------------|-----------------|-----------------| - |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | - |---------------|----------------|----------------|-----------------|-----------------| - |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | - |---------------|----------------|----------------|-----------------|-----------------| - |2WS(3CPU cycle)|60 < HCLK <= 84 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | - |---------------|----------------|----------------|-----------------|-----------------| - |3WS(4CPU cycle)| NA |72 < HCLK <= 84 |66 < HCLK <= 84 |60 < HCLK <= 80 | - |---------------|----------------|----------------|-----------------|-----------------| - |4WS(5CPU cycle)| NA | NA | NA |80 < HCLK <= 84 | - +-------------------------------------------------------------------------------------+ - - -@- On STM32F405xx/407xx and STM32F415xx/417xx devices: - (++) when VOS = '0', the maximum value of fHCLK = 144MHz. - (++) when VOS = '1', the maximum value of fHCLK = 168MHz. - [..] - On STM32F42xxx/43xxx devices: - (++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 120MHz. - (++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 144MHz. - (++) when VOS[1:0] = '0x11', the maximum value of f is 168MHz - [..] - On STM32F401x devices: - (++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 64MHz. - (++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 84MHz. - You can use PWR_MainRegulatorModeConfig() function to control VOS bits. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the system clock (SYSCLK). - * @note The HSI is used (enabled by hardware) as system clock source after - * startup from Reset, wake-up from STOP and STANDBY mode, or in case - * of failure of the HSE used directly or indirectly as system clock - * (if the Clock Security System CSS is enabled). - * @note A switch from one clock source to another occurs only if the target - * clock source is ready (clock stable after startup delay or PLL locked). - * If a clock source which is not yet ready is selected, the switch will - * occur when the clock source will be ready. - * You can use RCC_GetSYSCLKSource() function to know which clock is - * currently used as system clock source. - * @param RCC_SYSCLKSource: specifies the clock source used as system clock. - * This parameter can be one of the following values: - * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source - * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source - * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source - * @retval None - */ -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); - - tmpreg = RCC->CFGR; - - /* Clear SW[1:0] bits */ - tmpreg &= ~RCC_CFGR_SW; - - /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ - tmpreg |= RCC_SYSCLKSource; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Returns the clock source used as system clock. - * @param None - * @retval The clock source used as system clock. The returned value can be one - * of the following: - * - 0x00: HSI used as system clock - * - 0x04: HSE used as system clock - * - 0x08: PLL used as system clock - */ -uint8_t RCC_GetSYSCLKSource(void) -{ - return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS)); -} - -/** - * @brief Configures the AHB clock (HCLK). - * @note Depending on the device voltage range, the software has to set correctly - * these bits to ensure that HCLK not exceed the maximum allowed frequency - * (for more details refer to section above - * "CPU, AHB and APB busses clocks configuration functions") - * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from - * the system clock (SYSCLK). - * This parameter can be one of the following values: - * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK - * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 - * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 - * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 - * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 - * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 - * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 - * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 - * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 - * @retval None - */ -void RCC_HCLKConfig(uint32_t RCC_SYSCLK) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_HCLK(RCC_SYSCLK)); - - tmpreg = RCC->CFGR; - - /* Clear HPRE[3:0] bits */ - tmpreg &= ~RCC_CFGR_HPRE; - - /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ - tmpreg |= RCC_SYSCLK; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - - -/** - * @brief Configures the Low Speed APB clock (PCLK1). - * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from - * the AHB clock (HCLK). - * This parameter can be one of the following values: - * @arg RCC_HCLK_Div1: APB1 clock = HCLK - * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2 - * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4 - * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8 - * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16 - * @retval None - */ -void RCC_PCLK1Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PCLK(RCC_HCLK)); - - tmpreg = RCC->CFGR; - - /* Clear PPRE1[2:0] bits */ - tmpreg &= ~RCC_CFGR_PPRE1; - - /* Set PPRE1[2:0] bits according to RCC_HCLK value */ - tmpreg |= RCC_HCLK; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Configures the High Speed APB clock (PCLK2). - * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from - * the AHB clock (HCLK). - * This parameter can be one of the following values: - * @arg RCC_HCLK_Div1: APB2 clock = HCLK - * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2 - * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4 - * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8 - * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16 - * @retval None - */ -void RCC_PCLK2Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PCLK(RCC_HCLK)); - - tmpreg = RCC->CFGR; - - /* Clear PPRE2[2:0] bits */ - tmpreg &= ~RCC_CFGR_PPRE2; - - /* Set PPRE2[2:0] bits according to RCC_HCLK value */ - tmpreg |= RCC_HCLK << 3; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Returns the frequencies of different on chip clocks; SYSCLK, HCLK, - * PCLK1 and PCLK2. - * - * @note The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) - * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) - * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * @note (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * @note (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value - * 25 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * @note The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold - * the clocks frequencies. - * - * @note This function can be used by the user application to compute the - * baudrate for the communication peripherals or configure other parameters. - * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function - * must be called to update the structure's field. Otherwise, any - * configuration based on this function will be incorrect. - * - * @retval None - */ -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) -{ - uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock source */ - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock source */ - RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock source */ - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN - SYSCLK = PLL_VCO / PLLP - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; - pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - - if (pllsource != 0) - { - /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - else - { - /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - - pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; - RCC_Clocks->SYSCLK_Frequency = pllvco/pllp; - break; - default: - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - } - /* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/ - - /* Get HCLK prescaler */ - tmp = RCC->CFGR & RCC_CFGR_HPRE; - tmp = tmp >> 4; - presc = APBAHBPrescTable[tmp]; - /* HCLK clock frequency */ - RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; - - /* Get PCLK1 prescaler */ - tmp = RCC->CFGR & RCC_CFGR_PPRE1; - tmp = tmp >> 10; - presc = APBAHBPrescTable[tmp]; - /* PCLK1 clock frequency */ - RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; - - /* Get PCLK2 prescaler */ - tmp = RCC->CFGR & RCC_CFGR_PPRE2; - tmp = tmp >> 13; - presc = APBAHBPrescTable[tmp]; - /* PCLK2 clock frequency */ - RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; -} - -/** - * @} - */ - -/** @defgroup RCC_Group3 Peripheral clocks configuration functions - * @brief Peripheral clocks configuration functions - * -@verbatim - =============================================================================== - ##### Peripheral clocks configuration functions ##### - =============================================================================== - [..] This section provide functions allowing to configure the Peripheral clocks. - - (#) The RTC clock which is derived from the LSI, LSE or HSE clock divided - by 2 to 31. - - (#) After restart from Reset or wakeup from STANDBY, all peripherals are off - except internal SRAM, Flash and JTAG. Before to start using a peripheral - you have to enable its interface clock. You can do this using - RCC_AHBPeriphClockCmd(), RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions. - - (#) To reset the peripherals configuration (to the default state after device reset) - you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and - RCC_APB1PeriphResetCmd() functions. - - (#) To further reduce power consumption in SLEEP mode the peripheral clocks - can be disabled prior to executing the WFI or WFE instructions. - You can do this using RCC_AHBPeriphClockLPModeCmd(), - RCC_APB2PeriphClockLPModeCmd() and RCC_APB1PeriphClockLPModeCmd() functions. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the RTC clock (RTCCLK). - * @note As the RTC clock configuration bits are in the Backup domain and write - * access is denied to this domain after reset, you have to enable write - * access using PWR_BackupAccessCmd(ENABLE) function before to configure - * the RTC clock source (to be done once after reset). - * @note Once the RTC clock is configured it can't be changed unless the - * Backup domain is reset using RCC_BackupResetCmd() function, or by - * a Power On Reset (POR). - * - * @param RCC_RTCCLKSource: specifies the RTC clock source. - * This parameter can be one of the following values: - * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock - * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock - * @arg RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected - * as RTC clock, where x:[2,31] - * - * @note If the LSE or LSI is used as RTC clock source, the RTC continues to - * work in STOP and STANDBY modes, and can be used as wakeup source. - * However, when the HSE clock is used as RTC clock source, the RTC - * cannot be used in STOP and STANDBY modes. - * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as - * RTC clock source). - * - * @retval None - */ -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); - - if ((RCC_RTCCLKSource & 0x00000300) == 0x00000300) - { /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */ - tmpreg = RCC->CFGR; - - /* Clear RTCPRE[4:0] bits */ - tmpreg &= ~RCC_CFGR_RTCPRE; - - /* Configure HSE division factor for RTC clock */ - tmpreg |= (RCC_RTCCLKSource & 0xFFFFCFF); - - /* Store the new value */ - RCC->CFGR = tmpreg; - } - - /* Select the RTC clock source */ - RCC->BDCR |= (RCC_RTCCLKSource & 0x00000FFF); -} - -/** - * @brief Enables or disables the RTC clock. - * @note This function must be used only after the RTC clock source was selected - * using the RCC_RTCCLKConfig function. - * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_RTCCLKCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState; -} - -/** - * @brief Forces or releases the Backup domain reset. - * @note This function resets the RTC peripheral (including the backup registers) - * and the RTC clock source selection in RCC_CSR register. - * @note The BKPSRAM is not affected by this reset. - * @param NewState: new state of the Backup domain reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_BackupResetCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the I2S clock source (I2SCLK). - * @note This function must be called before enabling the I2S APB clock. - * @param RCC_I2SCLKSource: specifies the I2S clock source. - * This parameter can be one of the following values: - * @arg RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source - * @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin - * used as I2S clock source - * @retval None - */ -void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource)); - - *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource; -} - -/** - * @brief Configures the SAI clock Divider coming from PLLI2S. - * - * @note This function can be used only for STM32F42xxx/43xxx devices. - * - * @note This function must be called before enabling the PLLI2S. - * - * @param RCC_PLLI2SDivQ: specifies the PLLI2S division factor for SAI1 clock . - * This parameter must be a number between 1 and 32. - * SAI1 clock frequency = f(PLLI2S_Q) / RCC_PLLI2SDivQ - * - * @retval None - */ -void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(RCC_PLLI2SDivQ)); - - tmpreg = RCC->DCKCFGR; - - /* Clear PLLI2SDIVQ[4:0] bits */ - tmpreg &= ~(RCC_DCKCFGR_PLLI2SDIVQ); - - /* Set PLLI2SDIVQ values */ - tmpreg |= (RCC_PLLI2SDivQ - 1); - - /* Store the new value */ - RCC->DCKCFGR = tmpreg; -} - -/** - * @brief Configures the SAI clock Divider coming from PLLSAI. - * - * @note This function can be used only for STM32F42xxx/43xxx devices. - * - * @note This function must be called before enabling the PLLSAI. - * - * @param RCC_PLLSAIDivQ: specifies the PLLSAI division factor for SAI1 clock . - * This parameter must be a number between 1 and 32. - * SAI1 clock frequency = f(PLLSAI_Q) / RCC_PLLSAIDivQ - * - * @retval None - */ -void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(RCC_PLLSAIDivQ)); - - tmpreg = RCC->DCKCFGR; - - /* Clear PLLI2SDIVQ[4:0] and PLLSAIDIVQ[4:0] bits */ - tmpreg &= ~(RCC_DCKCFGR_PLLSAIDIVQ); - - /* Set PLLSAIDIVQ values */ - tmpreg |= ((RCC_PLLSAIDivQ - 1) << 8); - - /* Store the new value */ - RCC->DCKCFGR = tmpreg; -} - -/** - * @brief Configures SAI1BlockA clock source selection. - * - * @note This function can be used only for STM32F42xxx/43xxx devices. - * - * @note This function must be called before enabling PLLSAI, PLLI2S and - * the SAI clock. - * @param RCC_SAIBlockACLKSource: specifies the SAI Block A clock source. - * This parameter can be one of the following values: - * @arg RCC_SAIACLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used - * as SAI1 Block A clock - * @arg RCC_SAIACLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used - * as SAI1 Block A clock - * @arg RCC_SAIACLKSource_Ext: External clock mapped on the I2S_CKIN pin - * used as SAI1 Block A clock - * @retval None - */ -void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_SAIACLK_SOURCE(RCC_SAIBlockACLKSource)); - - tmpreg = RCC->DCKCFGR; - - /* Clear RCC_DCKCFGR_SAI1ASRC[1:0] bits */ - tmpreg &= ~RCC_DCKCFGR_SAI1ASRC; - - /* Set SAI Block A source selection value */ - tmpreg |= RCC_SAIBlockACLKSource; - - /* Store the new value */ - RCC->DCKCFGR = tmpreg; -} - -/** - * @brief Configures SAI1BlockB clock source selection. - * - * @note This function can be used only for STM32F42xxx/43xxx devices. - * - * @note This function must be called before enabling PLLSAI, PLLI2S and - * the SAI clock. - * @param RCC_SAIBlockBCLKSource: specifies the SAI Block B clock source. - * This parameter can be one of the following values: - * @arg RCC_SAIBCLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used - * as SAI1 Block B clock - * @arg RCC_SAIBCLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used - * as SAI1 Block B clock - * @arg RCC_SAIBCLKSource_Ext: External clock mapped on the I2S_CKIN pin - * used as SAI1 Block B clock - * @retval None - */ -void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_SAIBCLK_SOURCE(RCC_SAIBlockBCLKSource)); - - tmpreg = RCC->DCKCFGR; - - /* Clear RCC_DCKCFGR_SAI1BSRC[1:0] bits */ - tmpreg &= ~RCC_DCKCFGR_SAI1BSRC; - - /* Set SAI Block B source selection value */ - tmpreg |= RCC_SAIBlockBCLKSource; - - /* Store the new value */ - RCC->DCKCFGR = tmpreg; -} - - -/** - * @brief Configures the LTDC clock Divider coming from PLLSAI. - * - * @note The LTDC peripheral is only available with STM32F429xx/439xx Devices. - * - * @note This function must be called before enabling the PLLSAI. - * - * @param RCC_PLLSAIDivR: specifies the PLLSAI division factor for LTDC clock . - * This parameter must be a number between 2 and 16. - * LTDC clock frequency = f(PLLSAI_R) / RCC_PLLSAIDivR - * - * @retval None - */ -void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PLLSAI_DIVR_VALUE(RCC_PLLSAIDivR)); - - tmpreg = RCC->DCKCFGR; - - /* Clear PLLSAIDIVR[2:0] bits */ - tmpreg &= ~RCC_DCKCFGR_PLLSAIDIVR; - - /* Set PLLSAIDIVR values */ - tmpreg |= RCC_PLLSAIDivR; - - /* Store the new value */ - RCC->DCKCFGR = tmpreg; -} - -/** - * @brief Configures the Timers clocks prescalers selection. - * - * @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx devices. - * - * @param RCC_TIMCLKPrescaler : specifies the Timers clocks prescalers selection - * This parameter can be one of the following values: - * @arg RCC_TIMPrescDesactivated: The Timers kernels clocks prescaler is - * equal to HPRE if PPREx is corresponding to division by 1 or 2, - * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to - * division by 4 or more. - * - * @arg RCC_TIMPrescActivated: The Timers kernels clocks prescaler is - * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, - * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding - * to division by 8 or more. - * @retval None - */ -void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler) -{ - /* Check the parameters */ - assert_param(IS_RCC_TIMCLK_PRESCALER(RCC_TIMCLKPrescaler)); - - *(__IO uint32_t *) DCKCFGR_TIMPRE_BB = RCC_TIMCLKPrescaler; - -} - -/** - * @brief Enables or disables the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_AHB1Periph_GPIOA: GPIOA clock - * @arg RCC_AHB1Periph_GPIOB: GPIOB clock - * @arg RCC_AHB1Periph_GPIOC: GPIOC clock - * @arg RCC_AHB1Periph_GPIOD: GPIOD clock - * @arg RCC_AHB1Periph_GPIOE: GPIOE clock - * @arg RCC_AHB1Periph_GPIOF: GPIOF clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOI: GPIOI clock - * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices) - * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices) - * @arg RCC_AHB1Periph_CRC: CRC clock - * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock - * @arg RCC_AHB1Periph_CCMDATARAMEN CCM data RAM interface clock - * @arg RCC_AHB1Periph_DMA1: DMA1 clock - * @arg RCC_AHB1Periph_DMA2: DMA2 clock - * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices) - * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock - * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock - * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock - * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock - * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock - * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB1_CLOCK_PERIPH(RCC_AHB1Periph)); - - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->AHB1ENR |= RCC_AHB1Periph; - } - else - { - RCC->AHB1ENR &= ~RCC_AHB1Periph; - } -} - -/** - * @brief Enables or disables the AHB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_AHB2Periph_DCMI: DCMI clock - * @arg RCC_AHB2Periph_CRYP: CRYP clock - * @arg RCC_AHB2Periph_HASH: HASH clock - * @arg RCC_AHB2Periph_RNG: RNG clock - * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHB2ENR |= RCC_AHB2Periph; - } - else - { - RCC->AHB2ENR &= ~RCC_AHB2Periph; - } -} - -/** - * @brief Enables or disables the AHB3 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock. - * This parameter must be: RCC_AHB3Periph_FSMC - * or RCC_AHB3Periph_FMC (STM32F42xxx/43xxx devices) - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHB3ENR |= RCC_AHB3Periph; - } - else - { - RCC->AHB3ENR &= ~RCC_AHB3Periph; - } -} - -/** - * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2: TIM2 clock - * @arg RCC_APB1Periph_TIM3: TIM3 clock - * @arg RCC_APB1Periph_TIM4: TIM4 clock - * @arg RCC_APB1Periph_TIM5: TIM5 clock - * @arg RCC_APB1Periph_TIM6: TIM6 clock - * @arg RCC_APB1Periph_TIM7: TIM7 clock - * @arg RCC_APB1Periph_TIM12: TIM12 clock - * @arg RCC_APB1Periph_TIM13: TIM13 clock - * @arg RCC_APB1Periph_TIM14: TIM14 clock - * @arg RCC_APB1Periph_WWDG: WWDG clock - * @arg RCC_APB1Periph_SPI2: SPI2 clock - * @arg RCC_APB1Periph_SPI3: SPI3 clock - * @arg RCC_APB1Periph_USART2: USART2 clock - * @arg RCC_APB1Periph_USART3: USART3 clock - * @arg RCC_APB1Periph_UART4: UART4 clock - * @arg RCC_APB1Periph_UART5: UART5 clock - * @arg RCC_APB1Periph_I2C1: I2C1 clock - * @arg RCC_APB1Periph_I2C2: I2C2 clock - * @arg RCC_APB1Periph_I2C3: I2C3 clock - * @arg RCC_APB1Periph_CAN1: CAN1 clock - * @arg RCC_APB1Periph_CAN2: CAN2 clock - * @arg RCC_APB1Periph_PWR: PWR clock - * @arg RCC_APB1Periph_DAC: DAC clock - * @arg RCC_APB1Periph_UART7: UART7 clock - * @arg RCC_APB1Periph_UART8: UART8 clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->APB1ENR |= RCC_APB1Periph; - } - else - { - RCC->APB1ENR &= ~RCC_APB1Periph; - } -} - -/** - * @brief Enables or disables the High Speed APB (APB2) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_TIM1: TIM1 clock - * @arg RCC_APB2Periph_TIM8: TIM8 clock - * @arg RCC_APB2Periph_USART1: USART1 clock - * @arg RCC_APB2Periph_USART6: USART6 clock - * @arg RCC_APB2Periph_ADC1: ADC1 clock - * @arg RCC_APB2Periph_ADC2: ADC2 clock - * @arg RCC_APB2Periph_ADC3: ADC3 clock - * @arg RCC_APB2Periph_SDIO: SDIO clock - * @arg RCC_APB2Periph_SPI1: SPI1 clock - * @arg RCC_APB2Periph_SPI4: SPI4 clock - * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock - * @arg RCC_APB2Periph_TIM9: TIM9 clock - * @arg RCC_APB2Periph_TIM10: TIM10 clock - * @arg RCC_APB2Periph_TIM11: TIM11 clock - * @arg RCC_APB2Periph_SPI5: SPI5 clock - * @arg RCC_APB2Periph_SPI6: SPI6 clock - * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx devices) - * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices) - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->APB2ENR |= RCC_APB2Periph; - } - else - { - RCC->APB2ENR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Forces or releases AHB1 peripheral reset. - * @param RCC_AHB1Periph: specifies the AHB1 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_AHB1Periph_GPIOA: GPIOA clock - * @arg RCC_AHB1Periph_GPIOB: GPIOB clock - * @arg RCC_AHB1Periph_GPIOC: GPIOC clock - * @arg RCC_AHB1Periph_GPIOD: GPIOD clock - * @arg RCC_AHB1Periph_GPIOE: GPIOE clock - * @arg RCC_AHB1Periph_GPIOF: GPIOF clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOI: GPIOI clock - * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices) - * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxxdevices) - * @arg RCC_AHB1Periph_CRC: CRC clock - * @arg RCC_AHB1Periph_DMA1: DMA1 clock - * @arg RCC_AHB1Periph_DMA2: DMA2 clock - * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices) - * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock - * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock - * - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB1_RESET_PERIPH(RCC_AHB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHB1RSTR |= RCC_AHB1Periph; - } - else - { - RCC->AHB1RSTR &= ~RCC_AHB1Periph; - } -} - -/** - * @brief Forces or releases AHB2 peripheral reset. - * @param RCC_AHB2Periph: specifies the AHB2 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_AHB2Periph_DCMI: DCMI clock - * @arg RCC_AHB2Periph_CRYP: CRYP clock - * @arg RCC_AHB2Periph_HASH: HASH clock - * @arg RCC_AHB2Periph_RNG: RNG clock - * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHB2RSTR |= RCC_AHB2Periph; - } - else - { - RCC->AHB2RSTR &= ~RCC_AHB2Periph; - } -} - -/** - * @brief Forces or releases AHB3 peripheral reset. - * @param RCC_AHB3Periph: specifies the AHB3 peripheral to reset. - * This parameter must be: RCC_AHB3Periph_FSMC - * or RCC_AHB3Periph_FMC (STM32F42xxx/43xxx devices) - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHB3RSTR |= RCC_AHB3Periph; - } - else - { - RCC->AHB3RSTR &= ~RCC_AHB3Periph; - } -} - -/** - * @brief Forces or releases Low Speed APB (APB1) peripheral reset. - * @param RCC_APB1Periph: specifies the APB1 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2: TIM2 clock - * @arg RCC_APB1Periph_TIM3: TIM3 clock - * @arg RCC_APB1Periph_TIM4: TIM4 clock - * @arg RCC_APB1Periph_TIM5: TIM5 clock - * @arg RCC_APB1Periph_TIM6: TIM6 clock - * @arg RCC_APB1Periph_TIM7: TIM7 clock - * @arg RCC_APB1Periph_TIM12: TIM12 clock - * @arg RCC_APB1Periph_TIM13: TIM13 clock - * @arg RCC_APB1Periph_TIM14: TIM14 clock - * @arg RCC_APB1Periph_WWDG: WWDG clock - * @arg RCC_APB1Periph_SPI2: SPI2 clock - * @arg RCC_APB1Periph_SPI3: SPI3 clock - * @arg RCC_APB1Periph_USART2: USART2 clock - * @arg RCC_APB1Periph_USART3: USART3 clock - * @arg RCC_APB1Periph_UART4: UART4 clock - * @arg RCC_APB1Periph_UART5: UART5 clock - * @arg RCC_APB1Periph_I2C1: I2C1 clock - * @arg RCC_APB1Periph_I2C2: I2C2 clock - * @arg RCC_APB1Periph_I2C3: I2C3 clock - * @arg RCC_APB1Periph_CAN1: CAN1 clock - * @arg RCC_APB1Periph_CAN2: CAN2 clock - * @arg RCC_APB1Periph_PWR: PWR clock - * @arg RCC_APB1Periph_DAC: DAC clock - * @arg RCC_APB1Periph_UART7: UART7 clock - * @arg RCC_APB1Periph_UART8: UART8 clock - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB1RSTR |= RCC_APB1Periph; - } - else - { - RCC->APB1RSTR &= ~RCC_APB1Periph; - } -} - -/** - * @brief Forces or releases High Speed APB (APB2) peripheral reset. - * @param RCC_APB2Periph: specifies the APB2 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_TIM1: TIM1 clock - * @arg RCC_APB2Periph_TIM8: TIM8 clock - * @arg RCC_APB2Periph_USART1: USART1 clock - * @arg RCC_APB2Periph_USART6: USART6 clock - * @arg RCC_APB2Periph_ADC1: ADC1 clock - * @arg RCC_APB2Periph_ADC2: ADC2 clock - * @arg RCC_APB2Periph_ADC3: ADC3 clock - * @arg RCC_APB2Periph_SDIO: SDIO clock - * @arg RCC_APB2Periph_SPI1: SPI1 clock - * @arg RCC_APB2Periph_SPI4: SPI4 clock - * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock - * @arg RCC_APB2Periph_TIM9: TIM9 clock - * @arg RCC_APB2Periph_TIM10: TIM10 clock - * @arg RCC_APB2Periph_TIM11: TIM11 clock - * @arg RCC_APB2Periph_SPI5: SPI5 clock - * @arg RCC_APB2Periph_SPI6: SPI6 clock - * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx devices) - * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices) - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_RESET_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB2RSTR |= RCC_APB2Periph; - } - else - { - RCC->APB2RSTR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_AHB1Periph_GPIOA: GPIOA clock - * @arg RCC_AHB1Periph_GPIOB: GPIOB clock - * @arg RCC_AHB1Periph_GPIOC: GPIOC clock - * @arg RCC_AHB1Periph_GPIOD: GPIOD clock - * @arg RCC_AHB1Periph_GPIOE: GPIOE clock - * @arg RCC_AHB1Periph_GPIOF: GPIOF clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOI: GPIOI clock - * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices) - * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices) - * @arg RCC_AHB1Periph_CRC: CRC clock - * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock - * @arg RCC_AHB1Periph_DMA1: DMA1 clock - * @arg RCC_AHB1Periph_DMA2: DMA2 clock - * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices) - * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock - * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock - * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock - * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock - * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock - * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB1_LPMODE_PERIPH(RCC_AHB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->AHB1LPENR |= RCC_AHB1Periph; - } - else - { - RCC->AHB1LPENR &= ~RCC_AHB1Periph; - } -} - -/** - * @brief Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_AHB2Periph_DCMI: DCMI clock - * @arg RCC_AHB2Periph_CRYP: CRYP clock - * @arg RCC_AHB2Periph_HASH: HASH clock - * @arg RCC_AHB2Periph_RNG: RNG clock - * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->AHB2LPENR |= RCC_AHB2Periph; - } - else - { - RCC->AHB2LPENR &= ~RCC_AHB2Periph; - } -} - -/** - * @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock. - * This parameter must be: RCC_AHB3Periph_FSMC - * or RCC_AHB3Periph_FMC (STM32F429x/439x devices) - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->AHB3LPENR |= RCC_AHB3Periph; - } - else - { - RCC->AHB3LPENR &= ~RCC_AHB3Periph; - } -} - -/** - * @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2: TIM2 clock - * @arg RCC_APB1Periph_TIM3: TIM3 clock - * @arg RCC_APB1Periph_TIM4: TIM4 clock - * @arg RCC_APB1Periph_TIM5: TIM5 clock - * @arg RCC_APB1Periph_TIM6: TIM6 clock - * @arg RCC_APB1Periph_TIM7: TIM7 clock - * @arg RCC_APB1Periph_TIM12: TIM12 clock - * @arg RCC_APB1Periph_TIM13: TIM13 clock - * @arg RCC_APB1Periph_TIM14: TIM14 clock - * @arg RCC_APB1Periph_WWDG: WWDG clock - * @arg RCC_APB1Periph_SPI2: SPI2 clock - * @arg RCC_APB1Periph_SPI3: SPI3 clock - * @arg RCC_APB1Periph_USART2: USART2 clock - * @arg RCC_APB1Periph_USART3: USART3 clock - * @arg RCC_APB1Periph_UART4: UART4 clock - * @arg RCC_APB1Periph_UART5: UART5 clock - * @arg RCC_APB1Periph_I2C1: I2C1 clock - * @arg RCC_APB1Periph_I2C2: I2C2 clock - * @arg RCC_APB1Periph_I2C3: I2C3 clock - * @arg RCC_APB1Periph_CAN1: CAN1 clock - * @arg RCC_APB1Periph_CAN2: CAN2 clock - * @arg RCC_APB1Periph_PWR: PWR clock - * @arg RCC_APB1Periph_DAC: DAC clock - * @arg RCC_APB1Periph_UART7: UART7 clock - * @arg RCC_APB1Periph_UART8: UART8 clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB1LPENR |= RCC_APB1Periph; - } - else - { - RCC->APB1LPENR &= ~RCC_APB1Periph; - } -} - -/** - * @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_TIM1: TIM1 clock - * @arg RCC_APB2Periph_TIM8: TIM8 clock - * @arg RCC_APB2Periph_USART1: USART1 clock - * @arg RCC_APB2Periph_USART6: USART6 clock - * @arg RCC_APB2Periph_ADC1: ADC1 clock - * @arg RCC_APB2Periph_ADC2: ADC2 clock - * @arg RCC_APB2Periph_ADC3: ADC3 clock - * @arg RCC_APB2Periph_SDIO: SDIO clock - * @arg RCC_APB2Periph_SPI1: SPI1 clock - * @arg RCC_APB2Periph_SPI4: SPI4 clock - * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock - * @arg RCC_APB2Periph_TIM9: TIM9 clock - * @arg RCC_APB2Periph_TIM10: TIM10 clock - * @arg RCC_APB2Periph_TIM11: TIM11 clock - * @arg RCC_APB2Periph_SPI5: SPI5 clock - * @arg RCC_APB2Periph_SPI6: SPI6 clock - * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx devices) - * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices) - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB2LPENR |= RCC_APB2Periph; - } - else - { - RCC->APB2LPENR &= ~RCC_APB2Periph; - } -} - -/** - * @} - */ - -/** @defgroup RCC_Group4 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified RCC interrupts. - * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: main PLL ready interrupt - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt - * @arg RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx devices) - * @param NewState: new state of the specified RCC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_IT(RCC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts */ - *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT; - } - else - { - /* Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts */ - *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; - } -} - -/** - * @brief Checks whether the specified RCC flag is set or not. - * @param RCC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready - * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready - * @arg RCC_FLAG_PLLRDY: main PLL clock ready - * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready - * @arg RCC_FLAG_PLLSAIRDY: PLLSAI clock ready (only for STM32F42xxx/43xxx devices) - * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready - * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready - * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset - * @arg RCC_FLAG_PINRST: Pin reset - * @arg RCC_FLAG_PORRST: POR/PDR reset - * @arg RCC_FLAG_SFTRST: Software reset - * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset - * @arg RCC_FLAG_WWDGRST: Window Watchdog reset - * @arg RCC_FLAG_LPWRRST: Low Power reset - * @retval The new state of RCC_FLAG (SET or RESET). - */ -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) -{ - uint32_t tmp = 0; - uint32_t statusreg = 0; - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_RCC_FLAG(RCC_FLAG)); - - /* Get the RCC register index */ - tmp = RCC_FLAG >> 5; - if (tmp == 1) /* The flag to check is in CR register */ - { - statusreg = RCC->CR; - } - else if (tmp == 2) /* The flag to check is in BDCR register */ - { - statusreg = RCC->BDCR; - } - else /* The flag to check is in CSR register */ - { - statusreg = RCC->CSR; - } - - /* Get the flag position */ - tmp = RCC_FLAG & FLAG_MASK; - if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the RCC reset flags. - * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, - * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST - * @param None - * @retval None - */ -void RCC_ClearFlag(void) -{ - /* Set RMVF bit to clear the reset flags */ - RCC->CSR |= RCC_CSR_RMVF; -} - -/** - * @brief Checks whether the specified RCC interrupt has occurred or not. - * @param RCC_IT: specifies the RCC interrupt source to check. - * This parameter can be one of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: main PLL ready interrupt - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt - * @arg RCC_IT_PLLSAIRDY: PLLSAI clock ready interrupt (only for STM32F42xxx/43xxx devices) - * @arg RCC_IT_CSS: Clock Security System interrupt - * @retval The new state of RCC_IT (SET or RESET). - */ -ITStatus RCC_GetITStatus(uint8_t RCC_IT) -{ - ITStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_RCC_GET_IT(RCC_IT)); - - /* Check the status of the specified RCC interrupt */ - if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the RCC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the RCC's interrupt pending bits. - * @param RCC_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: main PLL ready interrupt - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt - * @arg RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx devices) - * @arg RCC_IT_CSS: Clock Security System interrupt - * @retval None - */ -void RCC_ClearITPendingBit(uint8_t RCC_IT) -{ - /* Check the parameters */ - assert_param(IS_RCC_CLEAR_IT(RCC_IT)); - - /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt - pending bits */ - *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm32f4xx_rcc.h b/stm/stmperiph/stm32f4xx_rcc.h deleted file mode 100644 index 6abb55160..000000000 --- a/stm/stmperiph/stm32f4xx_rcc.h +++ /dev/null @@ -1,615 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_rcc.h - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief This file contains all the functions prototypes for the RCC firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_RCC_H -#define __STM32F4xx_RCC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RCC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -typedef struct -{ - uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */ - uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */ - uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */ - uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */ -}RCC_ClocksTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup RCC_Exported_Constants - * @{ - */ - -/** @defgroup RCC_HSE_configuration - * @{ - */ -#define RCC_HSE_OFF ((uint8_t)0x00) -#define RCC_HSE_ON ((uint8_t)0x01) -#define RCC_HSE_Bypass ((uint8_t)0x05) -#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ - ((HSE) == RCC_HSE_Bypass)) -/** - * @} - */ - -/** @defgroup RCC_PLL_Clock_Source - * @{ - */ -#define RCC_PLLSource_HSI ((uint32_t)0x00000000) -#define RCC_PLLSource_HSE ((uint32_t)0x00400000) -#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \ - ((SOURCE) == RCC_PLLSource_HSE)) -#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63) -#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) -#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) -#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15)) - -#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) -#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) - -#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) -#define IS_RCC_PLLSAIN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) -#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) -#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) - -#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) -#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) - -#define RCC_PLLSAIDivR_Div2 ((uint32_t)0x00000000) -#define RCC_PLLSAIDivR_Div4 ((uint32_t)0x00010000) -#define RCC_PLLSAIDivR_Div8 ((uint32_t)0x00020000) -#define RCC_PLLSAIDivR_Div16 ((uint32_t)0x00030000) -#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDivR_Div2) ||\ - ((VALUE) == RCC_PLLSAIDivR_Div4) ||\ - ((VALUE) == RCC_PLLSAIDivR_Div8) ||\ - ((VALUE) == RCC_PLLSAIDivR_Div16)) - -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Source - * @{ - */ -#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) -#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) -#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) -#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ - ((SOURCE) == RCC_SYSCLKSource_HSE) || \ - ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) -/** - * @} - */ - -/** @defgroup RCC_AHB_Clock_Source - * @{ - */ -#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) -#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) -#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) -#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) -#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) -#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) -#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) -#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) -#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) -#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ - ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ - ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ - ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ - ((HCLK) == RCC_SYSCLK_Div512)) -/** - * @} - */ - -/** @defgroup RCC_APB1_APB2_Clock_Source - * @{ - */ -#define RCC_HCLK_Div1 ((uint32_t)0x00000000) -#define RCC_HCLK_Div2 ((uint32_t)0x00001000) -#define RCC_HCLK_Div4 ((uint32_t)0x00001400) -#define RCC_HCLK_Div8 ((uint32_t)0x00001800) -#define RCC_HCLK_Div16 ((uint32_t)0x00001C00) -#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ - ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ - ((PCLK) == RCC_HCLK_Div16)) -/** - * @} - */ - -/** @defgroup RCC_Interrupt_Source - * @{ - */ -#define RCC_IT_LSIRDY ((uint8_t)0x01) -#define RCC_IT_LSERDY ((uint8_t)0x02) -#define RCC_IT_HSIRDY ((uint8_t)0x04) -#define RCC_IT_HSERDY ((uint8_t)0x08) -#define RCC_IT_PLLRDY ((uint8_t)0x10) -#define RCC_IT_PLLI2SRDY ((uint8_t)0x20) -#define RCC_IT_PLLSAIRDY ((uint8_t)0x40) -#define RCC_IT_CSS ((uint8_t)0x80) - -#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) -#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ - ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ - ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ - ((IT) == RCC_IT_PLLSAIRDY) || ((IT) == RCC_IT_PLLI2SRDY)) -#define IS_RCC_CLEAR_IT(IT)((IT) != 0x00) - -/** - * @} - */ - -/** @defgroup RCC_LSE_Configuration - * @{ - */ -#define RCC_LSE_OFF ((uint8_t)0x00) -#define RCC_LSE_ON ((uint8_t)0x01) -#define RCC_LSE_Bypass ((uint8_t)0x04) -#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ - ((LSE) == RCC_LSE_Bypass)) -/** - * @} - */ - -/** @defgroup RCC_RTC_Clock_Source - * @{ - */ -#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) -#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) -#define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300) -#define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300) -#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300) -#define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300) -#define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300) -#define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300) -#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300) -#define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300) -#define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300) -#define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300) -#define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300) -#define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300) -#define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300) -#define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300) -#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300) -#define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300) -#define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300) -#define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300) -#define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300) -#define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300) -#define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300) -#define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300) -#define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300) -#define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300) -#define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300) -#define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300) -#define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300) -#define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300) -#define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300) -#define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300) -#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ - ((SOURCE) == RCC_RTCCLKSource_LSI) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div31)) -/** - * @} - */ - -/** @defgroup RCC_I2S_Clock_Source - * @{ - */ -#define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00) -#define RCC_I2S2CLKSource_Ext ((uint8_t)0x01) - -#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext)) -/** - * @} - */ - -/** @defgroup RCC_SAI_BlockA_Clock_Source - * @{ - */ -#define RCC_SAIACLKSource_PLLSAI ((uint32_t)0x00000000) -#define RCC_SAIACLKSource_PLLI2S ((uint32_t)0x00100000) -#define RCC_SAIACLKSource_Ext ((uint32_t)0x00200000) - -#define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S) ||\ - ((SOURCE) == RCC_SAIACLKSource_PLLSAI) ||\ - ((SOURCE) == RCC_SAIACLKSource_Ext)) -/** - * @} - */ - -/** @defgroup RCC_SAI_BlockB_Clock_Source - * @{ - */ -#define RCC_SAIBCLKSource_PLLSAI ((uint32_t)0x00000000) -#define RCC_SAIBCLKSource_PLLI2S ((uint32_t)0x00400000) -#define RCC_SAIBCLKSource_Ext ((uint32_t)0x00800000) - -#define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S) ||\ - ((SOURCE) == RCC_SAIBCLKSource_PLLSAI) ||\ - ((SOURCE) == RCC_SAIBCLKSource_Ext)) -/** - * @} - */ - -/** @defgroup RCC_TIM_PRescaler_Selection - * @{ - */ -#define RCC_TIMPrescDesactivated ((uint8_t)0x00) -#define RCC_TIMPrescActivated ((uint8_t)0x01) - -#define IS_RCC_TIMCLK_PRESCALER(VALUE) (((VALUE) == RCC_TIMPrescDesactivated) || ((VALUE) == RCC_TIMPrescActivated)) -/** - * @} - */ - -/** @defgroup RCC_AHB1_Peripherals - * @{ - */ -#define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001) -#define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002) -#define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004) -#define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008) -#define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010) -#define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020) -#define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040) -#define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080) -#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100) -#define RCC_AHB1Periph_GPIOJ ((uint32_t)0x00000200) -#define RCC_AHB1Periph_GPIOK ((uint32_t)0x00000400) -#define RCC_AHB1Periph_CRC ((uint32_t)0x00001000) -#define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000) -#define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000) -#define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000) -#define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000) -#define RCC_AHB1Periph_SRAM3 ((uint32_t)0x00080000) -#define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000) -#define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000) -#define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000) -#define RCC_AHB1Periph_DMA2D ((uint32_t)0x00800000) -#define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000) -#define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000) -#define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000) -#define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000) -#define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000) -#define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000) - -#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x810BE800) == 0x00) && ((PERIPH) != 0x00)) -#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD1FE800) == 0x00) && ((PERIPH) != 0x00)) -#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81106800) == 0x00) && ((PERIPH) != 0x00)) - -/** - * @} - */ - -/** @defgroup RCC_AHB2_Peripherals - * @{ - */ -#define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001) -#define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010) -#define RCC_AHB2Periph_HASH ((uint32_t)0x00000020) -#define RCC_AHB2Periph_RNG ((uint32_t)0x00000040) -#define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080) -#define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup RCC_AHB3_Peripherals - * @{ - */ -#if defined (STM32F40_41xxx) -#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001) -#endif /* STM32F40_41xxx */ - -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) -#define RCC_AHB3Periph_FMC ((uint32_t)0x00000001) -#endif /* STM32F427_437xx || STM32F429_439xx */ - -#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup RCC_APB1_Peripherals - * @{ - */ -#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) -#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) -#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) -#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) -#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) -#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) -#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) -#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) -#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) -#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) -#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) -#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) -#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) -#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) -#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) -#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) -#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) -#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) -#define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000) -#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) -#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) -#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) -#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) -#define RCC_APB1Periph_UART7 ((uint32_t)0x40000000) -#define RCC_APB1Periph_UART8 ((uint32_t)0x80000000) -#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x09013600) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup RCC_APB2_Peripherals - * @{ - */ -#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001) -#define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002) -#define RCC_APB2Periph_USART1 ((uint32_t)0x00000010) -#define RCC_APB2Periph_USART6 ((uint32_t)0x00000020) -#define RCC_APB2Periph_ADC ((uint32_t)0x00000100) -#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100) -#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200) -#define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400) -#define RCC_APB2Periph_SDIO ((uint32_t)0x00000800) -#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) -#define RCC_APB2Periph_SPI4 ((uint32_t)0x00002000) -#define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000) -#define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000) -#define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000) -#define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000) -#define RCC_APB2Periph_SPI5 ((uint32_t)0x00100000) -#define RCC_APB2Periph_SPI6 ((uint32_t)0x00200000) -#define RCC_APB2Periph_SAI1 ((uint32_t)0x00400000) -#define RCC_APB2Periph_LTDC ((uint32_t)0x04000000) - -#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFB8880CC) == 0x00) && ((PERIPH) != 0x00)) -#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFB8886CC) == 0x00) && ((PERIPH) != 0x00)) - -/** - * @} - */ - -/** @defgroup RCC_MCO1_Clock_Source_Prescaler - * @{ - */ -#define RCC_MCO1Source_HSI ((uint32_t)0x00000000) -#define RCC_MCO1Source_LSE ((uint32_t)0x00200000) -#define RCC_MCO1Source_HSE ((uint32_t)0x00400000) -#define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000) -#define RCC_MCO1Div_1 ((uint32_t)0x00000000) -#define RCC_MCO1Div_2 ((uint32_t)0x04000000) -#define RCC_MCO1Div_3 ((uint32_t)0x05000000) -#define RCC_MCO1Div_4 ((uint32_t)0x06000000) -#define RCC_MCO1Div_5 ((uint32_t)0x07000000) -#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \ - ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK)) - -#define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \ - ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \ - ((DIV) == RCC_MCO1Div_5)) -/** - * @} - */ - -/** @defgroup RCC_MCO2_Clock_Source_Prescaler - * @{ - */ -#define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000) -#define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000) -#define RCC_MCO2Source_HSE ((uint32_t)0x80000000) -#define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000) -#define RCC_MCO2Div_1 ((uint32_t)0x00000000) -#define RCC_MCO2Div_2 ((uint32_t)0x20000000) -#define RCC_MCO2Div_3 ((uint32_t)0x28000000) -#define RCC_MCO2Div_4 ((uint32_t)0x30000000) -#define RCC_MCO2Div_5 ((uint32_t)0x38000000) -#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \ - ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK)) - -#define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \ - ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \ - ((DIV) == RCC_MCO2Div_5)) -/** - * @} - */ - -/** @defgroup RCC_Flag - * @{ - */ -#define RCC_FLAG_HSIRDY ((uint8_t)0x21) -#define RCC_FLAG_HSERDY ((uint8_t)0x31) -#define RCC_FLAG_PLLRDY ((uint8_t)0x39) -#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B) -#define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3D) -#define RCC_FLAG_LSERDY ((uint8_t)0x41) -#define RCC_FLAG_LSIRDY ((uint8_t)0x61) -#define RCC_FLAG_BORRST ((uint8_t)0x79) -#define RCC_FLAG_PINRST ((uint8_t)0x7A) -#define RCC_FLAG_PORRST ((uint8_t)0x7B) -#define RCC_FLAG_SFTRST ((uint8_t)0x7C) -#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) -#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) -#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) - -#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ - ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ - ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \ - ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ - ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \ - ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST)|| \ - ((FLAG) == RCC_FLAG_PLLI2SRDY)|| ((FLAG) == RCC_FLAG_PLLSAIRDY)) - -#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the RCC clock configuration to the default reset state */ -void RCC_DeInit(void); - -/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ -void RCC_HSEConfig(uint8_t RCC_HSE); -ErrorStatus RCC_WaitForHSEStartUp(void); -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); -void RCC_HSICmd(FunctionalState NewState); -void RCC_LSEConfig(uint8_t RCC_LSE); -void RCC_LSICmd(FunctionalState NewState); -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ); -void RCC_PLLCmd(FunctionalState NewState); - -#if defined (STM32F40_41xxx) || defined (STM32F401xx) -void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR); -#endif /* STM32F40_41xxx || STM32F401xx */ - -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) -void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR); -#endif /* STM32F41_43xxx */ - -void RCC_PLLI2SCmd(FunctionalState NewState); -void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR); -void RCC_PLLSAICmd(FunctionalState NewState); -void RCC_ClockSecuritySystemCmd(FunctionalState NewState); -void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div); -void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div); - -/* System, AHB and APB busses clocks configuration functions ******************/ -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); -uint8_t RCC_GetSYSCLKSource(void); -void RCC_HCLKConfig(uint32_t RCC_SYSCLK); -void RCC_PCLK1Config(uint32_t RCC_HCLK); -void RCC_PCLK2Config(uint32_t RCC_HCLK); -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); - -/* Peripheral clocks configuration functions **********************************/ -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); -void RCC_RTCCLKCmd(FunctionalState NewState); -void RCC_BackupResetCmd(FunctionalState NewState); -void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource); -void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ); -void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ); -void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource); -void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource); -void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR); -void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler); - -void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); -void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); -void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); - -void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); -void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); -void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); - -void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); -void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); -void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); -void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); -void RCC_ClearFlag(void); -ITStatus RCC_GetITStatus(uint8_t RCC_IT); -void RCC_ClearITPendingBit(uint8_t RCC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_RCC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm32f4xx_rng.c b/stm/stmperiph/stm32f4xx_rng.c deleted file mode 100644 index 4746dd6bd..000000000 --- a/stm/stmperiph/stm32f4xx_rng.c +++ /dev/null @@ -1,397 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_rng.c - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief This file provides firmware functions to manage the following - * functionalities of the Random Number Generator (RNG) peripheral: - * + Initialization and Configuration - * + Get 32 bit Random number - * + Interrupts and flags management - * -@verbatim - - =================================================================== - ##### How to use this driver ##### - =================================================================== - [..] - (#) Enable The RNG controller clock using - RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_RNG, ENABLE) function. - - (#) Activate the RNG peripheral using RNG_Cmd() function. - - (#) Wait until the 32 bit Random number Generator contains a valid random data - (using polling/interrupt mode). For more details, refer to "Interrupts and - flags management functions" module description. - - (#) Get the 32 bit Random number using RNG_GetRandomNumber() function - - (#) To get another 32 bit Random number, go to step 3. - - -@endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_rng.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup RNG - * @brief RNG driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RNG_Private_Functions - * @{ - */ - -/** @defgroup RNG_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to - (+) Initialize the RNG peripheral - (+) Enable or disable the RNG peripheral - -@endverbatim - * @{ - */ - -/** - * @brief De-initializes the RNG peripheral registers to their default reset values. - * @param None - * @retval None - */ -void RNG_DeInit(void) -{ - /* Enable RNG reset state */ - RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, ENABLE); - - /* Release RNG from reset state */ - RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, DISABLE); -} - -/** - * @brief Enables or disables the RNG peripheral. - * @param NewState: new state of the RNG peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RNG_Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the RNG */ - RNG->CR |= RNG_CR_RNGEN; - } - else - { - /* Disable the RNG */ - RNG->CR &= ~RNG_CR_RNGEN; - } -} -/** - * @} - */ - -/** @defgroup RNG_Group2 Get 32 bit Random number function - * @brief Get 32 bit Random number function - * - -@verbatim - =============================================================================== - ##### Get 32 bit Random number function ##### - =============================================================================== - [..] This section provides a function allowing to get the 32 bit Random number - - (@) Before to call this function you have to wait till DRDY flag is set, - using RNG_GetFlagStatus(RNG_FLAG_DRDY) function. - -@endverbatim - * @{ - */ - - -/** - * @brief Returns a 32-bit random number. - * - * @note Before to call this function you have to wait till DRDY (data ready) - * flag is set, using RNG_GetFlagStatus(RNG_FLAG_DRDY) function. - * @note Each time the the Random number data is read (using RNG_GetRandomNumber() - * function), the RNG_FLAG_DRDY flag is automatically cleared. - * @note In the case of a seed error, the generation of random numbers is - * interrupted for as long as the SECS bit is '1'. If a number is - * available in the RNG_DR register, it must not be used because it may - * not have enough entropy. In this case, it is recommended to clear the - * SEIS bit(using RNG_ClearFlag(RNG_FLAG_SECS) function), then disable - * and enable the RNG peripheral (using RNG_Cmd() function) to - * reinitialize and restart the RNG. - * @note In the case of a clock error, the RNG is no more able to generate - * random numbers because the PLL48CLK clock is not correct. User have - * to check that the clock controller is correctly configured to provide - * the RNG clock and clear the CEIS bit (using RNG_ClearFlag(RNG_FLAG_CECS) - * function) . The clock error has no impact on the previously generated - * random numbers, and the RNG_DR register contents can be used. - * - * @param None - * @retval 32-bit random number. - */ -uint32_t RNG_GetRandomNumber(void) -{ - /* Return the 32 bit random number from the DR register */ - return RNG->DR; -} - - -/** - * @} - */ - -/** @defgroup RNG_Group3 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure the RNG Interrupts and - to get the status and clear flags and Interrupts pending bits. - - [..] The RNG provides 3 Interrupts sources and 3 Flags: - - *** Flags : *** - =============== - [..] - (#) RNG_FLAG_DRDY : In the case of the RNG_DR register contains valid - random data. it is cleared by reading the valid data(using - RNG_GetRandomNumber() function). - - (#) RNG_FLAG_CECS : In the case of a seed error detection. - - (#) RNG_FLAG_SECS : In the case of a clock error detection. - - *** Interrupts *** - ================== - [..] If enabled, an RNG interrupt is pending : - - (#) In the case of the RNG_DR register contains valid random data. - This interrupt source is cleared once the RNG_DR register has been read - (using RNG_GetRandomNumber() function) until a new valid value is - computed; or - (#) In the case of a seed error : One of the following faulty sequences has - been detected: - (++) More than 64 consecutive bits at the same value (0 or 1) - (++) More than 32 consecutive alternance of 0 and 1 (0101010101...01) - This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_SEI) - function; or - (#) In the case of a clock error : the PLL48CLK (RNG peripheral clock source) - was not correctly detected (fPLL48CLK< fHCLK/16). This interrupt source is - cleared using RNG_ClearITPendingBit(RNG_IT_CEI) function. - -@- note In this case, User have to check that the clock controller is - correctly configured to provide the RNG clock. - - *** Managing the RNG controller events : *** - ============================================ - [..] The user should identify which mode will be used in his application to manage - the RNG controller events: Polling mode or Interrupt mode. - - (#) In the Polling Mode it is advised to use the following functions: - (++) RNG_GetFlagStatus() : to check if flags events occur. - (++) RNG_ClearFlag() : to clear the flags events. - - -@@- RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag(). it is cleared only - by reading the Random number data. - - (#) In the Interrupt Mode it is advised to use the following functions: - (++) RNG_ITConfig() : to enable or disable the interrupt source. - (++) RNG_GetITStatus() : to check if Interrupt occurs. - (++) RNG_ClearITPendingBit() : to clear the Interrupt pending Bit - (corresponding Flag). - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the RNG interrupt. - * @note The RNG provides 3 interrupt sources, - * - Computed data is ready event (DRDY), and - * - Seed error Interrupt (SEI) and - * - Clock error Interrupt (CEI), - * all these interrupts sources are enabled by setting the IE bit in - * CR register. However, each interrupt have its specific status bit - * (see RNG_GetITStatus() function) and clear bit except the DRDY event - * (see RNG_ClearITPendingBit() function). - * @param NewState: new state of the RNG interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RNG_ITConfig(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the RNG interrupt */ - RNG->CR |= RNG_CR_IE; - } - else - { - /* Disable the RNG interrupt */ - RNG->CR &= ~RNG_CR_IE; - } -} - -/** - * @brief Checks whether the specified RNG flag is set or not. - * @param RNG_FLAG: specifies the RNG flag to check. - * This parameter can be one of the following values: - * @arg RNG_FLAG_DRDY: Data Ready flag. - * @arg RNG_FLAG_CECS: Clock Error Current flag. - * @arg RNG_FLAG_SECS: Seed Error Current flag. - * @retval The new state of RNG_FLAG (SET or RESET). - */ -FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_RNG_GET_FLAG(RNG_FLAG)); - - /* Check the status of the specified RNG flag */ - if ((RNG->SR & RNG_FLAG) != (uint8_t)RESET) - { - /* RNG_FLAG is set */ - bitstatus = SET; - } - else - { - /* RNG_FLAG is reset */ - bitstatus = RESET; - } - /* Return the RNG_FLAG status */ - return bitstatus; -} - - -/** - * @brief Clears the RNG flags. - * @param RNG_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg RNG_FLAG_CECS: Clock Error Current flag. - * @arg RNG_FLAG_SECS: Seed Error Current flag. - * @note RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag() function. - * This flag is cleared only by reading the Random number data (using - * RNG_GetRandomNumber() function). - * @retval None - */ -void RNG_ClearFlag(uint8_t RNG_FLAG) -{ - /* Check the parameters */ - assert_param(IS_RNG_CLEAR_FLAG(RNG_FLAG)); - /* Clear the selected RNG flags */ - RNG->SR = ~(uint32_t)(((uint32_t)RNG_FLAG) << 4); -} - -/** - * @brief Checks whether the specified RNG interrupt has occurred or not. - * @param RNG_IT: specifies the RNG interrupt source to check. - * This parameter can be one of the following values: - * @arg RNG_IT_CEI: Clock Error Interrupt. - * @arg RNG_IT_SEI: Seed Error Interrupt. - * @retval The new state of RNG_IT (SET or RESET). - */ -ITStatus RNG_GetITStatus(uint8_t RNG_IT) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_RNG_GET_IT(RNG_IT)); - - /* Check the status of the specified RNG interrupt */ - if ((RNG->SR & RNG_IT) != (uint8_t)RESET) - { - /* RNG_IT is set */ - bitstatus = SET; - } - else - { - /* RNG_IT is reset */ - bitstatus = RESET; - } - /* Return the RNG_IT status */ - return bitstatus; -} - - -/** - * @brief Clears the RNG interrupt pending bit(s). - * @param RNG_IT: specifies the RNG interrupt pending bit(s) to clear. - * This parameter can be any combination of the following values: - * @arg RNG_IT_CEI: Clock Error Interrupt. - * @arg RNG_IT_SEI: Seed Error Interrupt. - * @retval None - */ -void RNG_ClearITPendingBit(uint8_t RNG_IT) -{ - /* Check the parameters */ - assert_param(IS_RNG_IT(RNG_IT)); - - /* Clear the selected RNG interrupt pending bit */ - RNG->SR = (uint8_t)~RNG_IT; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm32f4xx_rng.h b/stm/stmperiph/stm32f4xx_rng.h deleted file mode 100644 index 874c9bab5..000000000 --- a/stm/stmperiph/stm32f4xx_rng.h +++ /dev/null @@ -1,120 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_rng.h - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief This file contains all the functions prototypes for the Random - * Number Generator(RNG) firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_RNG_H -#define __STM32F4xx_RNG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RNG - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup RNG_Exported_Constants - * @{ - */ - -/** @defgroup RNG_flags_definition - * @{ - */ -#define RNG_FLAG_DRDY ((uint8_t)0x0001) /*!< Data ready */ -#define RNG_FLAG_CECS ((uint8_t)0x0002) /*!< Clock error current status */ -#define RNG_FLAG_SECS ((uint8_t)0x0004) /*!< Seed error current status */ - -#define IS_RNG_GET_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_DRDY) || \ - ((RNG_FLAG) == RNG_FLAG_CECS) || \ - ((RNG_FLAG) == RNG_FLAG_SECS)) -#define IS_RNG_CLEAR_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_CECS) || \ - ((RNG_FLAG) == RNG_FLAG_SECS)) -/** - * @} - */ - -/** @defgroup RNG_interrupts_definition - * @{ - */ -#define RNG_IT_CEI ((uint8_t)0x20) /*!< Clock error interrupt */ -#define RNG_IT_SEI ((uint8_t)0x40) /*!< Seed error interrupt */ - -#define IS_RNG_IT(IT) ((((IT) & (uint8_t)0x9F) == 0x00) && ((IT) != 0x00)) -#define IS_RNG_GET_IT(RNG_IT) (((RNG_IT) == RNG_IT_CEI) || ((RNG_IT) == RNG_IT_SEI)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the RNG configuration to the default reset state *****/ -void RNG_DeInit(void); - -/* Configuration function *****************************************************/ -void RNG_Cmd(FunctionalState NewState); - -/* Get 32 bit Random number function ******************************************/ -uint32_t RNG_GetRandomNumber(void); - -/* Interrupts and flags management functions **********************************/ -void RNG_ITConfig(FunctionalState NewState); -FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG); -void RNG_ClearFlag(uint8_t RNG_FLAG); -ITStatus RNG_GetITStatus(uint8_t RNG_IT); -void RNG_ClearITPendingBit(uint8_t RNG_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_RNG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm32f4xx_rtc.c b/stm/stmperiph/stm32f4xx_rtc.c deleted file mode 100644 index 5d96db5a3..000000000 --- a/stm/stmperiph/stm32f4xx_rtc.c +++ /dev/null @@ -1,2761 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_rtc.c - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief This file provides firmware functions to manage the following - * functionalities of the Real-Time Clock (RTC) peripheral: - * + Initialization - * + Calendar (Time and Date) configuration - * + Alarms (Alarm A and Alarm B) configuration - * + WakeUp Timer configuration - * + Daylight Saving configuration - * + Output pin Configuration - * + Coarse digital Calibration configuration - * + Smooth digital Calibration configuration - * + TimeStamp configuration - * + Tampers configuration - * + Backup Data Registers configuration - * + Shift control synchronisation - * + RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration - * + Interrupts and flags management - * -@verbatim - - =================================================================== - ##### Backup Domain Operating Condition ##### - =================================================================== - [..] The real-time clock (RTC), the RTC backup registers, and the backup - SRAM (BKP SRAM) can be powered from the VBAT voltage when the main - VDD supply is powered off. - To retain the content of the RTC backup registers, backup SRAM, and supply - the RTC when VDD is turned off, VBAT pin can be connected to an optional - standby voltage supplied by a battery or by another source. - - [..] To allow the RTC to operate even when the main digital supply (VDD) is turned - off, the VBAT pin powers the following blocks: - (#) The RTC - (#) The LSE oscillator - (#) The backup SRAM when the low power backup regulator is enabled - (#) PC13 to PC15 I/Os, plus PI8 I/O (when available) - - [..] When the backup domain is supplied by VDD (analog switch connected to VDD), - the following functions are available: - (#) PC14 and PC15 can be used as either GPIO or LSE pins - (#) PC13 can be used as a GPIO or as the RTC_AF1 pin - (#) PI8 can be used as a GPIO or as the RTC_AF2 pin - - [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT - because VDD is not present), the following functions are available: - (#) PC14 and PC15 can be used as LSE pins only - (#) PC13 can be used as the RTC_AF1 pin - (#) PI8 can be used as the RTC_AF2 pin - - - ##### Backup Domain Reset ##### - =================================================================== - [..] The backup domain reset sets all RTC registers and the RCC_BDCR register - to their reset values. The BKPSRAM is not affected by this reset. The only - way of resetting the BKPSRAM is through the Flash interface by requesting - a protection level change from 1 to 0. - [..] A backup domain reset is generated when one of the following events occurs: - (#) Software reset, triggered by setting the BDRST bit in the - RCC Backup domain control register (RCC_BDCR). You can use the - RCC_BackupResetCmd(). - (#) VDD or VBAT power on, if both supplies have previously been powered off. - - - ##### Backup Domain Access ##### - =================================================================== - [..] After reset, the backup domain (RTC registers, RTC backup data - registers and backup SRAM) is protected against possible unwanted write - accesses. - [..] To enable access to the RTC Domain and RTC registers, proceed as follows: - (+) Enable the Power Controller (PWR) APB1 interface clock using the - RCC_APB1PeriphClockCmd() function. - (+) Enable access to RTC domain using the PWR_BackupAccessCmd() function. - (+) Select the RTC clock source using the RCC_RTCCLKConfig() function. - (+) Enable RTC Clock using the RCC_RTCCLKCmd() function. - - - ##### How to use RTC Driver ##### - =================================================================== - [..] - (+) Enable the RTC domain access (see description in the section above) - (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour - format using the RTC_Init() function. - - *** Time and Date configuration *** - =================================== - [..] - (+) To configure the RTC Calendar (Time and Date) use the RTC_SetTime() - and RTC_SetDate() functions. - (+) To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate() functions. - (+) Use the RTC_DayLightSavingConfig() function to add or sub one - hour to the RTC Calendar. - - *** Alarm configuration *** - =========================== - [..] - (+) To configure the RTC Alarm use the RTC_SetAlarm() function. - (+) Enable the selected RTC Alarm using the RTC_AlarmCmd() function - (+) To read the RTC Alarm, use the RTC_GetAlarm() function. - (+) To read the RTC alarm SubSecond, use the RTC_GetAlarmSubSecond() function. - - *** RTC Wakeup configuration *** - ================================ - [..] - (+) Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig() - function. - (+) Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter() function - (+) Enable the RTC WakeUp using the RTC_WakeUpCmd() function - (+) To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter() - function. - - *** Outputs configuration *** - ============================= - [..] The RTC has 2 different outputs: - (+) AFO_ALARM: this output is used to manage the RTC Alarm A, Alarm B - and WaKeUp signals. To output the selected RTC signal on RTC_AF1 pin, use the - RTC_OutputConfig() function. - (+) AFO_CALIB: this output is 512Hz signal or 1Hz. To output the RTC Clock on - RTC_AF1 pin, use the RTC_CalibOutputCmd() function. - - *** Smooth digital Calibration configuration *** - ================================================ - [..] - (+) Configure the RTC Original Digital Calibration Value and the corresponding - calibration cycle period (32s,16s and 8s) using the RTC_SmoothCalibConfig() - function. - - *** Coarse digital Calibration configuration *** - ================================================ - [..] - (+) Configure the RTC Coarse Calibration Value and the corresponding - sign using the RTC_CoarseCalibConfig() function. - (+) Enable the RTC Coarse Calibration using the RTC_CoarseCalibCmd() function - - *** TimeStamp configuration *** - =============================== - [..] - (+) Configure the RTC_AF1 trigger and enables the RTC TimeStamp using the RTC - _TimeStampCmd() function. - (+) To read the RTC TimeStamp Time and Date register, use the RTC_GetTimeStamp() - function. - (+) To read the RTC TimeStamp SubSecond register, use the - RTC_GetTimeStampSubSecond() function. - (+) The TAMPER1 alternate function can be mapped either to RTC_AF1(PC13) - or RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in - RTC_TAFCR register. You can use the RTC_TamperPinSelection() function to - select the corresponding pin. - - *** Tamper configuration *** - ============================ - [..] - (+) Enable the RTC Tamper using the RTC_TamperCmd() function. - (+) Configure the Tamper filter count using RTC_TamperFilterConfig() - function. - (+) Configure the RTC Tamper trigger Edge or Level according to the Tamper - filter (if equal to 0 Edge else Level) value using the RTC_TamperConfig() - function. - (+) Configure the Tamper sampling frequency using RTC_TamperSamplingFreqConfig() - function. - (+) Configure the Tamper precharge or discharge duration using - RTC_TamperPinsPrechargeDuration() function. - (+) Enable the Tamper Pull-UP using RTC_TamperPullUpDisableCmd() function. - (+) Enable the Time stamp on Tamper detection event using - TC_TSOnTamperDetecCmd() function. - (+) The TIMESTAMP alternate function can be mapped to either RTC_AF1 - or RTC_AF2 depending on the value of the TSINSEL bit in the RTC_TAFCR - register. You can use the RTC_TimeStampPinSelection() function to select - the corresponding pin. - - *** Backup Data Registers configuration *** - =========================================== - [..] - (+) To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister() - function. - (+) To read the RTC Backup Data registers, use the RTC_ReadBackupRegister() - function. - - - ##### RTC and low power modes ##### - =================================================================== - [..] The MCU can be woken up from a low power mode by an RTC alternate - function. - [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), - RTC wakeup, RTC tamper event detection and RTC time stamp event detection. - These RTC alternate functions can wake up the system from the Stop and - Standby lowpower modes. - [..] The system can also wake up from low power modes without depending - on an external interrupt (Auto-wakeup mode), by using the RTC alarm - or the RTC wakeup events. - [..] The RTC provides a programmable time base for waking up from the - Stop or Standby mode at regular intervals. - Wakeup from STOP and Standby modes is possible only when the RTC clock source - is LSE or LSI. - - - ##### Selection of RTC_AF1 alternate functions ##### - =================================================================== - [..] The RTC_AF1 pin (PC13) can be used for the following purposes: - (+) AFO_ALARM output - (+) AFO_CALIB output - (+) AFI_TAMPER - (+) AFI_TIMESTAMP - - [..] - +-------------------------------------------------------------------------------------------------------------+ - | Pin |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE | - | configuration | ENABLED | ENABLED | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM | - | and function | | | | | selection | selection |Configuration | - |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - | Alarm out | | | | | Don't | Don't | | - | output OD | 1 |Don't care|Don't care | Don't care | care | care | 0 | - |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - | Alarm out | | | | | Don't | Don't | | - | output PP | 1 |Don't care|Don't care | Don't care | care | care | 1 | - |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - | Calibration out | | | | | Don't | Don't | | - | output PP | 0 | 1 |Don't care | Don't care | care | care | Don't care | - |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - | TAMPER input | | | | | | Don't | | - | floating | 0 | 0 | 1 | 0 | 0 | care | Don't care | - |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - | TIMESTAMP and | | | | | | | | - | TAMPER input | 0 | 0 | 1 | 1 | 0 | 0 | Don't care | - | floating | | | | | | | | - |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - | TIMESTAMP input | | | | | Don't | | | - | floating | 0 | 0 | 0 | 1 | care | 0 | Don't care | - |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - | Standard GPIO | 0 | 0 | 0 | 0 | Don't care | Don't care | Don't care | - +-------------------------------------------------------------------------------------------------------------+ - - - ##### Selection of RTC_AF2 alternate functions ##### - =================================================================== - [..] The RTC_AF2 pin (PI8) can be used for the following purposes: - (+) AFI_TAMPER - (+) AFI_TIMESTAMP - [..] - +---------------------------------------------------------------------------------------+ - | Pin |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE | - | configuration | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM | - | and function | | | selection | selection |Configuration | - |-----------------|-----------|--------------|------------|--------------|--------------| - | TAMPER input | | | | Don't | | - | floating | 1 | 0 | 1 | care | Don't care | - |-----------------|-----------|--------------|------------|--------------|--------------| - | TIMESTAMP and | | | | | | - | TAMPER input | 1 | 1 | 1 | 1 | Don't care | - | floating | | | | | | - |-----------------|-----------|--------------|------------|--------------|--------------| - | TIMESTAMP input | | | Don't | | | - | floating | 0 | 1 | care | 1 | Don't care | - |-----------------|-----------|--------------|------------|--------------|--------------| - | Standard GPIO | 0 | 0 | Don't care | Don't care | Don't care | - +---------------------------------------------------------------------------------------+ - - -@endverbatim - - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_rtc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup RTC - * @brief RTC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* Masks Definition */ -#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F) -#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F) -#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) -#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F) -#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \ - RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \ - RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \ - RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \ - RTC_FLAG_RECALPF | RTC_FLAG_SHPF)) - -#define INITMODE_TIMEOUT ((uint32_t) 0x00010000) -#define SYNCHRO_TIMEOUT ((uint32_t) 0x00020000) -#define RECALPF_TIMEOUT ((uint32_t) 0x00020000) -#define SHPF_TIMEOUT ((uint32_t) 0x00001000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static uint8_t RTC_ByteToBcd2(uint8_t Value); -static uint8_t RTC_Bcd2ToByte(uint8_t Value); - -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RTC_Private_Functions - * @{ - */ - -/** @defgroup RTC_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - - [..] This section provide functions allowing to initialize and configure the RTC - Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers - Write protection, enter and exit the RTC initialization mode, RTC registers - synchronization check and reference clock detection enable. - - (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. It is - split into 2 programmable prescalers to minimize power consumption. - (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler. - (++) When both prescalers are used, it is recommended to configure the - asynchronous prescaler to a high value to minimize consumption. - - (#) All RTC registers are Write protected. Writing to the RTC registers - is enabled by writing a key into the Write Protection register, RTC_WPR. - - (#) To Configure the RTC Calendar, user application should enter initialization - mode. In this mode, the calendar counter is stopped and its value can be - updated. When the initialization sequence is complete, the calendar restarts - counting after 4 RTCCLK cycles. - - (#) To read the calendar through the shadow registers after Calendar initialization, - calendar update or after wakeup from low power modes the software must first - clear the RSF flag. The software must then wait until it is set again before - reading the calendar, which means that the calendar registers have been - correctly copied into the RTC_TR and RTC_DR shadow registers. - The RTC_WaitForSynchro() function implements the above software sequence - (RSF clear and RSF check). - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the RTC registers to their default reset values. - * @note This function doesn't reset the RTC Clock source and RTC Backup Data - * registers. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC registers are deinitialized - * - ERROR: RTC registers are not deinitialized - */ -ErrorStatus RTC_DeInit(void) -{ - __IO uint32_t wutcounter = 0x00; - uint32_t wutwfstatus = 0x00; - ErrorStatus status = ERROR; - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Reset TR, DR and CR registers */ - RTC->TR = (uint32_t)0x00000000; - RTC->DR = (uint32_t)0x00002101; - /* Reset All CR bits except CR[2:0] */ - RTC->CR &= (uint32_t)0x00000007; - - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - do - { - wutwfstatus = RTC->ISR & RTC_ISR_WUTWF; - wutcounter++; - } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); - - if ((RTC->ISR & RTC_ISR_WUTWF) == RESET) - { - status = ERROR; - } - else - { - /* Reset all RTC CR register bits */ - RTC->CR &= (uint32_t)0x00000000; - RTC->WUTR = (uint32_t)0x0000FFFF; - RTC->PRER = (uint32_t)0x007F00FF; - RTC->CALIBR = (uint32_t)0x00000000; - RTC->ALRMAR = (uint32_t)0x00000000; - RTC->ALRMBR = (uint32_t)0x00000000; - RTC->SHIFTR = (uint32_t)0x00000000; - RTC->CALR = (uint32_t)0x00000000; - RTC->ALRMASSR = (uint32_t)0x00000000; - RTC->ALRMBSSR = (uint32_t)0x00000000; - - /* Reset ISR register and exit initialization mode */ - RTC->ISR = (uint32_t)0x00000000; - - /* Reset Tamper and alternate functions configuration register */ - RTC->TAFCR = 0x00000000; - - if(RTC_WaitForSynchro() == ERROR) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Initializes the RTC registers according to the specified parameters - * in RTC_InitStruct. - * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains - * the configuration information for the RTC peripheral. - * @note The RTC Prescaler register is write protected and can be written in - * initialization mode only. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC registers are initialized - * - ERROR: RTC registers are not initialized - */ -ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat)); - assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv)); - assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Clear RTC CR FMT Bit */ - RTC->CR &= ((uint32_t)~(RTC_CR_FMT)); - /* Set RTC_CR register */ - RTC->CR |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat)); - - /* Configure the RTC PRER */ - RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv); - RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16); - - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - status = SUCCESS; - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Fills each RTC_InitStruct member with its default value. - * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be - * initialized. - * @retval None - */ -void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct) -{ - /* Initialize the RTC_HourFormat member */ - RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24; - - /* Initialize the RTC_AsynchPrediv member */ - RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F; - - /* Initialize the RTC_SynchPrediv member */ - RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF; -} - -/** - * @brief Enables or disables the RTC registers write protection. - * @note All the RTC registers are write protected except for RTC_ISR[13:8], - * RTC_TAFCR and RTC_BKPxR. - * @note Writing a wrong key reactivates the write protection. - * @note The protection mechanism is not affected by system reset. - * @param NewState: new state of the write protection. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_WriteProtectionCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - } - else - { - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - } -} - -/** - * @brief Enters the RTC Initialization mode. - * @note The RTC Initialization mode is write protected, use the - * RTC_WriteProtectionCmd(DISABLE) before calling this function. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC is in Init mode - * - ERROR: RTC is not in Init mode - */ -ErrorStatus RTC_EnterInitMode(void) -{ - __IO uint32_t initcounter = 0x00; - ErrorStatus status = ERROR; - uint32_t initstatus = 0x00; - - /* Check if the Initialization mode is set */ - if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET) - { - /* Set the Initialization mode */ - RTC->ISR = (uint32_t)RTC_INIT_MASK; - - /* Wait till RTC is in INIT state and if Time out is reached exit */ - do - { - initstatus = RTC->ISR & RTC_ISR_INITF; - initcounter++; - } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00)); - - if ((RTC->ISR & RTC_ISR_INITF) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - } - else - { - status = SUCCESS; - } - - return (status); -} - -/** - * @brief Exits the RTC Initialization mode. - * @note When the initialization sequence is complete, the calendar restarts - * counting after 4 RTCCLK cycles. - * @note The RTC Initialization mode is write protected, use the - * RTC_WriteProtectionCmd(DISABLE) before calling this function. - * @param None - * @retval None - */ -void RTC_ExitInitMode(void) -{ - /* Exit Initialization mode */ - RTC->ISR &= (uint32_t)~RTC_ISR_INIT; -} - -/** - * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are - * synchronized with RTC APB clock. - * @note The RTC Resynchronization mode is write protected, use the - * RTC_WriteProtectionCmd(DISABLE) before calling this function. - * @note To read the calendar through the shadow registers after Calendar - * initialization, calendar update or after wakeup from low power modes - * the software must first clear the RSF flag. - * The software must then wait until it is set again before reading - * the calendar, which means that the calendar registers have been - * correctly copied into the RTC_TR and RTC_DR shadow registers. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC registers are synchronised - * - ERROR: RTC registers are not synchronised - */ -ErrorStatus RTC_WaitForSynchro(void) -{ - __IO uint32_t synchrocounter = 0; - ErrorStatus status = ERROR; - uint32_t synchrostatus = 0x00; - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear RSF flag */ - RTC->ISR &= (uint32_t)RTC_RSF_MASK; - - /* Wait the registers to be synchronised */ - do - { - synchrostatus = RTC->ISR & RTC_ISR_RSF; - synchrocounter++; - } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00)); - - if ((RTC->ISR & RTC_ISR_RSF) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return (status); -} - -/** - * @brief Enables or disables the RTC reference clock detection. - * @param NewState: new state of the RTC reference clock. - * This parameter can be: ENABLE or DISABLE. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC reference clock detection is enabled - * - ERROR: RTC reference clock detection is disabled - */ -ErrorStatus RTC_RefClockCmd(FunctionalState NewState) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - if (NewState != DISABLE) - { - /* Enable the RTC reference clock detection */ - RTC->CR |= RTC_CR_REFCKON; - } - else - { - /* Disable the RTC reference clock detection */ - RTC->CR &= ~RTC_CR_REFCKON; - } - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - status = SUCCESS; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Enables or Disables the Bypass Shadow feature. - * @note When the Bypass Shadow is enabled the calendar value are taken - * directly from the Calendar counter. - * @param NewState: new state of the Bypass Shadow feature. - * This parameter can be: ENABLE or DISABLE. - * @retval None -*/ -void RTC_BypassShadowCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - if (NewState != DISABLE) - { - /* Set the BYPSHAD bit */ - RTC->CR |= (uint8_t)RTC_CR_BYPSHAD; - } - else - { - /* Reset the BYPSHAD bit */ - RTC->CR &= (uint8_t)~RTC_CR_BYPSHAD; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @} - */ - -/** @defgroup RTC_Group2 Time and Date configuration functions - * @brief Time and Date configuration functions - * -@verbatim - =============================================================================== - ##### Time and Date configuration functions ##### - =============================================================================== - - [..] This section provide functions allowing to program and read the RTC Calendar - (Time and Date). - -@endverbatim - * @{ - */ - -/** - * @brief Set the RTC current time. - * @param RTC_Format: specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains - * the time configuration information for the RTC. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Time register is configured - * - ERROR: RTC Time register is not configured - */ -ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) -{ - uint32_t tmpreg = 0; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - if (RTC_Format == RTC_Format_BIN) - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours)); - assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); - } - else - { - RTC_TimeStruct->RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours)); - } - assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes)); - assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds)); - } - else - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours); - assert_param(IS_RTC_HOUR12(tmpreg)); - assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); - } - else - { - RTC_TimeStruct->RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours))); - } - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds))); - } - - /* Check the input parameters format */ - if (RTC_Format != RTC_Format_BIN) - { - tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \ - ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \ - ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \ - ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16)); - } - else - { - tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \ - (((uint32_t)RTC_TimeStruct->RTC_H12) << 16)); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Set the RTC_TR register */ - RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); - - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if ((RTC->CR & RTC_CR_BYPSHAD) == RESET) - { - if(RTC_WaitForSynchro() == ERROR) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - else - { - status = SUCCESS; - } - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Fills each RTC_TimeStruct member with its default value - * (Time = 00h:00min:00sec). - * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be - * initialized. - * @retval None - */ -void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct) -{ - /* Time = 00h:00min:00sec */ - RTC_TimeStruct->RTC_H12 = RTC_H12_AM; - RTC_TimeStruct->RTC_Hours = 0; - RTC_TimeStruct->RTC_Minutes = 0; - RTC_TimeStruct->RTC_Seconds = 0; -} - -/** - * @brief Get the RTC current Time. - * @param RTC_Format: specifies the format of the returned parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will - * contain the returned current time configuration. - * @retval None - */ -void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - /* Get the RTC_TR register */ - tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); - - /* Fill the structure fields with the read parameters */ - RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16); - RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8); - RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU)); - RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); - - /* Check the input parameters format */ - if (RTC_Format == RTC_Format_BIN) - { - /* Convert the structure parameters to Binary format */ - RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours); - RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes); - RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds); - } -} - -/** - * @brief Gets the RTC current Calendar Sub seconds value. - * @note This function freeze the Time and Date registers after reading the - * SSR register. - * @param None - * @retval RTC current Calendar Sub seconds value. - */ -uint32_t RTC_GetSubSecond(void) -{ - uint32_t tmpreg = 0; - - /* Get sub seconds values from the correspondent registers*/ - tmpreg = (uint32_t)(RTC->SSR); - - /* Read DR register to unfroze calendar registers */ - (void) (RTC->DR); - - return (tmpreg); -} - -/** - * @brief Set the RTC current date. - * @param RTC_Format: specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains - * the date configuration information for the RTC. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Date register is configured - * - ERROR: RTC Date register is not configured - */ -ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) -{ - uint32_t tmpreg = 0; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10)) - { - RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A; - } - if (RTC_Format == RTC_Format_BIN) - { - assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year)); - assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month)); - assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date)); - } - else - { - assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year))); - tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month); - assert_param(IS_RTC_MONTH(tmpreg)); - tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date); - assert_param(IS_RTC_DATE(tmpreg)); - } - assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay)); - - /* Check the input parameters format */ - if (RTC_Format != RTC_Format_BIN) - { - tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \ - (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \ - ((uint32_t)RTC_DateStruct->RTC_Date) | \ - (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13)); - } - else - { - tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \ - ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13)); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Set the RTC_DR register */ - RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK); - - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if ((RTC->CR & RTC_CR_BYPSHAD) == RESET) - { - if(RTC_WaitForSynchro() == ERROR) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - else - { - status = SUCCESS; - } - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Fills each RTC_DateStruct member with its default value - * (Monday, January 01 xx00). - * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be - * initialized. - * @retval None - */ -void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct) -{ - /* Monday, January 01 xx00 */ - RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday; - RTC_DateStruct->RTC_Date = 1; - RTC_DateStruct->RTC_Month = RTC_Month_January; - RTC_DateStruct->RTC_Year = 0; -} - -/** - * @brief Get the RTC current date. - * @param RTC_Format: specifies the format of the returned parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will - * contain the returned current date configuration. - * @retval None - */ -void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - /* Get the RTC_TR register */ - tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK); - - /* Fill the structure fields with the read parameters */ - RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16); - RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8); - RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU)); - RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13); - - /* Check the input parameters format */ - if (RTC_Format == RTC_Format_BIN) - { - /* Convert the structure parameters to Binary format */ - RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year); - RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month); - RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date); - } -} - -/** - * @} - */ - -/** @defgroup RTC_Group3 Alarms configuration functions - * @brief Alarms (Alarm A and Alarm B) configuration functions - * -@verbatim - =============================================================================== - ##### Alarms A and B configuration functions ##### - =============================================================================== - - [..] This section provide functions allowing to program and read the RTC Alarms. - -@endverbatim - * @{ - */ - -/** - * @brief Set the specified RTC Alarm. - * @note The Alarm register can only be written when the corresponding Alarm - * is disabled (Use the RTC_AlarmCmd(DISABLE)). - * @param RTC_Format: specifies the format of the returned parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_Alarm: specifies the alarm to be configured. - * This parameter can be one of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @arg RTC_Alarm_B: to select Alarm B - * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that - * contains the alarm configuration parameters. - * @retval None - */ -void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - assert_param(IS_RTC_ALARM(RTC_Alarm)); - assert_param(IS_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask)); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel)); - - if (RTC_Format == RTC_Format_BIN) - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)); - assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)); - } - else - { - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)); - } - assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)); - assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)); - - if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date) - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay)); - } - else - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay)); - } - } - else - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours); - assert_param(IS_RTC_HOUR12(tmpreg)); - assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)); - } - else - { - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours))); - } - - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds))); - - if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date) - { - tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); - } - else - { - tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); - } - } - - /* Check the input parameters format */ - if (RTC_Format != RTC_Format_BIN) - { - tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); - } - else - { - tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Alarm register */ - if (RTC_Alarm == RTC_Alarm_A) - { - RTC->ALRMAR = (uint32_t)tmpreg; - } - else - { - RTC->ALRMBR = (uint32_t)tmpreg; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Fills each RTC_AlarmStruct member with its default value - * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask = - * all fields are masked). - * @param RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which - * will be initialized. - * @retval None - */ -void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct) -{ - /* Alarm Time Settings : Time = 00h:00mn:00sec */ - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM; - RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0; - RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0; - RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0; - - /* Alarm Date Settings : Date = 1st day of the month */ - RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date; - RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1; - - /* Alarm Masks Settings : Mask = all fields are not masked */ - RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None; -} - -/** - * @brief Get the RTC Alarm value and masks. - * @param RTC_Format: specifies the format of the output parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_Alarm: specifies the alarm to be read. - * This parameter can be one of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @arg RTC_Alarm_B: to select Alarm B - * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will - * contains the output alarm configuration values. - * @retval None - */ -void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - assert_param(IS_RTC_ALARM(RTC_Alarm)); - - /* Get the RTC_ALRMxR register */ - if (RTC_Alarm == RTC_Alarm_A) - { - tmpreg = (uint32_t)(RTC->ALRMAR); - } - else - { - tmpreg = (uint32_t)(RTC->ALRMBR); - } - - /* Fill the structure with the read parameters */ - RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \ - RTC_ALRMAR_HU)) >> 16); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \ - RTC_ALRMAR_MNU)) >> 8); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \ - RTC_ALRMAR_SU)); - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16); - RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24); - RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); - RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All); - - if (RTC_Format == RTC_Format_BIN) - { - RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ - RTC_AlarmTime.RTC_Hours); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ - RTC_AlarmTime.RTC_Minutes); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ - RTC_AlarmTime.RTC_Seconds); - RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); - } -} - -/** - * @brief Enables or disables the specified RTC Alarm. - * @param RTC_Alarm: specifies the alarm to be configured. - * This parameter can be any combination of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @arg RTC_Alarm_B: to select Alarm B - * @param NewState: new state of the specified alarm. - * This parameter can be: ENABLE or DISABLE. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Alarm is enabled/disabled - * - ERROR: RTC Alarm is not enabled/disabled - */ -ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState) -{ - __IO uint32_t alarmcounter = 0x00; - uint32_t alarmstatus = 0x00; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_CMD_ALARM(RTC_Alarm)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Alarm state */ - if (NewState != DISABLE) - { - RTC->CR |= (uint32_t)RTC_Alarm; - - status = SUCCESS; - } - else - { - /* Disable the Alarm in RTC_CR register */ - RTC->CR &= (uint32_t)~RTC_Alarm; - - /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ - do - { - alarmstatus = RTC->ISR & (RTC_Alarm >> 8); - alarmcounter++; - } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00)); - - if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Configure the RTC AlarmA/B Sub seconds value and mask.* - * @note This function is performed only when the Alarm is disabled. - * @param RTC_Alarm: specifies the alarm to be configured. - * This parameter can be one of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @arg RTC_Alarm_B: to select Alarm B - * @param RTC_AlarmSubSecondValue: specifies the Sub seconds value. - * This parameter can be a value from 0 to 0x00007FFF. - * @param RTC_AlarmSubSecondMask: specifies the Sub seconds Mask. - * This parameter can be any combination of the following values: - * @arg RTC_AlarmSubSecondMask_All : All Alarm SS fields are masked. - * There is no comparison on sub seconds for Alarm. - * @arg RTC_AlarmSubSecondMask_SS14_1 : SS[14:1] are don't care in Alarm comparison. - * Only SS[0] is compared - * @arg RTC_AlarmSubSecondMask_SS14_2 : SS[14:2] are don't care in Alarm comparison. - * Only SS[1:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_3 : SS[14:3] are don't care in Alarm comparison. - * Only SS[2:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_4 : SS[14:4] are don't care in Alarm comparison. - * Only SS[3:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_5 : SS[14:5] are don't care in Alarm comparison. - * Only SS[4:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_6 : SS[14:6] are don't care in Alarm comparison. - * Only SS[5:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_7 : SS[14:7] are don't care in Alarm comparison. - * Only SS[6:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_8 : SS[14:8] are don't care in Alarm comparison. - * Only SS[7:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_9 : SS[14:9] are don't care in Alarm comparison. - * Only SS[8:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_10: SS[14:10] are don't care in Alarm comparison. - * Only SS[9:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_11: SS[14:11] are don't care in Alarm comparison. - * Only SS[10:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_12: SS[14:12] are don't care in Alarm comparison. - * Only SS[11:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_13: SS[14:13] are don't care in Alarm comparison. - * Only SS[12:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14 : SS[14] is don't care in Alarm comparison. - * Only SS[13:0] are compared - * @arg RTC_AlarmSubSecondMask_None : SS[14:0] are compared and must match - * to activate alarm - * @retval None - */ -void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_ALARM(RTC_Alarm)); - assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue)); - assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(RTC_AlarmSubSecondMask)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Alarm A or Alarm B Sub Second registers */ - tmpreg = (uint32_t) (uint32_t)(RTC_AlarmSubSecondValue) | (uint32_t)(RTC_AlarmSubSecondMask); - - if (RTC_Alarm == RTC_Alarm_A) - { - /* Configure the Alarm A Sub Second register */ - RTC->ALRMASSR = tmpreg; - } - else - { - /* Configure the Alarm B Sub Second register */ - RTC->ALRMBSSR = tmpreg; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - -} - -/** - * @brief Gets the RTC Alarm Sub seconds value. - * @param RTC_Alarm: specifies the alarm to be read. - * This parameter can be one of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @arg RTC_Alarm_B: to select Alarm B - * @param None - * @retval RTC Alarm Sub seconds value. - */ -uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm) -{ - uint32_t tmpreg = 0; - - /* Get the RTC_ALRMxR register */ - if (RTC_Alarm == RTC_Alarm_A) - { - tmpreg = (uint32_t)((RTC->ALRMASSR) & RTC_ALRMASSR_SS); - } - else - { - tmpreg = (uint32_t)((RTC->ALRMBSSR) & RTC_ALRMBSSR_SS); - } - - return (tmpreg); -} - -/** - * @} - */ - -/** @defgroup RTC_Group4 WakeUp Timer configuration functions - * @brief WakeUp Timer configuration functions - * -@verbatim - =============================================================================== - ##### WakeUp Timer configuration functions ##### - =============================================================================== - - [..] This section provide functions allowing to program and read the RTC WakeUp. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the RTC Wakeup clock source. - * @note The WakeUp Clock source can only be changed when the RTC WakeUp - * is disabled (Use the RTC_WakeUpCmd(DISABLE)). - * @param RTC_WakeUpClock: Wakeup Clock source. - * This parameter can be one of the following values: - * @arg RTC_WakeUpClock_RTCCLK_Div16: RTC Wakeup Counter Clock = RTCCLK/16 - * @arg RTC_WakeUpClock_RTCCLK_Div8: RTC Wakeup Counter Clock = RTCCLK/8 - * @arg RTC_WakeUpClock_RTCCLK_Div4: RTC Wakeup Counter Clock = RTCCLK/4 - * @arg RTC_WakeUpClock_RTCCLK_Div2: RTC Wakeup Counter Clock = RTCCLK/2 - * @arg RTC_WakeUpClock_CK_SPRE_16bits: RTC Wakeup Counter Clock = CK_SPRE - * @arg RTC_WakeUpClock_CK_SPRE_17bits: RTC Wakeup Counter Clock = CK_SPRE - * @retval None - */ -void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock) -{ - /* Check the parameters */ - assert_param(IS_RTC_WAKEUP_CLOCK(RTC_WakeUpClock)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear the Wakeup Timer clock source bits in CR register */ - RTC->CR &= (uint32_t)~RTC_CR_WUCKSEL; - - /* Configure the clock source */ - RTC->CR |= (uint32_t)RTC_WakeUpClock; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Configures the RTC Wakeup counter. - * @note The RTC WakeUp counter can only be written when the RTC WakeUp - * is disabled (Use the RTC_WakeUpCmd(DISABLE)). - * @param RTC_WakeUpCounter: specifies the WakeUp counter. - * This parameter can be a value from 0x0000 to 0xFFFF. - * @retval None - */ -void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter) -{ - /* Check the parameters */ - assert_param(IS_RTC_WAKEUP_COUNTER(RTC_WakeUpCounter)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Wakeup Timer counter */ - RTC->WUTR = (uint32_t)RTC_WakeUpCounter; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Returns the RTC WakeUp timer counter value. - * @param None - * @retval The RTC WakeUp Counter value. - */ -uint32_t RTC_GetWakeUpCounter(void) -{ - /* Get the counter value */ - return ((uint32_t)(RTC->WUTR & RTC_WUTR_WUT)); -} - -/** - * @brief Enables or Disables the RTC WakeUp timer. - * @param NewState: new state of the WakeUp timer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -ErrorStatus RTC_WakeUpCmd(FunctionalState NewState) -{ - __IO uint32_t wutcounter = 0x00; - uint32_t wutwfstatus = 0x00; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - if (NewState != DISABLE) - { - /* Enable the Wakeup Timer */ - RTC->CR |= (uint32_t)RTC_CR_WUTE; - status = SUCCESS; - } - else - { - /* Disable the Wakeup Timer */ - RTC->CR &= (uint32_t)~RTC_CR_WUTE; - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - do - { - wutwfstatus = RTC->ISR & RTC_ISR_WUTWF; - wutcounter++; - } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); - - if ((RTC->ISR & RTC_ISR_WUTWF) == RESET) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @} - */ - -/** @defgroup RTC_Group5 Daylight Saving configuration functions - * @brief Daylight Saving configuration functions - * -@verbatim - =============================================================================== - ##### Daylight Saving configuration functions ##### - =============================================================================== - - [..] This section provide functions allowing to configure the RTC DayLight Saving. - -@endverbatim - * @{ - */ - -/** - * @brief Adds or substract one hour from the current time. - * @param RTC_DayLightSaveOperation: the value of hour adjustment. - * This parameter can be one of the following values: - * @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time) - * @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time) - * @param RTC_StoreOperation: Specifies the value to be written in the BCK bit - * in CR register to store the operation. - * This parameter can be one of the following values: - * @arg RTC_StoreOperation_Reset: BCK Bit Reset - * @arg RTC_StoreOperation_Set: BCK Bit Set - * @retval None - */ -void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation) -{ - /* Check the parameters */ - assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving)); - assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear the bits to be configured */ - RTC->CR &= (uint32_t)~(RTC_CR_BCK); - - /* Configure the RTC_CR register */ - RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation); - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Returns the RTC Day Light Saving stored operation. - * @param None - * @retval RTC Day Light Saving stored operation. - * - RTC_StoreOperation_Reset - * - RTC_StoreOperation_Set - */ -uint32_t RTC_GetStoreOperation(void) -{ - return (RTC->CR & RTC_CR_BCK); -} - -/** - * @} - */ - -/** @defgroup RTC_Group6 Output pin Configuration function - * @brief Output pin Configuration function - * -@verbatim - =============================================================================== - ##### Output pin Configuration function ##### - =============================================================================== - - [..] This section provide functions allowing to configure the RTC Output source. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the RTC output source (AFO_ALARM). - * @param RTC_Output: Specifies which signal will be routed to the RTC output. - * This parameter can be one of the following values: - * @arg RTC_Output_Disable: No output selected - * @arg RTC_Output_AlarmA: signal of AlarmA mapped to output - * @arg RTC_Output_AlarmB: signal of AlarmB mapped to output - * @arg RTC_Output_WakeUp: signal of WakeUp mapped to output - * @param RTC_OutputPolarity: Specifies the polarity of the output signal. - * This parameter can be one of the following: - * @arg RTC_OutputPolarity_High: The output pin is high when the - * ALRAF/ALRBF/WUTF is high (depending on OSEL) - * @arg RTC_OutputPolarity_Low: The output pin is low when the - * ALRAF/ALRBF/WUTF is high (depending on OSEL) - * @retval None - */ -void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity) -{ - /* Check the parameters */ - assert_param(IS_RTC_OUTPUT(RTC_Output)); - assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear the bits to be configured */ - RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL); - - /* Configure the output selection and polarity */ - RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity); - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @} - */ - -/** @defgroup RTC_Group7 Digital Calibration configuration functions - * @brief Coarse Calibration configuration functions - * -@verbatim - =============================================================================== - ##### Digital Calibration configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the Coarse calibration parameters. - * @param RTC_CalibSign: specifies the sign of the coarse calibration value. - * This parameter can be one of the following values: - * @arg RTC_CalibSign_Positive: The value sign is positive - * @arg RTC_CalibSign_Negative: The value sign is negative - * @param Value: value of coarse calibration expressed in ppm (coded on 5 bits). - * - * @note This Calibration value should be between 0 and 63 when using negative - * sign with a 2-ppm step. - * - * @note This Calibration value should be between 0 and 126 when using positive - * sign with a 4-ppm step. - * - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Coarse calibration are initialized - * - ERROR: RTC Coarse calibration are not initialized - */ -ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_CALIB_SIGN(RTC_CalibSign)); - assert_param(IS_RTC_CALIB_VALUE(Value)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Set the coarse calibration value */ - RTC->CALIBR = (uint32_t)(RTC_CalibSign | Value); - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - status = SUCCESS; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Enables or disables the Coarse calibration process. - * @param NewState: new state of the Coarse calibration. - * This parameter can be: ENABLE or DISABLE. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Coarse calibration are enabled/disabled - * - ERROR: RTC Coarse calibration are not enabled/disabled - */ -ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - if (NewState != DISABLE) - { - /* Enable the Coarse Calibration */ - RTC->CR |= (uint32_t)RTC_CR_DCE; - } - else - { - /* Disable the Coarse Calibration */ - RTC->CR &= (uint32_t)~RTC_CR_DCE; - } - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - status = SUCCESS; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Enables or disables the RTC clock to be output through the relative pin. - * @param NewState: new state of the digital calibration Output. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_CalibOutputCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - if (NewState != DISABLE) - { - /* Enable the RTC clock output */ - RTC->CR |= (uint32_t)RTC_CR_COE; - } - else - { - /* Disable the RTC clock output */ - RTC->CR &= (uint32_t)~RTC_CR_COE; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - * @param RTC_CalibOutput : Select the Calibration output Selection . - * This parameter can be one of the following values: - * @arg RTC_CalibOutput_512Hz: A signal has a regular waveform at 512Hz. - * @arg RTC_CalibOutput_1Hz : A signal has a regular waveform at 1Hz. - * @retval None -*/ -void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput) -{ - /* Check the parameters */ - assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /*clear flags before configuration */ - RTC->CR &= (uint32_t)~(RTC_CR_COSEL); - - /* Configure the RTC_CR register */ - RTC->CR |= (uint32_t)RTC_CalibOutput; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Configures the Smooth Calibration Settings. - * @param RTC_SmoothCalibPeriod : Select the Smooth Calibration Period. - * This parameter can be can be one of the following values: - * @arg RTC_SmoothCalibPeriod_32sec : The smooth calibration period is 32s. - * @arg RTC_SmoothCalibPeriod_16sec : The smooth calibration period is 16s. - * @arg RTC_SmoothCalibPeriod_8sec : The smooth calibartion period is 8s. - * @param RTC_SmoothCalibPlusPulses : Select to Set or reset the CALP bit. - * This parameter can be one of the following values: - * @arg RTC_SmoothCalibPlusPulses_Set : Add one RTCCLK puls every 2**11 pulses. - * @arg RTC_SmoothCalibPlusPulses_Reset: No RTCCLK pulses are added. - * @param RTC_SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits. - * This parameter can be one any value from 0 to 0x000001FF. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Calib registers are configured - * - ERROR: RTC Calib registers are not configured -*/ -ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, - uint32_t RTC_SmoothCalibPlusPulses, - uint32_t RTC_SmouthCalibMinusPulsesValue) -{ - ErrorStatus status = ERROR; - uint32_t recalpfcount = 0; - - /* Check the parameters */ - assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(RTC_SmoothCalibPeriod)); - assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses)); - assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* check if a calibration is pending*/ - if ((RTC->ISR & RTC_ISR_RECALPF) != RESET) - { - /* wait until the Calibration is completed*/ - while (((RTC->ISR & RTC_ISR_RECALPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT)) - { - recalpfcount++; - } - } - - /* check if the calibration pending is completed or if there is no calibration operation at all*/ - if ((RTC->ISR & RTC_ISR_RECALPF) == RESET) - { - /* Configure the Smooth calibration settings */ - RTC->CALR = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses | (uint32_t)RTC_SmouthCalibMinusPulsesValue); - - status = SUCCESS; - } - else - { - status = ERROR; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return (ErrorStatus)(status); -} - -/** - * @} - */ - - -/** @defgroup RTC_Group8 TimeStamp configuration functions - * @brief TimeStamp configuration functions - * -@verbatim - =============================================================================== - ##### TimeStamp configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or Disables the RTC TimeStamp functionality with the - * specified time stamp pin stimulating edge. - * @param RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is - * activated. - * This parameter can be one of the following: - * @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising - * edge of the related pin. - * @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the - * falling edge of the related pin. - * @param NewState: new state of the TimeStamp. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Get the RTC_CR register and clear the bits to be configured */ - tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); - - /* Get the new configuration */ - if (NewState != DISABLE) - { - tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE); - } - else - { - tmpreg |= (uint32_t)(RTC_TimeStampEdge); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Time Stamp TSEDGE and Enable bits */ - RTC->CR = (uint32_t)tmpreg; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Get the RTC TimeStamp value and masks. - * @param RTC_Format: specifies the format of the output parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will - * contains the TimeStamp time values. - * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will - * contains the TimeStamp date values. - * @retval None - */ -void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, - RTC_DateTypeDef* RTC_StampDateStruct) -{ - uint32_t tmptime = 0, tmpdate = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - /* Get the TimeStamp time and date registers values */ - tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK); - tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK); - - /* Fill the Time structure fields with the read parameters */ - RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16); - RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8); - RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU)); - RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); - - /* Fill the Date structure fields with the read parameters */ - RTC_StampDateStruct->RTC_Year = 0; - RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8); - RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU)); - RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13); - - /* Check the input parameters format */ - if (RTC_Format == RTC_Format_BIN) - { - /* Convert the Time structure parameters to Binary format */ - RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours); - RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes); - RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds); - - /* Convert the Date structure parameters to Binary format */ - RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month); - RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date); - RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay); - } -} - -/** - * @brief Get the RTC timestamp Sub seconds value. - * @param None - * @retval RTC current timestamp Sub seconds value. - */ -uint32_t RTC_GetTimeStampSubSecond(void) -{ - /* Get timestamp sub seconds values from the correspondent registers */ - return (uint32_t)(RTC->TSSSR); -} - -/** - * @} - */ - -/** @defgroup RTC_Group9 Tampers configuration functions - * @brief Tampers configuration functions - * -@verbatim - =============================================================================== - ##### Tampers configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the select Tamper pin edge. - * @param RTC_Tamper: Selected tamper pin. - * This parameter can be RTC_Tamper_1. - * @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that - * stimulates tamper event. - * This parameter can be one of the following values: - * @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event. - * @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event. - * @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event. - * @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event. - * @retval None - */ -void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER(RTC_Tamper)); - assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger)); - - if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge) - { - /* Configure the RTC_TAFCR register */ - RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1)); - } - else - { - /* Configure the RTC_TAFCR register */ - RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1); - } -} - -/** - * @brief Enables or Disables the Tamper detection. - * @param RTC_Tamper: Selected tamper pin. - * This parameter can be RTC_Tamper_1. - * @param NewState: new state of the tamper pin. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER(RTC_Tamper)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected Tamper pin */ - RTC->TAFCR |= (uint32_t)RTC_Tamper; - } - else - { - /* Disable the selected Tamper pin */ - RTC->TAFCR &= (uint32_t)~RTC_Tamper; - } -} - -/** - * @brief Configures the Tampers Filter. - * @param RTC_TamperFilter: Specifies the tampers filter. - * This parameter can be one of the following values: - * @arg RTC_TamperFilter_Disable: Tamper filter is disabled. - * @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive - * samples at the active level - * @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive - * samples at the active level - * @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive - * samples at the active level - * @retval None - */ -void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter)); - - /* Clear TAMPFLT[1:0] bits in the RTC_TAFCR register */ - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFLT); - - /* Configure the RTC_TAFCR register */ - RTC->TAFCR |= (uint32_t)RTC_TamperFilter; -} - -/** - * @brief Configures the Tampers Sampling Frequency. - * @param RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency. - * This parameter can be one of the following values: - * @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 32768 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 16384 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 8192 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 4096 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 2048 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 1024 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 512 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 256 - * @retval None - */ -void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq)); - - /* Clear TAMPFREQ[2:0] bits in the RTC_TAFCR register */ - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFREQ); - - /* Configure the RTC_TAFCR register */ - RTC->TAFCR |= (uint32_t)RTC_TamperSamplingFreq; -} - -/** - * @brief Configures the Tampers Pins input Precharge Duration. - * @param RTC_TamperPrechargeDuration: Specifies the Tampers Pins input - * Precharge Duration. - * This parameter can be one of the following values: - * @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are precharged before sampling during 1 RTCCLK cycle - * @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are precharged before sampling during 2 RTCCLK cycle - * @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are precharged before sampling during 4 RTCCLK cycle - * @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are precharged before sampling during 8 RTCCLK cycle - * @retval None - */ -void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration)); - - /* Clear TAMPPRCH[1:0] bits in the RTC_TAFCR register */ - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPPRCH); - - /* Configure the RTC_TAFCR register */ - RTC->TAFCR |= (uint32_t)RTC_TamperPrechargeDuration; -} - -/** - * @brief Enables or Disables the TimeStamp on Tamper Detection Event. - * @note The timestamp is valid even the TSE bit in tamper control register - * is reset. - * @param NewState: new state of the timestamp on tamper event. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Save timestamp on tamper detection event */ - RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPTS; - } - else - { - /* Tamper detection does not cause a timestamp to be saved */ - RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPTS; - } -} - -/** - * @brief Enables or Disables the Precharge of Tamper pin. - * @param NewState: new state of tamper pull up. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_TamperPullUpCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable precharge of the selected Tamper pin */ - RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPPUDIS; - } - else - { - /* Disable precharge of the selected Tamper pin */ - RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPPUDIS; - } -} - -/** - * @} - */ - -/** @defgroup RTC_Group10 Backup Data Registers configuration functions - * @brief Backup Data Registers configuration functions - * -@verbatim - =============================================================================== - ##### Backup Data Registers configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Writes a data in a specified RTC Backup data register. - * @param RTC_BKP_DR: RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to - * specify the register. - * @param Data: Data to be written in the specified RTC Backup data register. - * @retval None - */ -void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_RTC_BKP(RTC_BKP_DR)); - - tmp = RTC_BASE + 0x50; - tmp += (RTC_BKP_DR * 4); - - /* Write the specified register */ - *(__IO uint32_t *)tmp = (uint32_t)Data; -} - -/** - * @brief Reads data from the specified RTC Backup data Register. - * @param RTC_BKP_DR: RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to - * specify the register. - * @retval None - */ -uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_RTC_BKP(RTC_BKP_DR)); - - tmp = RTC_BASE + 0x50; - tmp += (RTC_BKP_DR * 4); - - /* Read the specified register */ - return (*(__IO uint32_t *)tmp); -} - -/** - * @} - */ - -/** @defgroup RTC_Group11 RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions - * @brief RTC Tamper and TimeStamp Pins Selection and Output Type Config - * configuration functions - * -@verbatim - ================================================================================================== - ##### RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions ##### - ================================================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Selects the RTC Tamper Pin. - * @param RTC_TamperPin: specifies the RTC Tamper Pin. - * This parameter can be one of the following values: - * @arg RTC_TamperPin_PC13: PC13 is selected as RTC Tamper Pin. - * @arg RTC_TamperPin_PI8: PI8 is selected as RTC Tamper Pin. - * @retval None - */ -void RTC_TamperPinSelection(uint32_t RTC_TamperPin) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER_PIN(RTC_TamperPin)); - - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPINSEL); - RTC->TAFCR |= (uint32_t)(RTC_TamperPin); -} - -/** - * @brief Selects the RTC TimeStamp Pin. - * @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin. - * This parameter can be one of the following values: - * @arg RTC_TimeStampPin_PC13: PC13 is selected as RTC TimeStamp Pin. - * @arg RTC_TimeStampPin_PI8: PI8 is selected as RTC TimeStamp Pin. - * @retval None - */ -void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin) -{ - /* Check the parameters */ - assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); - - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TSINSEL); - RTC->TAFCR |= (uint32_t)(RTC_TimeStampPin); -} - -/** - * @brief Configures the RTC Output Pin mode. - * @param RTC_OutputType: specifies the RTC Output (PC13) pin mode. - * This parameter can be one of the following values: - * @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in - * Open Drain mode. - * @arg RTC_OutputType_PushPull: RTC Output (PC13) is configured in - * Push Pull mode. - * @retval None - */ -void RTC_OutputTypeConfig(uint32_t RTC_OutputType) -{ - /* Check the parameters */ - assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType)); - - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE); - RTC->TAFCR |= (uint32_t)(RTC_OutputType); -} - -/** - * @} - */ - -/** @defgroup RTC_Group12 Shift control synchronisation functions - * @brief Shift control synchronisation functions - * -@verbatim - =============================================================================== - ##### Shift control synchronisation functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the Synchronization Shift Control Settings. - * @note When REFCKON is set, firmware must not write to Shift control register - * @param RTC_ShiftAdd1S : Select to add or not 1 second to the time Calendar. - * This parameter can be one of the following values : - * @arg RTC_ShiftAdd1S_Set : Add one second to the clock calendar. - * @arg RTC_ShiftAdd1S_Reset: No effect. - * @param RTC_ShiftSubFS: Select the number of Second Fractions to Substitute. - * This parameter can be one any value from 0 to 0x7FFF. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Shift registers are configured - * - ERROR: RTC Shift registers are not configured -*/ -ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS) -{ - ErrorStatus status = ERROR; - uint32_t shpfcount = 0; - - /* Check the parameters */ - assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S)); - assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Check if a Shift is pending*/ - if ((RTC->ISR & RTC_ISR_SHPF) != RESET) - { - /* Wait until the shift is completed*/ - while (((RTC->ISR & RTC_ISR_SHPF) != RESET) && (shpfcount != SHPF_TIMEOUT)) - { - shpfcount++; - } - } - - /* Check if the Shift pending is completed or if there is no Shift operation at all*/ - if ((RTC->ISR & RTC_ISR_SHPF) == RESET) - { - /* check if the reference clock detection is disabled */ - if((RTC->CR & RTC_CR_REFCKON) == RESET) - { - /* Configure the Shift settings */ - RTC->SHIFTR = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S); - - if(RTC_WaitForSynchro() == ERROR) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - else - { - status = ERROR; - } - } - else - { - status = ERROR; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return (ErrorStatus)(status); -} - -/** - * @} - */ - -/** @defgroup RTC_Group13 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - [..] All RTC interrupts are connected to the EXTI controller. - - (+) To enable the RTC Alarm interrupt, the following sequence is required: - (++) Configure and enable the EXTI Line 17 in interrupt mode and select - the rising edge sensitivity using the EXTI_Init() function. - (++) Configure and enable the RTC_Alarm IRQ channel in the NVIC using the - NVIC_Init() function. - (++) Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B) using - the RTC_SetAlarm() and RTC_AlarmCmd() functions. - - (+) To enable the RTC Wakeup interrupt, the following sequence is required: - (++) Configure and enable the EXTI Line 22 in interrupt mode and select the - rising edge sensitivity using the EXTI_Init() function. - (++) Configure and enable the RTC_WKUP IRQ channel in the NVIC using the - NVIC_Init() function. - (++) Configure the RTC to generate the RTC wakeup timer event using the - RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd() - functions. - - (+) To enable the RTC Tamper interrupt, the following sequence is required: - (++) Configure and enable the EXTI Line 21 in interrupt mode and select - the rising edge sensitivity using the EXTI_Init() function. - (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the - NVIC_Init() function. - (++) Configure the RTC to detect the RTC tamper event using the - RTC_TamperTriggerConfig() and RTC_TamperCmd() functions. - - (+) To enable the RTC TimeStamp interrupt, the following sequence is required: - (++) Configure and enable the EXTI Line 21 in interrupt mode and select the - rising edge sensitivity using the EXTI_Init() function. - (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the - NVIC_Init() function. - (++) Configure the RTC to detect the RTC time stamp event using the - RTC_TimeStampCmd() functions. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified RTC interrupts. - * @param RTC_IT: specifies the RTC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_TS: Time Stamp interrupt mask - * @arg RTC_IT_WUT: WakeUp Timer interrupt mask - * @arg RTC_IT_ALRB: Alarm B interrupt mask - * @arg RTC_IT_ALRA: Alarm A interrupt mask - * @arg RTC_IT_TAMP: Tamper event interrupt mask - * @param NewState: new state of the specified RTC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RTC_CONFIG_IT(RTC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - if (NewState != DISABLE) - { - /* Configure the Interrupts in the RTC_CR register */ - RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE); - /* Configure the Tamper Interrupt in the RTC_TAFCR */ - RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE); - } - else - { - /* Configure the Interrupts in the RTC_CR register */ - RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE); - /* Configure the Tamper Interrupt in the RTC_TAFCR */ - RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE); - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Checks whether the specified RTC flag is set or not. - * @param RTC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg RTC_FLAG_RECALPF: RECALPF event flag. - * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag - * @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag - * @arg RTC_FLAG_TSF: Time Stamp event flag - * @arg RTC_FLAG_WUTF: WakeUp Timer flag - * @arg RTC_FLAG_ALRBF: Alarm B flag - * @arg RTC_FLAG_ALRAF: Alarm A flag - * @arg RTC_FLAG_INITF: Initialization mode flag - * @arg RTC_FLAG_RSF: Registers Synchronized flag - * @arg RTC_FLAG_INITS: Registers Configured flag - * @arg RTC_FLAG_SHPF: Shift operation pending flag. - * @arg RTC_FLAG_WUTWF: WakeUp Timer Write flag - * @arg RTC_FLAG_ALRBWF: Alarm B Write flag - * @arg RTC_FLAG_ALRAWF: Alarm A write flag - * @retval The new state of RTC_FLAG (SET or RESET). - */ -FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); - - /* Get all the flags */ - tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK); - - /* Return the status of the flag */ - if ((tmpreg & RTC_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the RTC's pending flags. - * @param RTC_FLAG: specifies the RTC flag to clear. - * This parameter can be any combination of the following values: - * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag - * @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag - * @arg RTC_FLAG_TSF: Time Stamp event flag - * @arg RTC_FLAG_WUTF: WakeUp Timer flag - * @arg RTC_FLAG_ALRBF: Alarm B flag - * @arg RTC_FLAG_ALRAF: Alarm A flag - * @arg RTC_FLAG_RSF: Registers Synchronized flag - * @retval None - */ -void RTC_ClearFlag(uint32_t RTC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); - - /* Clear the Flags in the RTC_ISR register */ - RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); -} - -/** - * @brief Checks whether the specified RTC interrupt has occurred or not. - * @param RTC_IT: specifies the RTC interrupt source to check. - * This parameter can be one of the following values: - * @arg RTC_IT_TS: Time Stamp interrupt - * @arg RTC_IT_WUT: WakeUp Timer interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_TAMP1: Tamper 1 event interrupt - * @retval The new state of RTC_IT (SET or RESET). - */ -ITStatus RTC_GetITStatus(uint32_t RTC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpreg = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_RTC_GET_IT(RTC_IT)); - - /* Get the TAMPER Interrupt enable bit and pending bit */ - tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE)); - - /* Get the Interrupt enable Status */ - enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & (RTC_IT >> 15))); - - /* Get the Interrupt pending bit */ - tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4))); - - /* Get the status of the Interrupt */ - if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the RTC's interrupt pending bits. - * @param RTC_IT: specifies the RTC interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg RTC_IT_TS: Time Stamp interrupt - * @arg RTC_IT_WUT: WakeUp Timer interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_TAMP1: Tamper 1 event interrupt - * @retval None - */ -void RTC_ClearITPendingBit(uint32_t RTC_IT) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_CLEAR_IT(RTC_IT)); - - /* Get the RTC_ISR Interrupt pending bits mask */ - tmpreg = (uint32_t)(RTC_IT >> 4); - - /* Clear the interrupt pending bits in the RTC_ISR register */ - RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); -} - -/** - * @} - */ - -/** - * @brief Converts a 2 digit decimal to BCD format. - * @param Value: Byte to be converted. - * @retval Converted byte - */ -static uint8_t RTC_ByteToBcd2(uint8_t Value) -{ - uint8_t bcdhigh = 0; - - while (Value >= 10) - { - bcdhigh++; - Value -= 10; - } - - return ((uint8_t)(bcdhigh << 4) | Value); -} - -/** - * @brief Convert from 2 digit BCD to Binary. - * @param Value: BCD value to be converted. - * @retval Converted word - */ -static uint8_t RTC_Bcd2ToByte(uint8_t Value) -{ - uint8_t tmp = 0; - tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; - return (tmp + (Value & (uint8_t)0x0F)); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm32f4xx_rtc.h b/stm/stmperiph/stm32f4xx_rtc.h deleted file mode 100644 index a46227e53..000000000 --- a/stm/stmperiph/stm32f4xx_rtc.h +++ /dev/null @@ -1,881 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_rtc.h - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief This file contains all the functions prototypes for the RTC firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_RTC_H -#define __STM32F4xx_RTC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RTC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief RTC Init structures definition - */ -typedef struct -{ - uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format. - This parameter can be a value of @ref RTC_Hour_Formats */ - - uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. - This parameter must be set to a value lower than 0x7F */ - - uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. - This parameter must be set to a value lower than 0x7FFF */ -}RTC_InitTypeDef; - -/** - * @brief RTC Time structure definition - */ -typedef struct -{ - uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour. - This parameter must be set to a value in the 0-12 range - if the RTC_HourFormat_12 is selected or 0-23 range if - the RTC_HourFormat_24 is selected. */ - - uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes. - This parameter must be set to a value in the 0-59 range. */ - - uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds. - This parameter must be set to a value in the 0-59 range. */ - - uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time. - This parameter can be a value of @ref RTC_AM_PM_Definitions */ -}RTC_TimeTypeDef; - -/** - * @brief RTC Date structure definition - */ -typedef struct -{ - uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay. - This parameter can be a value of @ref RTC_WeekDay_Definitions */ - - uint8_t RTC_Month; /*!< Specifies the RTC Date Month (in BCD format). - This parameter can be a value of @ref RTC_Month_Date_Definitions */ - - uint8_t RTC_Date; /*!< Specifies the RTC Date. - This parameter must be set to a value in the 1-31 range. */ - - uint8_t RTC_Year; /*!< Specifies the RTC Date Year. - This parameter must be set to a value in the 0-99 range. */ -}RTC_DateTypeDef; - -/** - * @brief RTC Alarm structure definition - */ -typedef struct -{ - RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */ - - uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks. - This parameter can be a value of @ref RTC_AlarmMask_Definitions */ - - uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. - This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ - - uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. - If the Alarm Date is selected, this parameter - must be set to a value in the 1-31 range. - If the Alarm WeekDay is selected, this - parameter can be a value of @ref RTC_WeekDay_Definitions */ -}RTC_AlarmTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup RTC_Exported_Constants - * @{ - */ - - -/** @defgroup RTC_Hour_Formats - * @{ - */ -#define RTC_HourFormat_24 ((uint32_t)0x00000000) -#define RTC_HourFormat_12 ((uint32_t)0x00000040) -#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \ - ((FORMAT) == RTC_HourFormat_24)) -/** - * @} - */ - -/** @defgroup RTC_Asynchronous_Predivider - * @{ - */ -#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F) - -/** - * @} - */ - - -/** @defgroup RTC_Synchronous_Predivider - * @{ - */ -#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF) - -/** - * @} - */ - -/** @defgroup RTC_Time_Definitions - * @{ - */ -#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12)) -#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23) -#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59) -#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59) - -/** - * @} - */ - -/** @defgroup RTC_AM_PM_Definitions - * @{ - */ -#define RTC_H12_AM ((uint8_t)0x00) -#define RTC_H12_PM ((uint8_t)0x40) -#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM)) - -/** - * @} - */ - -/** @defgroup RTC_Year_Date_Definitions - * @{ - */ -#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99) - -/** - * @} - */ - -/** @defgroup RTC_Month_Date_Definitions - * @{ - */ - -/* Coded in BCD format */ -#define RTC_Month_January ((uint8_t)0x01) -#define RTC_Month_February ((uint8_t)0x02) -#define RTC_Month_March ((uint8_t)0x03) -#define RTC_Month_April ((uint8_t)0x04) -#define RTC_Month_May ((uint8_t)0x05) -#define RTC_Month_June ((uint8_t)0x06) -#define RTC_Month_July ((uint8_t)0x07) -#define RTC_Month_August ((uint8_t)0x08) -#define RTC_Month_September ((uint8_t)0x09) -#define RTC_Month_October ((uint8_t)0x10) -#define RTC_Month_November ((uint8_t)0x11) -#define RTC_Month_December ((uint8_t)0x12) -#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12)) -#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31)) - -/** - * @} - */ - -/** @defgroup RTC_WeekDay_Definitions - * @{ - */ - -#define RTC_Weekday_Monday ((uint8_t)0x01) -#define RTC_Weekday_Tuesday ((uint8_t)0x02) -#define RTC_Weekday_Wednesday ((uint8_t)0x03) -#define RTC_Weekday_Thursday ((uint8_t)0x04) -#define RTC_Weekday_Friday ((uint8_t)0x05) -#define RTC_Weekday_Saturday ((uint8_t)0x06) -#define RTC_Weekday_Sunday ((uint8_t)0x07) -#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ - ((WEEKDAY) == RTC_Weekday_Tuesday) || \ - ((WEEKDAY) == RTC_Weekday_Wednesday) || \ - ((WEEKDAY) == RTC_Weekday_Thursday) || \ - ((WEEKDAY) == RTC_Weekday_Friday) || \ - ((WEEKDAY) == RTC_Weekday_Saturday) || \ - ((WEEKDAY) == RTC_Weekday_Sunday)) -/** - * @} - */ - - -/** @defgroup RTC_Alarm_Definitions - * @{ - */ -#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31)) -#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ - ((WEEKDAY) == RTC_Weekday_Tuesday) || \ - ((WEEKDAY) == RTC_Weekday_Wednesday) || \ - ((WEEKDAY) == RTC_Weekday_Thursday) || \ - ((WEEKDAY) == RTC_Weekday_Friday) || \ - ((WEEKDAY) == RTC_Weekday_Saturday) || \ - ((WEEKDAY) == RTC_Weekday_Sunday)) - -/** - * @} - */ - - -/** @defgroup RTC_AlarmDateWeekDay_Definitions - * @{ - */ -#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000) -#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000) - -#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \ - ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay)) - -/** - * @} - */ - - -/** @defgroup RTC_AlarmMask_Definitions - * @{ - */ -#define RTC_AlarmMask_None ((uint32_t)0x00000000) -#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000) -#define RTC_AlarmMask_Hours ((uint32_t)0x00800000) -#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000) -#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080) -#define RTC_AlarmMask_All ((uint32_t)0x80808080) -#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET) - -/** - * @} - */ - -/** @defgroup RTC_Alarms_Definitions - * @{ - */ -#define RTC_Alarm_A ((uint32_t)0x00000100) -#define RTC_Alarm_B ((uint32_t)0x00000200) -#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B)) -#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET) - -/** - * @} - */ - - /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions - * @{ - */ -#define RTC_AlarmSubSecondMask_All ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. - There is no comparison on sub seconds - for Alarm */ -#define RTC_AlarmSubSecondMask_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm - comparison. Only SS[0] is compared. */ -#define RTC_AlarmSubSecondMask_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm - comparison. Only SS[1:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm - comparison. Only SS[2:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm - comparison. Only SS[3:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm - comparison. Only SS[4:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm - comparison. Only SS[5:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm - comparison. Only SS[6:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm - comparison. Only SS[7:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm - comparison. Only SS[8:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm - comparison. Only SS[9:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm - comparison. Only SS[10:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm - comparison.Only SS[11:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm - comparison. Only SS[12:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm - comparison.Only SS[13:0] are compared */ -#define RTC_AlarmSubSecondMask_None ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match - to activate alarm. */ -#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_AlarmSubSecondMask_All) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14) || \ - ((MASK) == RTC_AlarmSubSecondMask_None)) -/** - * @} - */ - -/** @defgroup RTC_Alarm_Sub_Seconds_Value - * @{ - */ - -#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF) - -/** - * @} - */ - -/** @defgroup RTC_Wakeup_Timer_Definitions - * @{ - */ -#define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000) -#define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001) -#define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002) -#define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003) -#define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004) -#define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006) -#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \ - ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \ - ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \ - ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \ - ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \ - ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits)) -#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF) -/** - * @} - */ - -/** @defgroup RTC_Time_Stamp_Edges_definitions - * @{ - */ -#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000) -#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008) -#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \ - ((EDGE) == RTC_TimeStampEdge_Falling)) -/** - * @} - */ - -/** @defgroup RTC_Output_selection_Definitions - * @{ - */ -#define RTC_Output_Disable ((uint32_t)0x00000000) -#define RTC_Output_AlarmA ((uint32_t)0x00200000) -#define RTC_Output_AlarmB ((uint32_t)0x00400000) -#define RTC_Output_WakeUp ((uint32_t)0x00600000) - -#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \ - ((OUTPUT) == RTC_Output_AlarmA) || \ - ((OUTPUT) == RTC_Output_AlarmB) || \ - ((OUTPUT) == RTC_Output_WakeUp)) - -/** - * @} - */ - -/** @defgroup RTC_Output_Polarity_Definitions - * @{ - */ -#define RTC_OutputPolarity_High ((uint32_t)0x00000000) -#define RTC_OutputPolarity_Low ((uint32_t)0x00100000) -#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \ - ((POL) == RTC_OutputPolarity_Low)) -/** - * @} - */ - - -/** @defgroup RTC_Digital_Calibration_Definitions - * @{ - */ -#define RTC_CalibSign_Positive ((uint32_t)0x00000000) -#define RTC_CalibSign_Negative ((uint32_t)0x00000080) -#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \ - ((SIGN) == RTC_CalibSign_Negative)) -#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20) - -/** - * @} - */ - - /** @defgroup RTC_Calib_Output_selection_Definitions - * @{ - */ -#define RTC_CalibOutput_512Hz ((uint32_t)0x00000000) -#define RTC_CalibOutput_1Hz ((uint32_t)0x00080000) -#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CalibOutput_512Hz) || \ - ((OUTPUT) == RTC_CalibOutput_1Hz)) -/** - * @} - */ - -/** @defgroup RTC_Smooth_calib_period_Definitions - * @{ - */ -#define RTC_SmoothCalibPeriod_32sec ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation - period is 32s, else 2exp20 RTCCLK seconds */ -#define RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation - period is 16s, else 2exp19 RTCCLK seconds */ -#define RTC_SmoothCalibPeriod_8sec ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation - period is 8s, else 2exp18 RTCCLK seconds */ -#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \ - ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \ - ((PERIOD) == RTC_SmoothCalibPeriod_8sec)) - -/** - * @} - */ - -/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions - * @{ - */ -#define RTC_SmoothCalibPlusPulses_Set ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added - during a X -second window = Y - CALM[8:0]. - with Y = 512, 256, 128 when X = 32, 16, 8 */ -#define RTC_SmoothCalibPlusPulses_Reset ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited - during a 32-second window = CALM[8:0]. */ -#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \ - ((PLUS) == RTC_SmoothCalibPlusPulses_Reset)) - -/** - * @} - */ - -/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions - * @{ - */ -#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF) - -/** - * @} - */ - -/** @defgroup RTC_DayLightSaving_Definitions - * @{ - */ -#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000) -#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000) -#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \ - ((SAVE) == RTC_DayLightSaving_ADD1H)) - -#define RTC_StoreOperation_Reset ((uint32_t)0x00000000) -#define RTC_StoreOperation_Set ((uint32_t)0x00040000) -#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \ - ((OPERATION) == RTC_StoreOperation_Set)) -/** - * @} - */ - -/** @defgroup RTC_Tamper_Trigger_Definitions - * @{ - */ -#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000) -#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001) -#define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000) -#define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000001) -#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \ - ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \ - ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \ - ((TRIGGER) == RTC_TamperTrigger_HighLevel)) - -/** - * @} - */ - -/** @defgroup RTC_Tamper_Filter_Definitions - * @{ - */ -#define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */ - -#define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2 - consecutive samples at the active level */ -#define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4 - consecutive samples at the active level */ -#define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8 - consecutive samples at the active leve. */ -#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \ - ((FILTER) == RTC_TamperFilter_2Sample) || \ - ((FILTER) == RTC_TamperFilter_4Sample) || \ - ((FILTER) == RTC_TamperFilter_8Sample)) -/** - * @} - */ - -/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions - * @{ - */ -#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 32768 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 16384 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 8192 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 4096 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 2048 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 1024 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 512 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 256 */ -#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256)) - -/** - * @} - */ - - /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions - * @{ - */ -#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before - sampling during 1 RTCCLK cycle */ -#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before - sampling during 2 RTCCLK cycles */ -#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before - sampling during 4 RTCCLK cycles */ -#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before - sampling during 8 RTCCLK cycles */ - -#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \ - ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \ - ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \ - ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK)) -/** - * @} - */ - -/** @defgroup RTC_Tamper_Pins_Definitions - * @{ - */ -#define RTC_Tamper_1 RTC_TAFCR_TAMP1E -#define IS_RTC_TAMPER(TAMPER) (((TAMPER) == RTC_Tamper_1)) - -/** - * @} - */ - -/** @defgroup RTC_Tamper_Pin_Selection - * @{ - */ -#define RTC_TamperPin_PC13 ((uint32_t)0x00000000) -#define RTC_TamperPin_PI8 ((uint32_t)0x00010000) -#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TamperPin_PC13) || \ - ((PIN) == RTC_TamperPin_PI8)) -/** - * @} - */ - -/** @defgroup RTC_TimeStamp_Pin_Selection - * @{ - */ -#define RTC_TimeStampPin_PC13 ((uint32_t)0x00000000) -#define RTC_TimeStampPin_PI8 ((uint32_t)0x00020000) -#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TimeStampPin_PC13) || \ - ((PIN) == RTC_TimeStampPin_PI8)) -/** - * @} - */ - -/** @defgroup RTC_Output_Type_ALARM_OUT - * @{ - */ -#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000) -#define RTC_OutputType_PushPull ((uint32_t)0x00040000) -#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \ - ((TYPE) == RTC_OutputType_PushPull)) - -/** - * @} - */ - -/** @defgroup RTC_Add_1_Second_Parameter_Definitions - * @{ - */ -#define RTC_ShiftAdd1S_Reset ((uint32_t)0x00000000) -#define RTC_ShiftAdd1S_Set ((uint32_t)0x80000000) -#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \ - ((SEL) == RTC_ShiftAdd1S_Set)) -/** - * @} - */ - -/** @defgroup RTC_Substract_Fraction_Of_Second_Value - * @{ - */ -#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF) - -/** - * @} - */ - -/** @defgroup RTC_Backup_Registers_Definitions - * @{ - */ - -#define RTC_BKP_DR0 ((uint32_t)0x00000000) -#define RTC_BKP_DR1 ((uint32_t)0x00000001) -#define RTC_BKP_DR2 ((uint32_t)0x00000002) -#define RTC_BKP_DR3 ((uint32_t)0x00000003) -#define RTC_BKP_DR4 ((uint32_t)0x00000004) -#define RTC_BKP_DR5 ((uint32_t)0x00000005) -#define RTC_BKP_DR6 ((uint32_t)0x00000006) -#define RTC_BKP_DR7 ((uint32_t)0x00000007) -#define RTC_BKP_DR8 ((uint32_t)0x00000008) -#define RTC_BKP_DR9 ((uint32_t)0x00000009) -#define RTC_BKP_DR10 ((uint32_t)0x0000000A) -#define RTC_BKP_DR11 ((uint32_t)0x0000000B) -#define RTC_BKP_DR12 ((uint32_t)0x0000000C) -#define RTC_BKP_DR13 ((uint32_t)0x0000000D) -#define RTC_BKP_DR14 ((uint32_t)0x0000000E) -#define RTC_BKP_DR15 ((uint32_t)0x0000000F) -#define RTC_BKP_DR16 ((uint32_t)0x00000010) -#define RTC_BKP_DR17 ((uint32_t)0x00000011) -#define RTC_BKP_DR18 ((uint32_t)0x00000012) -#define RTC_BKP_DR19 ((uint32_t)0x00000013) -#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \ - ((BKP) == RTC_BKP_DR1) || \ - ((BKP) == RTC_BKP_DR2) || \ - ((BKP) == RTC_BKP_DR3) || \ - ((BKP) == RTC_BKP_DR4) || \ - ((BKP) == RTC_BKP_DR5) || \ - ((BKP) == RTC_BKP_DR6) || \ - ((BKP) == RTC_BKP_DR7) || \ - ((BKP) == RTC_BKP_DR8) || \ - ((BKP) == RTC_BKP_DR9) || \ - ((BKP) == RTC_BKP_DR10) || \ - ((BKP) == RTC_BKP_DR11) || \ - ((BKP) == RTC_BKP_DR12) || \ - ((BKP) == RTC_BKP_DR13) || \ - ((BKP) == RTC_BKP_DR14) || \ - ((BKP) == RTC_BKP_DR15) || \ - ((BKP) == RTC_BKP_DR16) || \ - ((BKP) == RTC_BKP_DR17) || \ - ((BKP) == RTC_BKP_DR18) || \ - ((BKP) == RTC_BKP_DR19)) -/** - * @} - */ - -/** @defgroup RTC_Input_parameter_format_definitions - * @{ - */ -#define RTC_Format_BIN ((uint32_t)0x000000000) -#define RTC_Format_BCD ((uint32_t)0x000000001) -#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD)) - -/** - * @} - */ - -/** @defgroup RTC_Flags_Definitions - * @{ - */ -#define RTC_FLAG_RECALPF ((uint32_t)0x00010000) -#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000) -#define RTC_FLAG_TSOVF ((uint32_t)0x00001000) -#define RTC_FLAG_TSF ((uint32_t)0x00000800) -#define RTC_FLAG_WUTF ((uint32_t)0x00000400) -#define RTC_FLAG_ALRBF ((uint32_t)0x00000200) -#define RTC_FLAG_ALRAF ((uint32_t)0x00000100) -#define RTC_FLAG_INITF ((uint32_t)0x00000040) -#define RTC_FLAG_RSF ((uint32_t)0x00000020) -#define RTC_FLAG_INITS ((uint32_t)0x00000010) -#define RTC_FLAG_SHPF ((uint32_t)0x00000008) -#define RTC_FLAG_WUTWF ((uint32_t)0x00000004) -#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002) -#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001) -#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \ - ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \ - ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \ - ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \ - ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \ - ((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_RECALPF) || \ - ((FLAG) == RTC_FLAG_SHPF)) -#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET)) -/** - * @} - */ - -/** @defgroup RTC_Interrupts_Definitions - * @{ - */ -#define RTC_IT_TS ((uint32_t)0x00008000) -#define RTC_IT_WUT ((uint32_t)0x00004000) -#define RTC_IT_ALRB ((uint32_t)0x00002000) -#define RTC_IT_ALRA ((uint32_t)0x00001000) -#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */ -#define RTC_IT_TAMP1 ((uint32_t)0x00020000) - -#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET)) -#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \ - ((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \ - ((IT) == RTC_IT_TAMP1)) -#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFD0FFF) == (uint32_t)RESET)) - -/** - * @} - */ - -/** @defgroup RTC_Legacy - * @{ - */ -#define RTC_DigitalCalibConfig RTC_CoarseCalibConfig -#define RTC_DigitalCalibCmd RTC_CoarseCalibCmd - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the RTC configuration to the default reset state *****/ -ErrorStatus RTC_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct); -void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct); -void RTC_WriteProtectionCmd(FunctionalState NewState); -ErrorStatus RTC_EnterInitMode(void); -void RTC_ExitInitMode(void); -ErrorStatus RTC_WaitForSynchro(void); -ErrorStatus RTC_RefClockCmd(FunctionalState NewState); -void RTC_BypassShadowCmd(FunctionalState NewState); - -/* Time and Date configuration functions **************************************/ -ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); -void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct); -void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); -uint32_t RTC_GetSubSecond(void); -ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); -void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct); -void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); - -/* Alarms (Alarm A and Alarm B) configuration functions **********************/ -void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); -void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct); -void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); -ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState); -void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask); -uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm); - -/* WakeUp Timer configuration functions ***************************************/ -void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock); -void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter); -uint32_t RTC_GetWakeUpCounter(void); -ErrorStatus RTC_WakeUpCmd(FunctionalState NewState); - -/* Daylight Saving configuration functions ************************************/ -void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation); -uint32_t RTC_GetStoreOperation(void); - -/* Output pin Configuration function ******************************************/ -void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity); - -/* Digital Calibration configuration functions *********************************/ -ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value); -ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState); -void RTC_CalibOutputCmd(FunctionalState NewState); -void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput); -ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, - uint32_t RTC_SmoothCalibPlusPulses, - uint32_t RTC_SmouthCalibMinusPulsesValue); - -/* TimeStamp configuration functions ******************************************/ -void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState); -void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, - RTC_DateTypeDef* RTC_StampDateStruct); -uint32_t RTC_GetTimeStampSubSecond(void); - -/* Tampers configuration functions ********************************************/ -void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger); -void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState); -void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter); -void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq); -void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration); -void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState); -void RTC_TamperPullUpCmd(FunctionalState NewState); - -/* Backup Data Registers configuration functions ******************************/ -void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data); -uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR); - -/* RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration - functions ******************************************************************/ -void RTC_TamperPinSelection(uint32_t RTC_TamperPin); -void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin); -void RTC_OutputTypeConfig(uint32_t RTC_OutputType); - -/* RTC_Shift_control_synchonisation_functions *********************************/ -ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS); - -/* Interrupts and flags management functions **********************************/ -void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState); -FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG); -void RTC_ClearFlag(uint32_t RTC_FLAG); -ITStatus RTC_GetITStatus(uint32_t RTC_IT); -void RTC_ClearITPendingBit(uint32_t RTC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_RTC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm32f4xx_sdio.c b/stm/stmperiph/stm32f4xx_sdio.c deleted file mode 100644 index aead846a1..000000000 --- a/stm/stmperiph/stm32f4xx_sdio.c +++ /dev/null @@ -1,1011 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_sdio.c - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief This file provides firmware functions to manage the following - * functionalities of the Secure digital input/output interface (SDIO) - * peripheral: - * + Initialization and Configuration - * + Command path state machine (CPSM) management - * + Data path state machine (DPSM) management - * + SDIO IO Cards mode management - * + CE-ATA mode management - * + DMA transfers management - * + Interrupts and flags management - * -@verbatim - - =================================================================== - ##### How to use this driver ##### - =================================================================== - [..] - (#) The SDIO clock (SDIOCLK = 48 MHz) is coming from a specific output of PLL - (PLL48CLK). Before to start working with SDIO peripheral make sure that the - PLL is well configured. - The SDIO peripheral uses two clock signals: - (++) SDIO adapter clock (SDIOCLK = 48 MHz) - (++) APB2 bus clock (PCLK2) - - -@@- PCLK2 and SDIO_CK clock frequencies must respect the following condition: - Frequency(PCLK2) >= (3 / 8 x Frequency(SDIO_CK)) - - (#) Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE). - - (#) According to the SDIO mode, enable the GPIO clocks using - RCC_AHB1PeriphClockCmd() function. - The I/O can be one of the following configurations: - (++) 1-bit data length: SDIO_CMD, SDIO_CK and D0. - (++) 4-bit data length: SDIO_CMD, SDIO_CK and D[3:0]. - (++) 8-bit data length: SDIO_CMD, SDIO_CK and D[7:0]. - - (#) Peripheral alternate function: - (++) Connect the pin to the desired peripherals' Alternate Function (AF) - using GPIO_PinAFConfig() function - (++) Configure the desired pin in alternate function by: - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - (++) Select the type, pull-up/pull-down and output speed via GPIO_PuPd, - GPIO_OType and GPIO_Speed members - (++) Call GPIO_Init() function - - (#) Program the Clock Edge, Clock Bypass, Clock Power Save, Bus Wide, - hardware, flow control and the Clock Divider using the SDIO_Init() - function. - - (#) Enable the Power ON State using the SDIO_SetPowerState(SDIO_PowerState_ON) - function. - - (#) Enable the clock using the SDIO_ClockCmd() function. - - (#) Enable the NVIC and the corresponding interrupt using the function - SDIO_ITConfig() if you need to use interrupt mode. - - (#) When using the DMA mode - (++) Configure the DMA using DMA_Init() function - (++) Active the needed channel Request using SDIO_DMACmd() function - - (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode. - - (#) To control the CPSM (Command Path State Machine) and send - commands to the card use the SDIO_SendCommand(), - SDIO_GetCommandResponse() and SDIO_GetResponse() functions. First, user has - to fill the command structure (pointer to SDIO_CmdInitTypeDef) according - to the selected command to be sent. - The parameters that should be filled are: - (++) Command Argument - (++) Command Index - (++) Command Response type - (++) Command Wait - (++) CPSM Status (Enable or Disable). - - -@@- To check if the command is well received, read the SDIO_CMDRESP - register using the SDIO_GetCommandResponse(). - The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the - SDIO_GetResponse() function. - - (#) To control the DPSM (Data Path State Machine) and send/receive - data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(), - SDIO_ReadData(), SDIO_WriteData() and SDIO_GetFIFOCount() functions. - - *** Read Operations *** - ======================= - [..] - (#) First, user has to fill the data structure (pointer to - SDIO_DataInitTypeDef) according to the selected data type to be received. - The parameters that should be filled are: - (++) Data TimeOut - (++) Data Length - (++) Data Block size - (++) Data Transfer direction: should be from card (To SDIO) - (++) Data Transfer mode - (++) DPSM Status (Enable or Disable) - - (#) Configure the SDIO resources to receive the data from the card - according to selected transfer mode (Refer to Step 8, 9 and 10). - - (#) Send the selected Read command (refer to step 11). - - (#) Use the SDIO flags/interrupts to check the transfer status. - - *** Write Operations *** - ======================== - [..] - (#) First, user has to fill the data structure (pointer to - SDIO_DataInitTypeDef) according to the selected data type to be received. - The parameters that should be filled are: - (++) Data TimeOut - (++) Data Length - (++) Data Block size - (++) Data Transfer direction: should be to card (To CARD) - (++) Data Transfer mode - (++) DPSM Status (Enable or Disable) - - (#) Configure the SDIO resources to send the data to the card according to - selected transfer mode (Refer to Step 8, 9 and 10). - - (#) Send the selected Write command (refer to step 11). - - (#) Use the SDIO flags/interrupts to check the transfer status. - - -@endverbatim - * - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_sdio.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup SDIO - * @brief SDIO driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* ------------ SDIO registers bit address in the alias region ----------- */ -#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) - -/* --- CLKCR Register ---*/ -/* Alias word address of CLKEN bit */ -#define CLKCR_OFFSET (SDIO_OFFSET + 0x04) -#define CLKEN_BitNumber 0x08 -#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4)) - -/* --- CMD Register ---*/ -/* Alias word address of SDIOSUSPEND bit */ -#define CMD_OFFSET (SDIO_OFFSET + 0x0C) -#define SDIOSUSPEND_BitNumber 0x0B -#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4)) - -/* Alias word address of ENCMDCOMPL bit */ -#define ENCMDCOMPL_BitNumber 0x0C -#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4)) - -/* Alias word address of NIEN bit */ -#define NIEN_BitNumber 0x0D -#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4)) - -/* Alias word address of ATACMD bit */ -#define ATACMD_BitNumber 0x0E -#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4)) - -/* --- DCTRL Register ---*/ -/* Alias word address of DMAEN bit */ -#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) -#define DMAEN_BitNumber 0x03 -#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4)) - -/* Alias word address of RWSTART bit */ -#define RWSTART_BitNumber 0x08 -#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4)) - -/* Alias word address of RWSTOP bit */ -#define RWSTOP_BitNumber 0x09 -#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4)) - -/* Alias word address of RWMOD bit */ -#define RWMOD_BitNumber 0x0A -#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4)) - -/* Alias word address of SDIOEN bit */ -#define SDIOEN_BitNumber 0x0B -#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4)) - -/* ---------------------- SDIO registers bit mask ------------------------ */ -/* --- CLKCR Register ---*/ -/* CLKCR register clear mask */ -#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) - -/* --- PWRCTRL Register ---*/ -/* SDIO PWRCTRL Mask */ -#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC) - -/* --- DCTRL Register ---*/ -/* SDIO DCTRL Clear Mask */ -#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08) - -/* --- CMD Register ---*/ -/* CMD Register clear mask */ -#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800) - -/* SDIO RESP Registers Address */ -#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup SDIO_Private_Functions - * @{ - */ - -/** @defgroup SDIO_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the SDIO peripheral registers to their default reset values. - * @param None - * @retval None - */ -void SDIO_DeInit(void) -{ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, DISABLE); -} - -/** - * @brief Initializes the SDIO peripheral according to the specified - * parameters in the SDIO_InitStruct. - * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure - * that contains the configuration information for the SDIO peripheral. - * @retval None - */ -void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge)); - assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass)); - assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave)); - assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide)); - assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); - -/*---------------------------- SDIO CLKCR Configuration ------------------------*/ - /* Get the SDIO CLKCR value */ - tmpreg = SDIO->CLKCR; - - /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */ - tmpreg &= CLKCR_CLEAR_MASK; - - /* Set CLKDIV bits according to SDIO_ClockDiv value */ - /* Set PWRSAV bit according to SDIO_ClockPowerSave value */ - /* Set BYPASS bit according to SDIO_ClockBypass value */ - /* Set WIDBUS bits according to SDIO_BusWide value */ - /* Set NEGEDGE bits according to SDIO_ClockEdge value */ - /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */ - tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave | - SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide | - SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); - - /* Write to SDIO CLKCR */ - SDIO->CLKCR = tmpreg; -} - -/** - * @brief Fills each SDIO_InitStruct member with its default value. - * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which - * will be initialized. - * @retval None - */ -void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct) -{ - /* SDIO_InitStruct members default value */ - SDIO_InitStruct->SDIO_ClockDiv = 0x00; - SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising; - SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable; - SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; - SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b; - SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; -} - -/** - * @brief Enables or disables the SDIO Clock. - * @param NewState: new state of the SDIO Clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_ClockCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState; -} - -/** - * @brief Sets the power status of the controller. - * @param SDIO_PowerState: new state of the Power state. - * This parameter can be one of the following values: - * @arg SDIO_PowerState_OFF: SDIO Power OFF - * @arg SDIO_PowerState_ON: SDIO Power ON - * @retval None - */ -void SDIO_SetPowerState(uint32_t SDIO_PowerState) -{ - /* Check the parameters */ - assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState)); - - SDIO->POWER = SDIO_PowerState; -} - -/** - * @brief Gets the power status of the controller. - * @param None - * @retval Power status of the controller. The returned value can be one of the - * following values: - * - 0x00: Power OFF - * - 0x02: Power UP - * - 0x03: Power ON - */ -uint32_t SDIO_GetPowerState(void) -{ - return (SDIO->POWER & (~PWR_PWRCTRL_MASK)); -} - -/** - * @} - */ - -/** @defgroup SDIO_Group2 Command path state machine (CPSM) management functions - * @brief Command path state machine (CPSM) management functions - * -@verbatim - =============================================================================== - ##### Command path state machine (CPSM) management functions ##### - =============================================================================== - - This section provide functions allowing to program and read the Command path - state machine (CPSM). - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the SDIO Command according to the specified - * parameters in the SDIO_CmdInitStruct and send the command. - * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef - * structure that contains the configuration information for the SDIO - * command. - * @retval None - */ -void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex)); - assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response)); - assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait)); - assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM)); - -/*---------------------------- SDIO ARG Configuration ------------------------*/ - /* Set the SDIO Argument value */ - SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument; - -/*---------------------------- SDIO CMD Configuration ------------------------*/ - /* Get the SDIO CMD value */ - tmpreg = SDIO->CMD; - /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */ - tmpreg &= CMD_CLEAR_MASK; - /* Set CMDINDEX bits according to SDIO_CmdIndex value */ - /* Set WAITRESP bits according to SDIO_Response value */ - /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */ - /* Set CPSMEN bits according to SDIO_CPSM value */ - tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response - | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM; - - /* Write to SDIO CMD */ - SDIO->CMD = tmpreg; -} - -/** - * @brief Fills each SDIO_CmdInitStruct member with its default value. - * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef - * structure which will be initialized. - * @retval None - */ -void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct) -{ - /* SDIO_CmdInitStruct members default value */ - SDIO_CmdInitStruct->SDIO_Argument = 0x00; - SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00; - SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No; - SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable; -} - -/** - * @brief Returns command index of last command for which response received. - * @param None - * @retval Returns the command index of the last command response received. - */ -uint8_t SDIO_GetCommandResponse(void) -{ - return (uint8_t)(SDIO->RESPCMD); -} - -/** - * @brief Returns response received from the card for the last command. - * @param SDIO_RESP: Specifies the SDIO response register. - * This parameter can be one of the following values: - * @arg SDIO_RESP1: Response Register 1 - * @arg SDIO_RESP2: Response Register 2 - * @arg SDIO_RESP3: Response Register 3 - * @arg SDIO_RESP4: Response Register 4 - * @retval The Corresponding response register value. - */ -uint32_t SDIO_GetResponse(uint32_t SDIO_RESP) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_RESP(SDIO_RESP)); - - tmp = SDIO_RESP_ADDR + SDIO_RESP; - - return (*(__IO uint32_t *) tmp); -} - -/** - * @} - */ - -/** @defgroup SDIO_Group3 Data path state machine (DPSM) management functions - * @brief Data path state machine (DPSM) management functions - * -@verbatim - =============================================================================== - ##### Data path state machine (DPSM) management functions ##### - =============================================================================== - - This section provide functions allowing to program and read the Data path - state machine (DPSM). - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the SDIO data path according to the specified - * parameters in the SDIO_DataInitStruct. - * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure - * that contains the configuration information for the SDIO command. - * @retval None - */ -void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength)); - assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize)); - assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir)); - assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode)); - assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM)); - -/*---------------------------- SDIO DTIMER Configuration ---------------------*/ - /* Set the SDIO Data TimeOut value */ - SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut; - -/*---------------------------- SDIO DLEN Configuration -----------------------*/ - /* Set the SDIO DataLength value */ - SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength; - -/*---------------------------- SDIO DCTRL Configuration ----------------------*/ - /* Get the SDIO DCTRL value */ - tmpreg = SDIO->DCTRL; - /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */ - tmpreg &= DCTRL_CLEAR_MASK; - /* Set DEN bit according to SDIO_DPSM value */ - /* Set DTMODE bit according to SDIO_TransferMode value */ - /* Set DTDIR bit according to SDIO_TransferDir value */ - /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */ - tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir - | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM; - - /* Write to SDIO DCTRL */ - SDIO->DCTRL = tmpreg; -} - -/** - * @brief Fills each SDIO_DataInitStruct member with its default value. - * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure - * which will be initialized. - * @retval None - */ -void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct) -{ - /* SDIO_DataInitStruct members default value */ - SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF; - SDIO_DataInitStruct->SDIO_DataLength = 0x00; - SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b; - SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard; - SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; - SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable; -} - -/** - * @brief Returns number of remaining data bytes to be transferred. - * @param None - * @retval Number of remaining data bytes to be transferred - */ -uint32_t SDIO_GetDataCounter(void) -{ - return SDIO->DCOUNT; -} - -/** - * @brief Read one data word from Rx FIFO. - * @param None - * @retval Data received - */ -uint32_t SDIO_ReadData(void) -{ - return SDIO->FIFO; -} - -/** - * @brief Write one data word to Tx FIFO. - * @param Data: 32-bit data word to write. - * @retval None - */ -void SDIO_WriteData(uint32_t Data) -{ - SDIO->FIFO = Data; -} - -/** - * @brief Returns the number of words left to be written to or read from FIFO. - * @param None - * @retval Remaining number of words. - */ -uint32_t SDIO_GetFIFOCount(void) -{ - return SDIO->FIFOCNT; -} - -/** - * @} - */ - -/** @defgroup SDIO_Group4 SDIO IO Cards mode management functions - * @brief SDIO IO Cards mode management functions - * -@verbatim - =============================================================================== - ##### SDIO IO Cards mode management functions ##### - =============================================================================== - - This section provide functions allowing to program and read the SDIO IO Cards. - -@endverbatim - * @{ - */ - -/** - * @brief Starts the SD I/O Read Wait operation. - * @param NewState: new state of the Start SDIO Read Wait operation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_StartSDIOReadWait(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState; -} - -/** - * @brief Stops the SD I/O Read Wait operation. - * @param NewState: new state of the Stop SDIO Read Wait operation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_StopSDIOReadWait(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState; -} - -/** - * @brief Sets one of the two options of inserting read wait interval. - * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode. - * This parameter can be: - * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK - * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2 - * @retval None - */ -void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) -{ - /* Check the parameters */ - assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode)); - - *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode; -} - -/** - * @brief Enables or disables the SD I/O Mode Operation. - * @param NewState: new state of SDIO specific operation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SetSDIOOperation(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the SD I/O Mode suspend command sending. - * @param NewState: new state of the SD I/O Mode suspend command. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SendSDIOSuspendCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup SDIO_Group5 CE-ATA mode management functions - * @brief CE-ATA mode management functions - * -@verbatim - =============================================================================== - ##### CE-ATA mode management functions ##### - =============================================================================== - - This section provide functions allowing to program and read the CE-ATA card. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the command completion signal. - * @param NewState: new state of command completion signal. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_CommandCompletionCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the CE-ATA interrupt. - * @param NewState: new state of CE-ATA interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_CEATAITCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1)); -} - -/** - * @brief Sends CE-ATA command (CMD61). - * @param NewState: new state of CE-ATA command. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SendCEATACmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup SDIO_Group6 DMA transfers management functions - * @brief DMA transfers management functions - * -@verbatim - =============================================================================== - ##### DMA transfers management functions ##### - =============================================================================== - - This section provide functions allowing to program SDIO DMA transfer. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the SDIO DMA request. - * @param NewState: new state of the selected SDIO DMA request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_DMACmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup SDIO_Group7 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the SDIO interrupts. - * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled. - * This parameter can be one or a combination of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt - * @arg SDIO_IT_TXACT: Data transmit in progress interrupt - * @arg SDIO_IT_RXACT: Data receive in progress interrupt - * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt - * @param NewState: new state of the specified SDIO interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SDIO_IT(SDIO_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the SDIO interrupts */ - SDIO->MASK |= SDIO_IT; - } - else - { - /* Disable the SDIO interrupts */ - SDIO->MASK &= ~SDIO_IT; - } -} - -/** - * @brief Checks whether the specified SDIO flag is set or not. - * @param SDIO_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDIO_FLAG_CTIMEOUT: Command response timeout - * @arg SDIO_FLAG_DTIMEOUT: Data timeout - * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) - * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) - * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode. - * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDIO_FLAG_CMDACT: Command transfer in progress - * @arg SDIO_FLAG_TXACT: Data transmit in progress - * @arg SDIO_FLAG_RXACT: Data receive in progress - * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty - * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full - * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full - * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full - * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty - * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty - * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO - * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO - * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received - * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval The new state of SDIO_FLAG (SET or RESET). - */ -FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_SDIO_FLAG(SDIO_FLAG)); - - if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the SDIO's pending flags. - * @param SDIO_FLAG: specifies the flag to clear. - * This parameter can be one or a combination of the following values: - * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDIO_FLAG_CTIMEOUT: Command response timeout - * @arg SDIO_FLAG_DTIMEOUT: Data timeout - * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) - * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) - * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode - * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received - * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval None - */ -void SDIO_ClearFlag(uint32_t SDIO_FLAG) -{ - /* Check the parameters */ - assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG)); - - SDIO->ICR = SDIO_FLAG; -} - -/** - * @brief Checks whether the specified SDIO interrupt has occurred or not. - * @param SDIO_IT: specifies the SDIO interrupt source to check. - * This parameter can be one of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt - * @arg SDIO_IT_TXACT: Data transmit in progress interrupt - * @arg SDIO_IT_RXACT: Data receive in progress interrupt - * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt - * @retval The new state of SDIO_IT (SET or RESET). - */ -ITStatus SDIO_GetITStatus(uint32_t SDIO_IT) -{ - ITStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_SDIO_GET_IT(SDIO_IT)); - if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the SDIO's interrupt pending bits. - * @param SDIO_IT: specifies the interrupt pending bit to clear. - * This parameter can be one or a combination of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval None - */ -void SDIO_ClearITPendingBit(uint32_t SDIO_IT) -{ - /* Check the parameters */ - assert_param(IS_SDIO_CLEAR_IT(SDIO_IT)); - - SDIO->ICR = SDIO_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm32f4xx_sdio.h b/stm/stmperiph/stm32f4xx_sdio.h deleted file mode 100644 index 05e0afa3c..000000000 --- a/stm/stmperiph/stm32f4xx_sdio.h +++ /dev/null @@ -1,536 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_sdio.h - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief This file contains all the functions prototypes for the SDIO firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_SDIO_H -#define __STM32F4xx_SDIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SDIO - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -typedef struct -{ - uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref SDIO_Clock_Edge */ - - uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is - enabled or disabled. - This parameter can be a value of @ref SDIO_Clock_Bypass */ - - uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or - disabled when the bus is idle. - This parameter can be a value of @ref SDIO_Clock_Power_Save */ - - uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width. - This parameter can be a value of @ref SDIO_Bus_Wide */ - - uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled. - This parameter can be a value of @ref SDIO_Hardware_Flow_Control */ - - uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller. - This parameter can be a value between 0x00 and 0xFF. */ - -} SDIO_InitTypeDef; - -typedef struct -{ - uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent - to a card as part of a command message. If a command - contains an argument, it must be loaded into this register - before writing the command to the command register */ - - uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */ - - uint32_t SDIO_Response; /*!< Specifies the SDIO response type. - This parameter can be a value of @ref SDIO_Response_Type */ - - uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait for interrupt request is enabled or disabled. - This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ - - uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) - is enabled or disabled. - This parameter can be a value of @ref SDIO_CPSM_State */ -} SDIO_CmdInitTypeDef; - -typedef struct -{ - uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ - - uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */ - - uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer. - This parameter can be a value of @ref SDIO_Data_Block_Size */ - - uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer - is a read or write. - This parameter can be a value of @ref SDIO_Transfer_Direction */ - - uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode. - This parameter can be a value of @ref SDIO_Transfer_Type */ - - uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM) - is enabled or disabled. - This parameter can be a value of @ref SDIO_DPSM_State */ -} SDIO_DataInitTypeDef; - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup SDIO_Exported_Constants - * @{ - */ - -/** @defgroup SDIO_Clock_Edge - * @{ - */ - -#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000) -#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000) -#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \ - ((EDGE) == SDIO_ClockEdge_Falling)) -/** - * @} - */ - -/** @defgroup SDIO_Clock_Bypass - * @{ - */ - -#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000) -#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) -#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \ - ((BYPASS) == SDIO_ClockBypass_Enable)) -/** - * @} - */ - -/** @defgroup SDIO_Clock_Power_Save - * @{ - */ - -#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000) -#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) -#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \ - ((SAVE) == SDIO_ClockPowerSave_Enable)) -/** - * @} - */ - -/** @defgroup SDIO_Bus_Wide - * @{ - */ - -#define SDIO_BusWide_1b ((uint32_t)0x00000000) -#define SDIO_BusWide_4b ((uint32_t)0x00000800) -#define SDIO_BusWide_8b ((uint32_t)0x00001000) -#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \ - ((WIDE) == SDIO_BusWide_8b)) - -/** - * @} - */ - -/** @defgroup SDIO_Hardware_Flow_Control - * @{ - */ - -#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000) -#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000) -#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \ - ((CONTROL) == SDIO_HardwareFlowControl_Enable)) -/** - * @} - */ - -/** @defgroup SDIO_Power_State - * @{ - */ - -#define SDIO_PowerState_OFF ((uint32_t)0x00000000) -#define SDIO_PowerState_ON ((uint32_t)0x00000003) -#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) -/** - * @} - */ - - -/** @defgroup SDIO_Interrupt_sources - * @{ - */ - -#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001) -#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002) -#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004) -#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008) -#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010) -#define SDIO_IT_RXOVERR ((uint32_t)0x00000020) -#define SDIO_IT_CMDREND ((uint32_t)0x00000040) -#define SDIO_IT_CMDSENT ((uint32_t)0x00000080) -#define SDIO_IT_DATAEND ((uint32_t)0x00000100) -#define SDIO_IT_STBITERR ((uint32_t)0x00000200) -#define SDIO_IT_DBCKEND ((uint32_t)0x00000400) -#define SDIO_IT_CMDACT ((uint32_t)0x00000800) -#define SDIO_IT_TXACT ((uint32_t)0x00001000) -#define SDIO_IT_RXACT ((uint32_t)0x00002000) -#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000) -#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000) -#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000) -#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000) -#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000) -#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000) -#define SDIO_IT_TXDAVL ((uint32_t)0x00100000) -#define SDIO_IT_RXDAVL ((uint32_t)0x00200000) -#define SDIO_IT_SDIOIT ((uint32_t)0x00400000) -#define SDIO_IT_CEATAEND ((uint32_t)0x00800000) -#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00)) -/** - * @} - */ - -/** @defgroup SDIO_Command_Index - * @{ - */ - -#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) -/** - * @} - */ - -/** @defgroup SDIO_Response_Type - * @{ - */ - -#define SDIO_Response_No ((uint32_t)0x00000000) -#define SDIO_Response_Short ((uint32_t)0x00000040) -#define SDIO_Response_Long ((uint32_t)0x000000C0) -#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \ - ((RESPONSE) == SDIO_Response_Short) || \ - ((RESPONSE) == SDIO_Response_Long)) -/** - * @} - */ - -/** @defgroup SDIO_Wait_Interrupt_State - * @{ - */ - -#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */ -#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */ -#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */ -#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \ - ((WAIT) == SDIO_Wait_Pend)) -/** - * @} - */ - -/** @defgroup SDIO_CPSM_State - * @{ - */ - -#define SDIO_CPSM_Disable ((uint32_t)0x00000000) -#define SDIO_CPSM_Enable ((uint32_t)0x00000400) -#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable)) -/** - * @} - */ - -/** @defgroup SDIO_Response_Registers - * @{ - */ - -#define SDIO_RESP1 ((uint32_t)0x00000000) -#define SDIO_RESP2 ((uint32_t)0x00000004) -#define SDIO_RESP3 ((uint32_t)0x00000008) -#define SDIO_RESP4 ((uint32_t)0x0000000C) -#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \ - ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4)) -/** - * @} - */ - -/** @defgroup SDIO_Data_Length - * @{ - */ - -#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) -/** - * @} - */ - -/** @defgroup SDIO_Data_Block_Size - * @{ - */ - -#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000) -#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010) -#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020) -#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030) -#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040) -#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050) -#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060) -#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070) -#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080) -#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090) -#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0) -#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0) -#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0) -#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0) -#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0) -#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \ - ((SIZE) == SDIO_DataBlockSize_2b) || \ - ((SIZE) == SDIO_DataBlockSize_4b) || \ - ((SIZE) == SDIO_DataBlockSize_8b) || \ - ((SIZE) == SDIO_DataBlockSize_16b) || \ - ((SIZE) == SDIO_DataBlockSize_32b) || \ - ((SIZE) == SDIO_DataBlockSize_64b) || \ - ((SIZE) == SDIO_DataBlockSize_128b) || \ - ((SIZE) == SDIO_DataBlockSize_256b) || \ - ((SIZE) == SDIO_DataBlockSize_512b) || \ - ((SIZE) == SDIO_DataBlockSize_1024b) || \ - ((SIZE) == SDIO_DataBlockSize_2048b) || \ - ((SIZE) == SDIO_DataBlockSize_4096b) || \ - ((SIZE) == SDIO_DataBlockSize_8192b) || \ - ((SIZE) == SDIO_DataBlockSize_16384b)) -/** - * @} - */ - -/** @defgroup SDIO_Transfer_Direction - * @{ - */ - -#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000) -#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002) -#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \ - ((DIR) == SDIO_TransferDir_ToSDIO)) -/** - * @} - */ - -/** @defgroup SDIO_Transfer_Type - * @{ - */ - -#define SDIO_TransferMode_Block ((uint32_t)0x00000000) -#define SDIO_TransferMode_Stream ((uint32_t)0x00000004) -#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \ - ((MODE) == SDIO_TransferMode_Block)) -/** - * @} - */ - -/** @defgroup SDIO_DPSM_State - * @{ - */ - -#define SDIO_DPSM_Disable ((uint32_t)0x00000000) -#define SDIO_DPSM_Enable ((uint32_t)0x00000001) -#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable)) -/** - * @} - */ - -/** @defgroup SDIO_Flags - * @{ - */ - -#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001) -#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002) -#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004) -#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008) -#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010) -#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020) -#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040) -#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080) -#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100) -#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200) -#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400) -#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800) -#define SDIO_FLAG_TXACT ((uint32_t)0x00001000) -#define SDIO_FLAG_RXACT ((uint32_t)0x00002000) -#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000) -#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000) -#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000) -#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000) -#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000) -#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000) -#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000) -#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000) -#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000) -#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000) -#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \ - ((FLAG) == SDIO_FLAG_DCRCFAIL) || \ - ((FLAG) == SDIO_FLAG_CTIMEOUT) || \ - ((FLAG) == SDIO_FLAG_DTIMEOUT) || \ - ((FLAG) == SDIO_FLAG_TXUNDERR) || \ - ((FLAG) == SDIO_FLAG_RXOVERR) || \ - ((FLAG) == SDIO_FLAG_CMDREND) || \ - ((FLAG) == SDIO_FLAG_CMDSENT) || \ - ((FLAG) == SDIO_FLAG_DATAEND) || \ - ((FLAG) == SDIO_FLAG_STBITERR) || \ - ((FLAG) == SDIO_FLAG_DBCKEND) || \ - ((FLAG) == SDIO_FLAG_CMDACT) || \ - ((FLAG) == SDIO_FLAG_TXACT) || \ - ((FLAG) == SDIO_FLAG_RXACT) || \ - ((FLAG) == SDIO_FLAG_TXFIFOHE) || \ - ((FLAG) == SDIO_FLAG_RXFIFOHF) || \ - ((FLAG) == SDIO_FLAG_TXFIFOF) || \ - ((FLAG) == SDIO_FLAG_RXFIFOF) || \ - ((FLAG) == SDIO_FLAG_TXFIFOE) || \ - ((FLAG) == SDIO_FLAG_RXFIFOE) || \ - ((FLAG) == SDIO_FLAG_TXDAVL) || \ - ((FLAG) == SDIO_FLAG_RXDAVL) || \ - ((FLAG) == SDIO_FLAG_SDIOIT) || \ - ((FLAG) == SDIO_FLAG_CEATAEND)) - -#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00)) - -#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \ - ((IT) == SDIO_IT_DCRCFAIL) || \ - ((IT) == SDIO_IT_CTIMEOUT) || \ - ((IT) == SDIO_IT_DTIMEOUT) || \ - ((IT) == SDIO_IT_TXUNDERR) || \ - ((IT) == SDIO_IT_RXOVERR) || \ - ((IT) == SDIO_IT_CMDREND) || \ - ((IT) == SDIO_IT_CMDSENT) || \ - ((IT) == SDIO_IT_DATAEND) || \ - ((IT) == SDIO_IT_STBITERR) || \ - ((IT) == SDIO_IT_DBCKEND) || \ - ((IT) == SDIO_IT_CMDACT) || \ - ((IT) == SDIO_IT_TXACT) || \ - ((IT) == SDIO_IT_RXACT) || \ - ((IT) == SDIO_IT_TXFIFOHE) || \ - ((IT) == SDIO_IT_RXFIFOHF) || \ - ((IT) == SDIO_IT_TXFIFOF) || \ - ((IT) == SDIO_IT_RXFIFOF) || \ - ((IT) == SDIO_IT_TXFIFOE) || \ - ((IT) == SDIO_IT_RXFIFOE) || \ - ((IT) == SDIO_IT_TXDAVL) || \ - ((IT) == SDIO_IT_RXDAVL) || \ - ((IT) == SDIO_IT_SDIOIT) || \ - ((IT) == SDIO_IT_CEATAEND)) - -#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00)) - -/** - * @} - */ - -/** @defgroup SDIO_Read_Wait_Mode - * @{ - */ - -#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000) -#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001) -#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \ - ((MODE) == SDIO_ReadWaitMode_DATA2)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/* Function used to set the SDIO configuration to the default reset state ****/ -void SDIO_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); -void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct); -void SDIO_ClockCmd(FunctionalState NewState); -void SDIO_SetPowerState(uint32_t SDIO_PowerState); -uint32_t SDIO_GetPowerState(void); - -/* Command path state machine (CPSM) management functions *********************/ -void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); -void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct); -uint8_t SDIO_GetCommandResponse(void); -uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); - -/* Data path state machine (DPSM) management functions ************************/ -void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct); -void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct); -uint32_t SDIO_GetDataCounter(void); -uint32_t SDIO_ReadData(void); -void SDIO_WriteData(uint32_t Data); -uint32_t SDIO_GetFIFOCount(void); - -/* SDIO IO Cards mode management functions ************************************/ -void SDIO_StartSDIOReadWait(FunctionalState NewState); -void SDIO_StopSDIOReadWait(FunctionalState NewState); -void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); -void SDIO_SetSDIOOperation(FunctionalState NewState); -void SDIO_SendSDIOSuspendCmd(FunctionalState NewState); - -/* CE-ATA mode management functions *******************************************/ -void SDIO_CommandCompletionCmd(FunctionalState NewState); -void SDIO_CEATAITCmd(FunctionalState NewState); -void SDIO_SendCEATACmd(FunctionalState NewState); - -/* DMA transfers management functions *****************************************/ -void SDIO_DMACmd(FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState); -FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG); -void SDIO_ClearFlag(uint32_t SDIO_FLAG); -ITStatus SDIO_GetITStatus(uint32_t SDIO_IT); -void SDIO_ClearITPendingBit(uint32_t SDIO_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_SDIO_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm32f4xx_spi.c b/stm/stmperiph/stm32f4xx_spi.c deleted file mode 100644 index eb725f46e..000000000 --- a/stm/stmperiph/stm32f4xx_spi.c +++ /dev/null @@ -1,1312 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_spi.c - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief This file provides firmware functions to manage the following - * functionalities of the Serial peripheral interface (SPI): - * + Initialization and Configuration - * + Data transfers functions - * + Hardware CRC Calculation - * + DMA transfers management - * + Interrupts and flags management - * -@verbatim - - =================================================================== - ##### How to use this driver ##### - =================================================================== - [..] - (#) Enable peripheral clock using the following functions - RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE) for SPI1 - RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE) for SPI2 - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI3 - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI4 - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI5 - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI6. - - (#) Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHB1PeriphClockCmd() - function. In I2S mode, if an external clock source is used then the I2S - CKIN pin GPIO clock should also be enabled. - - (#) Peripherals alternate function: - (++) Connect the pin to the desired peripherals' Alternate Function (AF) - using GPIO_PinAFConfig() function - (++) Configure the desired pin in alternate function by: - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - (++) Select the type, pull-up/pull-down and output speed via GPIO_PuPd, - GPIO_OType and GPIO_Speed members - (++) Call GPIO_Init() function In I2S mode, if an external clock source is - used then the I2S CKIN pin should be also configured in Alternate - function Push-pull pull-up mode. - - (#) Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave - Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() - function. - In I2S mode, program the Mode, Standard, Data Format, MCLK Output, Audio - frequency and Polarity using I2S_Init() function. For I2S mode, make sure - that either: - (++) I2S PLL is configured using the functions - RCC_I2SCLKConfig(RCC_I2S2CLKSource_PLLI2S), RCC_PLLI2SCmd(ENABLE) and - RCC_GetFlagStatus(RCC_FLAG_PLLI2SRDY); or - (++) External clock source is configured using the function - RCC_I2SCLKConfig(RCC_I2S2CLKSource_Ext) and after setting correctly - the define constant I2S_EXTERNAL_CLOCK_VAL in the stm32f4xx_conf.h file. - - (#) Enable the NVIC and the corresponding interrupt using the function - SPI_ITConfig() if you need to use interrupt mode. - - (#) When using the DMA mode - (++) Configure the DMA using DMA_Init() function - (++) Active the needed channel Request using SPI_I2S_DMACmd() function - - (#) Enable the SPI using the SPI_Cmd() function or enable the I2S using - I2S_Cmd(). - - (#) Enable the DMA using the DMA_Cmd() function when using DMA mode. - - (#) Optionally, you can enable/configure the following parameters without - re-initialization (i.e there is no need to call again SPI_Init() function): - (++) When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx) - is programmed as Data direction parameter using the SPI_Init() function - it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx - using the SPI_BiDirectionalLineConfig() function. - (++) When SPI_NSS_Soft is selected as Slave Select Management parameter - using the SPI_Init() function it can be possible to manage the - NSS internal signal using the SPI_NSSInternalSoftwareConfig() function. - (++) Reconfigure the data size using the SPI_DataSizeConfig() function - (++) Enable or disable the SS output using the SPI_SSOutputCmd() function - - (#) To use the CRC Hardware calculation feature refer to the Peripheral - CRC hardware Calculation subsection. - - - [..] It is possible to use SPI in I2S full duplex mode, in this case, each SPI - peripheral is able to manage sending and receiving data simultaneously - using two data lines. Each SPI peripheral has an extended block called I2Sxext - (ie. I2S2ext for SPI2 and I2S3ext for SPI3). - The extension block is not a full SPI IP, it is used only as I2S slave to - implement full duplex mode. The extension block uses the same clock sources - as its master. - To configure I2S full duplex you have to: - - (#) Configure SPIx in I2S mode (I2S_Init() function) as described above. - - (#) Call the I2S_FullDuplexConfig() function using the same strucutre passed to - I2S_Init() function. - - (#) Call I2S_Cmd() for SPIx then for its extended block. - - (#) To configure interrupts or DMA requests and to get/clear flag status, - use I2Sxext instance for the extension block. - - [..] Functions that can be called with I2Sxext instances are: I2S_Cmd(), - I2S_FullDuplexConfig(), SPI_I2S_ReceiveData(), SPI_I2S_SendData(), - SPI_I2S_DMACmd(), SPI_I2S_ITConfig(), SPI_I2S_GetFlagStatus(), - SPI_I2S_ClearFlag(), SPI_I2S_GetITStatus() and SPI_I2S_ClearITPendingBit(). - - Example: To use SPI3 in Full duplex mode (SPI3 is Master Tx, I2S3ext is Slave Rx): - - RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE); - I2S_StructInit(&I2SInitStruct); - I2SInitStruct.Mode = I2S_Mode_MasterTx; - I2S_Init(SPI3, &I2SInitStruct); - I2S_FullDuplexConfig(SPI3ext, &I2SInitStruct) - I2S_Cmd(SPI3, ENABLE); - I2S_Cmd(SPI3ext, ENABLE); - ... - while (SPI_I2S_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET) - {} - SPI_I2S_SendData(SPI3, txdata[i]); - ... - while (SPI_I2S_GetFlagStatus(I2S3ext, SPI_FLAG_RXNE) == RESET) - {} - rxdata[i] = SPI_I2S_ReceiveData(I2S3ext); - ... - - [..] - (@) In I2S mode: if an external clock is used as source clock for the I2S, - then the define I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should - be enabled and set to the value of the source clock frequency (in Hz). - - (@) In SPI mode: To use the SPI TI mode, call the function SPI_TIModeCmd() - just after calling the function SPI_Init(). - -@endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_spi.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup SPI - * @brief SPI driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* SPI registers Masks */ -#define CR1_CLEAR_MASK ((uint16_t)0x3040) -#define I2SCFGR_CLEAR_MASK ((uint16_t)0xF040) - -/* RCC PLLs masks */ -#define PLLCFGR_PPLR_MASK ((uint32_t)0x70000000) -#define PLLCFGR_PPLN_MASK ((uint32_t)0x00007FC0) - -#define SPI_CR2_FRF ((uint16_t)0x0010) -#define SPI_SR_TIFRFE ((uint16_t)0x0100) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup SPI_Private_Functions - * @{ - */ - -/** @defgroup SPI_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides a set of functions allowing to initialize the SPI - Direction, SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS - Management, SPI Baud Rate Prescaler, SPI First Bit and SPI CRC Polynomial. - - [..] The SPI_Init() function follows the SPI configuration procedures for Master - mode and Slave mode (details for these procedures are available in reference - manual (RM0090)). - -@endverbatim - * @{ - */ - -/** - * @brief De-initialize the SPIx peripheral registers to their default reset values. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 - * in SPI mode or 2 or 3 in I2S mode. - * - * @note The extended I2S blocks (ie. I2S2ext and I2S3ext blocks) are de-initialized - * when the relative I2S peripheral is de-initialized (the extended block's clock - * is managed by the I2S peripheral clock). - * - * @retval None - */ -void SPI_I2S_DeInit(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - if (SPIx == SPI1) - { - /* Enable SPI1 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); - /* Release SPI1 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); - } - else if (SPIx == SPI2) - { - /* Enable SPI2 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); - /* Release SPI2 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); - } - else if (SPIx == SPI3) - { - /* Enable SPI3 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); - /* Release SPI3 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); - } - else if (SPIx == SPI4) - { - /* Enable SPI4 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI4, ENABLE); - /* Release SPI4 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI4, DISABLE); - } - else if (SPIx == SPI5) - { - /* Enable SPI5 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI5, ENABLE); - /* Release SPI5 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI5, DISABLE); - } - else - { - if (SPIx == SPI6) - { - /* Enable SPI6 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI6, ENABLE); - /* Release SPI6 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI6, DISABLE); - } - } -} - -/** - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the SPI_InitStruct. - * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. - * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral. - * @retval None - */ -void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) -{ - uint16_t tmpreg = 0; - - /* check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Check the SPI parameters */ - assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); - assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); - assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize)); - assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); - assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); - assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); - assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); - assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); - assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); - -/*---------------------------- SPIx CR1 Configuration ------------------------*/ - /* Get the SPIx CR1 value */ - tmpreg = SPIx->CR1; - /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ - tmpreg &= CR1_CLEAR_MASK; - /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler - master/salve mode, CPOL and CPHA */ - /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ - /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ - /* Set LSBFirst bit according to SPI_FirstBit value */ - /* Set BR bits according to SPI_BaudRatePrescaler value */ - /* Set CPOL bit according to SPI_CPOL value */ - /* Set CPHA bit according to SPI_CPHA value */ - tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | - SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | - SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | - SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); - /* Write to SPIx CR1 */ - SPIx->CR1 = tmpreg; - - /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ - SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD); -/*---------------------------- SPIx CRCPOLY Configuration --------------------*/ - /* Write to SPIx CRCPOLY */ - SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; -} - -/** - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the I2S_InitStruct. - * @param SPIx: where x can be 2 or 3 to select the SPI peripheral (configured in I2S mode). - * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral - * configured in I2S mode. - * - * @note The function calculates the optimal prescaler needed to obtain the most - * accurate audio frequency (depending on the I2S clock source, the PLL values - * and the product configuration). But in case the prescaler value is greater - * than 511, the default value (0x02) will be configured instead. - * - * @note if an external clock is used as source clock for the I2S, then the define - * I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should be enabled and set - * to the value of the the source clock frequency (in Hz). - * - * @retval None - */ -void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) -{ - uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; - uint32_t tmp = 0, i2sclk = 0; -#ifndef I2S_EXTERNAL_CLOCK_VAL - uint32_t pllm = 0, plln = 0, pllr = 0; -#endif /* I2S_EXTERNAL_CLOCK_VAL */ - - /* Check the I2S parameters */ - assert_param(IS_SPI_23_PERIPH(SPIx)); - assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); - assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); - assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); - assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput)); - assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq)); - assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); - -/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ - /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ - SPIx->I2SCFGR &= I2SCFGR_CLEAR_MASK; - SPIx->I2SPR = 0x0002; - - /* Get the I2SCFGR register value */ - tmpreg = SPIx->I2SCFGR; - - /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ - if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) - { - i2sodd = (uint16_t)0; - i2sdiv = (uint16_t)2; - } - /* If the requested audio frequency is not the default, compute the prescaler */ - else - { - /* Check the frame length (For the Prescaler computing) *******************/ - if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) - { - /* Packet length is 16 bits */ - packetlength = 1; - } - else - { - /* Packet length is 32 bits */ - packetlength = 2; - } - - /* Get I2S source Clock frequency ****************************************/ - - /* If an external I2S clock has to be used, this define should be set - in the project configuration or in the stm32f4xx_conf.h file */ - #ifdef I2S_EXTERNAL_CLOCK_VAL - /* Set external clock as I2S clock source */ - if ((RCC->CFGR & RCC_CFGR_I2SSRC) == 0) - { - RCC->CFGR |= (uint32_t)RCC_CFGR_I2SSRC; - } - - /* Set the I2S clock to the external clock value */ - i2sclk = I2S_EXTERNAL_CLOCK_VAL; - - #else /* There is no define for External I2S clock source */ - /* Set PLLI2S as I2S clock source */ - if ((RCC->CFGR & RCC_CFGR_I2SSRC) != 0) - { - RCC->CFGR &= ~(uint32_t)RCC_CFGR_I2SSRC; - } - - /* Get the PLLI2SN value */ - plln = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & \ - (RCC_PLLI2SCFGR_PLLI2SN >> 6)); - - /* Get the PLLI2SR value */ - pllr = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & \ - (RCC_PLLI2SCFGR_PLLI2SR >> 28)); - - /* Get the PLLM value */ - pllm = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM); - - /* Get the I2S source clock value */ - i2sclk = (uint32_t)(((HSE_VALUE / pllm) * plln) / pllr); - #endif /* I2S_EXTERNAL_CLOCK_VAL */ - - /* Compute the Real divider depending on the MCLK output state, with a floating point */ - if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) - { - /* MCLK output is enabled */ - tmp = (uint16_t)(((((i2sclk / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); - } - else - { - /* MCLK output is disabled */ - tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5); - } - - /* Remove the flatting point */ - tmp = tmp / 10; - - /* Check the parity of the divider */ - i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); - - /* Compute the i2sdiv prescaler */ - i2sdiv = (uint16_t)((tmp - i2sodd) / 2); - - /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ - i2sodd = (uint16_t) (i2sodd << 8); - } - - /* Test if the divider is 1 or 0 or greater than 0xFF */ - if ((i2sdiv < 2) || (i2sdiv > 0xFF)) - { - /* Set the default values */ - i2sdiv = 2; - i2sodd = 0; - } - - /* Write to SPIx I2SPR register the computed value */ - SPIx->I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); - - /* Configure the I2S with the SPI_InitStruct values */ - tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \ - (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ - (uint16_t)I2S_InitStruct->I2S_CPOL)))); - - /* Write to SPIx I2SCFGR */ - SPIx->I2SCFGR = tmpreg; -} - -/** - * @brief Fills each SPI_InitStruct member with its default value. - * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized. - * @retval None - */ -void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) -{ -/*--------------- Reset SPI init structure parameters values -----------------*/ - /* Initialize the SPI_Direction member */ - SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; - /* initialize the SPI_Mode member */ - SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; - /* initialize the SPI_DataSize member */ - SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; - /* Initialize the SPI_CPOL member */ - SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; - /* Initialize the SPI_CPHA member */ - SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; - /* Initialize the SPI_NSS member */ - SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; - /* Initialize the SPI_BaudRatePrescaler member */ - SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; - /* Initialize the SPI_FirstBit member */ - SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; - /* Initialize the SPI_CRCPolynomial member */ - SPI_InitStruct->SPI_CRCPolynomial = 7; -} - -/** - * @brief Fills each I2S_InitStruct member with its default value. - * @param I2S_InitStruct: pointer to a I2S_InitTypeDef structure which will be initialized. - * @retval None - */ -void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct) -{ -/*--------------- Reset I2S init structure parameters values -----------------*/ - /* Initialize the I2S_Mode member */ - I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; - - /* Initialize the I2S_Standard member */ - I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; - - /* Initialize the I2S_DataFormat member */ - I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; - - /* Initialize the I2S_MCLKOutput member */ - I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; - - /* Initialize the I2S_AudioFreq member */ - I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; - - /* Initialize the I2S_CPOL member */ - I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; -} - -/** - * @brief Enables or disables the specified SPI peripheral. - * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. - * @param NewState: new state of the SPIx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI peripheral */ - SPIx->CR1 |= SPI_CR1_SPE; - } - else - { - /* Disable the selected SPI peripheral */ - SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE); - } -} - -/** - * @brief Enables or disables the specified SPI peripheral (in I2S mode). - * @param SPIx: where x can be 2 or 3 to select the SPI peripheral (or I2Sxext - * for full duplex mode). - * @param NewState: new state of the SPIx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_23_PERIPH_EXT(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected SPI peripheral (in I2S mode) */ - SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE; - } - else - { - /* Disable the selected SPI peripheral in I2S mode */ - SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE); - } -} - -/** - * @brief Configures the data size for the selected SPI. - * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. - * @param SPI_DataSize: specifies the SPI data size. - * This parameter can be one of the following values: - * @arg SPI_DataSize_16b: Set data frame format to 16bit - * @arg SPI_DataSize_8b: Set data frame format to 8bit - * @retval None - */ -void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_DATASIZE(SPI_DataSize)); - /* Clear DFF bit */ - SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b; - /* Set new DFF bit value */ - SPIx->CR1 |= SPI_DataSize; -} - -/** - * @brief Selects the data transfer direction in bidirectional mode for the specified SPI. - * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. - * @param SPI_Direction: specifies the data transfer direction in bidirectional mode. - * This parameter can be one of the following values: - * @arg SPI_Direction_Tx: Selects Tx transmission direction - * @arg SPI_Direction_Rx: Selects Rx receive direction - * @retval None - */ -void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_DIRECTION(SPI_Direction)); - if (SPI_Direction == SPI_Direction_Tx) - { - /* Set the Tx only mode */ - SPIx->CR1 |= SPI_Direction_Tx; - } - else - { - /* Set the Rx only mode */ - SPIx->CR1 &= SPI_Direction_Rx; - } -} - -/** - * @brief Configures internally by software the NSS pin for the selected SPI. - * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. - * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. - * This parameter can be one of the following values: - * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally - * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally - * @retval None - */ -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); - if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) - { - /* Set NSS pin internally by software */ - SPIx->CR1 |= SPI_NSSInternalSoft_Set; - } - else - { - /* Reset NSS pin internally by software */ - SPIx->CR1 &= SPI_NSSInternalSoft_Reset; - } -} - -/** - * @brief Enables or disables the SS output for the selected SPI. - * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. - * @param NewState: new state of the SPIx SS output. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI SS output */ - SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE; - } - else - { - /* Disable the selected SPI SS output */ - SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE); - } -} - -/** - * @brief Enables or disables the SPIx/I2Sx DMA interface. - * - * @note This function can be called only after the SPI_Init() function has - * been called. - * @note When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA - * are not taken into consideration and are configured by hardware - * respectively to the TI mode requirements. - * - * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 - * @param NewState: new state of the selected SPI TI communication mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the TI mode for the selected SPI peripheral */ - SPIx->CR2 |= SPI_CR2_FRF; - } - else - { - /* Disable the TI mode for the selected SPI peripheral */ - SPIx->CR2 &= (uint16_t)~SPI_CR2_FRF; - } -} - -/** - * @brief Configures the full duplex mode for the I2Sx peripheral using its - * extension I2Sxext according to the specified parameters in the - * I2S_InitStruct. - * @param I2Sxext: where x can be 2 or 3 to select the I2S peripheral extension block. - * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that - * contains the configuration information for the specified I2S peripheral - * extension. - * - * @note The structure pointed by I2S_InitStruct parameter should be the same - * used for the master I2S peripheral. In this case, if the master is - * configured as transmitter, the slave will be receiver and vice versa. - * Or you can force a different mode by modifying the field I2S_Mode to the - * value I2S_SlaveRx or I2S_SlaveTx indepedently of the master configuration. - * - * @note The I2S full duplex extension can be configured in slave mode only. - * - * @retval None - */ -void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct) -{ - uint16_t tmpreg = 0, tmp = 0; - - /* Check the I2S parameters */ - assert_param(IS_I2S_EXT_PERIPH(I2Sxext)); - assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); - assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); - assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); - assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); - -/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ - /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ - I2Sxext->I2SCFGR &= I2SCFGR_CLEAR_MASK; - I2Sxext->I2SPR = 0x0002; - - /* Get the I2SCFGR register value */ - tmpreg = I2Sxext->I2SCFGR; - - /* Get the mode to be configured for the extended I2S */ - if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveTx)) - { - tmp = I2S_Mode_SlaveRx; - } - else - { - if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterRx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveRx)) - { - tmp = I2S_Mode_SlaveTx; - } - } - - - /* Configure the I2S with the SPI_InitStruct values */ - tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \ - (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ - (uint16_t)I2S_InitStruct->I2S_CPOL)))); - - /* Write to SPIx I2SCFGR */ - I2Sxext->I2SCFGR = tmpreg; -} - -/** - * @} - */ - -/** @defgroup SPI_Group2 Data transfers functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### Data transfers functions ##### - =============================================================================== - - [..] This section provides a set of functions allowing to manage the SPI data - transfers. In reception, data are received and then stored into an internal - Rx buffer while. In transmission, data are first stored into an internal Tx - buffer before being transmitted. - - [..] The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData() - function and returns the Rx buffered value. Whereas a write access to the SPI_DR - can be done using SPI_I2S_SendData() function and stores the written data into - Tx buffer. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @retval The value of the received data. - */ -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - - /* Return the data in the DR register */ - return SPIx->DR; -} - -/** - * @brief Transmits a Data through the SPIx/I2Sx peripheral. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @param Data: Data to be transmitted. - * @retval None - */ -void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - - /* Write in the DR register the data to be sent */ - SPIx->DR = Data; -} - -/** - * @} - */ - -/** @defgroup SPI_Group3 Hardware CRC Calculation functions - * @brief Hardware CRC Calculation functions - * -@verbatim - =============================================================================== - ##### Hardware CRC Calculation functions ##### - =============================================================================== - - [..] This section provides a set of functions allowing to manage the SPI CRC hardware - calculation - - [..] SPI communication using CRC is possible through the following procedure: - (#) Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler, - Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() - function. - (#) Enable the CRC calculation using the SPI_CalculateCRC() function. - (#) Enable the SPI using the SPI_Cmd() function - (#) Before writing the last data to the TX buffer, set the CRCNext bit using the - SPI_TransmitCRC() function to indicate that after transmission of the last - data, the CRC should be transmitted. - (#) After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT - bit is reset. The CRC is also received and compared against the SPI_RXCRCR - value. - If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt - can be generated when the SPI_I2S_IT_ERR interrupt is enabled. - - [..] - (@) It is advised not to read the calculated CRC values during the communication. - - (@) When the SPI is in slave mode, be careful to enable CRC calculation only - when the clock is stable, that is, when the clock is in the steady state. - If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive - to the SCK slave input clock as soon as CRCEN is set, and this, whatever - the value of the SPE bit. - - (@) With high bitrate frequencies, be careful when transmitting the CRC. - As the number of used CPU cycles has to be as low as possible in the CRC - transfer phase, it is forbidden to call software functions in the CRC - transmission sequence to avoid errors in the last data and CRC reception. - In fact, CRCNEXT bit has to be written before the end of the transmission/reception - of the last data. - - (@) For high bit rate frequencies, it is advised to use the DMA mode to avoid the - degradation of the SPI speed performance due to CPU accesses impacting the - SPI bandwidth. - - (@) When the STM32F4xx is configured as slave and the NSS hardware mode is - used, the NSS pin needs to be kept low between the data phase and the CRC - phase. - - (@) When the SPI is configured in slave mode with the CRC feature enabled, CRC - calculation takes place even if a high level is applied on the NSS pin. - This may happen for example in case of a multi-slave environment where the - communication master addresses slaves alternately. - - (@) Between a slave de-selection (high level on NSS) and a new slave selection - (low level on NSS), the CRC value should be cleared on both master and slave - sides in order to resynchronize the master and slave for their respective - CRC calculation. - - (@) To clear the CRC, follow the procedure below: - (#@) Disable SPI using the SPI_Cmd() function - (#@) Disable the CRC calculation using the SPI_CalculateCRC() function. - (#@) Enable the CRC calculation using the SPI_CalculateCRC() function. - (#@) Enable SPI using the SPI_Cmd() function. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the CRC value calculation of the transferred bytes. - * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. - * @param NewState: new state of the SPIx CRC value calculation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI CRC calculation */ - SPIx->CR1 |= SPI_CR1_CRCEN; - } - else - { - /* Disable the selected SPI CRC calculation */ - SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN); - } -} - -/** - * @brief Transmit the SPIx CRC value. - * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. - * @retval None - */ -void SPI_TransmitCRC(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Enable the selected SPI CRC transmission */ - SPIx->CR1 |= SPI_CR1_CRCNEXT; -} - -/** - * @brief Returns the transmit or the receive CRC register value for the specified SPI. - * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. - * @param SPI_CRC: specifies the CRC register to be read. - * This parameter can be one of the following values: - * @arg SPI_CRC_Tx: Selects Tx CRC register - * @arg SPI_CRC_Rx: Selects Rx CRC register - * @retval The selected CRC register value.. - */ -uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC) -{ - uint16_t crcreg = 0; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_CRC(SPI_CRC)); - if (SPI_CRC != SPI_CRC_Rx) - { - /* Get the Tx CRC register */ - crcreg = SPIx->TXCRCR; - } - else - { - /* Get the Rx CRC register */ - crcreg = SPIx->RXCRCR; - } - /* Return the selected CRC register */ - return crcreg; -} - -/** - * @brief Returns the CRC Polynomial register value for the specified SPI. - * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. - * @retval The CRC Polynomial register value. - */ -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Return the CRC polynomial register */ - return SPIx->CRCPR; -} - -/** - * @} - */ - -/** @defgroup SPI_Group4 DMA transfers management functions - * @brief DMA transfers management functions - * -@verbatim - =============================================================================== - ##### DMA transfers management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the SPIx/I2Sx DMA interface. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request - * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request - * @param NewState: new state of the selected SPI DMA transfer request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq)); - - if (NewState != DISABLE) - { - /* Enable the selected SPI DMA requests */ - SPIx->CR2 |= SPI_I2S_DMAReq; - } - else - { - /* Disable the selected SPI DMA requests */ - SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq; - } -} - -/** - * @} - */ - -/** @defgroup SPI_Group5 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - - [..] This section provides a set of functions allowing to configure the SPI Interrupts - sources and check or clear the flags or pending bits status. - The user should identify which mode will be used in his application to manage - the communication: Polling mode, Interrupt mode or DMA mode. - - *** Polling Mode *** - ==================== -[..] In Polling Mode, the SPI/I2S communication can be managed by 9 flags: - (#) SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register - (#) SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register - (#) SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI. - (#) SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur - (#) SPI_FLAG_MODF : to indicate if a Mode Fault error occur - (#) SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur - (#) I2S_FLAG_TIFRFE: to indicate a Frame Format error occurs. - (#) I2S_FLAG_UDR: to indicate an Underrun error occurs. - (#) I2S_FLAG_CHSIDE: to indicate Channel Side. - - (@) Do not use the BSY flag to handle each data transmission or reception. It is - better to use the TXE and RXNE flags instead. - - [..] In this Mode it is advised to use the following functions: - (+) FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); - (+) void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); - - *** Interrupt Mode *** - ====================== - [..] In Interrupt Mode, the SPI communication can be managed by 3 interrupt sources - and 7 pending bits: - (+) Pending Bits: - (##) SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register - (##) SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register - (##) SPI_IT_CRCERR : to indicate if a CRC Calculation error occur (available in SPI mode only) - (##) SPI_IT_MODF : to indicate if a Mode Fault error occur (available in SPI mode only) - (##) SPI_I2S_IT_OVR : to indicate if an Overrun error occur - (##) I2S_IT_UDR : to indicate an Underrun Error occurs (available in I2S mode only). - (##) I2S_FLAG_TIFRFE : to indicate a Frame Format error occurs (available in TI mode only). - - (+) Interrupt Source: - (##) SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty - interrupt. - (##) SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not - empty interrupt. - (##) SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt. - - [..] In this Mode it is advised to use the following functions: - (+) void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); - (+) ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - (+) void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - - *** DMA Mode *** - ================ - [..] In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests: - (#) SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request - (#) SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request - - [..] In this Mode it is advised to use the following function: - (+) void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState - NewState); - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified SPI/I2S interrupts. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled. - * This parameter can be one of the following values: - * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask - * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask - * @arg SPI_I2S_IT_ERR: Error interrupt mask - * @param NewState: new state of the specified SPI interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) -{ - uint16_t itpos = 0, itmask = 0 ; - - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT)); - - /* Get the SPI IT index */ - itpos = SPI_I2S_IT >> 4; - - /* Set the IT mask */ - itmask = (uint16_t)1 << (uint16_t)itpos; - - if (NewState != DISABLE) - { - /* Enable the selected SPI interrupt */ - SPIx->CR2 |= itmask; - } - else - { - /* Disable the selected SPI interrupt */ - SPIx->CR2 &= (uint16_t)~itmask; - } -} - -/** - * @brief Checks whether the specified SPIx/I2Sx flag is set or not. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @param SPI_I2S_FLAG: specifies the SPI flag to check. - * This parameter can be one of the following values: - * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag. - * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag. - * @arg SPI_I2S_FLAG_BSY: Busy flag. - * @arg SPI_I2S_FLAG_OVR: Overrun flag. - * @arg SPI_FLAG_MODF: Mode Fault flag. - * @arg SPI_FLAG_CRCERR: CRC Error flag. - * @arg SPI_I2S_FLAG_TIFRFE: Format Error. - * @arg I2S_FLAG_UDR: Underrun Error flag. - * @arg I2S_FLAG_CHSIDE: Channel Side flag. - * @retval The new state of SPI_I2S_FLAG (SET or RESET). - */ -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); - - /* Check the status of the specified SPI flag */ - if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET) - { - /* SPI_I2S_FLAG is set */ - bitstatus = SET; - } - else - { - /* SPI_I2S_FLAG is reset */ - bitstatus = RESET; - } - /* Return the SPI_I2S_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the SPIx CRC Error (CRCERR) flag. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @param SPI_I2S_FLAG: specifies the SPI flag to clear. - * This function clears only CRCERR flag. - * @arg SPI_FLAG_CRCERR: CRC Error flag. - * - * @note OVR (OverRun error) flag is cleared by software sequence: a read - * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read - * operation to SPI_SR register (SPI_I2S_GetFlagStatus()). - * @note UDR (UnderRun error) flag is cleared by a read operation to - * SPI_SR register (SPI_I2S_GetFlagStatus()). - * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write - * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a - * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI). - * - * @retval None - */ -void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG)); - - /* Clear the selected SPI CRC Error (CRCERR) flag */ - SPIx->SR = (uint16_t)~SPI_I2S_FLAG; -} - -/** - * @brief Checks whether the specified SPIx/I2Sx interrupt has occurred or not. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @param SPI_I2S_IT: specifies the SPI interrupt source to check. - * This parameter can be one of the following values: - * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt. - * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt. - * @arg SPI_I2S_IT_OVR: Overrun interrupt. - * @arg SPI_IT_MODF: Mode Fault interrupt. - * @arg SPI_IT_CRCERR: CRC Error interrupt. - * @arg I2S_IT_UDR: Underrun interrupt. - * @arg SPI_I2S_IT_TIFRFE: Format Error interrupt. - * @retval The new state of SPI_I2S_IT (SET or RESET). - */ -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itpos = 0, itmask = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT)); - - /* Get the SPI_I2S_IT index */ - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - - /* Get the SPI_I2S_IT IT mask */ - itmask = SPI_I2S_IT >> 4; - - /* Set the IT mask */ - itmask = 0x01 << itmask; - - /* Get the SPI_I2S_IT enable bit status */ - enablestatus = (SPIx->CR2 & itmask) ; - - /* Check the status of the specified SPI interrupt */ - if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus) - { - /* SPI_I2S_IT is set */ - bitstatus = SET; - } - else - { - /* SPI_I2S_IT is reset */ - bitstatus = RESET; - } - /* Return the SPI_I2S_IT status */ - return bitstatus; -} - -/** - * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear. - * This function clears only CRCERR interrupt pending bit. - * @arg SPI_IT_CRCERR: CRC Error interrupt. - * - * @note OVR (OverRun Error) interrupt pending bit is cleared by software - * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) - * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()). - * @note UDR (UnderRun Error) interrupt pending bit is cleared by a read - * operation to SPI_SR register (SPI_I2S_GetITStatus()). - * @note MODF (Mode Fault) interrupt pending bit is cleared by software sequence: - * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) - * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable - * the SPI). - * @retval None - */ -void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) -{ - uint16_t itpos = 0; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT)); - - /* Get the SPI_I2S IT index */ - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - - /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */ - SPIx->SR = (uint16_t)~itpos; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm32f4xx_spi.h b/stm/stmperiph/stm32f4xx_spi.h deleted file mode 100644 index 7f4834bfd..000000000 --- a/stm/stmperiph/stm32f4xx_spi.h +++ /dev/null @@ -1,549 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_spi.h - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief This file contains all the functions prototypes for the SPI - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_SPI_H -#define __STM32F4xx_SPI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SPI - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief SPI Init structure definition - */ - -typedef struct -{ - uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. - This parameter can be a value of @ref SPI_data_direction */ - - uint16_t SPI_Mode; /*!< Specifies the SPI operating mode. - This parameter can be a value of @ref SPI_mode */ - - uint16_t SPI_DataSize; /*!< Specifies the SPI data size. - This parameter can be a value of @ref SPI_data_size */ - - uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. - This parameter can be a value of @ref SPI_Clock_Polarity */ - - uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. - This parameter can be a value of @ref SPI_Clock_Phase */ - - uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by - hardware (NSS pin) or by software using the SSI bit. - This parameter can be a value of @ref SPI_Slave_Select_management */ - - uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be - used to configure the transmit and receive SCK clock. - This parameter can be a value of @ref SPI_BaudRate_Prescaler - @note The communication clock is derived from the master - clock. The slave clock does not need to be set. */ - - uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. - This parameter can be a value of @ref SPI_MSB_LSB_transmission */ - - uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ -}SPI_InitTypeDef; - -/** - * @brief I2S Init structure definition - */ - -typedef struct -{ - - uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. - This parameter can be a value of @ref I2S_Mode */ - - uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. - This parameter can be a value of @ref I2S_Standard */ - - uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. - This parameter can be a value of @ref I2S_Data_Format */ - - uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. - This parameter can be a value of @ref I2S_MCLK_Output */ - - uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. - This parameter can be a value of @ref I2S_Audio_Frequency */ - - uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. - This parameter can be a value of @ref I2S_Clock_Polarity */ -}I2S_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup SPI_Exported_Constants - * @{ - */ - -#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ - ((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3) || \ - ((PERIPH) == SPI4) || \ - ((PERIPH) == SPI5) || \ - ((PERIPH) == SPI6)) - -#define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1) || \ - ((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3) || \ - ((PERIPH) == SPI4) || \ - ((PERIPH) == SPI5) || \ - ((PERIPH) == SPI6) || \ - ((PERIPH) == I2S2ext) || \ - ((PERIPH) == I2S3ext)) - -#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3)) - -#define IS_SPI_23_PERIPH_EXT(PERIPH) (((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3) || \ - ((PERIPH) == I2S2ext) || \ - ((PERIPH) == I2S3ext)) - -#define IS_I2S_EXT_PERIPH(PERIPH) (((PERIPH) == I2S2ext) || \ - ((PERIPH) == I2S3ext)) - - -/** @defgroup SPI_data_direction - * @{ - */ - -#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) -#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) -#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) -#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) -#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ - ((MODE) == SPI_Direction_2Lines_RxOnly) || \ - ((MODE) == SPI_Direction_1Line_Rx) || \ - ((MODE) == SPI_Direction_1Line_Tx)) -/** - * @} - */ - -/** @defgroup SPI_mode - * @{ - */ - -#define SPI_Mode_Master ((uint16_t)0x0104) -#define SPI_Mode_Slave ((uint16_t)0x0000) -#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ - ((MODE) == SPI_Mode_Slave)) -/** - * @} - */ - -/** @defgroup SPI_data_size - * @{ - */ - -#define SPI_DataSize_16b ((uint16_t)0x0800) -#define SPI_DataSize_8b ((uint16_t)0x0000) -#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \ - ((DATASIZE) == SPI_DataSize_8b)) -/** - * @} - */ - -/** @defgroup SPI_Clock_Polarity - * @{ - */ - -#define SPI_CPOL_Low ((uint16_t)0x0000) -#define SPI_CPOL_High ((uint16_t)0x0002) -#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ - ((CPOL) == SPI_CPOL_High)) -/** - * @} - */ - -/** @defgroup SPI_Clock_Phase - * @{ - */ - -#define SPI_CPHA_1Edge ((uint16_t)0x0000) -#define SPI_CPHA_2Edge ((uint16_t)0x0001) -#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ - ((CPHA) == SPI_CPHA_2Edge)) -/** - * @} - */ - -/** @defgroup SPI_Slave_Select_management - * @{ - */ - -#define SPI_NSS_Soft ((uint16_t)0x0200) -#define SPI_NSS_Hard ((uint16_t)0x0000) -#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ - ((NSS) == SPI_NSS_Hard)) -/** - * @} - */ - -/** @defgroup SPI_BaudRate_Prescaler - * @{ - */ - -#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) -#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) -#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) -#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) -#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) -#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) -#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) -#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) -#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_256)) -/** - * @} - */ - -/** @defgroup SPI_MSB_LSB_transmission - * @{ - */ - -#define SPI_FirstBit_MSB ((uint16_t)0x0000) -#define SPI_FirstBit_LSB ((uint16_t)0x0080) -#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ - ((BIT) == SPI_FirstBit_LSB)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Mode - * @{ - */ - -#define I2S_Mode_SlaveTx ((uint16_t)0x0000) -#define I2S_Mode_SlaveRx ((uint16_t)0x0100) -#define I2S_Mode_MasterTx ((uint16_t)0x0200) -#define I2S_Mode_MasterRx ((uint16_t)0x0300) -#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ - ((MODE) == I2S_Mode_SlaveRx) || \ - ((MODE) == I2S_Mode_MasterTx)|| \ - ((MODE) == I2S_Mode_MasterRx)) -/** - * @} - */ - - -/** @defgroup SPI_I2S_Standard - * @{ - */ - -#define I2S_Standard_Phillips ((uint16_t)0x0000) -#define I2S_Standard_MSB ((uint16_t)0x0010) -#define I2S_Standard_LSB ((uint16_t)0x0020) -#define I2S_Standard_PCMShort ((uint16_t)0x0030) -#define I2S_Standard_PCMLong ((uint16_t)0x00B0) -#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ - ((STANDARD) == I2S_Standard_MSB) || \ - ((STANDARD) == I2S_Standard_LSB) || \ - ((STANDARD) == I2S_Standard_PCMShort) || \ - ((STANDARD) == I2S_Standard_PCMLong)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Data_Format - * @{ - */ - -#define I2S_DataFormat_16b ((uint16_t)0x0000) -#define I2S_DataFormat_16bextended ((uint16_t)0x0001) -#define I2S_DataFormat_24b ((uint16_t)0x0003) -#define I2S_DataFormat_32b ((uint16_t)0x0005) -#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ - ((FORMAT) == I2S_DataFormat_16bextended) || \ - ((FORMAT) == I2S_DataFormat_24b) || \ - ((FORMAT) == I2S_DataFormat_32b)) -/** - * @} - */ - -/** @defgroup SPI_I2S_MCLK_Output - * @{ - */ - -#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) -#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) -#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ - ((OUTPUT) == I2S_MCLKOutput_Disable)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Audio_Frequency - * @{ - */ - -#define I2S_AudioFreq_192k ((uint32_t)192000) -#define I2S_AudioFreq_96k ((uint32_t)96000) -#define I2S_AudioFreq_48k ((uint32_t)48000) -#define I2S_AudioFreq_44k ((uint32_t)44100) -#define I2S_AudioFreq_32k ((uint32_t)32000) -#define I2S_AudioFreq_22k ((uint32_t)22050) -#define I2S_AudioFreq_16k ((uint32_t)16000) -#define I2S_AudioFreq_11k ((uint32_t)11025) -#define I2S_AudioFreq_8k ((uint32_t)8000) -#define I2S_AudioFreq_Default ((uint32_t)2) - -#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \ - ((FREQ) <= I2S_AudioFreq_192k)) || \ - ((FREQ) == I2S_AudioFreq_Default)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Clock_Polarity - * @{ - */ - -#define I2S_CPOL_Low ((uint16_t)0x0000) -#define I2S_CPOL_High ((uint16_t)0x0008) -#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ - ((CPOL) == I2S_CPOL_High)) -/** - * @} - */ - -/** @defgroup SPI_I2S_DMA_transfer_requests - * @{ - */ - -#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) -#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) -#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) -/** - * @} - */ - -/** @defgroup SPI_NSS_internal_software_management - * @{ - */ - -#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) -#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) -#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ - ((INTERNAL) == SPI_NSSInternalSoft_Reset)) -/** - * @} - */ - -/** @defgroup SPI_CRC_Transmit_Receive - * @{ - */ - -#define SPI_CRC_Tx ((uint8_t)0x00) -#define SPI_CRC_Rx ((uint8_t)0x01) -#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) -/** - * @} - */ - -/** @defgroup SPI_direction_transmit_receive - * @{ - */ - -#define SPI_Direction_Rx ((uint16_t)0xBFFF) -#define SPI_Direction_Tx ((uint16_t)0x4000) -#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ - ((DIRECTION) == SPI_Direction_Tx)) -/** - * @} - */ - -/** @defgroup SPI_I2S_interrupts_definition - * @{ - */ - -#define SPI_I2S_IT_TXE ((uint8_t)0x71) -#define SPI_I2S_IT_RXNE ((uint8_t)0x60) -#define SPI_I2S_IT_ERR ((uint8_t)0x50) -#define I2S_IT_UDR ((uint8_t)0x53) -#define SPI_I2S_IT_TIFRFE ((uint8_t)0x58) - -#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ - ((IT) == SPI_I2S_IT_RXNE) || \ - ((IT) == SPI_I2S_IT_ERR)) - -#define SPI_I2S_IT_OVR ((uint8_t)0x56) -#define SPI_IT_MODF ((uint8_t)0x55) -#define SPI_IT_CRCERR ((uint8_t)0x54) - -#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR)) - -#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE)|| ((IT) == SPI_I2S_IT_TXE) || \ - ((IT) == SPI_IT_CRCERR) || ((IT) == SPI_IT_MODF) || \ - ((IT) == SPI_I2S_IT_OVR) || ((IT) == I2S_IT_UDR) ||\ - ((IT) == SPI_I2S_IT_TIFRFE)) -/** - * @} - */ - -/** @defgroup SPI_I2S_flags_definition - * @{ - */ - -#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) -#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) -#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) -#define I2S_FLAG_UDR ((uint16_t)0x0008) -#define SPI_FLAG_CRCERR ((uint16_t)0x0010) -#define SPI_FLAG_MODF ((uint16_t)0x0020) -#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) -#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) -#define SPI_I2S_FLAG_TIFRFE ((uint16_t)0x0100) - -#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) -#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ - ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ - ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \ - ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \ - ((FLAG) == SPI_I2S_FLAG_TIFRFE)) -/** - * @} - */ - -/** @defgroup SPI_CRC_polynomial - * @{ - */ - -#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) -/** - * @} - */ - -/** @defgroup SPI_I2S_Legacy - * @{ - */ - -#define SPI_DMAReq_Tx SPI_I2S_DMAReq_Tx -#define SPI_DMAReq_Rx SPI_I2S_DMAReq_Rx -#define SPI_IT_TXE SPI_I2S_IT_TXE -#define SPI_IT_RXNE SPI_I2S_IT_RXNE -#define SPI_IT_ERR SPI_I2S_IT_ERR -#define SPI_IT_OVR SPI_I2S_IT_OVR -#define SPI_FLAG_RXNE SPI_I2S_FLAG_RXNE -#define SPI_FLAG_TXE SPI_I2S_FLAG_TXE -#define SPI_FLAG_OVR SPI_I2S_FLAG_OVR -#define SPI_FLAG_BSY SPI_I2S_FLAG_BSY -#define SPI_DeInit SPI_I2S_DeInit -#define SPI_ITConfig SPI_I2S_ITConfig -#define SPI_DMACmd SPI_I2S_DMACmd -#define SPI_SendData SPI_I2S_SendData -#define SPI_ReceiveData SPI_I2S_ReceiveData -#define SPI_GetFlagStatus SPI_I2S_GetFlagStatus -#define SPI_ClearFlag SPI_I2S_ClearFlag -#define SPI_GetITStatus SPI_I2S_GetITStatus -#define SPI_ClearITPendingBit SPI_I2S_ClearITPendingBit -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the SPI configuration to the default reset state *****/ -void SPI_I2S_DeInit(SPI_TypeDef* SPIx); - -/* Initialization and Configuration functions *********************************/ -void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); -void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); -void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); -void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); -void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); -void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); -void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); - -void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct); - -/* Data transfers functions ***************************************************/ -void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); - -/* Hardware CRC Calculation functions *****************************************/ -void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_TransmitCRC(SPI_TypeDef* SPIx); -uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); - -/* DMA transfers management functions *****************************************/ -void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); -void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); -void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_SPI_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm32f4xx_syscfg.c b/stm/stmperiph/stm32f4xx_syscfg.c deleted file mode 100644 index 638f76115..000000000 --- a/stm/stmperiph/stm32f4xx_syscfg.c +++ /dev/null @@ -1,240 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_syscfg.c - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief This file provides firmware functions to manage the SYSCFG peripheral. - * - @verbatim - - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] This driver provides functions for: - - (#) Remapping the memory accessible in the code area using SYSCFG_MemoryRemapConfig() - - (#) Swapping the internal flash Bank1 and Bank2 this features is only visible for - STM32F42xxx/43xxx devices Devices. - - (#) Manage the EXTI lines connection to the GPIOs using SYSCFG_EXTILineConfig() - - (#) Select the ETHERNET media interface (RMII/RII) using SYSCFG_ETH_MediaInterfaceConfig() - - -@- SYSCFG APB clock must be enabled to get write access to SYSCFG registers, - using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_syscfg.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup SYSCFG - * @brief SYSCFG driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* ------------ RCC registers bit address in the alias region ----------- */ -#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE) -/* --- MEMRMP Register ---*/ -/* Alias word address of UFB_MODE bit */ -#define MEMRMP_OFFSET SYSCFG_OFFSET -#define UFB_MODE_BitNumber ((uint8_t)0x8) -#define UFB_MODE_BB (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (UFB_MODE_BitNumber * 4)) - - -/* --- PMC Register ---*/ -/* Alias word address of MII_RMII_SEL bit */ -#define PMC_OFFSET (SYSCFG_OFFSET + 0x04) -#define MII_RMII_SEL_BitNumber ((uint8_t)0x17) -#define PMC_MII_RMII_SEL_BB (PERIPH_BB_BASE + (PMC_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4)) - -/* --- CMPCR Register ---*/ -/* Alias word address of CMP_PD bit */ -#define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20) -#define CMP_PD_BitNumber ((uint8_t)0x00) -#define CMPCR_CMP_PD_BB (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4)) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup SYSCFG_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the Alternate Functions (remap and EXTI configuration) - * registers to their default reset values. - * @param None - * @retval None - */ -void SYSCFG_DeInit(void) -{ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE); -} - -/** - * @brief Changes the mapping of the specified pin. - * @param SYSCFG_Memory: selects the memory remapping. - * This parameter can be one of the following values: - * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000 - * @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000 - * @arg SYSCFG_MemoryRemap_FSMC: FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 for STM32F405xx/407xx and STM32F415xx/417xx devices. - * @arg SYSCFG_MemoryRemap_FMC: FMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 for STM32F42xxx/43xxx devices. - * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM (112kB) mapped at 0x00000000 - * @arg SYSCFG_MemoryRemap_SDRAM: FMC (External SDRAM) mapped at 0x00000000 for STM32F42xxx/43xxx devices. - * @retval None - */ -void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap) -{ - /* Check the parameters */ - assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap)); - - SYSCFG->MEMRMP = SYSCFG_MemoryRemap; -} - -/** - * @brief Enables or disables the Interal FLASH Bank Swapping. - * - * @note This function can be used only for STM32F42xxx/43xxx devices. - * - * @param NewState: new state of Interal FLASH Bank swapping. - * This parameter can be one of the following values: - * @arg ENABLE: Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) - * and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000) - * @arg DISABLE:(the default state) Flash Bank1 mapped at 0x08000000 (and aliased @0x0000 0000) - and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000) - * @retval None - */ -void SYSCFG_MemorySwappingBank(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) UFB_MODE_BB = (uint32_t)NewState; -} - -/** - * @brief Selects the GPIO pin used as EXTI Line. - * @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source for - * EXTI lines where x can be (A..K) for STM32F42xxx/43xxx devices, (A..I) - * for STM32F405xx/407xx and STM32F415xx/417xx devices or (A, B, C, D and H) - * for STM32401xx devices. - * - * @param EXTI_PinSourcex: specifies the EXTI line to be configured. - * This parameter can be EXTI_PinSourcex where x can be (0..15, except - * for EXTI_PortSourceGPIOI x can be (0..11) for STM32F405xx/407xx - * and STM32F405xx/407xx devices and for EXTI_PortSourceGPIOK x can - * be (0..7) for STM32F42xxx/43xxx devices. - * - * @retval None - */ -void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex) -{ - uint32_t tmp = 0x00; - - /* Check the parameters */ - assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx)); - assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex)); - - tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)); - SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp; - SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03))); -} - -/** - * @brief Selects the ETHERNET media interface - * @param SYSCFG_ETH_MediaInterface: specifies the Media Interface mode. - * This parameter can be one of the following values: - * @arg SYSCFG_ETH_MediaInterface_MII: MII mode selected - * @arg SYSCFG_ETH_MediaInterface_RMII: RMII mode selected - * @retval None - */ -void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface) -{ - assert_param(IS_SYSCFG_ETH_MEDIA_INTERFACE(SYSCFG_ETH_MediaInterface)); - /* Configure MII_RMII selection bit */ - *(__IO uint32_t *) PMC_MII_RMII_SEL_BB = SYSCFG_ETH_MediaInterface; -} - -/** - * @brief Enables or disables the I/O Compensation Cell. - * @note The I/O compensation cell can be used only when the device supply - * voltage ranges from 2.4 to 3.6 V. - * @param NewState: new state of the I/O Compensation Cell. - * This parameter can be one of the following values: - * @arg ENABLE: I/O compensation cell enabled - * @arg DISABLE: I/O compensation cell power-down mode - * @retval None - */ -void SYSCFG_CompensationCellCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMPCR_CMP_PD_BB = (uint32_t)NewState; -} - -/** - * @brief Checks whether the I/O Compensation Cell ready flag is set or not. - * @param None - * @retval The new state of the I/O Compensation Cell ready flag (SET or RESET) - */ -FlagStatus SYSCFG_GetCompensationCellStatus(void) -{ - FlagStatus bitstatus = RESET; - - if ((SYSCFG->CMPCR & SYSCFG_CMPCR_READY ) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm32f4xx_syscfg.h b/stm/stmperiph/stm32f4xx_syscfg.h deleted file mode 100644 index 7d3cc4288..000000000 --- a/stm/stmperiph/stm32f4xx_syscfg.h +++ /dev/null @@ -1,210 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_syscfg.h - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief This file contains all the functions prototypes for the SYSCFG firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_SYSCFG_H -#define __STM32F4xx_SYSCFG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SYSCFG - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup SYSCFG_Exported_Constants - * @{ - */ - -/** @defgroup SYSCFG_EXTI_Port_Sources - * @{ - */ -#define EXTI_PortSourceGPIOA ((uint8_t)0x00) -#define EXTI_PortSourceGPIOB ((uint8_t)0x01) -#define EXTI_PortSourceGPIOC ((uint8_t)0x02) -#define EXTI_PortSourceGPIOD ((uint8_t)0x03) -#define EXTI_PortSourceGPIOE ((uint8_t)0x04) -#define EXTI_PortSourceGPIOF ((uint8_t)0x05) -#define EXTI_PortSourceGPIOG ((uint8_t)0x06) -#define EXTI_PortSourceGPIOH ((uint8_t)0x07) -#define EXTI_PortSourceGPIOI ((uint8_t)0x08) -#define EXTI_PortSourceGPIOJ ((uint8_t)0x09) -#define EXTI_PortSourceGPIOK ((uint8_t)0x0A) - -#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOF) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOG) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOH) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOI) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOJ) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOK)) - -/** - * @} - */ - - -/** @defgroup SYSCFG_EXTI_Pin_Sources - * @{ - */ -#define EXTI_PinSource0 ((uint8_t)0x00) -#define EXTI_PinSource1 ((uint8_t)0x01) -#define EXTI_PinSource2 ((uint8_t)0x02) -#define EXTI_PinSource3 ((uint8_t)0x03) -#define EXTI_PinSource4 ((uint8_t)0x04) -#define EXTI_PinSource5 ((uint8_t)0x05) -#define EXTI_PinSource6 ((uint8_t)0x06) -#define EXTI_PinSource7 ((uint8_t)0x07) -#define EXTI_PinSource8 ((uint8_t)0x08) -#define EXTI_PinSource9 ((uint8_t)0x09) -#define EXTI_PinSource10 ((uint8_t)0x0A) -#define EXTI_PinSource11 ((uint8_t)0x0B) -#define EXTI_PinSource12 ((uint8_t)0x0C) -#define EXTI_PinSource13 ((uint8_t)0x0D) -#define EXTI_PinSource14 ((uint8_t)0x0E) -#define EXTI_PinSource15 ((uint8_t)0x0F) -#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \ - ((PINSOURCE) == EXTI_PinSource1) || \ - ((PINSOURCE) == EXTI_PinSource2) || \ - ((PINSOURCE) == EXTI_PinSource3) || \ - ((PINSOURCE) == EXTI_PinSource4) || \ - ((PINSOURCE) == EXTI_PinSource5) || \ - ((PINSOURCE) == EXTI_PinSource6) || \ - ((PINSOURCE) == EXTI_PinSource7) || \ - ((PINSOURCE) == EXTI_PinSource8) || \ - ((PINSOURCE) == EXTI_PinSource9) || \ - ((PINSOURCE) == EXTI_PinSource10) || \ - ((PINSOURCE) == EXTI_PinSource11) || \ - ((PINSOURCE) == EXTI_PinSource12) || \ - ((PINSOURCE) == EXTI_PinSource13) || \ - ((PINSOURCE) == EXTI_PinSource14) || \ - ((PINSOURCE) == EXTI_PinSource15)) -/** - * @} - */ - - -/** @defgroup SYSCFG_Memory_Remap_Config - * @{ - */ -#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00) -#define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01) -#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03) -#define SYSCFG_MemoryRemap_SDRAM ((uint8_t)0x04) - -#if defined (STM32F40_41xxx) -#define SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02) -#endif /* STM32F40_41xxx */ - -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) -#define SYSCFG_MemoryRemap_FMC ((uint8_t)0x02) -#endif /* STM32F427_437xx || STM32F429_439xx */ - -#if defined (STM32F40_41xxx) -#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ - ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \ - ((REMAP) == SYSCFG_MemoryRemap_SRAM) || \ - ((REMAP) == SYSCFG_MemoryRemap_FSMC)) -#endif /* STM32F40_41xxx */ - -#if defined (STM32F401xx) -#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ - ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \ - ((REMAP) == SYSCFG_MemoryRemap_SRAM)) -#endif /* STM32F401xx */ - -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) -#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ - ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \ - ((REMAP) == SYSCFG_MemoryRemap_SRAM) || \ - ((REMAP) == SYSCFG_MemoryRemap_SDRAM) || \ - ((REMAP) == SYSCFG_MemoryRemap_FMC)) -#endif /* STM32F427_437xx || STM32F429_439xx */ - -/** - * @} - */ - - -/** @defgroup SYSCFG_ETHERNET_Media_Interface - * @{ - */ -#define SYSCFG_ETH_MediaInterface_MII ((uint32_t)0x00000000) -#define SYSCFG_ETH_MediaInterface_RMII ((uint32_t)0x00000001) - -#define IS_SYSCFG_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == SYSCFG_ETH_MediaInterface_MII) || \ - ((INTERFACE) == SYSCFG_ETH_MediaInterface_RMII)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -void SYSCFG_DeInit(void); -void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap); -void SYSCFG_MemorySwappingBank(FunctionalState NewState); -void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex); -void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface); -void SYSCFG_CompensationCellCmd(FunctionalState NewState); -FlagStatus SYSCFG_GetCompensationCellStatus(void); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_SYSCFG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm32f4xx_tim.c b/stm/stmperiph/stm32f4xx_tim.c deleted file mode 100644 index 9a17ac316..000000000 --- a/stm/stmperiph/stm32f4xx_tim.c +++ /dev/null @@ -1,3365 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_tim.c - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief This file provides firmware functions to manage the following - * functionalities of the TIM peripheral: - * + TimeBase management - * + Output Compare management - * + Input Capture management - * + Advanced-control timers (TIM1 and TIM8) specific features - * + Interrupts, DMA and flags management - * + Clocks management - * + Synchronization management - * + Specific interface management - * + Specific remapping management - * - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - This driver provides functions to configure and program the TIM - of all STM32F4xx devices. - These functions are split in 9 groups: - - (#) TIM TimeBase management: this group includes all needed functions - to configure the TM Timebase unit: - (++) Set/Get Prescaler - (++) Set/Get Autoreload - (++) Counter modes configuration - (++) Set Clock division - (++) Select the One Pulse mode - (++) Update Request Configuration - (++) Update Disable Configuration - (++) Auto-Preload Configuration - (++) Enable/Disable the counter - - (#) TIM Output Compare management: this group includes all needed - functions to configure the Capture/Compare unit used in Output - compare mode: - (++) Configure each channel, independently, in Output Compare mode - (++) Select the output compare modes - (++) Select the Polarities of each channel - (++) Set/Get the Capture/Compare register values - (++) Select the Output Compare Fast mode - (++) Select the Output Compare Forced mode - (++) Output Compare-Preload Configuration - (++) Clear Output Compare Reference - (++) Select the OCREF Clear signal - (++) Enable/Disable the Capture/Compare Channels - - (#) TIM Input Capture management: this group includes all needed - functions to configure the Capture/Compare unit used in - Input Capture mode: - (++) Configure each channel in input capture mode - (++) Configure Channel1/2 in PWM Input mode - (++) Set the Input Capture Prescaler - (++) Get the Capture/Compare values - - (#) Advanced-control timers (TIM1 and TIM8) specific features - (++) Configures the Break input, dead time, Lock level, the OSSI, - the OSSR State and the AOE(automatic output enable) - (++) Enable/Disable the TIM peripheral Main Outputs - (++) Select the Commutation event - (++) Set/Reset the Capture Compare Preload Control bit - - (#) TIM interrupts, DMA and flags management - (++) Enable/Disable interrupt sources - (++) Get flags status - (++) Clear flags/ Pending bits - (++) Enable/Disable DMA requests - (++) Configure DMA burst mode - (++) Select CaptureCompare DMA request - - (#) TIM clocks management: this group includes all needed functions - to configure the clock controller unit: - (++) Select internal/External clock - (++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx - - (#) TIM synchronization management: this group includes all needed - functions to configure the Synchronization unit: - (++) Select Input Trigger - (++) Select Output Trigger - (++) Select Master Slave Mode - (++) ETR Configuration when used as external trigger - - (#) TIM specific interface management, this group includes all - needed functions to use the specific TIM interface: - (++) Encoder Interface Configuration - (++) Select Hall Sensor - - (#) TIM specific remapping management includes the Remapping - configuration of specific timers - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_tim.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup TIM - * @brief TIM driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* ---------------------- TIM registers bit mask ------------------------ */ -#define SMCR_ETR_MASK ((uint16_t)0x00FF) -#define CCMR_OFFSET ((uint16_t)0x0018) -#define CCER_CCE_SET ((uint16_t)0x0001) -#define CCER_CCNE_SET ((uint16_t)0x0004) -#define CCMR_OC13M_MASK ((uint16_t)0xFF8F) -#define CCMR_OC24M_MASK ((uint16_t)0x8FFF) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); - -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup TIM_Private_Functions - * @{ - */ - -/** @defgroup TIM_Group1 TimeBase management functions - * @brief TimeBase management functions - * -@verbatim - =============================================================================== - ##### TimeBase management functions ##### - =============================================================================== - - - ##### TIM Driver: how to use it in Timing(Time base) Mode ##### - =============================================================================== - [..] - To use the Timer in Timing(Time base) mode, the following steps are mandatory: - - (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function - - (#) Fill the TIM_TimeBaseInitStruct with the desired parameters. - - (#) Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure the Time Base unit - with the corresponding configuration - - (#) Enable the NVIC if you need to generate the update interrupt. - - (#) Enable the corresponding interrupt using the function TIM_ITConfig(TIMx, TIM_IT_Update) - - (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. - - -@- All other functions can be used separately to modify, if needed, - a specific feature of the Timer. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the TIMx peripheral registers to their default reset values. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @retval None - - */ -void TIM_DeInit(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - if (TIMx == TIM1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); - } - else if (TIMx == TIM2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); - } - else if (TIMx == TIM3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); - } - else if (TIMx == TIM4) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); - } - else if (TIMx == TIM5) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); - } - else if (TIMx == TIM6) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); - } - else if (TIMx == TIM7) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); - } - else if (TIMx == TIM8) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); - } - else if (TIMx == TIM9) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); - } - else if (TIMx == TIM10) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); - } - else if (TIMx == TIM11) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); - } - else if (TIMx == TIM12) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE); - } - else if (TIMx == TIM13) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE); - } - else - { - if (TIMx == TIM14) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); - } - } -} - -/** - * @brief Initializes the TIMx Time Base Unit peripheral according to - * the specified parameters in the TIM_TimeBaseInitStruct. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) -{ - uint16_t tmpcr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); - assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); - - tmpcr1 = TIMx->CR1; - - if((TIMx == TIM1) || (TIMx == TIM8)|| - (TIMx == TIM2) || (TIMx == TIM3)|| - (TIMx == TIM4) || (TIMx == TIM5)) - { - /* Select the Counter Mode */ - tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS)); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; - } - - if((TIMx != TIM6) && (TIMx != TIM7)) - { - /* Set the clock division */ - tmpcr1 &= (uint16_t)(~TIM_CR1_CKD); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; - } - - TIMx->CR1 = tmpcr1; - - /* Set the Autoreload value */ - TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; - - /* Set the Prescaler value */ - TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; - - if ((TIMx == TIM1) || (TIMx == TIM8)) - { - /* Set the Repetition Counter value */ - TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; - } - - /* Generate an update event to reload the Prescaler - and the repetition counter(only for TIM1 and TIM8) value immediatly */ - TIMx->EGR = TIM_PSCReloadMode_Immediate; -} - -/** - * @brief Fills each TIM_TimeBaseInitStruct member with its default value. - * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef - * structure which will be initialized. - * @retval None - */ -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) -{ - /* Set the default configuration */ - TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF; - TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; - TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; - TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; - TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; -} - -/** - * @brief Configures the TIMx Prescaler. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param Prescaler: specifies the Prescaler Register value - * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode - * This parameter can be one of the following values: - * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. - * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly. - * @retval None - */ -void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); - /* Set the Prescaler value */ - TIMx->PSC = Prescaler; - /* Set or reset the UG Bit */ - TIMx->EGR = TIM_PSCReloadMode; -} - -/** - * @brief Specifies the TIMx Counter Mode to be used. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_CounterMode: specifies the Counter Mode to be used - * This parameter can be one of the following values: - * @arg TIM_CounterMode_Up: TIM Up Counting Mode - * @arg TIM_CounterMode_Down: TIM Down Counting Mode - * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 - * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 - * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 - * @retval None - */ -void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) -{ - uint16_t tmpcr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); - - tmpcr1 = TIMx->CR1; - - /* Reset the CMS and DIR Bits */ - tmpcr1 &= (uint16_t)~(TIM_CR1_DIR | TIM_CR1_CMS); - - /* Set the Counter Mode */ - tmpcr1 |= TIM_CounterMode; - - /* Write to TIMx CR1 register */ - TIMx->CR1 = tmpcr1; -} - -/** - * @brief Sets the TIMx Counter Register value - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param Counter: specifies the Counter register new value. - * @retval None - */ -void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Set the Counter Register value */ - TIMx->CNT = Counter; -} - -/** - * @brief Sets the TIMx Autoreload Register value - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param Autoreload: specifies the Autoreload register new value. - * @retval None - */ -void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Set the Autoreload Register value */ - TIMx->ARR = Autoreload; -} - -/** - * @brief Gets the TIMx Counter value. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @retval Counter Register value - */ -uint32_t TIM_GetCounter(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Get the Counter Register value */ - return TIMx->CNT; -} - -/** - * @brief Gets the TIMx Prescaler value. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @retval Prescaler Register value. - */ -uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Get the Prescaler Register value */ - return TIMx->PSC; -} - -/** - * @brief Enables or Disables the TIMx Update event. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param NewState: new state of the TIMx UDIS bit - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the Update Disable Bit */ - TIMx->CR1 |= TIM_CR1_UDIS; - } - else - { - /* Reset the Update Disable Bit */ - TIMx->CR1 &= (uint16_t)~TIM_CR1_UDIS; - } -} - -/** - * @brief Configures the TIMx Update Request Interrupt source. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_UpdateSource: specifies the Update source. - * This parameter can be one of the following values: - * @arg TIM_UpdateSource_Global: Source of update is the counter - * overflow/underflow or the setting of UG bit, or an update - * generation through the slave mode controller. - * @arg TIM_UpdateSource_Regular: Source of update is counter overflow/underflow. - * @retval None - */ -void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); - - if (TIM_UpdateSource != TIM_UpdateSource_Global) - { - /* Set the URS Bit */ - TIMx->CR1 |= TIM_CR1_URS; - } - else - { - /* Reset the URS Bit */ - TIMx->CR1 &= (uint16_t)~TIM_CR1_URS; - } -} - -/** - * @brief Enables or disables TIMx peripheral Preload register on ARR. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param NewState: new state of the TIMx peripheral Preload register - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the ARR Preload Bit */ - TIMx->CR1 |= TIM_CR1_ARPE; - } - else - { - /* Reset the ARR Preload Bit */ - TIMx->CR1 &= (uint16_t)~TIM_CR1_ARPE; - } -} - -/** - * @brief Selects the TIMx's One Pulse Mode. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_OPMode: specifies the OPM Mode to be used. - * This parameter can be one of the following values: - * @arg TIM_OPMode_Single - * @arg TIM_OPMode_Repetitive - * @retval None - */ -void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); - - /* Reset the OPM Bit */ - TIMx->CR1 &= (uint16_t)~TIM_CR1_OPM; - - /* Configure the OPM Mode */ - TIMx->CR1 |= TIM_OPMode; -} - -/** - * @brief Sets the TIMx Clock Division value. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_CKD: specifies the clock division value. - * This parameter can be one of the following value: - * @arg TIM_CKD_DIV1: TDTS = Tck_tim - * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim - * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim - * @retval None - */ -void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_CKD_DIV(TIM_CKD)); - - /* Reset the CKD Bits */ - TIMx->CR1 &= (uint16_t)(~TIM_CR1_CKD); - - /* Set the CKD value */ - TIMx->CR1 |= TIM_CKD; -} - -/** - * @brief Enables or disables the specified TIM peripheral. - * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral. - * @param NewState: new state of the TIMx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the TIM Counter */ - TIMx->CR1 |= TIM_CR1_CEN; - } - else - { - /* Disable the TIM Counter */ - TIMx->CR1 &= (uint16_t)~TIM_CR1_CEN; - } -} -/** - * @} - */ - -/** @defgroup TIM_Group2 Output Compare management functions - * @brief Output Compare management functions - * -@verbatim - =============================================================================== - ##### Output Compare management functions ##### - =============================================================================== - - - ##### TIM Driver: how to use it in Output Compare Mode ##### - =============================================================================== - [..] - To use the Timer in Output Compare mode, the following steps are mandatory: - - (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) - function - - (#) Configure the TIM pins by configuring the corresponding GPIO pins - - (#) Configure the Time base unit as described in the first part of this driver, - (++) if needed, else the Timer will run with the default configuration: - Autoreload value = 0xFFFF - (++) Prescaler value = 0x0000 - (++) Counter mode = Up counting - (++) Clock Division = TIM_CKD_DIV1 - - (#) Fill the TIM_OCInitStruct with the desired parameters including: - (++) The TIM Output Compare mode: TIM_OCMode - (++) TIM Output State: TIM_OutputState - (++) TIM Pulse value: TIM_Pulse - (++) TIM Output Compare Polarity : TIM_OCPolarity - - (#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired - channel with the corresponding configuration - - (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. - - -@- All other functions can be used separately to modify, if needed, - a specific feature of the Timer. - - -@- In case of PWM mode, this function is mandatory: - TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE); - - -@- If the corresponding interrupt or DMA request are needed, the user should: - (+@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests). - (+@) Enable the corresponding interrupt (or DMA request) using the function - TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the TIMx Channel1 according to the specified parameters in - * the TIM_OCInitStruct. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= (uint16_t)~TIM_CCMR1_OC1M; - tmpccmrx &= (uint16_t)~TIM_CCMR1_CC1S; - /* Select the Output Compare Mode */ - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC1P; - /* Set the Output Compare Polarity */ - tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; - - /* Set the Output State */ - tmpccer |= TIM_OCInitStruct->TIM_OutputState; - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC1NP; - /* Set the Output N Polarity */ - tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; - /* Reset the Output N State */ - tmpccer &= (uint16_t)~TIM_CCER_CC1NE; - - /* Set the Output N State */ - tmpccer |= TIM_OCInitStruct->TIM_OutputNState; - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= (uint16_t)~TIM_CR2_OIS1; - tmpcr2 &= (uint16_t)~TIM_CR2_OIS1N; - /* Set the Output Idle state */ - tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; - /* Set the Output N Idle state */ - tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel2 according to the specified parameters - * in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint16_t)~TIM_CCMR1_OC2M; - tmpccmrx &= (uint16_t)~TIM_CCMR1_CC2S; - - /* Select the Output Compare Mode */ - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC2P; - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC2NP; - /* Set the Output N Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); - /* Reset the Output N State */ - tmpccer &= (uint16_t)~TIM_CCER_CC2NE; - - /* Set the Output N State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= (uint16_t)~TIM_CR2_OIS2; - tmpcr2 &= (uint16_t)~TIM_CR2_OIS2N; - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); - /* Set the Output N Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel3 according to the specified parameters - * in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - - /* Disable the Channel 3: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint16_t)~TIM_CCMR2_OC3M; - tmpccmrx &= (uint16_t)~TIM_CCMR2_CC3S; - /* Select the Output Compare Mode */ - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC3P; - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC3NP; - /* Set the Output N Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); - /* Reset the Output N State */ - tmpccer &= (uint16_t)~TIM_CCER_CC3NE; - - /* Set the Output N State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= (uint16_t)~TIM_CR2_OIS3; - tmpcr2 &= (uint16_t)~TIM_CR2_OIS3N; - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); - /* Set the Output N Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel4 according to the specified parameters - * in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint16_t)~TIM_CCMR2_OC4M; - tmpccmrx &= (uint16_t)~TIM_CCMR2_CC4S; - - /* Select the Output Compare Mode */ - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC4P; - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - /* Reset the Output Compare IDLE State */ - tmpcr2 &=(uint16_t) ~TIM_CR2_OIS4; - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Fills each TIM_OCInitStruct member with its default value. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will - * be initialized. - * @retval None - */ -void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - /* Set the default configuration */ - TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; - TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; - TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; - TIM_OCInitStruct->TIM_Pulse = 0x00000000; - TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; - TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; -} - -/** - * @brief Selects the TIM Output Compare Mode. - * @note This function disables the selected channel before changing the Output - * Compare Mode. If needed, user has to enable this channel using - * TIM_CCxCmd() and TIM_CCxNCmd() functions. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @param TIM_OCMode: specifies the TIM Output Compare Mode. - * This parameter can be one of the following values: - * @arg TIM_OCMode_Timing - * @arg TIM_OCMode_Active - * @arg TIM_OCMode_Toggle - * @arg TIM_OCMode_PWM1 - * @arg TIM_OCMode_PWM2 - * @arg TIM_ForcedAction_Active - * @arg TIM_ForcedAction_InActive - * @retval None - */ -void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) -{ - uint32_t tmp = 0; - uint16_t tmp1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_OCM(TIM_OCMode)); - - tmp = (uint32_t) TIMx; - tmp += CCMR_OFFSET; - - tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel; - - /* Disable the Channel: Reset the CCxE Bit */ - TIMx->CCER &= (uint16_t) ~tmp1; - - if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) - { - tmp += (TIM_Channel>>1); - - /* Reset the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp &= CCMR_OC13M_MASK; - - /* Configure the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp |= TIM_OCMode; - } - else - { - tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1; - - /* Reset the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp &= CCMR_OC24M_MASK; - - /* Configure the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8); - } -} - -/** - * @brief Sets the TIMx Capture Compare1 Register value - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param Compare1: specifies the Capture Compare1 register new value. - * @retval None - */ -void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - - /* Set the Capture Compare1 Register value */ - TIMx->CCR1 = Compare1; -} - -/** - * @brief Sets the TIMx Capture Compare2 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param Compare2: specifies the Capture Compare2 register new value. - * @retval None - */ -void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - - /* Set the Capture Compare2 Register value */ - TIMx->CCR2 = Compare2; -} - -/** - * @brief Sets the TIMx Capture Compare3 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param Compare3: specifies the Capture Compare3 register new value. - * @retval None - */ -void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Set the Capture Compare3 Register value */ - TIMx->CCR3 = Compare3; -} - -/** - * @brief Sets the TIMx Capture Compare4 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param Compare4: specifies the Capture Compare4 register new value. - * @retval None - */ -void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Set the Capture Compare4 Register value */ - TIMx->CCR4 = Compare4; -} - -/** - * @brief Forces the TIMx output 1 waveform to active or inactive level. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC1REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. - * @retval None - */ -void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC1M Bits */ - tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1M; - - /* Configure The Forced output Mode */ - tmpccmr1 |= TIM_ForcedAction; - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Forces the TIMx output 2 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC2REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. - * @retval None - */ -void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC2M Bits */ - tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2M; - - /* Configure The Forced output Mode */ - tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Forces the TIMx output 3 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC3REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. - * @retval None - */ -void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC1M Bits */ - tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3M; - - /* Configure The Forced output Mode */ - tmpccmr2 |= TIM_ForcedAction; - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Forces the TIMx output 4 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC4REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. - * @retval None - */ -void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC2M Bits */ - tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4M; - - /* Configure The Forced output Mode */ - tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR1. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC1PE Bit */ - tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC1PE); - - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr1 |= TIM_OCPreload; - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR2. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC2PE Bit */ - tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2PE); - - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR3. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC3PE Bit */ - tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC3PE); - - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr2 |= TIM_OCPreload; - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR4. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC4PE Bit */ - tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4PE); - - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx Output Compare 1 Fast feature. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC1FE Bit */ - tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1FE; - - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr1 |= TIM_OCFast; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Configures the TIMx Output Compare 2 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC2FE Bit */ - tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2FE); - - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Configures the TIMx Output Compare 3 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC3FE Bit */ - tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3FE; - - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr2 |= TIM_OCFast; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx Output Compare 4 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC4FE Bit */ - tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4FE); - - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Clears or safeguards the OCREF1 signal on an external event - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC1CE Bit */ - tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1CE; - - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr1 |= TIM_OCClear; - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Clears or safeguards the OCREF2 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC2CE Bit */ - tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2CE; - - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Clears or safeguards the OCREF3 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC3CE Bit */ - tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3CE; - - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr2 |= TIM_OCClear; - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Clears or safeguards the OCREF4 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC4CE Bit */ - tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4CE; - - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx channel 1 polarity. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC1 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC1P Bit */ - tmpccer &= (uint16_t)(~TIM_CCER_CC1P); - tmpccer |= TIM_OCPolarity; - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 1N polarity. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC1N Polarity - * This parameter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC1NP Bit */ - tmpccer &= (uint16_t)~TIM_CCER_CC1NP; - tmpccer |= TIM_OCNPolarity; - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 2 polarity. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_OCPolarity: specifies the OC2 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC2P Bit */ - tmpccer &= (uint16_t)(~TIM_CCER_CC2P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 4); - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 2N polarity. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC2N Polarity - * This parameter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC2NP Bit */ - tmpccer &= (uint16_t)~TIM_CCER_CC2NP; - tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 3 polarity. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC3 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC3P Bit */ - tmpccer &= (uint16_t)~TIM_CCER_CC3P; - tmpccer |= (uint16_t)(TIM_OCPolarity << 8); - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 3N polarity. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC3N Polarity - * This parameter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC3NP Bit */ - tmpccer &= (uint16_t)~TIM_CCER_CC3NP; - tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 4 polarity. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC4 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC4P Bit */ - tmpccer &= (uint16_t)~TIM_CCER_CC4P; - tmpccer |= (uint16_t)(TIM_OCPolarity << 12); - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel x. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. - * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. - * @retval None - */ -void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) -{ - uint16_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_CCX(TIM_CCx)); - - tmp = CCER_CCE_SET << TIM_Channel; - - /* Reset the CCxE Bit */ - TIMx->CCER &= (uint16_t)~ tmp; - - /* Set or reset the CCxE Bit */ - TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel xN. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. - * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. - * @retval None - */ -void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) -{ - uint16_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_CCXN(TIM_CCxN)); - - tmp = CCER_CCNE_SET << TIM_Channel; - - /* Reset the CCxNE Bit */ - TIMx->CCER &= (uint16_t) ~tmp; - - /* Set or reset the CCxNE Bit */ - TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); -} -/** - * @} - */ - -/** @defgroup TIM_Group3 Input Capture management functions - * @brief Input Capture management functions - * -@verbatim - =============================================================================== - ##### Input Capture management functions ##### - =============================================================================== - - ##### TIM Driver: how to use it in Input Capture Mode ##### - =============================================================================== - [..] - To use the Timer in Input Capture mode, the following steps are mandatory: - - (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) - function - - (#) Configure the TIM pins by configuring the corresponding GPIO pins - - (#) Configure the Time base unit as described in the first part of this driver, - if needed, else the Timer will run with the default configuration: - (++) Autoreload value = 0xFFFF - (++) Prescaler value = 0x0000 - (++) Counter mode = Up counting - (++) Clock Division = TIM_CKD_DIV1 - - (#) Fill the TIM_ICInitStruct with the desired parameters including: - (++) TIM Channel: TIM_Channel - (++) TIM Input Capture polarity: TIM_ICPolarity - (++) TIM Input Capture selection: TIM_ICSelection - (++) TIM Input Capture Prescaler: TIM_ICPrescaler - (++) TIM Input CApture filter value: TIM_ICFilter - - (#) Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel - with the corresponding configuration and to measure only frequency - or duty cycle of the input signal, or, Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) - to configure the desired channels with the corresponding configuration - and to measure the frequency and the duty cycle of the input signal - - (#) Enable the NVIC or the DMA to read the measured frequency. - - (#) Enable the corresponding interrupt (or DMA request) to read the Captured - value, using the function TIM_ITConfig(TIMx, TIM_IT_CCx) - (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) - - (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. - - (#) Use TIM_GetCapturex(TIMx); to read the captured value. - - -@- All other functions can be used separately to modify, if needed, - a specific feature of the Timer. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the TIM peripheral according to the specified parameters - * in the TIM_ICInitStruct. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); - assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); - assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); - - if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - /* TI1 Configuration */ - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) - { - /* TI2 Configuration */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) - { - /* TI3 Configuration */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - /* TI4 Configuration */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/** - * @brief Fills each TIM_ICInitStruct member with its default value. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will - * be initialized. - * @retval None - */ -void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - /* Set the default configuration */ - TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; - TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; - TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; - TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; - TIM_ICInitStruct->TIM_ICFilter = 0x00; -} - -/** - * @brief Configures the TIM peripheral according to the specified parameters - * in the TIM_ICInitStruct to measure an external PWM signal. - * @param TIMx: where x can be 1, 2, 3, 4, 5,8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - uint16_t icoppositepolarity = TIM_ICPolarity_Rising; - uint16_t icoppositeselection = TIM_ICSelection_DirectTI; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - - /* Select the Opposite Input Polarity */ - if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) - { - icoppositepolarity = TIM_ICPolarity_Falling; - } - else - { - icoppositepolarity = TIM_ICPolarity_Rising; - } - /* Select the Opposite Input */ - if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) - { - icoppositeselection = TIM_ICSelection_IndirectTI; - } - else - { - icoppositeselection = TIM_ICSelection_DirectTI; - } - if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - /* TI1 Configuration */ - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - /* TI2 Configuration */ - TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - /* TI2 Configuration */ - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - /* TI1 Configuration */ - TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/** - * @brief Gets the TIMx Input Capture 1 value. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @retval Capture Compare 1 Register value. - */ -uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - - /* Get the Capture 1 Register value */ - return TIMx->CCR1; -} - -/** - * @brief Gets the TIMx Input Capture 2 value. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @retval Capture Compare 2 Register value. - */ -uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - - /* Get the Capture 2 Register value */ - return TIMx->CCR2; -} - -/** - * @brief Gets the TIMx Input Capture 3 value. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @retval Capture Compare 3 Register value. - */ -uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Get the Capture 3 Register value */ - return TIMx->CCR3; -} - -/** - * @brief Gets the TIMx Input Capture 4 value. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @retval Capture Compare 4 Register value. - */ -uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Get the Capture 4 Register value */ - return TIMx->CCR4; -} - -/** - * @brief Sets the TIMx Input Capture 1 prescaler. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC1PSC Bits */ - TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC; - - /* Set the IC1PSC value */ - TIMx->CCMR1 |= TIM_ICPSC; -} - -/** - * @brief Sets the TIMx Input Capture 2 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC2PSC Bits */ - TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC; - - /* Set the IC2PSC value */ - TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8); -} - -/** - * @brief Sets the TIMx Input Capture 3 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC3PSC Bits */ - TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC; - - /* Set the IC3PSC value */ - TIMx->CCMR2 |= TIM_ICPSC; -} - -/** - * @brief Sets the TIMx Input Capture 4 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC4PSC Bits */ - TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC; - - /* Set the IC4PSC value */ - TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); -} -/** - * @} - */ - -/** @defgroup TIM_Group4 Advanced-control timers (TIM1 and TIM8) specific features - * @brief Advanced-control timers (TIM1 and TIM8) specific features - * -@verbatim - =============================================================================== - ##### Advanced-control timers (TIM1 and TIM8) specific features ##### - =============================================================================== - - ##### TIM Driver: how to use the Break feature ##### - =============================================================================== - [..] - After configuring the Timer channel(s) in the appropriate Output Compare mode: - - (#) Fill the TIM_BDTRInitStruct with the desired parameters for the Timer - Break Polarity, dead time, Lock level, the OSSI/OSSR State and the - AOE(automatic output enable). - - (#) Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer - - (#) Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE) - - (#) Once the break even occurs, the Timer's output signals are put in reset - state or in a known state (according to the configuration made in - TIM_BDTRConfig() function). - -@endverbatim - * @{ - */ - -/** - * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State - * and the AOE(automatic output enable). - * @param TIMx: where x can be 1 or 8 to select the TIM - * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that - * contains the BDTR Register configuration information for the TIM peripheral. - * @retval None - */ -void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); - assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); - assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); - assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); - assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); - assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); - - /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, - the OSSI State, the dead time value and the Automatic Output Enable Bit */ - TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | - TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | - TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | - TIM_BDTRInitStruct->TIM_AutomaticOutput; -} - -/** - * @brief Fills each TIM_BDTRInitStruct member with its default value. - * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which - * will be initialized. - * @retval None - */ -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) -{ - /* Set the default configuration */ - TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; - TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; - TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; - TIM_BDTRInitStruct->TIM_DeadTime = 0x00; - TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; - TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; - TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; -} - -/** - * @brief Enables or disables the TIM peripheral Main Outputs. - * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral. - * @param NewState: new state of the TIM peripheral Main Outputs. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the TIM Main Output */ - TIMx->BDTR |= TIM_BDTR_MOE; - } - else - { - /* Disable the TIM Main Output */ - TIMx->BDTR &= (uint16_t)~TIM_BDTR_MOE; - } -} - -/** - * @brief Selects the TIM peripheral Commutation event. - * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral - * @param NewState: new state of the Commutation event. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the COM Bit */ - TIMx->CR2 |= TIM_CR2_CCUS; - } - else - { - /* Reset the COM Bit */ - TIMx->CR2 &= (uint16_t)~TIM_CR2_CCUS; - } -} - -/** - * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. - * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral - * @param NewState: new state of the Capture Compare Preload Control bit - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the CCPC Bit */ - TIMx->CR2 |= TIM_CR2_CCPC; - } - else - { - /* Reset the CCPC Bit */ - TIMx->CR2 &= (uint16_t)~TIM_CR2_CCPC; - } -} -/** - * @} - */ - -/** @defgroup TIM_Group5 Interrupts DMA and flags management functions - * @brief Interrupts, DMA and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts, DMA and flags management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified TIM interrupts. - * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral. - * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg TIM_IT_Update: TIM update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * - * @note For TIM6 and TIM7 only the parameter TIM_IT_Update can be used - * @note For TIM9 and TIM12 only one of the following parameters can be used: TIM_IT_Update, - * TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. - * @note For TIM10, TIM11, TIM13 and TIM14 only one of the following parameters can - * be used: TIM_IT_Update or TIM_IT_CC1 - * @note TIM_IT_COM and TIM_IT_Break can be used only with TIM1 and TIM8 - * - * @param NewState: new state of the TIM interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_IT(TIM_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Interrupt sources */ - TIMx->DIER |= TIM_IT; - } - else - { - /* Disable the Interrupt sources */ - TIMx->DIER &= (uint16_t)~TIM_IT; - } -} - -/** - * @brief Configures the TIMx event to be generate by software. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_EventSource: specifies the event source. - * This parameter can be one or more of the following values: - * @arg TIM_EventSource_Update: Timer update Event source - * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source - * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source - * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source - * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source - * @arg TIM_EventSource_COM: Timer COM event source - * @arg TIM_EventSource_Trigger: Timer Trigger Event source - * @arg TIM_EventSource_Break: Timer Break event source - * - * @note TIM6 and TIM7 can only generate an update event. - * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8. - * - * @retval None - */ -void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); - - /* Set the event sources */ - TIMx->EGR = TIM_EventSource; -} - -/** - * @brief Checks whether the specified TIM flag is set or not. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg TIM_FLAG_Update: TIM update Flag - * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag - * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag - * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag - * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag - * @arg TIM_FLAG_COM: TIM Commutation Flag - * @arg TIM_FLAG_Trigger: TIM Trigger Flag - * @arg TIM_FLAG_Break: TIM Break Flag - * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag - * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag - * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag - * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag - * - * @note TIM6 and TIM7 can have only one update flag. - * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8. - * - * @retval The new state of TIM_FLAG (SET or RESET). - */ -FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); - - - if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the TIMx's pending flags. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_FLAG: specifies the flag bit to clear. - * This parameter can be any combination of the following values: - * @arg TIM_FLAG_Update: TIM update Flag - * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag - * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag - * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag - * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag - * @arg TIM_FLAG_COM: TIM Commutation Flag - * @arg TIM_FLAG_Trigger: TIM Trigger Flag - * @arg TIM_FLAG_Break: TIM Break Flag - * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag - * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag - * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag - * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag - * - * @note TIM6 and TIM7 can have only one update flag. - * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8. - * - * @retval None - */ -void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Clear the flags */ - TIMx->SR = (uint16_t)~TIM_FLAG; -} - -/** - * @brief Checks whether the TIM interrupt has occurred or not. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_IT: specifies the TIM interrupt source to check. - * This parameter can be one of the following values: - * @arg TIM_IT_Update: TIM update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * - * @note TIM6 and TIM7 can generate only an update interrupt. - * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. - * - * @retval The new state of the TIM_IT(SET or RESET). - */ -ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itstatus = 0x0, itenable = 0x0; - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_GET_IT(TIM_IT)); - - itstatus = TIMx->SR & TIM_IT; - - itenable = TIMx->DIER & TIM_IT; - if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the TIMx's interrupt pending bits. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_IT: specifies the pending bit to clear. - * This parameter can be any combination of the following values: - * @arg TIM_IT_Update: TIM1 update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * - * @note TIM6 and TIM7 can generate only an update interrupt. - * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. - * - * @retval None - */ -void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Clear the IT pending Bit */ - TIMx->SR = (uint16_t)~TIM_IT; -} - -/** - * @brief Configures the TIMx's DMA interface. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_DMABase: DMA Base address. - * This parameter can be one of the following values: - * @arg TIM_DMABase_CR1 - * @arg TIM_DMABase_CR2 - * @arg TIM_DMABase_SMCR - * @arg TIM_DMABase_DIER - * @arg TIM1_DMABase_SR - * @arg TIM_DMABase_EGR - * @arg TIM_DMABase_CCMR1 - * @arg TIM_DMABase_CCMR2 - * @arg TIM_DMABase_CCER - * @arg TIM_DMABase_CNT - * @arg TIM_DMABase_PSC - * @arg TIM_DMABase_ARR - * @arg TIM_DMABase_RCR - * @arg TIM_DMABase_CCR1 - * @arg TIM_DMABase_CCR2 - * @arg TIM_DMABase_CCR3 - * @arg TIM_DMABase_CCR4 - * @arg TIM_DMABase_BDTR - * @arg TIM_DMABase_DCR - * @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value - * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. - * @retval None - */ -void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); - assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); - - /* Set the DMA Base and the DMA Burst Length */ - TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; -} - -/** - * @brief Enables or disables the TIMx's DMA Requests. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral. - * @param TIM_DMASource: specifies the DMA Request sources. - * This parameter can be any combination of the following values: - * @arg TIM_DMA_Update: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_Trigger: TIM Trigger DMA source - * @param NewState: new state of the DMA Request sources. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST5_PERIPH(TIMx)); - assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DMA sources */ - TIMx->DIER |= TIM_DMASource; - } - else - { - /* Disable the DMA sources */ - TIMx->DIER &= (uint16_t)~TIM_DMASource; - } -} - -/** - * @brief Selects the TIMx peripheral Capture Compare DMA source. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param NewState: new state of the Capture Compare DMA source - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the CCDS Bit */ - TIMx->CR2 |= TIM_CR2_CCDS; - } - else - { - /* Reset the CCDS Bit */ - TIMx->CR2 &= (uint16_t)~TIM_CR2_CCDS; - } -} -/** - * @} - */ - -/** @defgroup TIM_Group6 Clocks management functions - * @brief Clocks management functions - * -@verbatim - =============================================================================== - ##### Clocks management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the TIMx internal Clock - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @retval None - */ -void TIM_InternalClockConfig(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - - /* Disable slave mode to clock the prescaler directly with the internal clock */ - TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS; -} - -/** - * @brief Configures the TIMx Internal Trigger as External Clock - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_InputTriggerSource: Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal Trigger 0 - * @arg TIM_TS_ITR1: Internal Trigger 1 - * @arg TIM_TS_ITR2: Internal Trigger 2 - * @arg TIM_TS_ITR3: Internal Trigger 3 - * @retval None - */ -void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); - - /* Select the Internal Trigger */ - TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); - - /* Select the External clock mode1 */ - TIMx->SMCR |= TIM_SlaveMode_External1; -} - -/** - * @brief Configures the TIMx Trigger as External Clock - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 - * to select the TIM peripheral. - * @param TIM_TIxExternalCLKSource: Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector - * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 - * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 - * @param TIM_ICPolarity: specifies the TIx Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param ICFilter: specifies the filter value. - * This parameter must be a value between 0x0 and 0xF. - * @retval None - */ -void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); - assert_param(IS_TIM_IC_FILTER(ICFilter)); - - /* Configure the Timer Input Clock Source */ - if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) - { - TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - else - { - TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - /* Select the Trigger source */ - TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); - /* Select the External clock mode1 */ - TIMx->SMCR |= TIM_SlaveMode_External1; -} - -/** - * @brief Configures the External clock Mode1 - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - /* Configure the ETR Clock source */ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - - /* Reset the SMS Bits */ - tmpsmcr &= (uint16_t)~TIM_SMCR_SMS; - - /* Select the External clock mode1 */ - tmpsmcr |= TIM_SlaveMode_External1; - - /* Select the Trigger selection : ETRF */ - tmpsmcr &= (uint16_t)~TIM_SMCR_TS; - tmpsmcr |= TIM_TS_ETRF; - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Configures the External clock Mode2 - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - - /* Configure the ETR Clock source */ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - - /* Enable the External clock mode2 */ - TIMx->SMCR |= TIM_SMCR_ECE; -} -/** - * @} - */ - -/** @defgroup TIM_Group7 Synchronization management functions - * @brief Synchronization management functions - * -@verbatim - =============================================================================== - ##### Synchronization management functions ##### - =============================================================================== - - ##### TIM Driver: how to use it in synchronization Mode ##### - =============================================================================== - [..] - - *** Case of two/several Timers *** - ================================== - [..] - (#) Configure the Master Timers using the following functions: - (++) void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); - (++) void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); - (#) Configure the Slave Timers using the following functions: - (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); - (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); - - *** Case of Timers and external trigger(ETR pin) *** - ==================================================== - [..] - (#) Configure the External trigger using this function: - (++) void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); - (#) Configure the Slave Timers using the following functions: - (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); - (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); - -@endverbatim - * @{ - */ - -/** - * @brief Selects the Input Trigger source - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 - * to select the TIM peripheral. - * @param TIM_InputTriggerSource: The Input Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal Trigger 0 - * @arg TIM_TS_ITR1: Internal Trigger 1 - * @arg TIM_TS_ITR2: Internal Trigger 2 - * @arg TIM_TS_ITR3: Internal Trigger 3 - * @arg TIM_TS_TI1F_ED: TI1 Edge Detector - * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 - * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 - * @arg TIM_TS_ETRF: External Trigger input - * @retval None - */ -void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) -{ - uint16_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - - /* Reset the TS Bits */ - tmpsmcr &= (uint16_t)~TIM_SMCR_TS; - - /* Set the Input Trigger source */ - tmpsmcr |= TIM_InputTriggerSource; - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Selects the TIMx Trigger Output Mode. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral. - * - * @param TIM_TRGOSource: specifies the Trigger Output source. - * This parameter can be one of the following values: - * - * - For all TIMx - * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output(TRGO) - * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO) - * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO) - * - * - For all TIMx except TIM6 and TIM7 - * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag - * is to be set, as soon as a capture or compare match occurs(TRGO) - * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO) - * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO) - * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO) - * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO) - * - * @retval None - */ -void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST5_PERIPH(TIMx)); - assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); - - /* Reset the MMS Bits */ - TIMx->CR2 &= (uint16_t)~TIM_CR2_MMS; - /* Select the TRGO source */ - TIMx->CR2 |= TIM_TRGOSource; -} - -/** - * @brief Selects the TIMx Slave Mode. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral. - * @param TIM_SlaveMode: specifies the Timer Slave Mode. - * This parameter can be one of the following values: - * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal(TRGI) reinitialize - * the counter and triggers an update of the registers - * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high - * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI - * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter - * @retval None - */ -void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); - - /* Reset the SMS Bits */ - TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS; - - /* Select the Slave Mode */ - TIMx->SMCR |= TIM_SlaveMode; -} - -/** - * @brief Sets or Resets the TIMx Master/Slave Mode. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral. - * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. - * This parameter can be one of the following values: - * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer - * and its slaves (through TRGO) - * @arg TIM_MasterSlaveMode_Disable: No action - * @retval None - */ -void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); - - /* Reset the MSM Bit */ - TIMx->SMCR &= (uint16_t)~TIM_SMCR_MSM; - - /* Set or Reset the MSM Bit */ - TIMx->SMCR |= TIM_MasterSlaveMode; -} - -/** - * @brief Configures the TIMx External Trigger (ETR). - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - - tmpsmcr = TIMx->SMCR; - - /* Reset the ETR Bits */ - tmpsmcr &= SMCR_ETR_MASK; - - /* Set the Prescaler, the Filter value and the Polarity */ - tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} -/** - * @} - */ - -/** @defgroup TIM_Group8 Specific interface management functions - * @brief Specific interface management functions - * -@verbatim - =============================================================================== - ##### Specific interface management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the TIMx Encoder Interface. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_EncoderMode: specifies the TIMx Encoder Mode. - * This parameter can be one of the following values: - * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. - * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. - * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending - * on the level of the other input. - * @param TIM_IC1Polarity: specifies the IC1 Polarity - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Falling: IC Falling edge. - * @arg TIM_ICPolarity_Rising: IC Rising edge. - * @param TIM_IC2Polarity: specifies the IC2 Polarity - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Falling: IC Falling edge. - * @arg TIM_ICPolarity_Rising: IC Rising edge. - * @retval None - */ -void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) -{ - uint16_t tmpsmcr = 0; - uint16_t tmpccmr1 = 0; - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); - assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); - assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - - /* Set the encoder Mode */ - tmpsmcr &= (uint16_t)~TIM_SMCR_SMS; - tmpsmcr |= TIM_EncoderMode; - - /* Select the Capture Compare 1 and the Capture Compare 2 as input */ - tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_CC2S); - tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; - - /* Set the TI1 and the TI2 Polarities */ - tmpccer &= ((uint16_t)~TIM_CCER_CC1P) & ((uint16_t)~TIM_CCER_CC2P); - tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Enables or disables the TIMx's Hall sensor interface. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param NewState: new state of the TIMx Hall sensor interface. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the TI1S Bit */ - TIMx->CR2 |= TIM_CR2_TI1S; - } - else - { - /* Reset the TI1S Bit */ - TIMx->CR2 &= (uint16_t)~TIM_CR2_TI1S; - } -} -/** - * @} - */ - -/** @defgroup TIM_Group9 Specific remapping management function - * @brief Specific remapping management function - * -@verbatim - =============================================================================== - ##### Specific remapping management function ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities. - * @param TIMx: where x can be 2, 5 or 11 to select the TIM peripheral. - * @param TIM_Remap: specifies the TIM input remapping source. - * This parameter can be one of the following values: - * @arg TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default) - * @arg TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trogger output. - * @arg TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF. - * @arg TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF. - * @arg TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default) - * @arg TIM5_LSI: TIM5 CH4 input is connected to LSI clock. - * @arg TIM5_LSE: TIM5 CH4 input is connected to LSE clock. - * @arg TIM5_RTC: TIM5 CH4 input is connected to RTC Output event. - * @arg TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default) - * @arg TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock - * (HSE divided by a programmable prescaler) - * @retval None - */ -void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_REMAP(TIM_Remap)); - - /* Set the Timer remapping configuration */ - TIMx->OR = TIM_Remap; -} -/** - * @} - */ - -/** - * @brief Configure the TI1 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 - * to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. - * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. - * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0; - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - - /* Select the Input and set the filter */ - tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_IC1F); - tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI2 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. - * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. - * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 4); - - /* Select the Input and set the filter */ - tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F); - tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); - tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); - - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI3 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. - * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. - * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - /* Disable the Channel 3: Reset the CC3E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E; - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 8); - - /* Select the Input and set the filter */ - tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR2_IC3F); - tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - - /* Select the Polarity and set the CC3E Bit */ - tmpccer &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI4 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. - * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. - * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E; - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 12); - - /* Select the Input and set the filter */ - tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F); - tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); - tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); - - /* Select the Polarity and set the CC4E Bit */ - tmpccer &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E); - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer ; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm32f4xx_tim.h b/stm/stmperiph/stm32f4xx_tim.h deleted file mode 100644 index 7983cc024..000000000 --- a/stm/stmperiph/stm32f4xx_tim.h +++ /dev/null @@ -1,1150 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_tim.h - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief This file contains all the functions prototypes for the TIM firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_TIM_H -#define __STM32F4xx_TIM_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup TIM - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief TIM Time Base Init structure definition - * @note This structure is used with all TIMx except for TIM6 and TIM7. - */ - -typedef struct -{ - uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t TIM_CounterMode; /*!< Specifies the counter mode. - This parameter can be a value of @ref TIM_Counter_Mode */ - - uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active - Auto-Reload Register at the next update event. - This parameter must be a number between 0x0000 and 0xFFFF. */ - - uint16_t TIM_ClockDivision; /*!< Specifies the clock division. - This parameter can be a value of @ref TIM_Clock_Division_CKD */ - - uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter - reaches zero, an update event is generated and counting restarts - from the RCR value (N). - This means in PWM mode that (N+1) corresponds to: - - the number of PWM periods in edge-aligned mode - - the number of half PWM period in center-aligned mode - This parameter must be a number between 0x00 and 0xFF. - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_TimeBaseInitTypeDef; - -/** - * @brief TIM Output Compare Init structure definition - */ - -typedef struct -{ - uint16_t TIM_OCMode; /*!< Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_State */ - - uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_N_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t TIM_OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_OCInitTypeDef; - -/** - * @brief TIM Input Capture Init structure definition - */ - -typedef struct -{ - - uint16_t TIM_Channel; /*!< Specifies the TIM channel. - This parameter can be a value of @ref TIM_Channel */ - - uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint16_t TIM_ICSelection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between 0x0 and 0xF */ -} TIM_ICInitTypeDef; - -/** - * @brief BDTR structure definition - * @note This structure is used only with TIM1 and TIM8. - */ - -typedef struct -{ - - uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode. - This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ - - uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state. - This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ - - uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. - This parameter can be a value of @ref TIM_Lock_level */ - - uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the - switching-on of the outputs. - This parameter can be a number between 0x00 and 0xFF */ - - uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. - This parameter can be a value of @ref TIM_Break_Input_enable_disable */ - - uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. - This parameter can be a value of @ref TIM_Break_Polarity */ - - uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. - This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ -} TIM_BDTRInitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup TIM_Exported_constants - * @{ - */ - -#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM6) || \ - ((PERIPH) == TIM7) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM9) || \ - ((PERIPH) == TIM10) || \ - ((PERIPH) == TIM11) || \ - ((PERIPH) == TIM12) || \ - (((PERIPH) == TIM13) || \ - ((PERIPH) == TIM14))) -/* LIST1: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9, TIM10, TIM11, TIM12, TIM13 and TIM14 */ -#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM9) || \ - ((PERIPH) == TIM10) || \ - ((PERIPH) == TIM11) || \ - ((PERIPH) == TIM12) || \ - ((PERIPH) == TIM13) || \ - ((PERIPH) == TIM14)) - -/* LIST2: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9 and TIM12 */ -#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM9) || \ - ((PERIPH) == TIM12)) -/* LIST3: TIM1, TIM2, TIM3, TIM4, TIM5 and TIM8 */ -#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM8)) -/* LIST4: TIM1 and TIM8 */ -#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM8)) -/* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */ -#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM6) || \ - ((PERIPH) == TIM7) || \ - ((PERIPH) == TIM8)) -/* LIST6: TIM2, TIM5 and TIM11 */ -#define IS_TIM_LIST6_PERIPH(TIMx)(((TIMx) == TIM2) || \ - ((TIMx) == TIM5) || \ - ((TIMx) == TIM11)) - -/** @defgroup TIM_Output_Compare_and_PWM_modes - * @{ - */ - -#define TIM_OCMode_Timing ((uint16_t)0x0000) -#define TIM_OCMode_Active ((uint16_t)0x0010) -#define TIM_OCMode_Inactive ((uint16_t)0x0020) -#define TIM_OCMode_Toggle ((uint16_t)0x0030) -#define TIM_OCMode_PWM1 ((uint16_t)0x0060) -#define TIM_OCMode_PWM2 ((uint16_t)0x0070) -#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ - ((MODE) == TIM_OCMode_Active) || \ - ((MODE) == TIM_OCMode_Inactive) || \ - ((MODE) == TIM_OCMode_Toggle)|| \ - ((MODE) == TIM_OCMode_PWM1) || \ - ((MODE) == TIM_OCMode_PWM2)) -#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ - ((MODE) == TIM_OCMode_Active) || \ - ((MODE) == TIM_OCMode_Inactive) || \ - ((MODE) == TIM_OCMode_Toggle)|| \ - ((MODE) == TIM_OCMode_PWM1) || \ - ((MODE) == TIM_OCMode_PWM2) || \ - ((MODE) == TIM_ForcedAction_Active) || \ - ((MODE) == TIM_ForcedAction_InActive)) -/** - * @} - */ - -/** @defgroup TIM_One_Pulse_Mode - * @{ - */ - -#define TIM_OPMode_Single ((uint16_t)0x0008) -#define TIM_OPMode_Repetitive ((uint16_t)0x0000) -#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ - ((MODE) == TIM_OPMode_Repetitive)) -/** - * @} - */ - -/** @defgroup TIM_Channel - * @{ - */ - -#define TIM_Channel_1 ((uint16_t)0x0000) -#define TIM_Channel_2 ((uint16_t)0x0004) -#define TIM_Channel_3 ((uint16_t)0x0008) -#define TIM_Channel_4 ((uint16_t)0x000C) - -#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2) || \ - ((CHANNEL) == TIM_Channel_3) || \ - ((CHANNEL) == TIM_Channel_4)) - -#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2)) -#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2) || \ - ((CHANNEL) == TIM_Channel_3)) -/** - * @} - */ - -/** @defgroup TIM_Clock_Division_CKD - * @{ - */ - -#define TIM_CKD_DIV1 ((uint16_t)0x0000) -#define TIM_CKD_DIV2 ((uint16_t)0x0100) -#define TIM_CKD_DIV4 ((uint16_t)0x0200) -#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ - ((DIV) == TIM_CKD_DIV2) || \ - ((DIV) == TIM_CKD_DIV4)) -/** - * @} - */ - -/** @defgroup TIM_Counter_Mode - * @{ - */ - -#define TIM_CounterMode_Up ((uint16_t)0x0000) -#define TIM_CounterMode_Down ((uint16_t)0x0010) -#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) -#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) -#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) -#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ - ((MODE) == TIM_CounterMode_Down) || \ - ((MODE) == TIM_CounterMode_CenterAligned1) || \ - ((MODE) == TIM_CounterMode_CenterAligned2) || \ - ((MODE) == TIM_CounterMode_CenterAligned3)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Polarity - * @{ - */ - -#define TIM_OCPolarity_High ((uint16_t)0x0000) -#define TIM_OCPolarity_Low ((uint16_t)0x0002) -#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ - ((POLARITY) == TIM_OCPolarity_Low)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Polarity - * @{ - */ - -#define TIM_OCNPolarity_High ((uint16_t)0x0000) -#define TIM_OCNPolarity_Low ((uint16_t)0x0008) -#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ - ((POLARITY) == TIM_OCNPolarity_Low)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_State - * @{ - */ - -#define TIM_OutputState_Disable ((uint16_t)0x0000) -#define TIM_OutputState_Enable ((uint16_t)0x0001) -#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ - ((STATE) == TIM_OutputState_Enable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_State - * @{ - */ - -#define TIM_OutputNState_Disable ((uint16_t)0x0000) -#define TIM_OutputNState_Enable ((uint16_t)0x0004) -#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ - ((STATE) == TIM_OutputNState_Enable)) -/** - * @} - */ - -/** @defgroup TIM_Capture_Compare_State - * @{ - */ - -#define TIM_CCx_Enable ((uint16_t)0x0001) -#define TIM_CCx_Disable ((uint16_t)0x0000) -#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ - ((CCX) == TIM_CCx_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Capture_Compare_N_State - * @{ - */ - -#define TIM_CCxN_Enable ((uint16_t)0x0004) -#define TIM_CCxN_Disable ((uint16_t)0x0000) -#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ - ((CCXN) == TIM_CCxN_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Break_Input_enable_disable - * @{ - */ - -#define TIM_Break_Enable ((uint16_t)0x1000) -#define TIM_Break_Disable ((uint16_t)0x0000) -#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ - ((STATE) == TIM_Break_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Break_Polarity - * @{ - */ - -#define TIM_BreakPolarity_Low ((uint16_t)0x0000) -#define TIM_BreakPolarity_High ((uint16_t)0x2000) -#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ - ((POLARITY) == TIM_BreakPolarity_High)) -/** - * @} - */ - -/** @defgroup TIM_AOE_Bit_Set_Reset - * @{ - */ - -#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) -#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) -#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ - ((STATE) == TIM_AutomaticOutput_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Lock_level - * @{ - */ - -#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) -#define TIM_LOCKLevel_1 ((uint16_t)0x0100) -#define TIM_LOCKLevel_2 ((uint16_t)0x0200) -#define TIM_LOCKLevel_3 ((uint16_t)0x0300) -#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ - ((LEVEL) == TIM_LOCKLevel_1) || \ - ((LEVEL) == TIM_LOCKLevel_2) || \ - ((LEVEL) == TIM_LOCKLevel_3)) -/** - * @} - */ - -/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state - * @{ - */ - -#define TIM_OSSIState_Enable ((uint16_t)0x0400) -#define TIM_OSSIState_Disable ((uint16_t)0x0000) -#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ - ((STATE) == TIM_OSSIState_Disable)) -/** - * @} - */ - -/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state - * @{ - */ - -#define TIM_OSSRState_Enable ((uint16_t)0x0800) -#define TIM_OSSRState_Disable ((uint16_t)0x0000) -#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ - ((STATE) == TIM_OSSRState_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Idle_State - * @{ - */ - -#define TIM_OCIdleState_Set ((uint16_t)0x0100) -#define TIM_OCIdleState_Reset ((uint16_t)0x0000) -#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ - ((STATE) == TIM_OCIdleState_Reset)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Idle_State - * @{ - */ - -#define TIM_OCNIdleState_Set ((uint16_t)0x0200) -#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) -#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ - ((STATE) == TIM_OCNIdleState_Reset)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Polarity - * @{ - */ - -#define TIM_ICPolarity_Rising ((uint16_t)0x0000) -#define TIM_ICPolarity_Falling ((uint16_t)0x0002) -#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) -#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ - ((POLARITY) == TIM_ICPolarity_Falling)|| \ - ((POLARITY) == TIM_ICPolarity_BothEdge)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Selection - * @{ - */ - -#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC2, IC1, IC4 or IC3, respectively. */ -#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ -#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ - ((SELECTION) == TIM_ICSelection_IndirectTI) || \ - ((SELECTION) == TIM_ICSelection_TRC)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Prescaler - * @{ - */ - -#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ -#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ -#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ -#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ -#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ - ((PRESCALER) == TIM_ICPSC_DIV2) || \ - ((PRESCALER) == TIM_ICPSC_DIV4) || \ - ((PRESCALER) == TIM_ICPSC_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_interrupt_sources - * @{ - */ - -#define TIM_IT_Update ((uint16_t)0x0001) -#define TIM_IT_CC1 ((uint16_t)0x0002) -#define TIM_IT_CC2 ((uint16_t)0x0004) -#define TIM_IT_CC3 ((uint16_t)0x0008) -#define TIM_IT_CC4 ((uint16_t)0x0010) -#define TIM_IT_COM ((uint16_t)0x0020) -#define TIM_IT_Trigger ((uint16_t)0x0040) -#define TIM_IT_Break ((uint16_t)0x0080) -#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) - -#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ - ((IT) == TIM_IT_CC1) || \ - ((IT) == TIM_IT_CC2) || \ - ((IT) == TIM_IT_CC3) || \ - ((IT) == TIM_IT_CC4) || \ - ((IT) == TIM_IT_COM) || \ - ((IT) == TIM_IT_Trigger) || \ - ((IT) == TIM_IT_Break)) -/** - * @} - */ - -/** @defgroup TIM_DMA_Base_address - * @{ - */ - -#define TIM_DMABase_CR1 ((uint16_t)0x0000) -#define TIM_DMABase_CR2 ((uint16_t)0x0001) -#define TIM_DMABase_SMCR ((uint16_t)0x0002) -#define TIM_DMABase_DIER ((uint16_t)0x0003) -#define TIM_DMABase_SR ((uint16_t)0x0004) -#define TIM_DMABase_EGR ((uint16_t)0x0005) -#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) -#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) -#define TIM_DMABase_CCER ((uint16_t)0x0008) -#define TIM_DMABase_CNT ((uint16_t)0x0009) -#define TIM_DMABase_PSC ((uint16_t)0x000A) -#define TIM_DMABase_ARR ((uint16_t)0x000B) -#define TIM_DMABase_RCR ((uint16_t)0x000C) -#define TIM_DMABase_CCR1 ((uint16_t)0x000D) -#define TIM_DMABase_CCR2 ((uint16_t)0x000E) -#define TIM_DMABase_CCR3 ((uint16_t)0x000F) -#define TIM_DMABase_CCR4 ((uint16_t)0x0010) -#define TIM_DMABase_BDTR ((uint16_t)0x0011) -#define TIM_DMABase_DCR ((uint16_t)0x0012) -#define TIM_DMABase_OR ((uint16_t)0x0013) -#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ - ((BASE) == TIM_DMABase_CR2) || \ - ((BASE) == TIM_DMABase_SMCR) || \ - ((BASE) == TIM_DMABase_DIER) || \ - ((BASE) == TIM_DMABase_SR) || \ - ((BASE) == TIM_DMABase_EGR) || \ - ((BASE) == TIM_DMABase_CCMR1) || \ - ((BASE) == TIM_DMABase_CCMR2) || \ - ((BASE) == TIM_DMABase_CCER) || \ - ((BASE) == TIM_DMABase_CNT) || \ - ((BASE) == TIM_DMABase_PSC) || \ - ((BASE) == TIM_DMABase_ARR) || \ - ((BASE) == TIM_DMABase_RCR) || \ - ((BASE) == TIM_DMABase_CCR1) || \ - ((BASE) == TIM_DMABase_CCR2) || \ - ((BASE) == TIM_DMABase_CCR3) || \ - ((BASE) == TIM_DMABase_CCR4) || \ - ((BASE) == TIM_DMABase_BDTR) || \ - ((BASE) == TIM_DMABase_DCR) || \ - ((BASE) == TIM_DMABase_OR)) -/** - * @} - */ - -/** @defgroup TIM_DMA_Burst_Length - * @{ - */ - -#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) -#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) -#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) -#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) -#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) -#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) -#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) -#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) -#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) -#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) -#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) -#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) -#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) -#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) -#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) -#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) -#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) -#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) -#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ - ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_18Transfers)) -/** - * @} - */ - -/** @defgroup TIM_DMA_sources - * @{ - */ - -#define TIM_DMA_Update ((uint16_t)0x0100) -#define TIM_DMA_CC1 ((uint16_t)0x0200) -#define TIM_DMA_CC2 ((uint16_t)0x0400) -#define TIM_DMA_CC3 ((uint16_t)0x0800) -#define TIM_DMA_CC4 ((uint16_t)0x1000) -#define TIM_DMA_COM ((uint16_t)0x2000) -#define TIM_DMA_Trigger ((uint16_t)0x4000) -#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) - -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Prescaler - * @{ - */ - -#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) -#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) -#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) -#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) -#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_Internal_Trigger_Selection - * @{ - */ - -#define TIM_TS_ITR0 ((uint16_t)0x0000) -#define TIM_TS_ITR1 ((uint16_t)0x0010) -#define TIM_TS_ITR2 ((uint16_t)0x0020) -#define TIM_TS_ITR3 ((uint16_t)0x0030) -#define TIM_TS_TI1F_ED ((uint16_t)0x0040) -#define TIM_TS_TI1FP1 ((uint16_t)0x0050) -#define TIM_TS_TI2FP2 ((uint16_t)0x0060) -#define TIM_TS_ETRF ((uint16_t)0x0070) -#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3) || \ - ((SELECTION) == TIM_TS_TI1F_ED) || \ - ((SELECTION) == TIM_TS_TI1FP1) || \ - ((SELECTION) == TIM_TS_TI2FP2) || \ - ((SELECTION) == TIM_TS_ETRF)) -#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3)) -/** - * @} - */ - -/** @defgroup TIM_TIx_External_Clock_Source - * @{ - */ - -#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) -#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) -#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) - -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Polarity - * @{ - */ -#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) -#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) -#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ - ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) -/** - * @} - */ - -/** @defgroup TIM_Prescaler_Reload_Mode - * @{ - */ - -#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) -#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) -#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ - ((RELOAD) == TIM_PSCReloadMode_Immediate)) -/** - * @} - */ - -/** @defgroup TIM_Forced_Action - * @{ - */ - -#define TIM_ForcedAction_Active ((uint16_t)0x0050) -#define TIM_ForcedAction_InActive ((uint16_t)0x0040) -#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ - ((ACTION) == TIM_ForcedAction_InActive)) -/** - * @} - */ - -/** @defgroup TIM_Encoder_Mode - * @{ - */ - -#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) -#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) -#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) -#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ - ((MODE) == TIM_EncoderMode_TI2) || \ - ((MODE) == TIM_EncoderMode_TI12)) -/** - * @} - */ - - -/** @defgroup TIM_Event_Source - * @{ - */ - -#define TIM_EventSource_Update ((uint16_t)0x0001) -#define TIM_EventSource_CC1 ((uint16_t)0x0002) -#define TIM_EventSource_CC2 ((uint16_t)0x0004) -#define TIM_EventSource_CC3 ((uint16_t)0x0008) -#define TIM_EventSource_CC4 ((uint16_t)0x0010) -#define TIM_EventSource_COM ((uint16_t)0x0020) -#define TIM_EventSource_Trigger ((uint16_t)0x0040) -#define TIM_EventSource_Break ((uint16_t)0x0080) -#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) - -/** - * @} - */ - -/** @defgroup TIM_Update_Source - * @{ - */ - -#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow - or the setting of UG bit, or an update generation - through the slave mode controller. */ -#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ -#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ - ((SOURCE) == TIM_UpdateSource_Regular)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Preload_State - * @{ - */ - -#define TIM_OCPreload_Enable ((uint16_t)0x0008) -#define TIM_OCPreload_Disable ((uint16_t)0x0000) -#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ - ((STATE) == TIM_OCPreload_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Fast_State - * @{ - */ - -#define TIM_OCFast_Enable ((uint16_t)0x0004) -#define TIM_OCFast_Disable ((uint16_t)0x0000) -#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ - ((STATE) == TIM_OCFast_Disable)) - -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Clear_State - * @{ - */ - -#define TIM_OCClear_Enable ((uint16_t)0x0080) -#define TIM_OCClear_Disable ((uint16_t)0x0000) -#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ - ((STATE) == TIM_OCClear_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Trigger_Output_Source - * @{ - */ - -#define TIM_TRGOSource_Reset ((uint16_t)0x0000) -#define TIM_TRGOSource_Enable ((uint16_t)0x0010) -#define TIM_TRGOSource_Update ((uint16_t)0x0020) -#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) -#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) -#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) -#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) -#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) -#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ - ((SOURCE) == TIM_TRGOSource_Enable) || \ - ((SOURCE) == TIM_TRGOSource_Update) || \ - ((SOURCE) == TIM_TRGOSource_OC1) || \ - ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC4Ref)) -/** - * @} - */ - -/** @defgroup TIM_Slave_Mode - * @{ - */ - -#define TIM_SlaveMode_Reset ((uint16_t)0x0004) -#define TIM_SlaveMode_Gated ((uint16_t)0x0005) -#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) -#define TIM_SlaveMode_External1 ((uint16_t)0x0007) -#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ - ((MODE) == TIM_SlaveMode_Gated) || \ - ((MODE) == TIM_SlaveMode_Trigger) || \ - ((MODE) == TIM_SlaveMode_External1)) -/** - * @} - */ - -/** @defgroup TIM_Master_Slave_Mode - * @{ - */ - -#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) -#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) -#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ - ((STATE) == TIM_MasterSlaveMode_Disable)) -/** - * @} - */ -/** @defgroup TIM_Remap - * @{ - */ - -#define TIM2_TIM8_TRGO ((uint16_t)0x0000) -#define TIM2_ETH_PTP ((uint16_t)0x0400) -#define TIM2_USBFS_SOF ((uint16_t)0x0800) -#define TIM2_USBHS_SOF ((uint16_t)0x0C00) - -#define TIM5_GPIO ((uint16_t)0x0000) -#define TIM5_LSI ((uint16_t)0x0040) -#define TIM5_LSE ((uint16_t)0x0080) -#define TIM5_RTC ((uint16_t)0x00C0) - -#define TIM11_GPIO ((uint16_t)0x0000) -#define TIM11_HSE ((uint16_t)0x0002) - -#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM2_TIM8_TRGO)||\ - ((TIM_REMAP) == TIM2_ETH_PTP)||\ - ((TIM_REMAP) == TIM2_USBFS_SOF)||\ - ((TIM_REMAP) == TIM2_USBHS_SOF)||\ - ((TIM_REMAP) == TIM5_GPIO)||\ - ((TIM_REMAP) == TIM5_LSI)||\ - ((TIM_REMAP) == TIM5_LSE)||\ - ((TIM_REMAP) == TIM5_RTC)||\ - ((TIM_REMAP) == TIM11_GPIO)||\ - ((TIM_REMAP) == TIM11_HSE)) - -/** - * @} - */ -/** @defgroup TIM_Flags - * @{ - */ - -#define TIM_FLAG_Update ((uint16_t)0x0001) -#define TIM_FLAG_CC1 ((uint16_t)0x0002) -#define TIM_FLAG_CC2 ((uint16_t)0x0004) -#define TIM_FLAG_CC3 ((uint16_t)0x0008) -#define TIM_FLAG_CC4 ((uint16_t)0x0010) -#define TIM_FLAG_COM ((uint16_t)0x0020) -#define TIM_FLAG_Trigger ((uint16_t)0x0040) -#define TIM_FLAG_Break ((uint16_t)0x0080) -#define TIM_FLAG_CC1OF ((uint16_t)0x0200) -#define TIM_FLAG_CC2OF ((uint16_t)0x0400) -#define TIM_FLAG_CC3OF ((uint16_t)0x0800) -#define TIM_FLAG_CC4OF ((uint16_t)0x1000) -#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ - ((FLAG) == TIM_FLAG_CC1) || \ - ((FLAG) == TIM_FLAG_CC2) || \ - ((FLAG) == TIM_FLAG_CC3) || \ - ((FLAG) == TIM_FLAG_CC4) || \ - ((FLAG) == TIM_FLAG_COM) || \ - ((FLAG) == TIM_FLAG_Trigger) || \ - ((FLAG) == TIM_FLAG_Break) || \ - ((FLAG) == TIM_FLAG_CC1OF) || \ - ((FLAG) == TIM_FLAG_CC2OF) || \ - ((FLAG) == TIM_FLAG_CC3OF) || \ - ((FLAG) == TIM_FLAG_CC4OF)) - -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Filer_Value - * @{ - */ - -#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Filter - * @{ - */ - -#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup TIM_Legacy - * @{ - */ - -#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer -#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers -#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers -#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers -#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers -#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers -#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers -#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers -#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers -#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers -#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers -#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers -#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers -#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers -#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers -#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers -#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers -#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* TimeBase management ********************************************************/ -void TIM_DeInit(TIM_TypeDef* TIMx); -void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); -void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); -void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); -void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter); -void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload); -uint32_t TIM_GetCounter(TIM_TypeDef* TIMx); -uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); -void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); -void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); -void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); -void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Output Compare management **************************************************/ -void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); -void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1); -void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2); -void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3); -void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4); -void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); -void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); - -/* Input Capture management ***************************************************/ -void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); -void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); -void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); -uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx); -uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx); -uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx); -uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx); -void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); - -/* Advanced-control timers (TIM1 and TIM8) specific features ******************/ -void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); -void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Interrupts, DMA and flags management ***************************************/ -void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); -void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); -FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); -void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); -ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); -void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); -void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); -void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); -void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Clocks management **********************************************************/ -void TIM_InternalClockConfig(TIM_TypeDef* TIMx); -void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); -void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter); -void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); -void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); - -/* Synchronization management *************************************************/ -void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); -void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); -void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); -void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); -void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); - -/* Specific interface management **********************************************/ -void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); -void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Specific remapping management **********************************************/ -void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_TIM_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm32f4xx_usart.c b/stm/stmperiph/stm32f4xx_usart.c deleted file mode 100644 index f786c942c..000000000 --- a/stm/stmperiph/stm32f4xx_usart.c +++ /dev/null @@ -1,1486 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_usart.c - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief This file provides firmware functions to manage the following - * functionalities of the Universal synchronous asynchronous receiver - * transmitter (USART): - * + Initialization and Configuration - * + Data transfers - * + Multi-Processor Communication - * + LIN mode - * + Half-duplex mode - * + Smartcard mode - * + IrDA mode - * + DMA transfers management - * + Interrupts and flags management - * - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - (#) Enable peripheral clock using the following functions - RCC_APB2PeriphClockCmd(RCC_APB2Periph_USARTx, ENABLE) for USART1 and USART6 - RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE) for USART2, USART3, - UART4 or UART5. - - (#) According to the USART mode, enable the GPIO clocks using - RCC_AHB1PeriphClockCmd() function. (The I/O can be TX, RX, CTS, - or/and SCLK). - - (#) Peripheral's alternate function: - (++) Connect the pin to the desired peripherals' Alternate - Function (AF) using GPIO_PinAFConfig() function - (++) Configure the desired pin in alternate function by: - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - (++) Select the type, pull-up/pull-down and output speed via - GPIO_PuPd, GPIO_OType and GPIO_Speed members - (++) Call GPIO_Init() function - - (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware - flow control and Mode(Receiver/Transmitter) using the USART_Init() - function. - - (#) For synchronous mode, enable the clock and program the polarity, - phase and last bit using the USART_ClockInit() function. - - (#) Enable the NVIC and the corresponding interrupt using the function - USART_ITConfig() if you need to use interrupt mode. - - (#) When using the DMA mode - (++) Configure the DMA using DMA_Init() function - (++) Active the needed channel Request using USART_DMACmd() function - - (#) Enable the USART using the USART_Cmd() function. - - (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode. - - -@- Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections - for more details - - [..] - In order to reach higher communication baudrates, it is possible to - enable the oversampling by 8 mode using the function USART_OverSampling8Cmd(). - This function should be called after enabling the USART clock (RCC_APBxPeriphClockCmd()) - and before calling the function USART_Init(). - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_usart.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup USART - * @brief USART driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/*!< USART CR1 register clear Mask ((~(uint16_t)0xE9F3)) */ -#define CR1_CLEAR_MASK ((uint16_t)(USART_CR1_M | USART_CR1_PCE | \ - USART_CR1_PS | USART_CR1_TE | \ - USART_CR1_RE)) - -/*!< USART CR2 register clock bits clear Mask ((~(uint16_t)0xF0FF)) */ -#define CR2_CLOCK_CLEAR_MASK ((uint16_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \ - USART_CR2_CPHA | USART_CR2_LBCL)) - -/*!< USART CR3 register clear Mask ((~(uint16_t)0xFCFF)) */ -#define CR3_CLEAR_MASK ((uint16_t)(USART_CR3_RTSE | USART_CR3_CTSE)) - -/*!< USART Interrupts mask */ -#define IT_MASK ((uint16_t)0x001F) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup USART_Private_Functions - * @{ - */ - -/** @defgroup USART_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the USART - in asynchronous and in synchronous modes. - (+) For the asynchronous mode only these parameters can be configured: - (++) Baud Rate - (++) Word Length - (++) Stop Bit - (++) Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - Depending on the frame length defined by the M bit (8-bits or 9-bits), - the possible USART frame formats are as listed in the following table: - +-------------------------------------------------------------+ - | M bit | PCE bit | USART frame | - |---------------------|---------------------------------------| - | 0 | 0 | | SB | 8 bit data | STB | | - |---------|-----------|---------------------------------------| - | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|-----------|---------------------------------------| - | 1 | 0 | | SB | 9 bit data | STB | | - |---------|-----------|---------------------------------------| - | 1 | 1 | | SB | 8 bit data | PB | STB | | - +-------------------------------------------------------------+ - (++) Hardware flow control - (++) Receiver/transmitter modes - - [..] - The USART_Init() function follows the USART asynchronous configuration - procedure (details for the procedure are available in reference manual (RM0090)). - - (+) For the synchronous mode in addition to the asynchronous mode parameters these - parameters should be also configured: - (++) USART Clock Enabled - (++) USART polarity - (++) USART phase - (++) USART LastBit - - [..] - These parameters can be configured using the USART_ClockInit() function. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the USARTx peripheral registers to their default reset values. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @retval None - */ -void USART_DeInit(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - if (USARTx == USART1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); - } - else if (USARTx == USART2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); - } - else if (USARTx == USART3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); - } - else if (USARTx == UART4) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); - } - else if (USARTx == UART5) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); - } - else if (USARTx == USART6) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, DISABLE); - } - else if (USARTx == UART7) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, DISABLE); - } - else - { - if (USARTx == UART8) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, DISABLE); - } - } -} - -/** - * @brief Initializes the USARTx peripheral according to the specified - * parameters in the USART_InitStruct . - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that contains - * the configuration information for the specified USART peripheral. - * @retval None - */ -void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) -{ - uint32_t tmpreg = 0x00, apbclock = 0x00; - uint32_t integerdivider = 0x00; - uint32_t fractionaldivider = 0x00; - RCC_ClocksTypeDef RCC_ClocksStatus; - - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); - assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); - assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); - assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); - assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode)); - assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); - - /* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */ - if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) - { - assert_param(IS_USART_1236_PERIPH(USARTx)); - } - -/*---------------------------- USART CR2 Configuration -----------------------*/ - tmpreg = USARTx->CR2; - - /* Clear STOP[13:12] bits */ - tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP); - - /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit : - Set STOP[13:12] bits according to USART_StopBits value */ - tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; - - /* Write to USART CR2 */ - USARTx->CR2 = (uint16_t)tmpreg; - -/*---------------------------- USART CR1 Configuration -----------------------*/ - tmpreg = USARTx->CR1; - - /* Clear M, PCE, PS, TE and RE bits */ - tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK); - - /* Configure the USART Word Length, Parity and mode: - Set the M bits according to USART_WordLength value - Set PCE and PS bits according to USART_Parity value - Set TE and RE bits according to USART_Mode value */ - tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | - USART_InitStruct->USART_Mode; - - /* Write to USART CR1 */ - USARTx->CR1 = (uint16_t)tmpreg; - -/*---------------------------- USART CR3 Configuration -----------------------*/ - tmpreg = USARTx->CR3; - - /* Clear CTSE and RTSE bits */ - tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK); - - /* Configure the USART HFC : - Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ - tmpreg |= USART_InitStruct->USART_HardwareFlowControl; - - /* Write to USART CR3 */ - USARTx->CR3 = (uint16_t)tmpreg; - -/*---------------------------- USART BRR Configuration -----------------------*/ - /* Configure the USART Baud Rate */ - RCC_GetClocksFreq(&RCC_ClocksStatus); - - if ((USARTx == USART1) || (USARTx == USART6)) - { - apbclock = RCC_ClocksStatus.PCLK2_Frequency; - } - else - { - apbclock = RCC_ClocksStatus.PCLK1_Frequency; - } - - /* Determine the integer part */ - if ((USARTx->CR1 & USART_CR1_OVER8) != 0) - { - /* Integer part computing in case Oversampling mode is 8 Samples */ - integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); - } - else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */ - { - /* Integer part computing in case Oversampling mode is 16 Samples */ - integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); - } - tmpreg = (integerdivider / 100) << 4; - - /* Determine the fractional part */ - fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); - - /* Implement the fractional part in the register */ - if ((USARTx->CR1 & USART_CR1_OVER8) != 0) - { - tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); - } - else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */ - { - tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); - } - - /* Write to USART BRR register */ - USARTx->BRR = (uint16_t)tmpreg; -} - -/** - * @brief Fills each USART_InitStruct member with its default value. - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void USART_StructInit(USART_InitTypeDef* USART_InitStruct) -{ - /* USART_InitStruct members default value */ - USART_InitStruct->USART_BaudRate = 9600; - USART_InitStruct->USART_WordLength = USART_WordLength_8b; - USART_InitStruct->USART_StopBits = USART_StopBits_1; - USART_InitStruct->USART_Parity = USART_Parity_No ; - USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; -} - -/** - * @brief Initializes the USARTx peripheral Clock according to the - * specified parameters in the USART_ClockInitStruct . - * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART peripheral. - * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure that - * contains the configuration information for the specified USART peripheral. - * @note The Smart Card and Synchronous modes are not available for UART4 and UART5. - * @retval None - */ -void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct) -{ - uint32_t tmpreg = 0x00; - /* Check the parameters */ - assert_param(IS_USART_1236_PERIPH(USARTx)); - assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock)); - assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL)); - assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA)); - assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit)); - -/*---------------------------- USART CR2 Configuration -----------------------*/ - tmpreg = USARTx->CR2; - /* Clear CLKEN, CPOL, CPHA and LBCL bits */ - tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK); - /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/ - /* Set CLKEN bit according to USART_Clock value */ - /* Set CPOL bit according to USART_CPOL value */ - /* Set CPHA bit according to USART_CPHA value */ - /* Set LBCL bit according to USART_LastBit value */ - tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | - USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; - /* Write to USART CR2 */ - USARTx->CR2 = (uint16_t)tmpreg; -} - -/** - * @brief Fills each USART_ClockInitStruct member with its default value. - * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure - * which will be initialized. - * @retval None - */ -void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) -{ - /* USART_ClockInitStruct members default value */ - USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; - USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; - USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; - USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; -} - -/** - * @brief Enables or disables the specified USART peripheral. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param NewState: new state of the USARTx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected USART by setting the UE bit in the CR1 register */ - USARTx->CR1 |= USART_CR1_UE; - } - else - { - /* Disable the selected USART by clearing the UE bit in the CR1 register */ - USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_UE); - } -} - -/** - * @brief Sets the system clock prescaler. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param USART_Prescaler: specifies the prescaler clock. - * @note The function is used for IrDA mode with UART4 and UART5. - * @retval None - */ -void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Clear the USART prescaler */ - USARTx->GTPR &= USART_GTPR_GT; - /* Set the USART prescaler */ - USARTx->GTPR |= USART_Prescaler; -} - -/** - * @brief Enables or disables the USART's 8x oversampling mode. - * @note This function has to be called before calling USART_Init() function - * in order to have correct baudrate Divider value. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param NewState: new state of the USART 8x oversampling mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */ - USARTx->CR1 |= USART_CR1_OVER8; - } - else - { - /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */ - USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_OVER8); - } -} - -/** - * @brief Enables or disables the USART's one bit sampling method. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param NewState: new state of the USART one bit sampling method. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_ONEBIT; - } - else - { - /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */ - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT); - } -} - -/** - * @} - */ - -/** @defgroup USART_Group2 Data transfers functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### Data transfers functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the USART data - transfers. - [..] - During an USART reception, data shifts in least significant bit first through - the RX pin. In this mode, the USART_DR register consists of a buffer (RDR) - between the internal bus and the received shift register. - [..] - When a transmission is taking place, a write instruction to the USART_DR register - stores the data in the TDR register and which is copied in the shift register - at the end of the current transmission. - [..] - The read access of the USART_DR register can be done using the USART_ReceiveData() - function and returns the RDR buffered value. Whereas a write access to the USART_DR - can be done using USART_SendData() function and stores the written data into - TDR buffer. - -@endverbatim - * @{ - */ - -/** - * @brief Transmits single data through the USARTx peripheral. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param Data: the data to transmit. - * @retval None - */ -void USART_SendData(USART_TypeDef* USARTx, uint16_t Data) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DATA(Data)); - - /* Transmit Data */ - USARTx->DR = (Data & (uint16_t)0x01FF); -} - -/** - * @brief Returns the most recent received data by the USARTx peripheral. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @retval The received data. - */ -uint16_t USART_ReceiveData(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Receive Data */ - return (uint16_t)(USARTx->DR & (uint16_t)0x01FF); -} - -/** - * @} - */ - -/** @defgroup USART_Group3 MultiProcessor Communication functions - * @brief Multi-Processor Communication functions - * -@verbatim - =============================================================================== - ##### Multi-Processor Communication functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the USART - multiprocessor communication. - [..] - For instance one of the USARTs can be the master, its TX output is connected - to the RX input of the other USART. The others are slaves, their respective - TX outputs are logically ANDed together and connected to the RX input of the - master. - [..] - USART multiprocessor communication is possible through the following procedure: - (#) Program the Baud rate, Word length = 9 bits, Stop bits, Parity, Mode - transmitter or Mode receiver and hardware flow control values using - the USART_Init() function. - (#) Configures the USART address using the USART_SetAddress() function. - (#) Configures the wake up method (USART_WakeUp_IdleLine or USART_WakeUp_AddressMark) - using USART_WakeUpConfig() function only for the slaves. - (#) Enable the USART using the USART_Cmd() function. - (#) Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() function. - [..] - The USART Slave exit from mute mode when receive the wake up condition. - -@endverbatim - * @{ - */ - -/** - * @brief Sets the address of the USART node. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param USART_Address: Indicates the address of the USART node. - * @retval None - */ -void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_ADDRESS(USART_Address)); - - /* Clear the USART address */ - USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_ADD); - /* Set the USART address node */ - USARTx->CR2 |= USART_Address; -} - -/** - * @brief Determines if the USART is in mute mode or not. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param NewState: new state of the USART mute mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ - USARTx->CR1 |= USART_CR1_RWU; - } - else - { - /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ - USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_RWU); - } -} -/** - * @brief Selects the USART WakeUp method. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param USART_WakeUp: specifies the USART wakeup method. - * This parameter can be one of the following values: - * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection - * @arg USART_WakeUp_AddressMark: WakeUp by an address mark - * @retval None - */ -void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_WAKEUP(USART_WakeUp)); - - USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_WAKE); - USARTx->CR1 |= USART_WakeUp; -} - -/** - * @} - */ - -/** @defgroup USART_Group4 LIN mode functions - * @brief LIN mode functions - * -@verbatim - =============================================================================== - ##### LIN mode functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the USART LIN - Mode communication. - [..] - In LIN mode, 8-bit data format with 1 stop bit is required in accordance with - the LIN standard. - [..] - Only this LIN Feature is supported by the USART IP: - (+) LIN Master Synchronous Break send capability and LIN slave break detection - capability : 13-bit break generation and 10/11 bit break detection - - [..] - USART LIN Master transmitter communication is possible through the following - procedure: - (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, - Mode transmitter or Mode receiver and hardware flow control values using - the USART_Init() function. - (#) Enable the USART using the USART_Cmd() function. - (#) Enable the LIN mode using the USART_LINCmd() function. - (#) Send the break character using USART_SendBreak() function. - [..] - USART LIN Master receiver communication is possible through the following procedure: - (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, - Mode transmitter or Mode receiver and hardware flow control values using - the USART_Init() function. - (#) Enable the USART using the USART_Cmd() function. - (#) Configures the break detection length using the USART_LINBreakDetectLengthConfig() - function. - (#) Enable the LIN mode using the USART_LINCmd() function. - - -@- In LIN mode, the following bits must be kept cleared: - (+@) CLKEN in the USART_CR2 register, - (+@) STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register. - -@endverbatim - * @{ - */ - -/** - * @brief Sets the USART LIN Break detection length. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param USART_LINBreakDetectLength: specifies the LIN break detection length. - * This parameter can be one of the following values: - * @arg USART_LINBreakDetectLength_10b: 10-bit break detection - * @arg USART_LINBreakDetectLength_11b: 11-bit break detection - * @retval None - */ -void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); - - USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LBDL); - USARTx->CR2 |= USART_LINBreakDetectLength; -} - -/** - * @brief Enables or disables the USART's LIN mode. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param NewState: new state of the USART LIN mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ - USARTx->CR2 |= USART_CR2_LINEN; - } - else - { - /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */ - USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LINEN); - } -} - -/** - * @brief Transmits break characters. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @retval None - */ -void USART_SendBreak(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Send break characters */ - USARTx->CR1 |= USART_CR1_SBK; -} - -/** - * @} - */ - -/** @defgroup USART_Group5 Halfduplex mode function - * @brief Half-duplex mode function - * -@verbatim - =============================================================================== - ##### Half-duplex mode function ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the USART - Half-duplex communication. - [..] - The USART can be configured to follow a single-wire half-duplex protocol where - the TX and RX lines are internally connected. - [..] - USART Half duplex communication is possible through the following procedure: - (#) Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter - or Mode receiver and hardware flow control values using the USART_Init() - function. - (#) Configures the USART address using the USART_SetAddress() function. - (#) Enable the USART using the USART_Cmd() function. - (#) Enable the half duplex mode using USART_HalfDuplexCmd() function. - - - -@- The RX pin is no longer used - -@- In Half-duplex mode the following bits must be kept cleared: - (+@) LINEN and CLKEN bits in the USART_CR2 register. - (+@) SCEN and IREN bits in the USART_CR3 register. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the USART's Half Duplex communication. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param NewState: new state of the USART Communication. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_HDSEL; - } - else - { - /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */ - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_HDSEL); - } -} - -/** - * @} - */ - - -/** @defgroup USART_Group6 Smartcard mode functions - * @brief Smartcard mode functions - * -@verbatim - =============================================================================== - ##### Smartcard mode functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the USART - Smartcard communication. - [..] - The Smartcard interface is designed to support asynchronous protocol Smartcards as - defined in the ISO 7816-3 standard. - [..] - The USART can provide a clock to the smartcard through the SCLK output. - In smartcard mode, SCLK is not associated to the communication but is simply derived - from the internal peripheral input clock through a 5-bit prescaler. - [..] - Smartcard communication is possible through the following procedure: - (#) Configures the Smartcard Prescaler using the USART_SetPrescaler() function. - (#) Configures the Smartcard Guard Time using the USART_SetGuardTime() function. - (#) Program the USART clock using the USART_ClockInit() function as following: - (++) USART Clock enabled - (++) USART CPOL Low - (++) USART CPHA on first edge - (++) USART Last Bit Clock Enabled - (#) Program the Smartcard interface using the USART_Init() function as following: - (++) Word Length = 9 Bits - (++) 1.5 Stop Bit - (++) Even parity - (++) BaudRate = 12096 baud - (++) Hardware flow control disabled (RTS and CTS signals) - (++) Tx and Rx enabled - (#) POptionally you can enable the parity error interrupt using the USART_ITConfig() - function - (#) PEnable the USART using the USART_Cmd() function. - (#) PEnable the Smartcard NACK using the USART_SmartCardNACKCmd() function. - (#) PEnable the Smartcard interface using the USART_SmartCardCmd() function. - - Please refer to the ISO 7816-3 specification for more details. - - -@- It is also possible to choose 0.5 stop bit for receiving but it is recommended - to use 1.5 stop bits for both transmitting and receiving to avoid switching - between the two configurations. - -@- In smartcard mode, the following bits must be kept cleared: - (+@) LINEN bit in the USART_CR2 register. - (+@) HDSEL and IREN bits in the USART_CR3 register. - -@- Smartcard mode is available on USART peripherals only (not available on UART4 - and UART5 peripherals). - -@endverbatim - * @{ - */ - -/** - * @brief Sets the specified USART guard time. - * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or - * UART peripheral. - * @param USART_GuardTime: specifies the guard time. - * @retval None - */ -void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime) -{ - /* Check the parameters */ - assert_param(IS_USART_1236_PERIPH(USARTx)); - - /* Clear the USART Guard time */ - USARTx->GTPR &= USART_GTPR_PSC; - /* Set the USART guard time */ - USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); -} - -/** - * @brief Enables or disables the USART's Smart Card mode. - * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or - * UART peripheral. - * @param NewState: new state of the Smart Card mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_1236_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the SC mode by setting the SCEN bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_SCEN; - } - else - { - /* Disable the SC mode by clearing the SCEN bit in the CR3 register */ - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_SCEN); - } -} - -/** - * @brief Enables or disables NACK transmission. - * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or - * UART peripheral. - * @param NewState: new state of the NACK transmission. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_1236_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the NACK transmission by setting the NACK bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_NACK; - } - else - { - /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */ - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_NACK); - } -} - -/** - * @} - */ - -/** @defgroup USART_Group7 IrDA mode functions - * @brief IrDA mode functions - * -@verbatim - =============================================================================== - ##### IrDA mode functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the USART - IrDA communication. - [..] - IrDA is a half duplex communication protocol. If the Transmitter is busy, any data - on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver - is busy, data on the TX from the USART to IrDA will not be encoded by IrDA. - While receiving data, transmission should be avoided as the data to be transmitted - could be corrupted. - [..] - IrDA communication is possible through the following procedure: - (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity, Transmitter/Receiver - modes and hardware flow control values using the USART_Init() function. - (#) Enable the USART using the USART_Cmd() function. - (#) Configures the IrDA pulse width by configuring the prescaler using - the USART_SetPrescaler() function. - (#) Configures the IrDA USART_IrDAMode_LowPower or USART_IrDAMode_Normal mode - using the USART_IrDAConfig() function. - (#) Enable the IrDA using the USART_IrDACmd() function. - - -@- A pulse of width less than two and greater than one PSC period(s) may or may - not be rejected. - -@- The receiver set up time should be managed by software. The IrDA physical layer - specification specifies a minimum of 10 ms delay between transmission and - reception (IrDA is a half duplex protocol). - -@- In IrDA mode, the following bits must be kept cleared: - (+@) LINEN, STOP and CLKEN bits in the USART_CR2 register. - (+@) SCEN and HDSEL bits in the USART_CR3 register. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the USART's IrDA interface. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param USART_IrDAMode: specifies the IrDA mode. - * This parameter can be one of the following values: - * @arg USART_IrDAMode_LowPower - * @arg USART_IrDAMode_Normal - * @retval None - */ -void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_IRDA_MODE(USART_IrDAMode)); - - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IRLP); - USARTx->CR3 |= USART_IrDAMode; -} - -/** - * @brief Enables or disables the USART's IrDA interface. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param NewState: new state of the IrDA mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the IrDA mode by setting the IREN bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_IREN; - } - else - { - /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */ - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IREN); - } -} - -/** - * @} - */ - -/** @defgroup USART_Group8 DMA transfers management functions - * @brief DMA transfers management functions - * -@verbatim - =============================================================================== - ##### DMA transfers management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the USART's DMA interface. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param USART_DMAReq: specifies the DMA request. - * This parameter can be any combination of the following values: - * @arg USART_DMAReq_Tx: USART DMA transmit request - * @arg USART_DMAReq_Rx: USART DMA receive request - * @param NewState: new state of the DMA Request sources. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DMAREQ(USART_DMAReq)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DMA transfer for selected requests by setting the DMAT and/or - DMAR bits in the USART CR3 register */ - USARTx->CR3 |= USART_DMAReq; - } - else - { - /* Disable the DMA transfer for selected requests by clearing the DMAT and/or - DMAR bits in the USART CR3 register */ - USARTx->CR3 &= (uint16_t)~USART_DMAReq; - } -} - -/** - * @} - */ - -/** @defgroup USART_Group9 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to configure the USART - Interrupts sources, DMA channels requests and check or clear the flags or - pending bits status. - The user should identify which mode will be used in his application to manage - the communication: Polling mode, Interrupt mode or DMA mode. - - *** Polling Mode *** - ==================== - [..] - In Polling Mode, the SPI communication can be managed by 10 flags: - (#) USART_FLAG_TXE : to indicate the status of the transmit buffer register - (#) USART_FLAG_RXNE : to indicate the status of the receive buffer register - (#) USART_FLAG_TC : to indicate the status of the transmit operation - (#) USART_FLAG_IDLE : to indicate the status of the Idle Line - (#) USART_FLAG_CTS : to indicate the status of the nCTS input - (#) USART_FLAG_LBD : to indicate the status of the LIN break detection - (#) USART_FLAG_NE : to indicate if a noise error occur - (#) USART_FLAG_FE : to indicate if a frame error occur - (#) USART_FLAG_PE : to indicate if a parity error occur - (#) USART_FLAG_ORE : to indicate if an Overrun error occur - [..] - In this Mode it is advised to use the following functions: - (+) FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); - (+) void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); - - *** Interrupt Mode *** - ====================== - [..] - In Interrupt Mode, the USART communication can be managed by 8 interrupt sources - and 10 pending bits: - - (#) Pending Bits: - - (##) USART_IT_TXE : to indicate the status of the transmit buffer register - (##) USART_IT_RXNE : to indicate the status of the receive buffer register - (##) USART_IT_TC : to indicate the status of the transmit operation - (##) USART_IT_IDLE : to indicate the status of the Idle Line - (##) USART_IT_CTS : to indicate the status of the nCTS input - (##) USART_IT_LBD : to indicate the status of the LIN break detection - (##) USART_IT_NE : to indicate if a noise error occur - (##) USART_IT_FE : to indicate if a frame error occur - (##) USART_IT_PE : to indicate if a parity error occur - (##) USART_IT_ORE : to indicate if an Overrun error occur - - (#) Interrupt Source: - - (##) USART_IT_TXE : specifies the interrupt source for the Tx buffer empty - interrupt. - (##) USART_IT_RXNE : specifies the interrupt source for the Rx buffer not - empty interrupt. - (##) USART_IT_TC : specifies the interrupt source for the Transmit complete - interrupt. - (##) USART_IT_IDLE : specifies the interrupt source for the Idle Line interrupt. - (##) USART_IT_CTS : specifies the interrupt source for the CTS interrupt. - (##) USART_IT_LBD : specifies the interrupt source for the LIN break detection - interrupt. - (##) USART_IT_PE : specifies the interrupt source for the parity error interrupt. - (##) USART_IT_ERR : specifies the interrupt source for the errors interrupt. - - -@@- Some parameters are coded in order to use them as interrupt source - or as pending bits. - [..] - In this Mode it is advised to use the following functions: - (+) void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); - (+) ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); - (+) void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); - - *** DMA Mode *** - ================ - [..] - In DMA Mode, the USART communication can be managed by 2 DMA Channel requests: - (#) USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request - (#) USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request - [..] - In this Mode it is advised to use the following function: - (+) void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified USART interrupts. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TXE: Transmit Data Register empty interrupt - * @arg USART_IT_TC: Transmission complete interrupt - * @arg USART_IT_RXNE: Receive Data register not empty interrupt - * @arg USART_IT_IDLE: Idle line detection interrupt - * @arg USART_IT_PE: Parity Error interrupt - * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) - * @param NewState: new state of the specified USARTx interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState) -{ - uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; - uint32_t usartxbase = 0x00; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CONFIG_IT(USART_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* The CTS interrupt is not available for UART4 and UART5 */ - if (USART_IT == USART_IT_CTS) - { - assert_param(IS_USART_1236_PERIPH(USARTx)); - } - - usartxbase = (uint32_t)USARTx; - - /* Get the USART register index */ - usartreg = (((uint8_t)USART_IT) >> 0x05); - - /* Get the interrupt position */ - itpos = USART_IT & IT_MASK; - itmask = (((uint32_t)0x01) << itpos); - - if (usartreg == 0x01) /* The IT is in CR1 register */ - { - usartxbase += 0x0C; - } - else if (usartreg == 0x02) /* The IT is in CR2 register */ - { - usartxbase += 0x10; - } - else /* The IT is in CR3 register */ - { - usartxbase += 0x14; - } - if (NewState != DISABLE) - { - *(__IO uint32_t*)usartxbase |= itmask; - } - else - { - *(__IO uint32_t*)usartxbase &= ~itmask; - } -} - -/** - * @brief Checks whether the specified USART flag is set or not. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param USART_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) - * @arg USART_FLAG_LBD: LIN Break detection flag - * @arg USART_FLAG_TXE: Transmit data register empty flag - * @arg USART_FLAG_TC: Transmission Complete flag - * @arg USART_FLAG_RXNE: Receive data register not empty flag - * @arg USART_FLAG_IDLE: Idle Line detection flag - * @arg USART_FLAG_ORE: OverRun Error flag - * @arg USART_FLAG_NE: Noise Error flag - * @arg USART_FLAG_FE: Framing Error flag - * @arg USART_FLAG_PE: Parity Error flag - * @retval The new state of USART_FLAG (SET or RESET). - */ -FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_FLAG(USART_FLAG)); - - /* The CTS flag is not available for UART4 and UART5 */ - if (USART_FLAG == USART_FLAG_CTS) - { - assert_param(IS_USART_1236_PERIPH(USARTx)); - } - - if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the USARTx's pending flags. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param USART_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). - * @arg USART_FLAG_LBD: LIN Break detection flag. - * @arg USART_FLAG_TC: Transmission Complete flag. - * @arg USART_FLAG_RXNE: Receive data register not empty flag. - * - * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) flags are cleared by software - * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) - * followed by a read operation to USART_DR register (USART_ReceiveData()). - * @note RXNE flag can be also cleared by a read to the USART_DR register - * (USART_ReceiveData()). - * @note TC flag can be also cleared by software sequence: a read operation to - * USART_SR register (USART_GetFlagStatus()) followed by a write operation - * to USART_DR register (USART_SendData()). - * @note TXE flag is cleared only by a write to the USART_DR register - * (USART_SendData()). - * - * @retval None - */ -void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); - - /* The CTS flag is not available for UART4 and UART5 */ - if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS) - { - assert_param(IS_USART_1236_PERIPH(USARTx)); - } - - USARTx->SR = (uint16_t)~USART_FLAG; -} - -/** - * @brief Checks whether the specified USART interrupt has occurred or not. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param USART_IT: specifies the USART interrupt source to check. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TXE: Transmit Data Register empty interrupt - * @arg USART_IT_TC: Transmission complete interrupt - * @arg USART_IT_RXNE: Receive Data register not empty interrupt - * @arg USART_IT_IDLE: Idle line detection interrupt - * @arg USART_IT_ORE_RX : OverRun Error interrupt if the RXNEIE bit is set - * @arg USART_IT_ORE_ER : OverRun Error interrupt if the EIE bit is set - * @arg USART_IT_NE: Noise Error interrupt - * @arg USART_IT_FE: Framing Error interrupt - * @arg USART_IT_PE: Parity Error interrupt - * @retval The new state of USART_IT (SET or RESET). - */ -ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT) -{ - uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_GET_IT(USART_IT)); - - /* The CTS interrupt is not available for UART4 and UART5 */ - if (USART_IT == USART_IT_CTS) - { - assert_param(IS_USART_1236_PERIPH(USARTx)); - } - - /* Get the USART register index */ - usartreg = (((uint8_t)USART_IT) >> 0x05); - /* Get the interrupt position */ - itmask = USART_IT & IT_MASK; - itmask = (uint32_t)0x01 << itmask; - - if (usartreg == 0x01) /* The IT is in CR1 register */ - { - itmask &= USARTx->CR1; - } - else if (usartreg == 0x02) /* The IT is in CR2 register */ - { - itmask &= USARTx->CR2; - } - else /* The IT is in CR3 register */ - { - itmask &= USARTx->CR3; - } - - bitpos = USART_IT >> 0x08; - bitpos = (uint32_t)0x01 << bitpos; - bitpos &= USARTx->SR; - if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/** - * @brief Clears the USARTx's interrupt pending bits. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param USART_IT: specifies the interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TC: Transmission complete interrupt. - * @arg USART_IT_RXNE: Receive Data register not empty interrupt. - * - * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) pending bits are cleared by - * software sequence: a read operation to USART_SR register - * (USART_GetITStatus()) followed by a read operation to USART_DR register - * (USART_ReceiveData()). - * @note RXNE pending bit can be also cleared by a read to the USART_DR register - * (USART_ReceiveData()). - * @note TC pending bit can be also cleared by software sequence: a read - * operation to USART_SR register (USART_GetITStatus()) followed by a write - * operation to USART_DR register (USART_SendData()). - * @note TXE pending bit is cleared only by a write to the USART_DR register - * (USART_SendData()). - * - * @retval None - */ -void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT) -{ - uint16_t bitpos = 0x00, itmask = 0x00; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CLEAR_IT(USART_IT)); - - /* The CTS interrupt is not available for UART4 and UART5 */ - if (USART_IT == USART_IT_CTS) - { - assert_param(IS_USART_1236_PERIPH(USARTx)); - } - - bitpos = USART_IT >> 0x08; - itmask = ((uint16_t)0x01 << (uint16_t)bitpos); - USARTx->SR = (uint16_t)~itmask; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm32f4xx_usart.h b/stm/stmperiph/stm32f4xx_usart.h deleted file mode 100644 index dc011da7b..000000000 --- a/stm/stmperiph/stm32f4xx_usart.h +++ /dev/null @@ -1,431 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_usart.h - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief This file contains all the functions prototypes for the USART - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_USART_H -#define __STM32F4xx_USART_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup USART - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief USART Init Structure definition - */ - -typedef struct -{ - uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. - The baud rate is computed using the following formula: - - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (USART_InitStruct->USART_BaudRate))) - - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 - Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */ - - uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref USART_Word_Length */ - - uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref USART_Stop_Bits */ - - uint16_t USART_Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref USART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref USART_Mode */ - - uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled - or disabled. - This parameter can be a value of @ref USART_Hardware_Flow_Control */ -} USART_InitTypeDef; - -/** - * @brief USART Clock Init Structure definition - */ - -typedef struct -{ - - uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled. - This parameter can be a value of @ref USART_Clock */ - - uint16_t USART_CPOL; /*!< Specifies the steady state of the serial clock. - This parameter can be a value of @ref USART_Clock_Polarity */ - - uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref USART_Clock_Phase */ - - uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted - data bit (MSB) has to be output on the SCLK pin in synchronous mode. - This parameter can be a value of @ref USART_Last_Bit */ -} USART_ClockInitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup USART_Exported_Constants - * @{ - */ - -#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2) || \ - ((PERIPH) == USART3) || \ - ((PERIPH) == UART4) || \ - ((PERIPH) == UART5) || \ - ((PERIPH) == USART6) || \ - ((PERIPH) == UART7) || \ - ((PERIPH) == UART8)) - -#define IS_USART_1236_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2) || \ - ((PERIPH) == USART3) || \ - ((PERIPH) == USART6)) - -/** @defgroup USART_Word_Length - * @{ - */ - -#define USART_WordLength_8b ((uint16_t)0x0000) -#define USART_WordLength_9b ((uint16_t)0x1000) - -#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ - ((LENGTH) == USART_WordLength_9b)) -/** - * @} - */ - -/** @defgroup USART_Stop_Bits - * @{ - */ - -#define USART_StopBits_1 ((uint16_t)0x0000) -#define USART_StopBits_0_5 ((uint16_t)0x1000) -#define USART_StopBits_2 ((uint16_t)0x2000) -#define USART_StopBits_1_5 ((uint16_t)0x3000) -#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ - ((STOPBITS) == USART_StopBits_0_5) || \ - ((STOPBITS) == USART_StopBits_2) || \ - ((STOPBITS) == USART_StopBits_1_5)) -/** - * @} - */ - -/** @defgroup USART_Parity - * @{ - */ - -#define USART_Parity_No ((uint16_t)0x0000) -#define USART_Parity_Even ((uint16_t)0x0400) -#define USART_Parity_Odd ((uint16_t)0x0600) -#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ - ((PARITY) == USART_Parity_Even) || \ - ((PARITY) == USART_Parity_Odd)) -/** - * @} - */ - -/** @defgroup USART_Mode - * @{ - */ - -#define USART_Mode_Rx ((uint16_t)0x0004) -#define USART_Mode_Tx ((uint16_t)0x0008) -#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) -/** - * @} - */ - -/** @defgroup USART_Hardware_Flow_Control - * @{ - */ -#define USART_HardwareFlowControl_None ((uint16_t)0x0000) -#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) -#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) -#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) -#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ - (((CONTROL) == USART_HardwareFlowControl_None) || \ - ((CONTROL) == USART_HardwareFlowControl_RTS) || \ - ((CONTROL) == USART_HardwareFlowControl_CTS) || \ - ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) -/** - * @} - */ - -/** @defgroup USART_Clock - * @{ - */ -#define USART_Clock_Disable ((uint16_t)0x0000) -#define USART_Clock_Enable ((uint16_t)0x0800) -#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ - ((CLOCK) == USART_Clock_Enable)) -/** - * @} - */ - -/** @defgroup USART_Clock_Polarity - * @{ - */ - -#define USART_CPOL_Low ((uint16_t)0x0000) -#define USART_CPOL_High ((uint16_t)0x0400) -#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) - -/** - * @} - */ - -/** @defgroup USART_Clock_Phase - * @{ - */ - -#define USART_CPHA_1Edge ((uint16_t)0x0000) -#define USART_CPHA_2Edge ((uint16_t)0x0200) -#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) - -/** - * @} - */ - -/** @defgroup USART_Last_Bit - * @{ - */ - -#define USART_LastBit_Disable ((uint16_t)0x0000) -#define USART_LastBit_Enable ((uint16_t)0x0100) -#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ - ((LASTBIT) == USART_LastBit_Enable)) -/** - * @} - */ - -/** @defgroup USART_Interrupt_definition - * @{ - */ - -#define USART_IT_PE ((uint16_t)0x0028) -#define USART_IT_TXE ((uint16_t)0x0727) -#define USART_IT_TC ((uint16_t)0x0626) -#define USART_IT_RXNE ((uint16_t)0x0525) -#define USART_IT_ORE_RX ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */ -#define USART_IT_IDLE ((uint16_t)0x0424) -#define USART_IT_LBD ((uint16_t)0x0846) -#define USART_IT_CTS ((uint16_t)0x096A) -#define USART_IT_ERR ((uint16_t)0x0060) -#define USART_IT_ORE_ER ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */ -#define USART_IT_NE ((uint16_t)0x0260) -#define USART_IT_FE ((uint16_t)0x0160) - -/** @defgroup USART_Legacy - * @{ - */ -#define USART_IT_ORE USART_IT_ORE_ER -/** - * @} - */ - -#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ - ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ - ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR)) -#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ - ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ - ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ - ((IT) == USART_IT_ORE_RX) || ((IT) == USART_IT_ORE_ER) || \ - ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE)) -#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS)) -/** - * @} - */ - -/** @defgroup USART_DMA_Requests - * @{ - */ - -#define USART_DMAReq_Tx ((uint16_t)0x0080) -#define USART_DMAReq_Rx ((uint16_t)0x0040) -#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) - -/** - * @} - */ - -/** @defgroup USART_WakeUp_methods - * @{ - */ - -#define USART_WakeUp_IdleLine ((uint16_t)0x0000) -#define USART_WakeUp_AddressMark ((uint16_t)0x0800) -#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ - ((WAKEUP) == USART_WakeUp_AddressMark)) -/** - * @} - */ - -/** @defgroup USART_LIN_Break_Detection_Length - * @{ - */ - -#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) -#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) -#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ - (((LENGTH) == USART_LINBreakDetectLength_10b) || \ - ((LENGTH) == USART_LINBreakDetectLength_11b)) -/** - * @} - */ - -/** @defgroup USART_IrDA_Low_Power - * @{ - */ - -#define USART_IrDAMode_LowPower ((uint16_t)0x0004) -#define USART_IrDAMode_Normal ((uint16_t)0x0000) -#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ - ((MODE) == USART_IrDAMode_Normal)) -/** - * @} - */ - -/** @defgroup USART_Flags - * @{ - */ - -#define USART_FLAG_CTS ((uint16_t)0x0200) -#define USART_FLAG_LBD ((uint16_t)0x0100) -#define USART_FLAG_TXE ((uint16_t)0x0080) -#define USART_FLAG_TC ((uint16_t)0x0040) -#define USART_FLAG_RXNE ((uint16_t)0x0020) -#define USART_FLAG_IDLE ((uint16_t)0x0010) -#define USART_FLAG_ORE ((uint16_t)0x0008) -#define USART_FLAG_NE ((uint16_t)0x0004) -#define USART_FLAG_FE ((uint16_t)0x0002) -#define USART_FLAG_PE ((uint16_t)0x0001) -#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ - ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ - ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ - ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ - ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE)) - -#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00)) - -#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 7500001)) -#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) -#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the USART configuration to the default reset state ***/ -void USART_DeInit(USART_TypeDef* USARTx); - -/* Initialization and Configuration functions *********************************/ -void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); -void USART_StructInit(USART_InitTypeDef* USART_InitStruct); -void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); -void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); -void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); -void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); - -/* Data transfers functions ***************************************************/ -void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); -uint16_t USART_ReceiveData(USART_TypeDef* USARTx); - -/* Multi-Processor Communication functions ************************************/ -void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); -void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp); -void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); - -/* LIN mode functions *********************************************************/ -void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength); -void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SendBreak(USART_TypeDef* USARTx); - -/* Half-duplex mode function **************************************************/ -void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); - -/* Smartcard mode functions ***************************************************/ -void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); - -/* IrDA mode functions ********************************************************/ -void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); -void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); - -/* DMA transfers management functions *****************************************/ -void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); -FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); -void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); -ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); -void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_USART_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm_misc.c b/stm/stmperiph/stm_misc.c deleted file mode 100644 index 875584a66..000000000 --- a/stm/stmperiph/stm_misc.c +++ /dev/null @@ -1,249 +0,0 @@ -/** - ****************************************************************************** - * @file misc.c - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief This file provides all the miscellaneous firmware functions (add-on - * to CMSIS functions). - * - * @verbatim - * - * =================================================================== - * How to configure Interrupts using driver - * =================================================================== - * - * This section provide functions allowing to configure the NVIC interrupts (IRQ). - * The Cortex-M4 exceptions are managed by CMSIS functions. - * - * 1. Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig() - * function according to the following table. - - * The table below gives the allowed values of the pre-emption priority and subpriority according - * to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function - * ========================================================================================================================== - * NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description - * ========================================================================================================================== - * NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority - * | | | 4 bits for subpriority - * -------------------------------------------------------------------------------------------------------------------------- - * NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority - * | | | 3 bits for subpriority - * -------------------------------------------------------------------------------------------------------------------------- - * NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority - * | | | 2 bits for subpriority - * -------------------------------------------------------------------------------------------------------------------------- - * NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority - * | | | 1 bits for subpriority - * -------------------------------------------------------------------------------------------------------------------------- - * NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority - * | | | 0 bits for subpriority - * ========================================================================================================================== - * - * 2. Enable and Configure the priority of the selected IRQ Channels using NVIC_Init() - * - * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. - * The pending IRQ priority will be managed only by the subpriority. - * - * @note IRQ priority order (sorted by highest to lowest priority): - * - Lowest pre-emption priority - * - Lowest subpriority - * - Lowest hardware priority (IRQ number) - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm_misc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup MISC - * @brief MISC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup MISC_Private_Functions - * @{ - */ - -/** - * @brief Configures the priority grouping: pre-emption priority and subpriority. - * @param NVIC_PriorityGroup: specifies the priority grouping bits length. - * This parameter can be one of the following values: - * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority - * 4 bits for subpriority - * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority - * 3 bits for subpriority - * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority - * 2 bits for subpriority - * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority - * 1 bits for subpriority - * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority - * 0 bits for subpriority - * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. - * The pending IRQ priority will be managed only by the subpriority. - * @retval None - */ -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) -{ - /* Check the parameters */ - assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); - - /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ - SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; -} - -/** - * @brief Initializes the NVIC peripheral according to the specified - * parameters in the NVIC_InitStruct. - * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() - * function should be called before. - * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains - * the configuration information for the specified NVIC peripheral. - * @retval None - */ -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) -{ - uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); - assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); - assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); - - if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) - { - /* Compute the Corresponding IRQ Priority --------------------------------*/ - tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; - tmppre = (0x4 - tmppriority); - tmpsub = tmpsub >> tmppriority; - - tmppriority = NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; - tmppriority |= (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub); - - tmppriority = tmppriority << 0x04; - - NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; - - /* Enable the Selected IRQ Channels --------------------------------------*/ - NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = - (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); - } - else - { - /* Disable the Selected IRQ Channels -------------------------------------*/ - NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = - (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); - } -} - -/** - * @brief Sets the vector table location and Offset. - * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. - * This parameter can be one of the following values: - * @arg NVIC_VectTab_RAM: Vector Table in internal SRAM. - * @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH. - * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200. - * @retval None - */ -void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) -{ - /* Check the parameters */ - assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); - assert_param(IS_NVIC_OFFSET(Offset)); - - SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); -} - -/** - * @brief Selects the condition for the system to enter low power mode. - * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. - * This parameter can be one of the following values: - * @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend. - * @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request. - * @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit. - * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_NVIC_LP(LowPowerMode)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - SCB->SCR |= LowPowerMode; - } - else - { - SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); - } -} - -/** - * @brief Configures the SysTick clock source. - * @param SysTick_CLKSource: specifies the SysTick clock source. - * This parameter can be one of the following values: - * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. - * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. - * @retval None - */ -void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) -{ - /* Check the parameters */ - assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); - if (SysTick_CLKSource == SysTick_CLKSource_HCLK) - { - SysTick->CTRL |= SysTick_CLKSource_HCLK; - } - else - { - SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/stm_misc.h b/stm/stmperiph/stm_misc.h deleted file mode 100644 index 2d08fdd63..000000000 --- a/stm/stmperiph/stm_misc.h +++ /dev/null @@ -1,178 +0,0 @@ -/** - ****************************************************************************** - * @file misc.h - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief This file contains all the functions prototypes for the miscellaneous - * firmware library functions (add-on to CMSIS functions). - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MISC_H -#define __MISC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup MISC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief NVIC Init Structure definition - */ - -typedef struct -{ - uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. - This parameter can be an enumerator of @ref IRQn_Type - enumeration (For the complete STM32 Devices IRQ Channels - list, please refer to stm32f4xx.h file) */ - - uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel - specified in NVIC_IRQChannel. This parameter can be a value - between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table - A lower priority value indicates a higher priority */ - - uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified - in NVIC_IRQChannel. This parameter can be a value - between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table - A lower priority value indicates a higher priority */ - - FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel - will be enabled or disabled. - This parameter can be set either to ENABLE or DISABLE */ -} NVIC_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup MISC_Exported_Constants - * @{ - */ - -/** @defgroup MISC_Vector_Table_Base - * @{ - */ - -#define NVIC_VectTab_RAM ((uint32_t)0x20000000) -#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) -#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ - ((VECTTAB) == NVIC_VectTab_FLASH)) -/** - * @} - */ - -/** @defgroup MISC_System_Low_Power - * @{ - */ - -#define NVIC_LP_SEVONPEND ((uint8_t)0x10) -#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) -#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) -#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ - ((LP) == NVIC_LP_SLEEPDEEP) || \ - ((LP) == NVIC_LP_SLEEPONEXIT)) -/** - * @} - */ - -/** @defgroup MISC_Preemption_Priority_Group - * @{ - */ - -#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority - 4 bits for subpriority */ -#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority - 3 bits for subpriority */ -#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority - 2 bits for subpriority */ -#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority - 1 bits for subpriority */ -#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority - 0 bits for subpriority */ - -#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ - ((GROUP) == NVIC_PriorityGroup_1) || \ - ((GROUP) == NVIC_PriorityGroup_2) || \ - ((GROUP) == NVIC_PriorityGroup_3) || \ - ((GROUP) == NVIC_PriorityGroup_4)) - -#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) - -/** - * @} - */ - -/** @defgroup MISC_SysTick_clock_source - * @{ - */ - -#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) -#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) -#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ - ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); -void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); -void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); -void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); - -#ifdef __cplusplus -} -#endif - -#endif /* __MISC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmperiph/system_stm32f4xx.h b/stm/stmperiph/system_stm32f4xx.h deleted file mode 100644 index 675593a84..000000000 --- a/stm/stmperiph/system_stm32f4xx.h +++ /dev/null @@ -1,105 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32f4xx.h - * @author MCD Application Team - * @version V1.3.0 - * @date 08-November-2013 - * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f4xx_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32F4XX_H -#define __SYSTEM_STM32F4XX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32F4xx_System_Includes - * @{ - */ - -/** - * @} - */ - - -/** @addtogroup STM32F4xx_System_Exported_types - * @{ - */ - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32F4XX_H */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmusb/usb_bsp.c b/stm/stmusb/usb_bsp.c deleted file mode 100644 index 0cd5146a2..000000000 --- a/stm/stmusb/usb_bsp.c +++ /dev/null @@ -1,272 +0,0 @@ -/** - ****************************************************************************** - * @file usb_bsp.c - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief This file is responsible to offer board support package and is - * configurable by user. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm_misc.h" -#include "stm32f4xx_gpio.h" -#include "stm32f4xx_rcc.h" -#include "usb_bsp.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY -* @{ -*/ - -/** @defgroup USB_BSP -* @brief This file is responsible to offer board support package -* @{ -*/ - -/** @defgroup USB_BSP_Private_Defines -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_BSP_Private_TypesDefinitions -* @{ -*/ -/** -* @} -*/ - - - - - -/** @defgroup USB_BSP_Private_Macros -* @{ -*/ -/** -* @} -*/ - -/** @defgroup USBH_BSP_Private_Variables -* @{ -*/ - -/** -* @} -*/ - -/** @defgroup USBH_BSP_Private_FunctionPrototypes -* @{ -*/ -/** -* @} -*/ - -/** @defgroup USB_BSP_Private_Functions -* @{ -*/ - - -/** -* @brief USB_OTG_BSP_Init -* Initilizes BSP configurations -* @param None -* @retval None -*/ - -void USB_OTG_BSP_Init(USB_OTG_CORE_HANDLE *pdev) { - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE); - - /* Configure DM DP Pins on PA11 and PA12 */ - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ; - GPIO_Init(GPIOA, &GPIO_InitStructure); - - GPIO_PinAFConfig(GPIOA, GPIO_PinSource11, GPIO_AF_OTG_FS); - GPIO_PinAFConfig(GPIOA, GPIO_PinSource12, GPIO_AF_OTG_FS); - - /* Configure VBUS Pin on PA9 (or disable VBUS_SENSING_ENABLED) */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ; - GPIO_Init(GPIOA, &GPIO_InitStructure); - -#if !defined(NETDUINO_PLUS_2) - // Configure ID pin on PA10 - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP ; - GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_OTG_FS); -#endif - - RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); - RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_OTG_FS, ENABLE); -} - -/** -* @brief USB_OTG_BSP_EnableInterrupt -* Enable USB Global interrupt -* @param None -* @retval None -*/ -void USB_OTG_BSP_EnableInterrupt(USB_OTG_CORE_HANDLE *pdev) { - // this assumes we use NVIC_PriorityGroup_4 - NVIC_InitTypeDef NVIC_InitStructure; - NVIC_InitStructure.NVIC_IRQChannel = OTG_FS_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 8; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); -} - -/** -* @brief BSP_Drive_VBUS -* Drives the Vbus signal through IO -* @param state : VBUS states -* @retval None -*/ - -void USB_OTG_BSP_DriveVBUS(USB_OTG_CORE_HANDLE *pdev, uint8_t state) { - //printf("DriveVBUS %p %u\n", pdev, state); - /* - On-chip 5 V VBUS generation is not supported. For this reason, a charge pump - or, if 5 V are available on the application board, a basic power switch, must - be added externally to drive the 5 V VBUS line. The external charge pump can - be driven by any GPIO output. When the application decides to power on VBUS - using the chosen GPIO, it must also set the port power bit in the host port - control and status register (PPWR bit in OTG_FS_HPRT). - - Bit 12 PPWR: Port power - The application uses this field to control power to this port, and the core - clears this bit on an overcurrent condition. - */ -#if 0 // not implemented -#ifndef USE_USB_OTG_HS - if (0 == state) { - /* DISABLE is needed on output of the Power Switch */ - GPIO_SetBits(HOST_POWERSW_PORT, HOST_POWERSW_VBUS); - } else { - /*ENABLE the Power Switch by driving the Enable LOW */ - GPIO_ResetBits(HOST_POWERSW_PORT, HOST_POWERSW_VBUS); - } -#endif -#endif -} - -/** - * @brief USB_OTG_BSP_ConfigVBUS - * Configures the IO for the Vbus and OverCurrent - * @param None - * @retval None - */ - -void USB_OTG_BSP_ConfigVBUS(USB_OTG_CORE_HANDLE *pdev) { - //printf("ConfigVBUS %p\n", pdev); -#if 0 // not implemented -#ifdef USE_USB_OTG_FS - GPIO_InitTypeDef GPIO_InitStructure; - -#ifdef USE_STM3210C_EVAL - RCC_APB2PeriphClockCmd(HOST_POWERSW_PORT_RCC, ENABLE); - - - /* Configure Power Switch Vbus Pin */ - GPIO_InitStructure.GPIO_Pin = HOST_POWERSW_VBUS; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; - GPIO_Init(HOST_POWERSW_PORT, &GPIO_InitStructure); -#else - #ifdef USE_USB_OTG_FS - RCC_AHB1PeriphClockCmd( RCC_AHB1Periph_GPIOH , ENABLE); - - GPIO_InitStructure.GPIO_Pin = HOST_POWERSW_VBUS; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ; - GPIO_Init(HOST_POWERSW_PORT,&GPIO_InitStructure); - #endif -#endif - - /* By Default, DISABLE is needed on output of the Power Switch */ - GPIO_SetBits(HOST_POWERSW_PORT, HOST_POWERSW_VBUS); - - USB_OTG_BSP_mDelay(200); /* Delay is need for stabilising the Vbus Low - in Reset Condition, when Vbus=1 and Reset-button is pressed by user */ -#endif -#endif -} - -/** -* @brief USB_OTG_BSP_uDelay -* This function provides delay time in micro sec -* @param usec : Value of delay required in micro sec -* @retval None -*/ -void USB_OTG_BSP_uDelay (const uint32_t usec) -{ - uint32_t count = 0; - const uint32_t utime = (168 * usec / 5); - do - { - if ( ++count > utime ) - { - return ; - } - } - while (1); -} - - -/** -* @brief USB_OTG_BSP_mDelay -* This function provides delay time in milli sec -* @param msec : Value of delay required in milli sec -* @retval None -*/ -void USB_OTG_BSP_mDelay (const uint32_t msec) -{ - USB_OTG_BSP_uDelay(msec * 1000); -} -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmusb/usb_bsp.h b/stm/stmusb/usb_bsp.h deleted file mode 100644 index 29763a906..000000000 --- a/stm/stmusb/usb_bsp.h +++ /dev/null @@ -1,103 +0,0 @@ -/** - ****************************************************************************** - * @file usb_bsp.h - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief Specific api's relative to the used hardware platform - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_BSP__H__ -#define __USB_BSP__H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_core.h" -#include "usb_conf.h" - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_BSP - * @brief This file is the - * @{ - */ - - -/** @defgroup USB_BSP_Exported_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_BSP_Exported_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_BSP_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_BSP_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_BSP_Exported_FunctionsPrototype - * @{ - */ -void BSP_Init(void); - -void USB_OTG_BSP_Init (USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_BSP_uDelay (const uint32_t usec); -void USB_OTG_BSP_mDelay (const uint32_t msec); -void USB_OTG_BSP_EnableInterrupt (USB_OTG_CORE_HANDLE *pdev); -#ifdef USE_HOST_MODE -void USB_OTG_BSP_ConfigVBUS(USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_BSP_DriveVBUS(USB_OTG_CORE_HANDLE *pdev,uint8_t state); -#endif -/** - * @} - */ - -#endif //__USB_BSP__H__ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/stm/stmusb/usb_conf.h b/stm/stmusb/usb_conf.h deleted file mode 100644 index 1ae713518..000000000 --- a/stm/stmusb/usb_conf.h +++ /dev/null @@ -1,350 +0,0 @@ -/** - ****************************************************************************** - * @file usb_conf.h - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief General low level driver configuration - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_CONF__H__ -#define __USB_CONF__H__ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" -//#include "stm324xg_eval.h" -//#include "stm324xg_eval_lcd.h" -//#include "stm324xg_eval_ioe.h" -//#include "stm324xg_eval_sdio_sd.h" - - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_CONF - * @brief USB low level driver configuration file - * @{ - */ - -/** @defgroup USB_CONF_Exported_Defines - * @{ - */ - -/* USB Core and PHY interface configuration. - Tip: To avoid modifying these defines each time you need to change the USB - configuration, you can declare the needed define in your toolchain - compiler preprocessor. - */ -/****************** USB OTG FS PHY CONFIGURATION ******************************* -* The USB OTG FS Core supports one on-chip Full Speed PHY. -* -* The USE_EMBEDDED_PHY symbol is defined in the project compiler preprocessor -* when FS core is used. -*******************************************************************************/ -#ifndef USE_USB_OTG_FS - #define USE_USB_OTG_FS -#endif /* USE_USB_OTG_FS */ - -#ifdef USE_USB_OTG_FS - #define USB_OTG_FS_CORE -#endif - -/****************** USB OTG HS PHY CONFIGURATION ******************************* -* The USB OTG HS Core supports two PHY interfaces: -* (i) An ULPI interface for the external High Speed PHY: the USB HS Core will -* operate in High speed mode -* (ii) An on-chip Full Speed PHY: the USB HS Core will operate in Full speed mode -* -* You can select the PHY to be used using one of these two defines: -* (i) USE_ULPI_PHY: if the USB OTG HS Core is to be used in High speed mode -* (ii) USE_EMBEDDED_PHY: if the USB OTG HS Core is to be used in Full speed mode -* -* Notes: -* - The USE_ULPI_PHY symbol is defined in the project compiler preprocessor as -* default PHY when HS core is used. -* - On STM322xG-EVAL and STM324xG-EVAL boards, only configuration(i) is available. -* Configuration (ii) need a different hardware, for more details refer to your -* STM32 device datasheet. -*******************************************************************************/ -#ifndef USE_USB_OTG_HS - //#define USE_USB_OTG_HS -#endif /* USE_USB_OTG_HS */ - -#ifndef USE_ULPI_PHY - //#define USE_ULPI_PHY -#endif /* USE_ULPI_PHY */ - -#ifndef USE_EMBEDDED_PHY - //#define USE_EMBEDDED_PHY -#endif /* USE_EMBEDDED_PHY */ - -#ifdef USE_USB_OTG_HS - #define USB_OTG_HS_CORE -#endif - -/******************************************************************************* -* FIFO Size Configuration in Device mode -* -* (i) Receive data FIFO size = RAM for setup packets + -* OUT endpoint control information + -* data OUT packets + miscellaneous -* Space = ONE 32-bits words -* --> RAM for setup packets = 10 spaces -* (n is the nbr of CTRL EPs the device core supports) -* --> OUT EP CTRL info = 1 space -* (one space for status information written to the FIFO along with each -* received packet) -* --> data OUT packets = (Largest Packet Size / 4) + 1 spaces -* (MINIMUM to receive packets) -* --> OR data OUT packets = at least 2*(Largest Packet Size / 4) + 1 spaces -* (if high-bandwidth EP is enabled or multiple isochronous EPs) -* --> miscellaneous = 1 space per OUT EP -* (one space for transfer complete status information also pushed to the -* FIFO with each endpoint's last packet) -* -* (ii)MINIMUM RAM space required for each IN EP Tx FIFO = MAX packet size for -* that particular IN EP. More space allocated in the IN EP Tx FIFO results -* in a better performance on the USB and can hide latencies on the AHB. -* -* (iii) TXn min size = 16 words. (n : Transmit FIFO index) -* (iv) When a TxFIFO is not used, the Configuration should be as follows: -* case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes) -* --> Txm can use the space allocated for Txn. -* case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes) -* --> Txn should be configured with the minimum space of 16 words -* (v) The FIFO is used optimally when used TxFIFOs are allocated in the top -* of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. -* (vi) In HS case 12 FIFO locations should be reserved for internal DMA registers -* so total FIFO size should be 1012 Only instead of 1024 -*******************************************************************************/ - -/****************** USB OTG HS CONFIGURATION **********************************/ -#ifdef USB_OTG_HS_CORE - #define RX_FIFO_HS_SIZE 512 - #define TX0_FIFO_HS_SIZE 128 - #define TX1_FIFO_HS_SIZE 372 - #define TX2_FIFO_HS_SIZE 64 - #define TX3_FIFO_HS_SIZE 0 - #define TX4_FIFO_HS_SIZE 0 - #define TX5_FIFO_HS_SIZE 0 - -// #define USB_OTG_HS_SOF_OUTPUT_ENABLED - - #ifdef USE_ULPI_PHY - #define USB_OTG_ULPI_PHY_ENABLED - #endif - #ifdef USE_EMBEDDED_PHY - #define USB_OTG_EMBEDDED_PHY_ENABLED - /* wakeup is working only when HS core is configured in FS mode */ - #define USB_OTG_HS_LOW_PWR_MGMT_SUPPORT - #endif - /* #define USB_OTG_HS_INTERNAL_DMA_ENABLED */ /* Be aware that enabling DMA mode will result in data being sent only by - multiple of 4 packet sizes. This is due to the fact that USB DMA does - not allow sending data from non word-aligned addresses. - For this specific application, it is advised to not enable this option - unless required. */ - #define USB_OTG_HS_DEDICATED_EP1_ENABLED -#endif - -/****************** USB OTG FS CONFIGURATION **********************************/ -#ifdef USB_OTG_FS_CORE - #define RX_FIFO_FS_SIZE 128 - #define TX0_FIFO_FS_SIZE 32 - #define TX1_FIFO_FS_SIZE 64 - #define TX2_FIFO_FS_SIZE 32 - #define TX3_FIFO_FS_SIZE 64 - -// #define USB_OTG_FS_LOW_PWR_MGMT_SUPPORT -// #define USB_OTG_FS_SOF_OUTPUT_ENABLED -#endif - -/****************** USB OTG MISC CONFIGURATION ********************************/ -#define VBUS_SENSING_ENABLED - -/* BEGIN host specific stuff */ - -/******************************************************************************* -* FIFO Size Configuration in Host mode -* -* (i) Receive data FIFO size = (Largest Packet Size / 4) + 1 or -* 2x (Largest Packet Size / 4) + 1, If a -* high-bandwidth channel or multiple isochronous -* channels are enabled -* -* (ii) For the host nonperiodic Transmit FIFO is the largest maximum packet size -* for all supported nonperiodic OUT channels. Typically, a space -* corresponding to two Largest Packet Size is recommended. -* -* (iii) The minimum amount of RAM required for Host periodic Transmit FIFO is -* the largest maximum packet size for all supported periodic OUT channels. -* If there is at least one High Bandwidth Isochronous OUT endpoint, -* then the space must be at least two times the maximum packet size for -* that channel. -*******************************************************************************/ - -/****************** USB OTG HS CONFIGURATION (for host) ***********************/ -#ifdef USB_OTG_HS_CORE - #define RX_FIFO_HS_SIZE 512 - #define TXH_NP_HS_FIFOSIZ 256 - #define TXH_P_HS_FIFOSIZ 256 - -// #define USB_OTG_HS_LOW_PWR_MGMT_SUPPORT -// #define USB_OTG_HS_SOF_OUTPUT_ENABLED - -// #define USB_OTG_INTERNAL_VBUS_ENABLED -#define USB_OTG_EXTERNAL_VBUS_ENABLED - - #ifdef USE_ULPI_PHY - #define USB_OTG_ULPI_PHY_ENABLED - #endif - #ifdef USE_EMBEDDED_PHY - #define USB_OTG_EMBEDDED_PHY_ENABLED - #endif - #define USB_OTG_HS_INTERNAL_DMA_ENABLED -// #define USB_OTG_HS_DEDICATED_EP1_ENABLED -#endif - -/****************** USB OTG FS CONFIGURATION (for host) ***********************/ -#ifdef USB_OTG_FS_CORE - //#define RX_FIFO_FS_SIZE 128 // already defined for device (and it's the same) - #define TXH_NP_FS_FIFOSIZ 96 - #define TXH_P_FS_FIFOSIZ 96 - -// #define USB_OTG_FS_LOW_PWR_MGMT_SUPPORT -// #define USB_OTG_FS_SOF_OUTPUT_ENABLED -#endif - -/* END host specific stuff */ - -/****************** USB OTG MODE CONFIGURATION ********************************/ -//#define USE_HOST_MODE // set in mpconfigport.h -//#define USE_DEVICE_MODE // set in mpconfigport.h -//#define USE_OTG_MODE // set in mpconfigport.h - -#ifndef USB_OTG_FS_CORE - #ifndef USB_OTG_HS_CORE - #error "USB_OTG_HS_CORE or USB_OTG_FS_CORE should be defined" - #endif -#endif - -#ifndef USE_DEVICE_MODE - #ifndef USE_HOST_MODE - #error "USE_DEVICE_MODE or USE_HOST_MODE should be defined" - #endif -#endif - -#ifndef USE_USB_OTG_HS - #ifndef USE_USB_OTG_FS - #error "USE_USB_OTG_HS or USE_USB_OTG_FS should be defined" - #endif -#else //USE_USB_OTG_HS - #ifndef USE_ULPI_PHY - #ifndef USE_EMBEDDED_PHY - #error "USE_ULPI_PHY or USE_EMBEDDED_PHY should be defined" - #endif - #endif -#endif - -/****************** C Compilers dependant keywords ****************************/ -/* In HS mode and when the DMA is used, all variables and data structures dealing - with the DMA during the transaction process should be 4-bytes aligned */ -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined (__GNUC__) /* GNU Compiler */ - #define __ALIGN_END __attribute__ ((aligned (4))) - #define __ALIGN_BEGIN - #else - #define __ALIGN_END - #if defined (__CC_ARM) /* ARM Compiler */ - #define __ALIGN_BEGIN __align(4) - #elif defined (__ICCARM__) /* IAR Compiler */ - #define __ALIGN_BEGIN - #elif defined (__TASKING__) /* TASKING Compiler */ - #define __ALIGN_BEGIN __align(4) - #endif /* __CC_ARM */ - #endif /* __GNUC__ */ -#else - #define __ALIGN_BEGIN - #define __ALIGN_END -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ - -/* __packed keyword used to decrease the data type alignment to 1-byte */ -#if defined (__CC_ARM) /* ARM Compiler */ - #define __packed __packed -#elif defined (__ICCARM__) /* IAR Compiler */ - #define __packed __packed -#elif defined ( __GNUC__ ) /* GNU Compiler */ - #ifndef __packed /* dpgeorge: add check for already defined symbol, since some compilers define it in cdefs.h */ - #define __packed __attribute__ ((__packed__)) - #endif -#elif defined (__TASKING__) /* TASKING Compiler */ - #define __packed __unaligned -#endif /* __CC_ARM */ - -/** - * @} - */ - - -/** @defgroup USB_CONF_Exported_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_CONF_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_CONF_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_CONF_Exported_FunctionsPrototype - * @{ - */ -/** - * @} - */ - - -#endif //__USB_CONF__H__ - - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/stm/stmusb/usb_core.c b/stm/stmusb/usb_core.c deleted file mode 100644 index 64dd3e4fc..000000000 --- a/stm/stmusb/usb_core.c +++ /dev/null @@ -1,2162 +0,0 @@ -/** - ****************************************************************************** - * @file usb_core.c - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief USB-OTG Core Layer - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_core.h" -#include "usb_bsp.h" - - -/** @addtogroup USB_OTG_DRIVER -* @{ -*/ - -/** @defgroup USB_CORE -* @brief This file includes the USB-OTG Core Layer -* @{ -*/ - - -/** @defgroup USB_CORE_Private_Defines -* @{ -*/ - -/** -* @} -*/ - - -/** @defgroup USB_CORE_Private_TypesDefinitions -* @{ -*/ -/** -* @} -*/ - - - -/** @defgroup USB_CORE_Private_Macros -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_CORE_Private_Variables -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_CORE_Private_FunctionPrototypes -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_CORE_Private_Functions -* @{ -*/ - -/** -* @brief USB_OTG_EnableCommonInt -* Initializes the commmon interrupts, used in both device and modes -* @param pdev : Selected device -* @retval None -*/ -static void USB_OTG_EnableCommonInt(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTMSK_TypeDef int_mask; - - int_mask.d32 = 0; - /* Clear any pending USB_OTG Interrupts */ -#ifndef USE_OTG_MODE - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GOTGINT, 0xFFFFFFFF); -#endif - /* Clear any pending interrupts */ - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, 0xBFFFFFFF); - /* Enable the interrupts in the INTMSK */ - int_mask.b.wkupintr = 1; - int_mask.b.usbsuspend = 1; - -#ifdef USE_OTG_MODE - int_mask.b.otgintr = 1; - int_mask.b.sessreqintr = 1; - int_mask.b.conidstschng = 1; -#endif - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTMSK, int_mask.d32); -} - -/** -* @brief USB_OTG_CoreReset : Soft reset of the core -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -static USB_OTG_STS USB_OTG_CoreReset(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - __IO USB_OTG_GRSTCTL_TypeDef greset; - uint32_t count = 0; - - greset.d32 = 0; - /* Wait for AHB master IDLE state. */ - do - { - USB_OTG_BSP_uDelay(3); - greset.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GRSTCTL); - if (++count > 200000) - { - return USB_OTG_OK; - } - } - while (greset.b.ahbidle == 0); - /* Core Soft Reset */ - count = 0; - greset.b.csftrst = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRSTCTL, greset.d32 ); - do - { - greset.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GRSTCTL); - if (++count > 200000) - { - break; - } - } - while (greset.b.csftrst == 1); - /* Wait for 3 PHY Clocks*/ - USB_OTG_BSP_uDelay(3); - return status; -} - -/** -* @brief USB_OTG_WritePacket : Writes a packet into the Tx FIFO associated -* with the EP -* @param pdev : Selected device -* @param src : source pointer -* @param ch_ep_num : end point number -* @param bytes : No. of bytes -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_WritePacket(USB_OTG_CORE_HANDLE *pdev, - uint8_t *src, - uint8_t ch_ep_num, - uint16_t len) -{ - USB_OTG_STS status = USB_OTG_OK; - if (pdev->cfg.dma_enable == 0) - { - uint32_t count32b= 0 , i= 0; - __IO uint32_t *fifo; - - count32b = (len + 3) / 4; - fifo = pdev->regs.DFIFO[ch_ep_num]; - for (i = 0; i < count32b; i++, src+=4) - { - USB_OTG_WRITE_REG32( fifo, *((__packed uint32_t *)src) ); - } - } - return status; -} - - -/** -* @brief USB_OTG_ReadPacket : Reads a packet from the Rx FIFO -* @param pdev : Selected device -* @param dest : Destination Pointer -* @param bytes : No. of bytes -* @retval None -*/ -void *USB_OTG_ReadPacket(USB_OTG_CORE_HANDLE *pdev, - uint8_t *dest, - uint16_t len) -{ - uint32_t i=0; - uint32_t count32b = (len + 3) / 4; - - __IO uint32_t *fifo = pdev->regs.DFIFO[0]; - - for ( i = 0; i < count32b; i++, dest += 4 ) - { - *(__packed uint32_t *)dest = USB_OTG_READ_REG32(fifo); - - } - return ((void *)dest); -} - -/** -* @brief USB_OTG_SelectCore -* Initialize core registers address. -* @param pdev : Selected device -* @param coreID : USB OTG Core ID -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_SelectCore(USB_OTG_CORE_HANDLE *pdev, - USB_OTG_CORE_ID_TypeDef coreID) -{ - uint32_t i , baseAddress = 0; - USB_OTG_STS status = USB_OTG_OK; - - pdev->cfg.dma_enable = 0; - - /* at startup the core is in FS mode */ - pdev->cfg.speed = USB_OTG_SPEED_FULL; - pdev->cfg.mps = USB_OTG_FS_MAX_PACKET_SIZE ; - - /* initialize device cfg following its address */ - if (coreID == USB_OTG_FS_CORE_ID) - { - baseAddress = USB_OTG_FS_BASE_ADDR; - pdev->cfg.coreID = USB_OTG_FS_CORE_ID; - pdev->cfg.host_channels = 8 ; - pdev->cfg.dev_endpoints = 4 ; - pdev->cfg.TotalFifoSize = 320; /* in 32-bits */ - pdev->cfg.phy_itface = USB_OTG_EMBEDDED_PHY; - -#ifdef USB_OTG_FS_SOF_OUTPUT_ENABLED - pdev->cfg.Sof_output = 1; -#endif - -#ifdef USB_OTG_FS_LOW_PWR_MGMT_SUPPORT - pdev->cfg.low_power = 1; -#endif - } - else if (coreID == USB_OTG_HS_CORE_ID) - { - baseAddress = USB_OTG_HS_BASE_ADDR; - pdev->cfg.coreID = USB_OTG_HS_CORE_ID; - pdev->cfg.host_channels = 12 ; - pdev->cfg.dev_endpoints = 6 ; - pdev->cfg.TotalFifoSize = 1280;/* in 32-bits */ - -#ifdef USB_OTG_ULPI_PHY_ENABLED - pdev->cfg.phy_itface = USB_OTG_ULPI_PHY; -#else -#ifdef USB_OTG_EMBEDDED_PHY_ENABLED - pdev->cfg.phy_itface = USB_OTG_EMBEDDED_PHY; -#endif -#endif - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - pdev->cfg.dma_enable = 1; -#endif - -#ifdef USB_OTG_HS_SOF_OUTPUT_ENABLED - pdev->cfg.Sof_output = 1; -#endif - -#ifdef USB_OTG_HS_LOW_PWR_MGMT_SUPPORT - pdev->cfg.low_power = 1; -#endif - - } - - pdev->regs.GREGS = (USB_OTG_GREGS *)(baseAddress + \ - USB_OTG_CORE_GLOBAL_REGS_OFFSET); - pdev->regs.DREGS = (USB_OTG_DREGS *) (baseAddress + \ - USB_OTG_DEV_GLOBAL_REG_OFFSET); - - for (i = 0; i < pdev->cfg.dev_endpoints; i++) - { - pdev->regs.INEP_REGS[i] = (USB_OTG_INEPREGS *) \ - (baseAddress + USB_OTG_DEV_IN_EP_REG_OFFSET + \ - (i * USB_OTG_EP_REG_OFFSET)); - pdev->regs.OUTEP_REGS[i] = (USB_OTG_OUTEPREGS *) \ - (baseAddress + USB_OTG_DEV_OUT_EP_REG_OFFSET + \ - (i * USB_OTG_EP_REG_OFFSET)); - } - pdev->regs.HREGS = (USB_OTG_HREGS *)(baseAddress + \ - USB_OTG_HOST_GLOBAL_REG_OFFSET); - pdev->regs.HPRT0 = (uint32_t *)(baseAddress + USB_OTG_HOST_PORT_REGS_OFFSET); - - for (i = 0; i < pdev->cfg.host_channels; i++) - { - pdev->regs.HC_REGS[i] = (USB_OTG_HC_REGS *)(baseAddress + \ - USB_OTG_HOST_CHAN_REGS_OFFSET + \ - (i * USB_OTG_CHAN_REGS_OFFSET)); - } - for (i = 0; i < pdev->cfg.host_channels; i++) - { - pdev->regs.DFIFO[i] = (uint32_t *)(baseAddress + USB_OTG_DATA_FIFO_OFFSET +\ - (i * USB_OTG_DATA_FIFO_SIZE)); - } - pdev->regs.PCGCCTL = (uint32_t *)(baseAddress + USB_OTG_PCGCCTL_OFFSET); - - return status; -} - - -/** -* @brief USB_OTG_CoreInit -* Initializes the USB_OTG controller registers and prepares the core -* device mode or host mode operation. -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_CoreInit(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_GUSBCFG_TypeDef usbcfg; - USB_OTG_GCCFG_TypeDef gccfg; - USB_OTG_GAHBCFG_TypeDef ahbcfg; - - usbcfg.d32 = 0; - gccfg.d32 = 0; - ahbcfg.d32 = 0; - - - - if (pdev->cfg.phy_itface == USB_OTG_ULPI_PHY) - { - gccfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GCCFG); - gccfg.b.pwdn = 0; - - if (pdev->cfg.Sof_output) - { - gccfg.b.sofouten = 1; - } - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GCCFG, gccfg.d32); - - /* Init The ULPI Interface */ - usbcfg.d32 = 0; - usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG); - - usbcfg.b.physel = 0; /* HS Interface */ -#ifdef USB_OTG_INTERNAL_VBUS_ENABLED - usbcfg.b.ulpi_ext_vbus_drv = 0; /* Use internal VBUS */ -#else -#ifdef USB_OTG_EXTERNAL_VBUS_ENABLED - usbcfg.b.ulpi_ext_vbus_drv = 1; /* Use external VBUS */ -#endif -#endif - usbcfg.b.term_sel_dl_pulse = 0; /* Data line pulsing using utmi_txvalid */ - - usbcfg.b.ulpi_fsls = 0; - usbcfg.b.ulpi_clk_sus_m = 0; - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GUSBCFG, usbcfg.d32); - - /* Reset after a PHY select */ - USB_OTG_CoreReset(pdev); - - if(pdev->cfg.dma_enable == 1) - { - - ahbcfg.b.hburstlen = 5; /* 64 x 32-bits*/ - ahbcfg.b.dmaenable = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32); - - } - } - else /* FS interface (embedded Phy) */ - { - - usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);; - usbcfg.b.physel = 1; /* FS Interface */ - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GUSBCFG, usbcfg.d32); - /* Reset after a PHY select and set Host mode */ - USB_OTG_CoreReset(pdev); - /* Deactivate the power down*/ - gccfg.d32 = 0; - gccfg.b.pwdn = 1; - - gccfg.b.vbussensingA = 1 ; - gccfg.b.vbussensingB = 1 ; -#ifndef VBUS_SENSING_ENABLED - gccfg.b.disablevbussensing = 1; -#endif - - if(pdev->cfg.Sof_output) - { - gccfg.b.sofouten = 1; - } - - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GCCFG, gccfg.d32); - USB_OTG_BSP_mDelay(20); - } - /* case the HS core is working in FS mode */ - if(pdev->cfg.dma_enable == 1) - { - - ahbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GAHBCFG); - ahbcfg.b.hburstlen = 5; /* 64 x 32-bits*/ - ahbcfg.b.dmaenable = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32); - - } - /* initialize OTG features */ -#ifdef USE_OTG_MODE - usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG); - usbcfg.b.hnpcap = 1; - usbcfg.b.srpcap = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, usbcfg.d32); - USB_OTG_EnableCommonInt(pdev); -#endif - return status; -} -/** -* @brief USB_OTG_EnableGlobalInt -* Enables the controller's Global Int in the AHB Config reg -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EnableGlobalInt(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_GAHBCFG_TypeDef ahbcfg; - - ahbcfg.d32 = 0; - ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ - USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GAHBCFG, 0, ahbcfg.d32); - return status; -} - - -/** -* @brief USB_OTG_DisableGlobalInt -* Enables the controller's Global Int in the AHB Config reg -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_DisableGlobalInt(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_GAHBCFG_TypeDef ahbcfg; - ahbcfg.d32 = 0; - ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ - USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32, 0); - return status; -} - - -/** -* @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO -* @param pdev : Selected device -* @param num : FO num -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_FlushTxFifo (USB_OTG_CORE_HANDLE *pdev , uint32_t num ) -{ - USB_OTG_STS status = USB_OTG_OK; - __IO USB_OTG_GRSTCTL_TypeDef greset; - - uint32_t count = 0; - greset.d32 = 0; - greset.b.txfflsh = 1; - greset.b.txfnum = num; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GRSTCTL, greset.d32 ); - do - { - greset.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRSTCTL); - if (++count > 200000) - { - break; - } - } - while (greset.b.txfflsh == 1); - /* Wait for 3 PHY Clocks*/ - USB_OTG_BSP_uDelay(3); - return status; -} - - -/** -* @brief USB_OTG_FlushRxFifo : Flush a Rx FIFO -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_FlushRxFifo( USB_OTG_CORE_HANDLE *pdev ) -{ - USB_OTG_STS status = USB_OTG_OK; - __IO USB_OTG_GRSTCTL_TypeDef greset; - uint32_t count = 0; - - greset.d32 = 0; - greset.b.rxfflsh = 1; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GRSTCTL, greset.d32 ); - do - { - greset.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRSTCTL); - if (++count > 200000) - { - break; - } - } - while (greset.b.rxfflsh == 1); - /* Wait for 3 PHY Clocks*/ - USB_OTG_BSP_uDelay(3); - return status; -} - - -/** -* @brief USB_OTG_SetCurrentMode : Set ID line -* @param pdev : Selected device -* @param mode : (Host/device) -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_SetCurrentMode(USB_OTG_CORE_HANDLE *pdev , uint8_t mode) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_GUSBCFG_TypeDef usbcfg; - - usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG); - - usbcfg.b.force_host = 0; - usbcfg.b.force_dev = 0; - - if ( mode == HOST_MODE) - { - usbcfg.b.force_host = 1; - } - else if ( mode == DEVICE_MODE) - { - usbcfg.b.force_dev = 1; - } - - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, usbcfg.d32); - USB_OTG_BSP_mDelay(50); - return status; -} - - -/** -* @brief USB_OTG_GetMode : Get current mode -* @param pdev : Selected device -* @retval current mode -*/ -uint32_t USB_OTG_GetMode(USB_OTG_CORE_HANDLE *pdev) -{ - return (USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTSTS ) & 0x1); -} - - -/** -* @brief USB_OTG_IsDeviceMode : Check if it is device mode -* @param pdev : Selected device -* @retval num_in_ep -*/ -uint8_t USB_OTG_IsDeviceMode(USB_OTG_CORE_HANDLE *pdev) -{ - return (USB_OTG_GetMode(pdev) != HOST_MODE); -} - - -/** -* @brief USB_OTG_IsHostMode : Check if it is host mode -* @param pdev : Selected device -* @retval num_in_ep -*/ -uint8_t USB_OTG_IsHostMode(USB_OTG_CORE_HANDLE *pdev) -{ - return (USB_OTG_GetMode(pdev) == HOST_MODE); -} - - -/** -* @brief USB_OTG_ReadCoreItr : returns the Core Interrupt register -* @param pdev : Selected device -* @retval Status -*/ -uint32_t USB_OTG_ReadCoreItr(USB_OTG_CORE_HANDLE *pdev) -{ - uint32_t v = 0; - v = USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTSTS); - v &= USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTMSK); - return v; -} - - -/** -* @brief USB_OTG_ReadOtgItr : returns the USB_OTG Interrupt register -* @param pdev : Selected device -* @retval Status -*/ -uint32_t USB_OTG_ReadOtgItr (USB_OTG_CORE_HANDLE *pdev) -{ - return (USB_OTG_READ_REG32 (&pdev->regs.GREGS->GOTGINT)); -} - -#ifdef USE_HOST_MODE -/** -* @brief USB_OTG_CoreInitHost : Initializes USB_OTG controller for host mode -* @param pdev : Selected device -* @retval status -*/ -USB_OTG_STS USB_OTG_CoreInitHost(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_FSIZ_TypeDef nptxfifosize; - USB_OTG_FSIZ_TypeDef ptxfifosize; - USB_OTG_HCFG_TypeDef hcfg; - -#ifdef USE_OTG_MODE - USB_OTG_GOTGCTL_TypeDef gotgctl; -#endif - - uint32_t i = 0; - - nptxfifosize.d32 = 0; - ptxfifosize.d32 = 0; -#ifdef USE_OTG_MODE - gotgctl.d32 = 0; -#endif - hcfg.d32 = 0; - - - /* configure charge pump IO */ - USB_OTG_BSP_ConfigVBUS(pdev); - - /* Restart the Phy Clock */ - USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, 0); - - /* Initialize Host Configuration Register */ - if (pdev->cfg.phy_itface == USB_OTG_ULPI_PHY) - { - USB_OTG_InitFSLSPClkSel(pdev , HCFG_30_60_MHZ); - } - else - { - USB_OTG_InitFSLSPClkSel(pdev , HCFG_48_MHZ); - } - USB_OTG_ResetPort(pdev); - - hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG); - hcfg.b.fslssupp = 0; - USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HCFG, hcfg.d32); - - /* Configure data FIFO sizes */ - /* Rx FIFO */ -#ifdef USB_OTG_FS_CORE - if(pdev->cfg.coreID == USB_OTG_FS_CORE_ID) - { - /* set Rx FIFO size */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_FS_SIZE); - nptxfifosize.b.startaddr = RX_FIFO_FS_SIZE; - nptxfifosize.b.depth = TXH_NP_FS_FIFOSIZ; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32); - - ptxfifosize.b.startaddr = RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ; - ptxfifosize.b.depth = TXH_P_FS_FIFOSIZ; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->HPTXFSIZ, ptxfifosize.d32); - } -#endif -#ifdef USB_OTG_HS_CORE - if (pdev->cfg.coreID == USB_OTG_HS_CORE_ID) - { - /* set Rx FIFO size */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_HS_SIZE); - nptxfifosize.b.startaddr = RX_FIFO_HS_SIZE; - nptxfifosize.b.depth = TXH_NP_HS_FIFOSIZ; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32); - - ptxfifosize.b.startaddr = RX_FIFO_HS_SIZE + TXH_NP_HS_FIFOSIZ; - ptxfifosize.b.depth = TXH_P_HS_FIFOSIZ; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->HPTXFSIZ, ptxfifosize.d32); - } -#endif - -#ifdef USE_OTG_MODE - /* Clear Host Set HNP Enable in the USB_OTG Control Register */ - gotgctl.b.hstsethnpen = 1; - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GOTGCTL, gotgctl.d32, 0); -#endif - - /* Make sure the FIFOs are flushed. */ - USB_OTG_FlushTxFifo(pdev, 0x10 ); /* all Tx FIFOs */ - USB_OTG_FlushRxFifo(pdev); - - - /* Clear all pending HC Interrupts */ - for (i = 0; i < pdev->cfg.host_channels; i++) - { - USB_OTG_WRITE_REG32( &pdev->regs.HC_REGS[i]->HCINT, 0xFFFFFFFF ); - USB_OTG_WRITE_REG32( &pdev->regs.HC_REGS[i]->HCINTMSK, 0 ); - } -#ifndef USE_OTG_MODE - USB_OTG_DriveVbus(pdev, 1); -#endif - - USB_OTG_EnableHostInt(pdev); - return status; -} - -/** -* @brief USB_OTG_IsEvenFrame -* This function returns the frame number for sof packet -* @param pdev : Selected device -* @retval Frame number -*/ -uint8_t USB_OTG_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev) -{ - return !(USB_OTG_READ_REG32(&pdev->regs.HREGS->HFNUM) & 0x1); -} - -/** -* @brief USB_OTG_DriveVbus : set/reset vbus -* @param pdev : Selected device -* @param state : VBUS state -* @retval None -*/ -void USB_OTG_DriveVbus (USB_OTG_CORE_HANDLE *pdev, uint8_t state) -{ - USB_OTG_HPRT0_TypeDef hprt0; - - hprt0.d32 = 0; - - /* enable disable the external charge pump */ - USB_OTG_BSP_DriveVBUS(pdev, state); - - /* Turn on the Host port power. */ - hprt0.d32 = USB_OTG_ReadHPRT0(pdev); - if ((hprt0.b.prtpwr == 0 ) && (state == 1 )) - { - hprt0.b.prtpwr = 1; - USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32); - } - if ((hprt0.b.prtpwr == 1 ) && (state == 0 )) - { - hprt0.b.prtpwr = 0; - USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32); - } - - USB_OTG_BSP_mDelay(200); -} -/** -* @brief USB_OTG_EnableHostInt: Enables the Host mode interrupts -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EnableHostInt(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_GINTMSK_TypeDef intmsk; - intmsk.d32 = 0; - /* Disable all interrupts. */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTMSK, 0); - - /* Clear any pending interrupts. */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, 0xFFFFFFFF); - - /* Enable the common interrupts */ - USB_OTG_EnableCommonInt(pdev); - - if (pdev->cfg.dma_enable == 0) - { - intmsk.b.rxstsqlvl = 1; - } - intmsk.b.portintr = 1; - intmsk.b.hcintr = 1; - intmsk.b.disconnect = 1; - intmsk.b.sofintr = 1; - intmsk.b.incomplisoout = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, intmsk.d32, intmsk.d32); - return status; -} - -/** -* @brief USB_OTG_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the -* HCFG register on the PHY type -* @param pdev : Selected device -* @param freq : clock frequency -* @retval None -*/ -void USB_OTG_InitFSLSPClkSel(USB_OTG_CORE_HANDLE *pdev , uint8_t freq) -{ - USB_OTG_HCFG_TypeDef hcfg; - - hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG); - hcfg.b.fslspclksel = freq; - USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HCFG, hcfg.d32); -} - - -/** -* @brief USB_OTG_ReadHPRT0 : Reads HPRT0 to modify later -* @param pdev : Selected device -* @retval HPRT0 value -*/ -uint32_t USB_OTG_ReadHPRT0(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_HPRT0_TypeDef hprt0; - - hprt0.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0); - hprt0.b.prtena = 0; - hprt0.b.prtconndet = 0; - hprt0.b.prtenchng = 0; - hprt0.b.prtovrcurrchng = 0; - return hprt0.d32; -} - - -/** -* @brief USB_OTG_ReadHostAllChannels_intr : Register PCD Callbacks -* @param pdev : Selected device -* @retval Status -*/ -uint32_t USB_OTG_ReadHostAllChannels_intr (USB_OTG_CORE_HANDLE *pdev) -{ - return (USB_OTG_READ_REG32 (&pdev->regs.HREGS->HAINT)); -} - - -/** -* @brief USB_OTG_ResetPort : Reset Host Port -* @param pdev : Selected device -* @retval status -* @note : (1)The application must wait at least 10 ms (+ 10 ms security) -* before clearing the reset bit. -*/ -uint32_t USB_OTG_ResetPort(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_HPRT0_TypeDef hprt0; - - hprt0.d32 = USB_OTG_ReadHPRT0(pdev); - hprt0.b.prtrst = 1; - USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32); - USB_OTG_BSP_mDelay (10); /* See Note #1 */ - hprt0.b.prtrst = 0; - USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32); - USB_OTG_BSP_mDelay (20); - return 1; -} - - -/** -* @brief USB_OTG_HC_Init : Prepares a host channel for transferring packets -* @param pdev : Selected device -* @param hc_num : channel number -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_HC_Init(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) -{ - USB_OTG_STS status = USB_OTG_OK; - uint32_t intr_enable = 0; - USB_OTG_HCINTMSK_TypeDef hcintmsk; - USB_OTG_GINTMSK_TypeDef gintmsk; - USB_OTG_HCCHAR_TypeDef hcchar; - USB_OTG_HCINTn_TypeDef hcint; - - - gintmsk.d32 = 0; - hcintmsk.d32 = 0; - hcchar.d32 = 0; - - /* Clear old interrupt conditions for this host channel. */ - hcint.d32 = 0xFFFFFFFF; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINT, hcint.d32); - - /* Enable channel interrupts required for this transfer. */ - hcintmsk.d32 = 0; - - if (pdev->cfg.dma_enable == 1) - { - hcintmsk.b.ahberr = 1; - } - - switch (pdev->host.hc[hc_num].ep_type) - { - case EP_TYPE_CTRL: - case EP_TYPE_BULK: - hcintmsk.b.xfercompl = 1; - hcintmsk.b.stall = 1; - hcintmsk.b.xacterr = 1; - hcintmsk.b.datatglerr = 1; - hcintmsk.b.nak = 1; - if (pdev->host.hc[hc_num].ep_is_in) - { - hcintmsk.b.bblerr = 1; - } - else - { - hcintmsk.b.nyet = 1; - if (pdev->host.hc[hc_num].do_ping) - { - hcintmsk.b.ack = 1; - } - } - break; - case EP_TYPE_INTR: - hcintmsk.b.xfercompl = 1; - hcintmsk.b.nak = 1; - hcintmsk.b.stall = 1; - hcintmsk.b.xacterr = 1; - hcintmsk.b.datatglerr = 1; - hcintmsk.b.frmovrun = 1; - - if (pdev->host.hc[hc_num].ep_is_in) - { - hcintmsk.b.bblerr = 1; - } - - break; - case EP_TYPE_ISOC: - hcintmsk.b.xfercompl = 1; - hcintmsk.b.frmovrun = 1; - hcintmsk.b.ack = 1; - - if (pdev->host.hc[hc_num].ep_is_in) - { - hcintmsk.b.xacterr = 1; - hcintmsk.b.bblerr = 1; - } - break; - } - - - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK, hcintmsk.d32); - - - /* Enable the top level host channel interrupt. */ - intr_enable = (1 << hc_num); - USB_OTG_MODIFY_REG32(&pdev->regs.HREGS->HAINTMSK, 0, intr_enable); - - /* Make sure host channel interrupts are enabled. */ - gintmsk.b.hcintr = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, 0, gintmsk.d32); - - /* Program the HCCHAR register */ - hcchar.d32 = 0; - hcchar.b.devaddr = pdev->host.hc[hc_num].dev_addr; - hcchar.b.epnum = pdev->host.hc[hc_num].ep_num; - hcchar.b.epdir = pdev->host.hc[hc_num].ep_is_in; - hcchar.b.lspddev = (pdev->host.hc[hc_num].speed == HPRT0_PRTSPD_LOW_SPEED); - hcchar.b.eptype = pdev->host.hc[hc_num].ep_type; - hcchar.b.mps = pdev->host.hc[hc_num].max_packet; - if (pdev->host.hc[hc_num].ep_type == HCCHAR_INTR) - { - hcchar.b.oddfrm = 1; - } - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32); - return status; -} - - -/** -* @brief USB_OTG_HC_StartXfer : Start transfer -* @param pdev : Selected device -* @param hc_num : channel number -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_HC_StartXfer(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_HCCHAR_TypeDef hcchar; - USB_OTG_HCTSIZn_TypeDef hctsiz; - USB_OTG_HNPTXSTS_TypeDef hnptxsts; - USB_OTG_HPTXSTS_TypeDef hptxsts; - USB_OTG_GINTMSK_TypeDef intmsk; - uint16_t len_words = 0; - - uint16_t num_packets; - uint16_t max_hc_pkt_count; - - max_hc_pkt_count = 256; - hctsiz.d32 = 0; - hcchar.d32 = 0; - intmsk.d32 = 0; - - /* Compute the expected number of packets associated to the transfer */ - if (pdev->host.hc[hc_num].xfer_len > 0) - { - num_packets = (pdev->host.hc[hc_num].xfer_len + \ - pdev->host.hc[hc_num].max_packet - 1) / pdev->host.hc[hc_num].max_packet; - - if (num_packets > max_hc_pkt_count) - { - num_packets = max_hc_pkt_count; - pdev->host.hc[hc_num].xfer_len = num_packets * \ - pdev->host.hc[hc_num].max_packet; - } - } - else - { - num_packets = 1; - } - if (pdev->host.hc[hc_num].ep_is_in) - { - pdev->host.hc[hc_num].xfer_len = num_packets * \ - pdev->host.hc[hc_num].max_packet; - } - /* Initialize the HCTSIZn register */ - hctsiz.b.xfersize = pdev->host.hc[hc_num].xfer_len; - hctsiz.b.pktcnt = num_packets; - hctsiz.b.pid = pdev->host.hc[hc_num].data_pid; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCTSIZ, hctsiz.d32); - - if (pdev->cfg.dma_enable == 1) - { - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCDMA, (unsigned int)pdev->host.hc[hc_num].xfer_buff); - } - - - hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR); - hcchar.b.oddfrm = USB_OTG_IsEvenFrame(pdev); - - /* Set host channel enable */ - hcchar.b.chen = 1; - hcchar.b.chdis = 0; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32); - - if (pdev->cfg.dma_enable == 0) /* Slave mode */ - { - if((pdev->host.hc[hc_num].ep_is_in == 0) && - (pdev->host.hc[hc_num].xfer_len > 0)) - { - switch(pdev->host.hc[hc_num].ep_type) - { - /* Non periodic transfer */ - case EP_TYPE_CTRL: - case EP_TYPE_BULK: - - hnptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS); - len_words = (pdev->host.hc[hc_num].xfer_len + 3) / 4; - - /* check if there is enough space in FIFO space */ - if(len_words > hnptxsts.b.nptxfspcavail) - { - /* need to process data in nptxfempty interrupt */ - intmsk.b.nptxfempty = 1; - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, intmsk.d32); - } - - break; - /* Periodic transfer */ - case EP_TYPE_INTR: - case EP_TYPE_ISOC: - hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS); - len_words = (pdev->host.hc[hc_num].xfer_len + 3) / 4; - /* check if there is enough space in FIFO space */ - if(len_words > hptxsts.b.ptxfspcavail) /* split the transfer */ - { - /* need to process data in ptxfempty interrupt */ - intmsk.b.ptxfempty = 1; - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, intmsk.d32); - } - break; - - default: - break; - } - - /* Write packet into the Tx FIFO. */ - USB_OTG_WritePacket(pdev, - pdev->host.hc[hc_num].xfer_buff , - hc_num, pdev->host.hc[hc_num].xfer_len); - } - } - return status; -} - - -/** -* @brief USB_OTG_HC_Halt : Halt channel -* @param pdev : Selected device -* @param hc_num : channel number -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_HC_Halt(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_HNPTXSTS_TypeDef nptxsts; - USB_OTG_HPTXSTS_TypeDef hptxsts; - USB_OTG_HCCHAR_TypeDef hcchar; - - nptxsts.d32 = 0; - hptxsts.d32 = 0; - hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR); - hcchar.b.chen = 1; - hcchar.b.chdis = 1; - - /* Check for space in the request queue to issue the halt. */ - if (hcchar.b.eptype == HCCHAR_CTRL || hcchar.b.eptype == HCCHAR_BULK) - { - nptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS); - if (nptxsts.b.nptxqspcavail == 0) - { - hcchar.b.chen = 0; - } - } - else - { - hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS); - if (hptxsts.b.ptxqspcavail == 0) - { - hcchar.b.chen = 0; - } - } - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32); - return status; -} - -/** -* @brief Issue a ping token -* @param None -* @retval : None -*/ -USB_OTG_STS USB_OTG_HC_DoPing(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_HCCHAR_TypeDef hcchar; - USB_OTG_HCTSIZn_TypeDef hctsiz; - - hctsiz.d32 = 0; - hctsiz.b.dopng = 1; - hctsiz.b.pktcnt = 1; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCTSIZ, hctsiz.d32); - - hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR); - hcchar.b.chen = 1; - hcchar.b.chdis = 0; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32); - return status; -} - -/** -* @brief Stop the device and clean up fifo's -* @param None -* @retval : None -*/ -void USB_OTG_StopHost(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_HCCHAR_TypeDef hcchar; - uint32_t i; - - USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HAINTMSK , 0); - USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HAINT, 0xFFFFFFFF); - /* Flush out any leftover queued requests. */ - - for (i = 0; i < pdev->cfg.host_channels; i++) - { - hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[i]->HCCHAR); - hcchar.b.chen = 0; - hcchar.b.chdis = 1; - hcchar.b.epdir = 0; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[i]->HCCHAR, hcchar.d32); - } - - /* Flush the FIFO */ - USB_OTG_FlushRxFifo(pdev); - USB_OTG_FlushTxFifo(pdev , 0x10 ); -} -#endif -#ifdef USE_DEVICE_MODE -/* PCD Core Layer */ - -/** -* @brief USB_OTG_InitDevSpeed :Initializes the DevSpd field of DCFG register -* depending the PHY type and the enumeration speed of the device. -* @param pdev : Selected device -* @retval : None -*/ -void USB_OTG_InitDevSpeed(USB_OTG_CORE_HANDLE *pdev , uint8_t speed) -{ - USB_OTG_DCFG_TypeDef dcfg; - - dcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCFG); - dcfg.b.devspd = speed; - USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCFG, dcfg.d32); -} - - -/** -* @brief USB_OTG_CoreInitDev : Initializes the USB_OTG controller registers -* for device mode -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_CoreInitDev (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DEPCTL_TypeDef depctl; - uint32_t i; - USB_OTG_DCFG_TypeDef dcfg; - USB_OTG_FSIZ_TypeDef nptxfifosize; - USB_OTG_FSIZ_TypeDef txfifosize; - USB_OTG_DIEPMSK_TypeDef msk; - USB_OTG_DTHRCTL_TypeDef dthrctl; - - depctl.d32 = 0; - dcfg.d32 = 0; - nptxfifosize.d32 = 0; - txfifosize.d32 = 0; - msk.d32 = 0; - - /* Restart the Phy Clock */ - USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, 0); - /* Device configuration register */ - dcfg.d32 = USB_OTG_READ_REG32( &pdev->regs.DREGS->DCFG); - dcfg.b.perfrint = DCFG_FRAME_INTERVAL_80; - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DCFG, dcfg.d32 ); - -#ifdef USB_OTG_FS_CORE - if(pdev->cfg.coreID == USB_OTG_FS_CORE_ID ) - { - - /* Set Full speed phy */ - USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_FULL); - - /* set Rx FIFO size */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_FS_SIZE); - - /* EP0 TX*/ - nptxfifosize.b.depth = TX0_FIFO_FS_SIZE; - nptxfifosize.b.startaddr = RX_FIFO_FS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32 ); - - - /* EP1 TX*/ - txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth; - txfifosize.b.depth = TX1_FIFO_FS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[0], txfifosize.d32 ); - - - /* EP2 TX*/ - txfifosize.b.startaddr += txfifosize.b.depth; - txfifosize.b.depth = TX2_FIFO_FS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[1], txfifosize.d32 ); - - - /* EP3 TX*/ - txfifosize.b.startaddr += txfifosize.b.depth; - txfifosize.b.depth = TX3_FIFO_FS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[2], txfifosize.d32 ); - } -#endif -#ifdef USB_OTG_HS_CORE - if(pdev->cfg.coreID == USB_OTG_HS_CORE_ID ) - { - - /* Set High speed phy */ - - if(pdev->cfg.phy_itface == USB_OTG_ULPI_PHY) - { - USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_HIGH); - } - else /* set High speed phy in Full speed mode */ - { - USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_HIGH_IN_FULL); - } - - /* set Rx FIFO size */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_HS_SIZE); - - /* EP0 TX*/ - nptxfifosize.b.depth = TX0_FIFO_HS_SIZE; - nptxfifosize.b.startaddr = RX_FIFO_HS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32 ); - - - /* EP1 TX*/ - txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth; - txfifosize.b.depth = TX1_FIFO_HS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[0], txfifosize.d32 ); - - - /* EP2 TX*/ - txfifosize.b.startaddr += txfifosize.b.depth; - txfifosize.b.depth = TX2_FIFO_HS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[1], txfifosize.d32 ); - - - /* EP3 TX*/ - txfifosize.b.startaddr += txfifosize.b.depth; - txfifosize.b.depth = TX3_FIFO_HS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[2], txfifosize.d32 ); - - /* EP4 TX*/ - txfifosize.b.startaddr += txfifosize.b.depth; - txfifosize.b.depth = TX4_FIFO_HS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[3], txfifosize.d32 ); - - - /* EP5 TX*/ - txfifosize.b.startaddr += txfifosize.b.depth; - txfifosize.b.depth = TX5_FIFO_HS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[4], txfifosize.d32 ); - } -#endif - /* Flush the FIFOs */ - USB_OTG_FlushTxFifo(pdev , 0x10); /* all Tx FIFOs */ - USB_OTG_FlushRxFifo(pdev); - /* Clear all pending Device Interrupts */ - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, 0 ); - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, 0 ); - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF ); - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, 0 ); - - for (i = 0; i < pdev->cfg.dev_endpoints; i++) - { - depctl.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[i]->DIEPCTL); - if (depctl.b.epena) - { - depctl.d32 = 0; - depctl.b.epdis = 1; - depctl.b.snak = 1; - } - else - { - depctl.d32 = 0; - } - USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPCTL, depctl.d32); - USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPTSIZ, 0); - USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF); - } - for (i = 0; i < pdev->cfg.dev_endpoints; i++) - { - USB_OTG_DEPCTL_TypeDef depctl; - depctl.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[i]->DOEPCTL); - if (depctl.b.epena) - { - depctl.d32 = 0; - depctl.b.epdis = 1; - depctl.b.snak = 1; - } - else - { - depctl.d32 = 0; - } - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPCTL, depctl.d32); - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPTSIZ, 0); - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF); - } - msk.d32 = 0; - msk.b.txfifoundrn = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPMSK, msk.d32, msk.d32); - - if (pdev->cfg.dma_enable == 1) - { - dthrctl.d32 = 0; - dthrctl.b.non_iso_thr_en = 1; - dthrctl.b.iso_thr_en = 1; - dthrctl.b.tx_thr_len = 64; - dthrctl.b.rx_thr_en = 1; - dthrctl.b.rx_thr_len = 64; - USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DTHRCTL, dthrctl.d32); - } - USB_OTG_EnableDevInt(pdev); - return status; -} - - -/** -* @brief USB_OTG_EnableDevInt : Enables the Device mode interrupts -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EnableDevInt(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_GINTMSK_TypeDef intmsk; - - intmsk.d32 = 0; - - /* Disable all interrupts. */ - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTMSK, 0); - /* Clear any pending interrupts */ - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, 0xBFFFFFFF); - /* Enable the common interrupts */ - USB_OTG_EnableCommonInt(pdev); - - if (pdev->cfg.dma_enable == 0) - { - intmsk.b.rxstsqlvl = 1; - } - - /* Enable interrupts matching to the Device mode ONLY */ - intmsk.b.usbsuspend = 1; - intmsk.b.usbreset = 1; - intmsk.b.enumdone = 1; - intmsk.b.inepintr = 1; - intmsk.b.outepintr = 1; - intmsk.b.sofintr = 1; - - intmsk.b.incomplisoin = 1; - intmsk.b.incomplisoout = 1; -#ifdef VBUS_SENSING_ENABLED - intmsk.b.sessreqintr = 1; - intmsk.b.otgintr = 1; -#endif - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, intmsk.d32); - return status; -} - - -/** -* @brief USB_OTG_GetDeviceSpeed -* Get the device speed from the device status register -* @param None -* @retval status -*/ -enum USB_OTG_SPEED USB_OTG_GetDeviceSpeed (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_DSTS_TypeDef dsts; - enum USB_OTG_SPEED speed = USB_SPEED_UNKNOWN; - - - dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); - - switch (dsts.b.enumspd) - { - case DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: - speed = USB_SPEED_HIGH; - break; - case DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ: - case DSTS_ENUMSPD_FS_PHY_48MHZ: - speed = USB_SPEED_FULL; - break; - - case DSTS_ENUMSPD_LS_PHY_6MHZ: - speed = USB_SPEED_LOW; - break; - } - - return speed; -} -/** -* @brief enables EP0 OUT to receive SETUP packets and configures EP0 -* for transmitting packets -* @param None -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EP0Activate(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DSTS_TypeDef dsts; - USB_OTG_DEPCTL_TypeDef diepctl; - USB_OTG_DCTL_TypeDef dctl; - - dctl.d32 = 0; - /* Read the Device Status and Endpoint 0 Control registers */ - dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); - diepctl.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[0]->DIEPCTL); - /* Set the MPS of the IN EP based on the enumeration speed */ - switch (dsts.b.enumspd) - { - case DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: - case DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ: - case DSTS_ENUMSPD_FS_PHY_48MHZ: - diepctl.b.mps = DEP0CTL_MPS_64; - break; - case DSTS_ENUMSPD_LS_PHY_6MHZ: - diepctl.b.mps = DEP0CTL_MPS_8; - break; - } - USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[0]->DIEPCTL, diepctl.d32); - dctl.b.cgnpinnak = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, dctl.d32); - return status; -} - - -/** -* @brief USB_OTG_EPActivate : Activates an EP -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EPActivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DEPCTL_TypeDef depctl; - USB_OTG_DAINT_TypeDef daintmsk; - __IO uint32_t *addr; - - - depctl.d32 = 0; - daintmsk.d32 = 0; - /* Read DEPCTLn register */ - if (ep->is_in == 1) - { - addr = &pdev->regs.INEP_REGS[ep->num]->DIEPCTL; - daintmsk.ep.in = 1 << ep->num; - } - else - { - addr = &pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL; - daintmsk.ep.out = 1 << ep->num; - } - /* If the EP is already active don't change the EP Control - * register. */ - depctl.d32 = USB_OTG_READ_REG32(addr); - if (!depctl.b.usbactep) - { - depctl.b.mps = ep->maxpacket; - depctl.b.eptype = ep->type; - depctl.b.txfnum = ep->tx_fifo_num; - depctl.b.setd0pid = 1; - depctl.b.usbactep = 1; - USB_OTG_WRITE_REG32(addr, depctl.d32); - } - /* Enable the Interrupt for this EP */ -#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED - if((ep->num == 1)&&(pdev->cfg.coreID == USB_OTG_HS_CORE_ID)) - { - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DEACHMSK, 0, daintmsk.d32); - } - else -#endif - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DAINTMSK, 0, daintmsk.d32); - return status; -} - - -/** -* @brief USB_OTG_EPDeactivate : Deactivates an EP -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EPDeactivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DEPCTL_TypeDef depctl; - USB_OTG_DAINT_TypeDef daintmsk; - __IO uint32_t *addr; - - depctl.d32 = 0; - daintmsk.d32 = 0; - /* Read DEPCTLn register */ - if (ep->is_in == 1) - { - addr = &pdev->regs.INEP_REGS[ep->num]->DIEPCTL; - daintmsk.ep.in = 1 << ep->num; - } - else - { - addr = &pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL; - daintmsk.ep.out = 1 << ep->num; - } - depctl.b.usbactep = 0; - USB_OTG_WRITE_REG32(addr, depctl.d32); - /* Disable the Interrupt for this EP */ - -#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED - if((ep->num == 1)&&(pdev->cfg.coreID == USB_OTG_HS_CORE_ID)) - { - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DEACHMSK, daintmsk.d32, 0); - } - else -#endif - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DAINTMSK, daintmsk.d32, 0); - return status; -} - - -/** -* @brief USB_OTG_EPStartXfer : Handle the setup for data xfer for an EP and -* starts the xfer -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EPStartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DEPCTL_TypeDef depctl; - USB_OTG_DEPXFRSIZ_TypeDef deptsiz; - USB_OTG_DSTS_TypeDef dsts; - uint32_t fifoemptymsk = 0; - - depctl.d32 = 0; - deptsiz.d32 = 0; - /* IN endpoint */ - if (ep->is_in == 1) - { - depctl.d32 = USB_OTG_READ_REG32(&(pdev->regs.INEP_REGS[ep->num]->DIEPCTL)); - deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.INEP_REGS[ep->num]->DIEPTSIZ)); - /* Zero Length Packet? */ - if (ep->xfer_len == 0) - { - deptsiz.b.xfersize = 0; - deptsiz.b.pktcnt = 1; - } - else - { - /* Program the transfer size and packet count - * as follows: xfersize = N * maxpacket + - * short_packet pktcnt = N + (short_packet - * exist ? 1 : 0) - */ - deptsiz.b.xfersize = ep->xfer_len; - deptsiz.b.pktcnt = (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket; - - if (ep->type == EP_TYPE_ISOC) - { - deptsiz.b.mc = 1; - } - } - USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPTSIZ, deptsiz.d32); - - if (pdev->cfg.dma_enable == 1) - { - USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPDMA, ep->dma_addr); - } - else - { - if (ep->type != EP_TYPE_ISOC) - { - /* Enable the Tx FIFO Empty Interrupt for this EP */ - if (ep->xfer_len > 0) - { - fifoemptymsk = 1 << ep->num; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, 0, fifoemptymsk); - } - } - } - - - if (ep->type == EP_TYPE_ISOC) - { - dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); - - if (((dsts.b.soffn)&0x1) == 0) - { - depctl.b.setd1pid = 1; - } - else - { - depctl.b.setd0pid = 1; - } - } - - /* EP enable, IN data in FIFO */ - depctl.b.cnak = 1; - depctl.b.epena = 1; - USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPCTL, depctl.d32); - - if (ep->type == EP_TYPE_ISOC) - { - USB_OTG_WritePacket(pdev, ep->xfer_buff, ep->num, ep->xfer_len); - } - } - else - { - /* OUT endpoint */ - depctl.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL)); - deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ)); - /* Program the transfer size and packet count as follows: - * pktcnt = N - * xfersize = N * maxpacket - */ - if (ep->xfer_len == 0) - { - deptsiz.b.xfersize = ep->maxpacket; - deptsiz.b.pktcnt = 1; - } - else - { - deptsiz.b.pktcnt = (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket; - deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket; - } - USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ, deptsiz.d32); - - if (pdev->cfg.dma_enable == 1) - { - USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPDMA, ep->dma_addr); - } - - if (ep->type == EP_TYPE_ISOC) - { - if (ep->even_odd_frame) - { - depctl.b.setd1pid = 1; - } - else - { - depctl.b.setd0pid = 1; - } - } - /* EP enable */ - depctl.b.cnak = 1; - depctl.b.epena = 1; - USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL, depctl.d32); - } - return status; -} - - -/** -* @brief USB_OTG_EP0StartXfer : Handle the setup for a data xfer for EP0 and -* starts the xfer -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EP0StartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DEPCTL_TypeDef depctl; - USB_OTG_DEP0XFRSIZ_TypeDef deptsiz; - USB_OTG_INEPREGS *in_regs; - uint32_t fifoemptymsk = 0; - - depctl.d32 = 0; - deptsiz.d32 = 0; - /* IN endpoint */ - if (ep->is_in == 1) - { - in_regs = pdev->regs.INEP_REGS[0]; - depctl.d32 = USB_OTG_READ_REG32(&in_regs->DIEPCTL); - deptsiz.d32 = USB_OTG_READ_REG32(&in_regs->DIEPTSIZ); - /* Zero Length Packet? */ - if (ep->xfer_len == 0) - { - deptsiz.b.xfersize = 0; - deptsiz.b.pktcnt = 1; - - } - else - { - if (ep->xfer_len > ep->maxpacket) - { - ep->xfer_len = ep->maxpacket; - deptsiz.b.xfersize = ep->maxpacket; - } - else - { - deptsiz.b.xfersize = ep->xfer_len; - } - deptsiz.b.pktcnt = 1; - } - USB_OTG_WRITE_REG32(&in_regs->DIEPTSIZ, deptsiz.d32); - - if (pdev->cfg.dma_enable == 1) - { - USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPDMA, ep->dma_addr); - } - - /* EP enable, IN data in FIFO */ - depctl.b.cnak = 1; - depctl.b.epena = 1; - USB_OTG_WRITE_REG32(&in_regs->DIEPCTL, depctl.d32); - - - - if (pdev->cfg.dma_enable == 0) - { - /* Enable the Tx FIFO Empty Interrupt for this EP */ - if (ep->xfer_len > 0) - { - { - fifoemptymsk |= 1 << ep->num; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, 0, fifoemptymsk); - } - } - } - } - else - { - /* OUT endpoint */ - depctl.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); - deptsiz.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ); - /* Program the transfer size and packet count as follows: - * xfersize = N * (maxpacket + 4 - (maxpacket % 4)) - * pktcnt = N */ - if (ep->xfer_len == 0) - { - deptsiz.b.xfersize = ep->maxpacket; - deptsiz.b.pktcnt = 1; - } - else - { - ep->xfer_len = ep->maxpacket; - deptsiz.b.xfersize = ep->maxpacket; - deptsiz.b.pktcnt = 1; - } - USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ, deptsiz.d32); - if (pdev->cfg.dma_enable == 1) - { - USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPDMA, ep->dma_addr); - } - /* EP enable */ - depctl.b.cnak = 1; - depctl.b.epena = 1; - USB_OTG_WRITE_REG32 (&(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL), depctl.d32); - - } - return status; -} - - -/** -* @brief USB_OTG_EPSetStall : Set the EP STALL -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EPSetStall(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DEPCTL_TypeDef depctl; - __IO uint32_t *depctl_addr; - - depctl.d32 = 0; - if (ep->is_in == 1) - { - depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL); - depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - /* set the disable and stall bits */ - if (depctl.b.epena) - { - depctl.b.epdis = 1; - } - depctl.b.stall = 1; - USB_OTG_WRITE_REG32(depctl_addr, depctl.d32); - } - else - { - depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); - depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - /* set the stall bit */ - depctl.b.stall = 1; - USB_OTG_WRITE_REG32(depctl_addr, depctl.d32); - } - return status; -} - - -/** -* @brief Clear the EP STALL -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EPClearStall(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DEPCTL_TypeDef depctl; - __IO uint32_t *depctl_addr; - - depctl.d32 = 0; - - if (ep->is_in == 1) - { - depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL); - } - else - { - depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); - } - depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - /* clear the stall bits */ - depctl.b.stall = 0; - if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK) - { - depctl.b.setd0pid = 1; /* DATA0 */ - } - USB_OTG_WRITE_REG32(depctl_addr, depctl.d32); - return status; -} - - -/** -* @brief USB_OTG_ReadDevAllOutEp_itr : returns OUT endpoint interrupt bits -* @param pdev : Selected device -* @retval OUT endpoint interrupt bits -*/ -uint32_t USB_OTG_ReadDevAllOutEp_itr(USB_OTG_CORE_HANDLE *pdev) -{ - uint32_t v; - v = USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINT); - v &= USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINTMSK); - return ((v & 0xffff0000) >> 16); -} - - -/** -* @brief USB_OTG_ReadDevOutEP_itr : returns Device OUT EP Interrupt register -* @param pdev : Selected device -* @param ep : end point number -* @retval Device OUT EP Interrupt register -*/ -uint32_t USB_OTG_ReadDevOutEP_itr(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum) -{ - uint32_t v; - v = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[epnum]->DOEPINT); - v &= USB_OTG_READ_REG32(&pdev->regs.DREGS->DOEPMSK); - return v; -} - - -/** -* @brief USB_OTG_ReadDevAllInEPItr : Get int status register -* @param pdev : Selected device -* @retval int status register -*/ -uint32_t USB_OTG_ReadDevAllInEPItr(USB_OTG_CORE_HANDLE *pdev) -{ - uint32_t v; - v = USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINT); - v &= USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINTMSK); - return (v & 0xffff); -} - -/** -* @brief configures EPO to receive SETUP packets -* @param None -* @retval : None -*/ -void USB_OTG_EP0_OutStart(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_DEP0XFRSIZ_TypeDef doeptsize0; - doeptsize0.d32 = 0; - doeptsize0.b.supcnt = 3; - doeptsize0.b.pktcnt = 1; - doeptsize0.b.xfersize = 8 * 3; - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPTSIZ, doeptsize0.d32 ); - - if (pdev->cfg.dma_enable == 1) - { - USB_OTG_DEPCTL_TypeDef doepctl; - doepctl.d32 = 0; - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPDMA, - (uint32_t)&pdev->dev.setup_packet); - - /* EP enable */ - doepctl.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[0]->DOEPCTL); - doepctl.b.epena = 1; - doepctl.d32 = 0x80008000; - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPCTL, doepctl.d32); - } -} - -/** -* @brief USB_OTG_RemoteWakeup : active remote wakeup signalling -* @param None -* @retval : None -*/ -void USB_OTG_ActiveRemoteWakeup(USB_OTG_CORE_HANDLE *pdev) -{ - - USB_OTG_DCTL_TypeDef dctl; - USB_OTG_DSTS_TypeDef dsts; - USB_OTG_PCGCCTL_TypeDef power; - - if (pdev->dev.DevRemoteWakeup) - { - dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); - if(dsts.b.suspsts == 1) - { - if(pdev->cfg.low_power) - { - /* un-gate USB Core clock */ - power.d32 = USB_OTG_READ_REG32(pdev->regs.PCGCCTL); - power.b.gatehclk = 0; - power.b.stoppclk = 0; - USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32); - } - /* active Remote wakeup signaling */ - dctl.d32 = 0; - dctl.b.rmtwkupsig = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, 0, dctl.d32); - USB_OTG_BSP_mDelay(5); - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, 0 ); - } - } -} - - -/** -* @brief USB_OTG_UngateClock : active USB Core clock -* @param None -* @retval : None -*/ -void USB_OTG_UngateClock(USB_OTG_CORE_HANDLE *pdev) -{ - if(pdev->cfg.low_power) - { - - USB_OTG_DSTS_TypeDef dsts; - USB_OTG_PCGCCTL_TypeDef power; - - dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); - - if(dsts.b.suspsts == 1) - { - /* un-gate USB Core clock */ - power.d32 = USB_OTG_READ_REG32(pdev->regs.PCGCCTL); - power.b.gatehclk = 0; - power.b.stoppclk = 0; - USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32); - - } - } -} - -/** -* @brief Stop the device and clean up fifo's -* @param None -* @retval : None -*/ -void USB_OTG_StopDevice(USB_OTG_CORE_HANDLE *pdev) -{ - uint32_t i; - - pdev->dev.device_status = 1; - - for (i = 0; i < pdev->cfg.dev_endpoints ; i++) - { - USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF); - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF); - } - - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, 0 ); - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, 0 ); - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, 0 ); - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF ); - - /* Flush the FIFO */ - USB_OTG_FlushRxFifo(pdev); - USB_OTG_FlushTxFifo(pdev , 0x10 ); -} - -/** -* @brief returns the EP Status -* @param pdev : Selected device -* ep : endpoint structure -* @retval : EP status -*/ - -uint32_t USB_OTG_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,USB_OTG_EP *ep) -{ - USB_OTG_DEPCTL_TypeDef depctl; - __IO uint32_t *depctl_addr; - uint32_t Status = 0; - - depctl.d32 = 0; - if (ep->is_in == 1) - { - depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL); - depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - - if (depctl.b.stall == 1) - Status = USB_OTG_EP_TX_STALL; - else if (depctl.b.naksts == 1) - Status = USB_OTG_EP_TX_NAK; - else - Status = USB_OTG_EP_TX_VALID; - - } - else - { - depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); - depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - if (depctl.b.stall == 1) - Status = USB_OTG_EP_RX_STALL; - else if (depctl.b.naksts == 1) - Status = USB_OTG_EP_RX_NAK; - else - Status = USB_OTG_EP_RX_VALID; - } - - /* Return the current status */ - return Status; -} - -/** -* @brief Set the EP Status -* @param pdev : Selected device -* Status : new Status -* ep : EP structure -* @retval : None -*/ -void USB_OTG_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep , uint32_t Status) -{ - USB_OTG_DEPCTL_TypeDef depctl; - __IO uint32_t *depctl_addr; - - depctl.d32 = 0; - - /* Process for IN endpoint */ - if (ep->is_in == 1) - { - depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL); - depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - - if (Status == USB_OTG_EP_TX_STALL) - { - USB_OTG_EPSetStall(pdev, ep); return; - } - else if (Status == USB_OTG_EP_TX_NAK) - depctl.b.snak = 1; - else if (Status == USB_OTG_EP_TX_VALID) - { - if (depctl.b.stall == 1) - { - ep->even_odd_frame = 0; - USB_OTG_EPClearStall(pdev, ep); - return; - } - depctl.b.cnak = 1; - depctl.b.usbactep = 1; - depctl.b.epena = 1; - } - else if (Status == USB_OTG_EP_TX_DIS) - depctl.b.usbactep = 0; - } - else /* Process for OUT endpoint */ - { - depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); - depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - - if (Status == USB_OTG_EP_RX_STALL) { - depctl.b.stall = 1; - } - else if (Status == USB_OTG_EP_RX_NAK) - depctl.b.snak = 1; - else if (Status == USB_OTG_EP_RX_VALID) - { - if (depctl.b.stall == 1) - { - ep->even_odd_frame = 0; - USB_OTG_EPClearStall(pdev, ep); - return; - } - depctl.b.cnak = 1; - depctl.b.usbactep = 1; - depctl.b.epena = 1; - } - else if (Status == USB_OTG_EP_RX_DIS) - { - depctl.b.usbactep = 0; - } - } - - USB_OTG_WRITE_REG32(depctl_addr, depctl.d32); -} - -#endif -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmusb/usb_core.h b/stm/stmusb/usb_core.h deleted file mode 100644 index c574665c5..000000000 --- a/stm/stmusb/usb_core.h +++ /dev/null @@ -1,417 +0,0 @@ -/** - ****************************************************************************** - * @file usb_core.h - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief Header of the Core Layer - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_CORE_H__ -#define __USB_CORE_H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_conf.h" -#include "usb_regs.h" -#include "usb_defines.h" - - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_CORE - * @brief usb otg driver core layer - * @{ - */ - - -/** @defgroup USB_CORE_Exported_Defines - * @{ - */ - -#define USB_OTG_EP0_IDLE 0 -#define USB_OTG_EP0_SETUP 1 -#define USB_OTG_EP0_DATA_IN 2 -#define USB_OTG_EP0_DATA_OUT 3 -#define USB_OTG_EP0_STATUS_IN 4 -#define USB_OTG_EP0_STATUS_OUT 5 -#define USB_OTG_EP0_STALL 6 - -#define USB_OTG_EP_TX_DIS 0x0000 -#define USB_OTG_EP_TX_STALL 0x0010 -#define USB_OTG_EP_TX_NAK 0x0020 -#define USB_OTG_EP_TX_VALID 0x0030 - -#define USB_OTG_EP_RX_DIS 0x0000 -#define USB_OTG_EP_RX_STALL 0x1000 -#define USB_OTG_EP_RX_NAK 0x2000 -#define USB_OTG_EP_RX_VALID 0x3000 -/** - * @} - */ -#define MAX_DATA_LENGTH 0x200 - -/** @defgroup USB_CORE_Exported_Types - * @{ - */ - - -typedef enum { - USB_OTG_OK = 0, - USB_OTG_FAIL -}USB_OTG_STS; - -typedef enum { - HC_IDLE = 0, - HC_XFRC, - HC_HALTED, - HC_NAK, - HC_NYET, - HC_STALL, - HC_XACTERR, - HC_BBLERR, - HC_DATATGLERR, -}HC_STATUS; - -typedef enum { - URB_IDLE = 0, - URB_DONE, - URB_NOTREADY, - URB_ERROR, - URB_STALL -}URB_STATE; - -typedef enum { - CTRL_START = 0, - CTRL_XFRC, - CTRL_HALTED, - CTRL_NAK, - CTRL_STALL, - CTRL_XACTERR, - CTRL_BBLERR, - CTRL_DATATGLERR, - CTRL_FAIL -}CTRL_STATUS; - - -typedef struct USB_OTG_hc -{ - uint8_t dev_addr ; - uint8_t ep_num; - uint8_t ep_is_in; - uint8_t speed; - uint8_t do_ping; - uint8_t ep_type; - uint16_t max_packet; - uint8_t data_pid; - uint8_t *xfer_buff; - uint32_t xfer_len; - uint32_t xfer_count; - uint8_t toggle_in; - uint8_t toggle_out; - uint32_t dma_addr; -} -USB_OTG_HC , *PUSB_OTG_HC; - -typedef struct USB_OTG_ep -{ - uint8_t num; - uint8_t is_in; - uint8_t is_stall; - uint8_t type; - uint8_t data_pid_start; - uint8_t even_odd_frame; - uint16_t tx_fifo_num; - uint32_t maxpacket; - /* transaction level variables*/ - uint8_t *xfer_buff; - uint32_t dma_addr; - uint32_t xfer_len; - uint32_t xfer_count; - /* Transfer level variables*/ - uint32_t rem_data_len; - uint32_t total_data_len; - uint32_t ctl_data_len; - -} - -USB_OTG_EP , *PUSB_OTG_EP; - - - -typedef struct USB_OTG_core_cfg -{ - uint8_t host_channels; - uint8_t dev_endpoints; - uint8_t speed; - uint8_t dma_enable; - uint16_t mps; - uint16_t TotalFifoSize; - uint8_t phy_itface; - uint8_t Sof_output; - uint8_t low_power; - uint8_t coreID; - -} -USB_OTG_CORE_CFGS, *PUSB_OTG_CORE_CFGS; - - - -typedef struct usb_setup_req { - - uint8_t bmRequest; - uint8_t bRequest; - uint16_t wValue; - uint16_t wIndex; - uint16_t wLength; -} USB_SETUP_REQ; - -typedef struct _Device_TypeDef -{ - uint8_t *(*GetDeviceDescriptor)( uint8_t speed , uint16_t *length); - uint8_t *(*GetLangIDStrDescriptor)( uint8_t speed , uint16_t *length); - uint8_t *(*GetManufacturerStrDescriptor)( uint8_t speed , uint16_t *length); - uint8_t *(*GetProductStrDescriptor)( uint8_t speed , uint16_t *length); - uint8_t *(*GetSerialStrDescriptor)( uint8_t speed , uint16_t *length); - uint8_t *(*GetConfigurationStrDescriptor)( uint8_t speed , uint16_t *length); - uint8_t *(*GetInterfaceStrDescriptor)( uint8_t speed , uint16_t *length); -} USBD_DEVICE, *pUSBD_DEVICE; - -//typedef struct USB_OTG_hPort -//{ -// void (*Disconnect) (void *phost); -// void (*Connect) (void *phost); -// uint8_t ConnStatus; -// uint8_t DisconnStatus; -// uint8_t ConnHandled; -// uint8_t DisconnHandled; -//} USB_OTG_hPort_TypeDef; - -typedef struct _Device_cb -{ - uint8_t (*Init) (void *pdev , uint8_t cfgidx); - uint8_t (*DeInit) (void *pdev , uint8_t cfgidx); - /* Control Endpoints*/ - uint8_t (*Setup) (void *pdev , USB_SETUP_REQ *req); - uint8_t (*EP0_TxSent) (void *pdev ); - uint8_t (*EP0_RxReady) (void *pdev ); - /* Class Specific Endpoints*/ - uint8_t (*DataIn) (void *pdev , uint8_t epnum); - uint8_t (*DataOut) (void *pdev , uint8_t epnum); - uint8_t (*SOF) (void *pdev); - uint8_t (*IsoINIncomplete) (void *pdev); - uint8_t (*IsoOUTIncomplete) (void *pdev); - - uint8_t *(*GetConfigDescriptor)( uint8_t speed , uint16_t *length); -#ifdef USB_OTG_HS_CORE - uint8_t *(*GetOtherConfigDescriptor)( uint8_t speed , uint16_t *length); -#endif - -#ifdef USB_SUPPORT_USER_STRING_DESC - uint8_t *(*GetUsrStrDescriptor)( uint8_t speed ,uint8_t index, uint16_t *length); -#endif - -} USBD_Class_cb_TypeDef; - - - -typedef struct _USBD_USR_PROP -{ - void (*Init)(void); - void (*DeviceReset)(uint8_t speed); - void (*DeviceConfigured)(void); - void (*DeviceSuspended)(void); - void (*DeviceResumed)(void); - - void (*DeviceConnected)(void); - void (*DeviceDisconnected)(void); - -} -USBD_Usr_cb_TypeDef; - -typedef struct _DCD -{ - uint8_t device_config; - uint8_t device_state; - uint8_t device_status; - uint8_t device_old_status; - uint8_t device_address; - uint8_t connection_status; - uint8_t test_mode; - uint32_t DevRemoteWakeup; - USB_OTG_EP in_ep [USB_OTG_MAX_TX_FIFOS]; - USB_OTG_EP out_ep [USB_OTG_MAX_TX_FIFOS]; - uint8_t setup_packet [8*3]; - USBD_Class_cb_TypeDef *class_cb; - USBD_Usr_cb_TypeDef *usr_cb; - USBD_DEVICE *usr_device; - uint8_t *pConfig_descriptor; - } -DCD_DEV , *DCD_PDEV; - - -typedef struct _HCD -{ - uint8_t Rx_Buffer [MAX_DATA_LENGTH]; - __IO uint32_t ConnSts; - __IO uint32_t ErrCnt[USB_OTG_MAX_TX_FIFOS]; - __IO uint32_t XferCnt[USB_OTG_MAX_TX_FIFOS]; - __IO HC_STATUS HC_Status[USB_OTG_MAX_TX_FIFOS]; - __IO URB_STATE URB_State[USB_OTG_MAX_TX_FIFOS]; - USB_OTG_HC hc [USB_OTG_MAX_TX_FIFOS]; - uint16_t channel [USB_OTG_MAX_TX_FIFOS]; -// USB_OTG_hPort_TypeDef *port_cb; -} -HCD_DEV , *USB_OTG_USBH_PDEV; - - -typedef struct _OTG -{ - uint8_t OTG_State; - uint8_t OTG_PrevState; - uint8_t OTG_Mode; -} -OTG_DEV , *USB_OTG_USBO_PDEV; - -typedef struct USB_OTG_handle -{ - USB_OTG_CORE_CFGS cfg; - USB_OTG_CORE_REGS regs; -#ifdef USE_DEVICE_MODE - DCD_DEV dev; -#endif -#ifdef USE_HOST_MODE - HCD_DEV host; -#endif -#ifdef USE_OTG_MODE - OTG_DEV otg; -#endif -} -USB_OTG_CORE_HANDLE , *PUSB_OTG_CORE_HANDLE; - -/** - * @} - */ - - -/** @defgroup USB_CORE_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USB_CORE_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_CORE_Exported_FunctionsPrototype - * @{ - */ - - -USB_OTG_STS USB_OTG_CoreInit (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_SelectCore (USB_OTG_CORE_HANDLE *pdev, - USB_OTG_CORE_ID_TypeDef coreID); -USB_OTG_STS USB_OTG_EnableGlobalInt (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_DisableGlobalInt(USB_OTG_CORE_HANDLE *pdev); -void* USB_OTG_ReadPacket (USB_OTG_CORE_HANDLE *pdev , - uint8_t *dest, - uint16_t len); -USB_OTG_STS USB_OTG_WritePacket (USB_OTG_CORE_HANDLE *pdev , - uint8_t *src, - uint8_t ch_ep_num, - uint16_t len); -USB_OTG_STS USB_OTG_FlushTxFifo (USB_OTG_CORE_HANDLE *pdev , uint32_t num); -USB_OTG_STS USB_OTG_FlushRxFifo (USB_OTG_CORE_HANDLE *pdev); - -uint32_t USB_OTG_ReadCoreItr (USB_OTG_CORE_HANDLE *pdev); -uint32_t USB_OTG_ReadOtgItr (USB_OTG_CORE_HANDLE *pdev); -uint8_t USB_OTG_IsHostMode (USB_OTG_CORE_HANDLE *pdev); -uint8_t USB_OTG_IsDeviceMode (USB_OTG_CORE_HANDLE *pdev); -uint32_t USB_OTG_GetMode (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_PhyInit (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_SetCurrentMode (USB_OTG_CORE_HANDLE *pdev, - uint8_t mode); - -/*********************** HOST APIs ********************************************/ -#ifdef USE_HOST_MODE -USB_OTG_STS USB_OTG_CoreInitHost (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_EnableHostInt (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_HC_Init (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num); -USB_OTG_STS USB_OTG_HC_Halt (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num); -USB_OTG_STS USB_OTG_HC_StartXfer (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num); -USB_OTG_STS USB_OTG_HC_DoPing (USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num); -uint32_t USB_OTG_ReadHostAllChannels_intr (USB_OTG_CORE_HANDLE *pdev); -uint32_t USB_OTG_ResetPort (USB_OTG_CORE_HANDLE *pdev); -uint32_t USB_OTG_ReadHPRT0 (USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_DriveVbus (USB_OTG_CORE_HANDLE *pdev, uint8_t state); -void USB_OTG_InitFSLSPClkSel (USB_OTG_CORE_HANDLE *pdev ,uint8_t freq); -uint8_t USB_OTG_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev) ; -void USB_OTG_StopHost (USB_OTG_CORE_HANDLE *pdev); -#endif -/********************* DEVICE APIs ********************************************/ -#ifdef USE_DEVICE_MODE -USB_OTG_STS USB_OTG_CoreInitDev (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_EnableDevInt (USB_OTG_CORE_HANDLE *pdev); -uint32_t USB_OTG_ReadDevAllInEPItr (USB_OTG_CORE_HANDLE *pdev); -enum USB_OTG_SPEED USB_OTG_GetDeviceSpeed (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_EP0Activate (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_EPActivate (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); -USB_OTG_STS USB_OTG_EPDeactivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); -USB_OTG_STS USB_OTG_EPStartXfer (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); -USB_OTG_STS USB_OTG_EP0StartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); -USB_OTG_STS USB_OTG_EPSetStall (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); -USB_OTG_STS USB_OTG_EPClearStall (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); -uint32_t USB_OTG_ReadDevAllOutEp_itr (USB_OTG_CORE_HANDLE *pdev); -uint32_t USB_OTG_ReadDevOutEP_itr (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum); -uint32_t USB_OTG_ReadDevAllInEPItr (USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_InitDevSpeed (USB_OTG_CORE_HANDLE *pdev , uint8_t speed); -uint8_t USBH_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_EP0_OutStart(USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_ActiveRemoteWakeup(USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_UngateClock(USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_StopDevice(USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep , uint32_t Status); -uint32_t USB_OTG_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,USB_OTG_EP *ep); -#endif -/** - * @} - */ - -#endif /* __USB_CORE_H__ */ - - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/stm/stmusb/usb_dcd.c b/stm/stmusb/usb_dcd.c deleted file mode 100644 index eac8c3371..000000000 --- a/stm/stmusb/usb_dcd.c +++ /dev/null @@ -1,478 +0,0 @@ -/** - ****************************************************************************** - * @file usb_dcd.c - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief Peripheral Device Interface Layer - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_dcd.h" -#include "usb_bsp.h" - - -/** @addtogroup USB_OTG_DRIVER -* @{ -*/ - -/** @defgroup USB_DCD -* @brief This file is the interface between EFSL ans Host mass-storage class -* @{ -*/ - - -/** @defgroup USB_DCD_Private_Defines -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_DCD_Private_TypesDefinitions -* @{ -*/ -/** -* @} -*/ - - - -/** @defgroup USB_DCD_Private_Macros -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_DCD_Private_Variables -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_DCD_Private_FunctionPrototypes -* @{ -*/ - -/** -* @} -*/ - - -/** @defgroup USB_DCD_Private_Functions -* @{ -*/ - - - -void DCD_Init(USB_OTG_CORE_HANDLE *pdev , - USB_OTG_CORE_ID_TypeDef coreID) -{ - uint32_t i; - USB_OTG_EP *ep; - - USB_OTG_SelectCore (pdev , coreID); - - pdev->dev.device_status = USB_OTG_DEFAULT; - pdev->dev.device_address = 0; - - /* Init ep structure */ - for (i = 0; i < pdev->cfg.dev_endpoints ; i++) - { - ep = &pdev->dev.in_ep[i]; - /* Init ep structure */ - ep->is_in = 1; - ep->num = i; - ep->tx_fifo_num = i; - /* Control until ep is actvated */ - ep->type = EP_TYPE_CTRL; - ep->maxpacket = USB_OTG_MAX_EP0_SIZE; - ep->xfer_buff = 0; - ep->xfer_len = 0; - } - - for (i = 0; i < pdev->cfg.dev_endpoints; i++) - { - ep = &pdev->dev.out_ep[i]; - /* Init ep structure */ - ep->is_in = 0; - ep->num = i; - ep->tx_fifo_num = i; - /* Control until ep is activated */ - ep->type = EP_TYPE_CTRL; - ep->maxpacket = USB_OTG_MAX_EP0_SIZE; - ep->xfer_buff = 0; - ep->xfer_len = 0; - } - - USB_OTG_DisableGlobalInt(pdev); - - /*Init the Core (common init.) */ - USB_OTG_CoreInit(pdev); - - - /* Force Device Mode*/ - USB_OTG_SetCurrentMode(pdev, DEVICE_MODE); - - /* Init Device */ - USB_OTG_CoreInitDev(pdev); - - - /* Enable USB Global interrupt */ - USB_OTG_EnableGlobalInt(pdev); -} - - -/** -* @brief Configure an EP -* @param pdev : Device instance -* @param epdesc : Endpoint Descriptor -* @retval : status -*/ -uint32_t DCD_EP_Open(USB_OTG_CORE_HANDLE *pdev , - uint8_t ep_addr, - uint16_t ep_mps, - uint8_t ep_type) -{ - USB_OTG_EP *ep; - - if ((ep_addr & 0x80) == 0x80) - { - ep = &pdev->dev.in_ep[ep_addr & 0x7F]; - } - else - { - ep = &pdev->dev.out_ep[ep_addr & 0x7F]; - } - ep->num = ep_addr & 0x7F; - - ep->is_in = (0x80 & ep_addr) != 0; - ep->maxpacket = ep_mps; - ep->type = ep_type; - if (ep->is_in) - { - /* Assign a Tx FIFO */ - ep->tx_fifo_num = ep->num; - } - /* Set initial data PID. */ - if (ep_type == USB_OTG_EP_BULK ) - { - ep->data_pid_start = 0; - } - USB_OTG_EPActivate(pdev , ep ); - return 0; -} -/** -* @brief called when an EP is disabled -* @param pdev: device instance -* @param ep_addr: endpoint address -* @retval : status -*/ -uint32_t DCD_EP_Close(USB_OTG_CORE_HANDLE *pdev , uint8_t ep_addr) -{ - USB_OTG_EP *ep; - - if ((ep_addr&0x80) == 0x80) - { - ep = &pdev->dev.in_ep[ep_addr & 0x7F]; - } - else - { - ep = &pdev->dev.out_ep[ep_addr & 0x7F]; - } - ep->num = ep_addr & 0x7F; - ep->is_in = (0x80 & ep_addr) != 0; - USB_OTG_EPDeactivate(pdev , ep ); - return 0; -} - - -/** -* @brief DCD_EP_PrepareRx -* @param pdev: device instance -* @param ep_addr: endpoint address -* @param pbuf: pointer to Rx buffer -* @param buf_len: data length -* @retval : status -*/ -uint32_t DCD_EP_PrepareRx( USB_OTG_CORE_HANDLE *pdev, - uint8_t ep_addr, - uint8_t *pbuf, - uint16_t buf_len) -{ - USB_OTG_EP *ep; - - ep = &pdev->dev.out_ep[ep_addr & 0x7F]; - - /*setup and start the Xfer */ - ep->xfer_buff = pbuf; - ep->xfer_len = buf_len; - ep->xfer_count = 0; - ep->is_in = 0; - ep->num = ep_addr & 0x7F; - - if (pdev->cfg.dma_enable == 1) - { - ep->dma_addr = (uint32_t)pbuf; - } - - if ( ep->num == 0 ) - { - USB_OTG_EP0StartXfer(pdev , ep); - } - else - { - USB_OTG_EPStartXfer(pdev, ep ); - } - return 0; -} - -/** -* @brief Transmit data over USB -* @param pdev: device instance -* @param ep_addr: endpoint address -* @param pbuf: pointer to Tx buffer -* @param buf_len: data length -* @retval : status -*/ -uint32_t DCD_EP_Tx ( USB_OTG_CORE_HANDLE *pdev, - uint8_t ep_addr, - uint8_t *pbuf, - uint32_t buf_len) -{ - USB_OTG_EP *ep; - - ep = &pdev->dev.in_ep[ep_addr & 0x7F]; - - /* Setup and start the Transfer */ - ep->is_in = 1; - ep->num = ep_addr & 0x7F; - ep->xfer_buff = pbuf; - ep->dma_addr = (uint32_t)pbuf; - ep->xfer_count = 0; - ep->xfer_len = buf_len; - - if ( ep->num == 0 ) - { - USB_OTG_EP0StartXfer(pdev , ep); - } - else - { - USB_OTG_EPStartXfer(pdev, ep ); - } - return 0; -} - - -/** -* @brief Stall an endpoint. -* @param pdev: device instance -* @param epnum: endpoint address -* @retval : status -*/ -uint32_t DCD_EP_Stall (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum) -{ - USB_OTG_EP *ep; - if ((0x80 & epnum) == 0x80) - { - ep = &pdev->dev.in_ep[epnum & 0x7F]; - } - else - { - ep = &pdev->dev.out_ep[epnum]; - } - - ep->is_stall = 1; - ep->num = epnum & 0x7F; - ep->is_in = ((epnum & 0x80) == 0x80); - - USB_OTG_EPSetStall(pdev , ep); - return (0); -} - - -/** -* @brief Clear stall condition on endpoints. -* @param pdev: device instance -* @param epnum: endpoint address -* @retval : status -*/ -uint32_t DCD_EP_ClrStall (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum) -{ - USB_OTG_EP *ep; - if ((0x80 & epnum) == 0x80) - { - ep = &pdev->dev.in_ep[epnum & 0x7F]; - } - else - { - ep = &pdev->dev.out_ep[epnum]; - } - - ep->is_stall = 0; - ep->num = epnum & 0x7F; - ep->is_in = ((epnum & 0x80) == 0x80); - - USB_OTG_EPClearStall(pdev , ep); - return (0); -} - - -/** -* @brief This Function flushes the FIFOs. -* @param pdev: device instance -* @param epnum: endpoint address -* @retval : status -*/ -uint32_t DCD_EP_Flush (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum) -{ - - if ((epnum & 0x80) == 0x80) - { - USB_OTG_FlushTxFifo(pdev, epnum & 0x7F); - } - else - { - USB_OTG_FlushRxFifo(pdev); - } - - return (0); -} - - -/** -* @brief This Function set USB device address -* @param pdev: device instance -* @param address: new device address -* @retval : status -*/ -void DCD_EP_SetAddress (USB_OTG_CORE_HANDLE *pdev, uint8_t address) -{ - USB_OTG_DCFG_TypeDef dcfg; - dcfg.d32 = 0; - dcfg.b.devaddr = address; - USB_OTG_MODIFY_REG32( &pdev->regs.DREGS->DCFG, 0, dcfg.d32); -} - -/** -* @brief Connect device (enable internal pull-up) -* @param pdev: device instance -* @retval : None -*/ -void DCD_DevConnect (USB_OTG_CORE_HANDLE *pdev) -{ -#ifndef USE_OTG_MODE - USB_OTG_DCTL_TypeDef dctl; - dctl.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCTL); - /* Connect device */ - dctl.b.sftdiscon = 0; - USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCTL, dctl.d32); - USB_OTG_BSP_mDelay(3); -#endif -} - - -/** -* @brief Disconnect device (disable internal pull-up) -* @param pdev: device instance -* @retval : None -*/ -void DCD_DevDisconnect (USB_OTG_CORE_HANDLE *pdev) -{ -#ifndef USE_OTG_MODE - USB_OTG_DCTL_TypeDef dctl; - dctl.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCTL); - /* Disconnect device for 3ms */ - dctl.b.sftdiscon = 1; - USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCTL, dctl.d32); - USB_OTG_BSP_mDelay(3); -#endif -} - - -/** -* @brief returns the EP Status -* @param pdev : Selected device -* epnum : endpoint address -* @retval : EP status -*/ - -uint32_t DCD_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,uint8_t epnum) -{ - USB_OTG_EP *ep; - uint32_t Status = 0; - - if ((0x80 & epnum) == 0x80) - { - ep = &pdev->dev.in_ep[epnum & 0x7F]; - } - else - { - ep = &pdev->dev.out_ep[epnum]; - } - - Status = USB_OTG_GetEPStatus(pdev ,ep); - - /* Return the current status */ - return Status; -} - -/** -* @brief Set the EP Status -* @param pdev : Selected device -* Status : new Status -* epnum : EP address -* @retval : None -*/ -void DCD_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum , uint32_t Status) -{ - USB_OTG_EP *ep; - - if ((0x80 & epnum) == 0x80) - { - ep = &pdev->dev.in_ep[epnum & 0x7F]; - } - else - { - ep = &pdev->dev.out_ep[epnum]; - } - - USB_OTG_SetEPStatus(pdev ,ep , Status); -} - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmusb/usb_dcd.h b/stm/stmusb/usb_dcd.h deleted file mode 100644 index 6922782a7..000000000 --- a/stm/stmusb/usb_dcd.h +++ /dev/null @@ -1,164 +0,0 @@ -/** - ****************************************************************************** - * @file usb_dcd.h - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief Peripheral Driver Header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __DCD_H__ -#define __DCD_H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_core.h" - - -/** @addtogroup USB_OTG_DRIVER -* @{ -*/ - -/** @defgroup USB_DCD -* @brief This file is the -* @{ -*/ - - -/** @defgroup USB_DCD_Exported_Defines -* @{ -*/ -#define USB_OTG_EP_CONTROL 0 -#define USB_OTG_EP_ISOC 1 -#define USB_OTG_EP_BULK 2 -#define USB_OTG_EP_INT 3 -#define USB_OTG_EP_MASK 3 - -/* Device Status */ -#define USB_OTG_DEFAULT 1 -#define USB_OTG_ADDRESSED 2 -#define USB_OTG_CONFIGURED 3 -#define USB_OTG_SUSPENDED 4 - -/** -* @} -*/ - - -/** @defgroup USB_DCD_Exported_Types -* @{ -*/ -/******************************************************************************** -Data structure type -********************************************************************************/ -typedef struct -{ - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bEndpointAddress; - uint8_t bmAttributes; - uint16_t wMaxPacketSize; - uint8_t bInterval; -} -EP_DESCRIPTOR , *PEP_DESCRIPTOR; - -/** -* @} -*/ - - -/** @defgroup USB_DCD_Exported_Macros -* @{ -*/ -/** -* @} -*/ - -/** @defgroup USB_DCD_Exported_Variables -* @{ -*/ -/** -* @} -*/ - -/** @defgroup USB_DCD_Exported_FunctionsPrototype -* @{ -*/ -/******************************************************************************** -EXPORTED FUNCTION FROM THE USB-OTG LAYER -********************************************************************************/ -void DCD_Init(USB_OTG_CORE_HANDLE *pdev , - USB_OTG_CORE_ID_TypeDef coreID); - -void DCD_DevConnect (USB_OTG_CORE_HANDLE *pdev); -void DCD_DevDisconnect (USB_OTG_CORE_HANDLE *pdev); -void DCD_EP_SetAddress (USB_OTG_CORE_HANDLE *pdev, - uint8_t address); -uint32_t DCD_EP_Open(USB_OTG_CORE_HANDLE *pdev , - uint8_t ep_addr, - uint16_t ep_mps, - uint8_t ep_type); - -uint32_t DCD_EP_Close (USB_OTG_CORE_HANDLE *pdev, - uint8_t ep_addr); - - -uint32_t DCD_EP_PrepareRx ( USB_OTG_CORE_HANDLE *pdev, - uint8_t ep_addr, - uint8_t *pbuf, - uint16_t buf_len); - -uint32_t DCD_EP_Tx (USB_OTG_CORE_HANDLE *pdev, - uint8_t ep_addr, - uint8_t *pbuf, - uint32_t buf_len); -uint32_t DCD_EP_Stall (USB_OTG_CORE_HANDLE *pdev, - uint8_t epnum); -uint32_t DCD_EP_ClrStall (USB_OTG_CORE_HANDLE *pdev, - uint8_t epnum); -uint32_t DCD_EP_Flush (USB_OTG_CORE_HANDLE *pdev, - uint8_t epnum); -uint32_t DCD_Handle_ISR(USB_OTG_CORE_HANDLE *pdev); - -uint32_t DCD_GetEPStatus(USB_OTG_CORE_HANDLE *pdev , - uint8_t epnum); - -void DCD_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , - uint8_t epnum , - uint32_t Status); - -/** -* @} -*/ - - -#endif //__DCD_H__ - - -/** -* @} -*/ - -/** -* @} -*/ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/stm/stmusb/usb_dcd_int.c b/stm/stmusb/usb_dcd_int.c deleted file mode 100644 index 4dd9ce839..000000000 --- a/stm/stmusb/usb_dcd_int.c +++ /dev/null @@ -1,879 +0,0 @@ -/** - ****************************************************************************** - * @file usb_dcd_int.c - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief Peripheral Device interrupt subroutines - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_dcd_int.h" -/** @addtogroup USB_OTG_DRIVER -* @{ -*/ - -/** @defgroup USB_DCD_INT -* @brief This file contains the interrupt subroutines for the Device mode. -* @{ -*/ - - -/** @defgroup USB_DCD_INT_Private_Defines -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_DCD_INT_Private_TypesDefinitions -* @{ -*/ -/** -* @} -*/ - - - -/** @defgroup USB_DCD_INT_Private_Macros -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_DCD_INT_Private_Variables -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_DCD_INT_Private_FunctionPrototypes -* @{ -*/ -/* static functions */ -static uint32_t DCD_ReadDevInEP (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum); - -/* Interrupt Handlers */ -static uint32_t DCD_HandleInEP_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t DCD_HandleOutEP_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t DCD_HandleSof_ISR(USB_OTG_CORE_HANDLE *pdev); - -static uint32_t DCD_HandleRxStatusQueueLevel_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t DCD_WriteEmptyTxFifo(USB_OTG_CORE_HANDLE *pdev , uint32_t epnum); - -static uint32_t DCD_HandleUsbReset_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t DCD_HandleEnumDone_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t DCD_HandleResume_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t DCD_HandleUSBSuspend_ISR(USB_OTG_CORE_HANDLE *pdev); - -static uint32_t DCD_IsoINIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t DCD_IsoOUTIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev); -#ifdef VBUS_SENSING_ENABLED -static uint32_t DCD_SessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t DCD_OTG_ISR(USB_OTG_CORE_HANDLE *pdev); -#endif - -/** -* @} -*/ - - -/** @defgroup USB_DCD_INT_Private_Functions -* @{ -*/ - - -#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED -/** -* @brief USBD_OTG_EP1OUT_ISR_Handler -* handles all USB Interrupts -* @param pdev: device instance -* @retval status -*/ -uint32_t USBD_OTG_EP1OUT_ISR_Handler (USB_OTG_CORE_HANDLE *pdev) -{ - - USB_OTG_DOEPINTn_TypeDef doepint; - USB_OTG_DEPXFRSIZ_TypeDef deptsiz; - - doepint.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[1]->DOEPINT); - doepint.d32&= USB_OTG_READ_REG32(&pdev->regs.DREGS->DOUTEP1MSK); - - /* Transfer complete */ - if ( doepint.b.xfercompl ) - { - /* Clear the bit in DOEPINTn for this interrupt */ - CLEAR_OUT_EP_INTR(1, xfercompl); - if (pdev->cfg.dma_enable == 1) - { - deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[1]->DOEPTSIZ)); - /*ToDo : handle more than one single MPS size packet */ - pdev->dev.out_ep[1].xfer_count = pdev->dev.out_ep[1].maxpacket - \ - deptsiz.b.xfersize; - } - /* Inform upper layer: data ready */ - /* RX COMPLETE */ - USBD_DCD_INT_fops->DataOutStage(pdev , 1); - - } - - /* Endpoint disable */ - if ( doepint.b.epdisabled ) - { - /* Clear the bit in DOEPINTn for this interrupt */ - CLEAR_OUT_EP_INTR(1, epdisabled); - } - - return 1; -} - -/** -* @brief USBD_OTG_EP1IN_ISR_Handler -* handles all USB Interrupts -* @param pdev: device instance -* @retval status -*/ -uint32_t USBD_OTG_EP1IN_ISR_Handler (USB_OTG_CORE_HANDLE *pdev) -{ - - USB_OTG_DIEPINTn_TypeDef diepint; - uint32_t fifoemptymsk, msk, emp; - - msk = USB_OTG_READ_REG32(&pdev->regs.DREGS->DINEP1MSK); - emp = USB_OTG_READ_REG32(&pdev->regs.DREGS->DIEPEMPMSK); - msk |= ((emp >> 1 ) & 0x1) << 7; - diepint.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[1]->DIEPINT) & msk; - - if ( diepint.b.xfercompl ) - { - fifoemptymsk = 0x1 << 1; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, fifoemptymsk, 0); - CLEAR_IN_EP_INTR(1, xfercompl); - /* TX COMPLETE */ - USBD_DCD_INT_fops->DataInStage(pdev , 1); - } - if ( diepint.b.epdisabled ) - { - CLEAR_IN_EP_INTR(1, epdisabled); - } - if ( diepint.b.timeout ) - { - CLEAR_IN_EP_INTR(1, timeout); - } - if (diepint.b.intktxfemp) - { - CLEAR_IN_EP_INTR(1, intktxfemp); - } - if (diepint.b.inepnakeff) - { - CLEAR_IN_EP_INTR(1, inepnakeff); - } - if (diepint.b.emptyintr) - { - DCD_WriteEmptyTxFifo(pdev , 1); - CLEAR_IN_EP_INTR(1, emptyintr); - } - return 1; -} -#endif - -/** -* @brief STM32_USBF_OTG_ISR_Handler -* handles all USB Interrupts -* @param pdev: device instance -* @retval status -*/ -uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintr_status; - uint32_t retval = 0; - - if (USB_OTG_IsDeviceMode(pdev)) /* ensure that we are in device mode */ - { - gintr_status.d32 = USB_OTG_ReadCoreItr(pdev); - if (!gintr_status.d32) /* avoid spurious interrupt */ - { - return 0; - } - - if (gintr_status.b.outepintr) - { - retval |= DCD_HandleOutEP_ISR(pdev); - } - - if (gintr_status.b.inepint) - { - retval |= DCD_HandleInEP_ISR(pdev); - } - - if (gintr_status.b.modemismatch) - { - USB_OTG_GINTSTS_TypeDef gintsts; - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.modemismatch = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); - } - - if (gintr_status.b.wkupintr) - { - retval |= DCD_HandleResume_ISR(pdev); - } - - if (gintr_status.b.usbsuspend) - { - retval |= DCD_HandleUSBSuspend_ISR(pdev); - } - if (gintr_status.b.sofintr) - { - retval |= DCD_HandleSof_ISR(pdev); - - } - - if (gintr_status.b.rxstsqlvl) - { - retval |= DCD_HandleRxStatusQueueLevel_ISR(pdev); - - } - - if (gintr_status.b.usbreset) - { - retval |= DCD_HandleUsbReset_ISR(pdev); - - } - if (gintr_status.b.enumdone) - { - retval |= DCD_HandleEnumDone_ISR(pdev); - } - - if (gintr_status.b.incomplisoin) - { - retval |= DCD_IsoINIncomplete_ISR(pdev); - } - - if (gintr_status.b.incomplisoout) - { - retval |= DCD_IsoOUTIncomplete_ISR(pdev); - } -#ifdef VBUS_SENSING_ENABLED - if (gintr_status.b.sessreqintr) - { - retval |= DCD_SessionRequest_ISR(pdev); - } - - if (gintr_status.b.otgintr) - { - retval |= DCD_OTG_ISR(pdev); - } -#endif - } - return retval; -} - -#ifdef VBUS_SENSING_ENABLED -/** -* @brief DCD_SessionRequest_ISR -* Indicates that the USB_OTG controller has detected a connection -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_SessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintsts; - USBD_DCD_INT_fops->DevConnected (pdev); - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.sessreqintr = 1; - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32); - return 1; -} - -/** -* @brief DCD_OTG_ISR -* Indicates that the USB_OTG controller has detected an OTG event: -* used to detect the end of session i.e. disconnection -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_OTG_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - - USB_OTG_GOTGINT_TypeDef gotgint; - - gotgint.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGINT); - - if (gotgint.b.sesenddet) - { - USBD_DCD_INT_fops->DevDisconnected (pdev); - } - /* Clear OTG interrupt */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGINT, gotgint.d32); - return 1; -} -#endif -/** -* @brief DCD_HandleResume_ISR -* Indicates that the USB_OTG controller has detected a resume or -* remote Wake-up sequence -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_HandleResume_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintsts; - USB_OTG_DCTL_TypeDef devctl; - USB_OTG_PCGCCTL_TypeDef power; - - if(pdev->cfg.low_power) - { - /* un-gate USB Core clock */ - power.d32 = USB_OTG_READ_REG32(pdev->regs.PCGCCTL); - power.b.gatehclk = 0; - power.b.stoppclk = 0; - USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32); - } - - /* Clear the Remote Wake-up Signaling */ - devctl.d32 = 0; - devctl.b.rmtwkupsig = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, devctl.d32, 0); - - /* Inform upper layer by the Resume Event */ - USBD_DCD_INT_fops->Resume (pdev); - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.wkupintr = 1; - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32); - return 1; -} - -/** -* @brief USB_OTG_HandleUSBSuspend_ISR -* Indicates that SUSPEND state has been detected on the USB -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_HandleUSBSuspend_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintsts; - USB_OTG_PCGCCTL_TypeDef power; - USB_OTG_DSTS_TypeDef dsts; - __IO uint8_t prev_status = 0; - - prev_status = pdev->dev.device_status; - USBD_DCD_INT_fops->Suspend (pdev); - - dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.usbsuspend = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); - - if((pdev->cfg.low_power) && (dsts.b.suspsts == 1) && - (pdev->dev.connection_status == 1) && - (prev_status == USB_OTG_CONFIGURED)) - { - /* switch-off the clocks */ - power.d32 = 0; - power.b.stoppclk = 1; - USB_OTG_MODIFY_REG32(pdev->regs.PCGCCTL, 0, power.d32); - - power.b.gatehclk = 1; - USB_OTG_MODIFY_REG32(pdev->regs.PCGCCTL, 0, power.d32); - - /* Request to enter Sleep mode after exit from current ISR */ - SCB->SCR |= (SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk); - } - return 1; -} - -/** -* @brief DCD_HandleInEP_ISR -* Indicates that an IN EP has a pending Interrupt -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_HandleInEP_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_DIEPINTn_TypeDef diepint; - - uint32_t ep_intr; - uint32_t epnum = 0; - uint32_t fifoemptymsk; - diepint.d32 = 0; - ep_intr = USB_OTG_ReadDevAllInEPItr(pdev); - - while ( ep_intr ) - { - if (ep_intr&0x1) /* In ITR */ - { - diepint.d32 = DCD_ReadDevInEP(pdev , epnum); /* Get In ITR status */ - if ( diepint.b.xfercompl ) - { - fifoemptymsk = 0x1 << epnum; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, fifoemptymsk, 0); - CLEAR_IN_EP_INTR(epnum, xfercompl); - /* TX COMPLETE */ - USBD_DCD_INT_fops->DataInStage(pdev , epnum); - - if (pdev->cfg.dma_enable == 1) - { - if((epnum == 0) && (pdev->dev.device_state == USB_OTG_EP0_STATUS_IN)) - { - /* prepare to rx more setup packets */ - USB_OTG_EP0_OutStart(pdev); - } - } - } - if ( diepint.b.timeout ) - { - CLEAR_IN_EP_INTR(epnum, timeout); - } - if (diepint.b.intktxfemp) - { - CLEAR_IN_EP_INTR(epnum, intktxfemp); - } - if (diepint.b.inepnakeff) - { - CLEAR_IN_EP_INTR(epnum, inepnakeff); - } - if ( diepint.b.epdisabled ) - { - CLEAR_IN_EP_INTR(epnum, epdisabled); - } - if (diepint.b.emptyintr) - { - - DCD_WriteEmptyTxFifo(pdev , epnum); - - CLEAR_IN_EP_INTR(epnum, emptyintr); - } - } - epnum++; - ep_intr >>= 1; - } - - return 1; -} - -/** -* @brief DCD_HandleOutEP_ISR -* Indicates that an OUT EP has a pending Interrupt -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_HandleOutEP_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - uint32_t ep_intr; - USB_OTG_DOEPINTn_TypeDef doepint; - USB_OTG_DEPXFRSIZ_TypeDef deptsiz; - uint32_t epnum = 0; - - doepint.d32 = 0; - - /* Read in the device interrupt bits */ - ep_intr = USB_OTG_ReadDevAllOutEp_itr(pdev); - - while ( ep_intr ) - { - if (ep_intr&0x1) - { - - doepint.d32 = USB_OTG_ReadDevOutEP_itr(pdev, epnum); - - /* Transfer complete */ - if ( doepint.b.xfercompl ) - { - /* Clear the bit in DOEPINTn for this interrupt */ - CLEAR_OUT_EP_INTR(epnum, xfercompl); - if (pdev->cfg.dma_enable == 1) - { - deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[epnum]->DOEPTSIZ)); - /*ToDo : handle more than one single MPS size packet */ - pdev->dev.out_ep[epnum].xfer_count = pdev->dev.out_ep[epnum].maxpacket - \ - deptsiz.b.xfersize; - } - /* Inform upper layer: data ready */ - /* RX COMPLETE */ - USBD_DCD_INT_fops->DataOutStage(pdev , epnum); - - if (pdev->cfg.dma_enable == 1) - { - if((epnum == 0) && (pdev->dev.device_state == USB_OTG_EP0_STATUS_OUT)) - { - /* prepare to rx more setup packets */ - USB_OTG_EP0_OutStart(pdev); - } - } - } - /* Endpoint disable */ - if ( doepint.b.epdisabled ) - { - /* Clear the bit in DOEPINTn for this interrupt */ - CLEAR_OUT_EP_INTR(epnum, epdisabled); - } - /* Setup Phase Done (control EPs) */ - if ( doepint.b.setup ) - { - - /* inform the upper layer that a setup packet is available */ - /* SETUP COMPLETE */ - USBD_DCD_INT_fops->SetupStage(pdev); - CLEAR_OUT_EP_INTR(epnum, setup); - } - } - epnum++; - ep_intr >>= 1; - } - return 1; -} - -/** -* @brief DCD_HandleSof_ISR -* Handles the SOF Interrupts -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_HandleSof_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef GINTSTS; - - - USBD_DCD_INT_fops->SOF(pdev); - - /* Clear interrupt */ - GINTSTS.d32 = 0; - GINTSTS.b.sofintr = 1; - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, GINTSTS.d32); - - return 1; -} - -/** -* @brief DCD_HandleRxStatusQueueLevel_ISR -* Handles the Rx Status Queue Level Interrupt -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_HandleRxStatusQueueLevel_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTMSK_TypeDef int_mask; - USB_OTG_DRXSTS_TypeDef status; - USB_OTG_EP *ep; - - /* Disable the Rx Status Queue Level interrupt */ - int_mask.d32 = 0; - int_mask.b.rxstsqlvl = 1; - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, int_mask.d32, 0); - - /* Get the Status from the top of the FIFO */ - status.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRXSTSP ); - - ep = &pdev->dev.out_ep[status.b.epnum]; - - switch (status.b.pktsts) - { - case STS_GOUT_NAK: - break; - case STS_DATA_UPDT: - if (status.b.bcnt) - { - USB_OTG_ReadPacket(pdev,ep->xfer_buff, status.b.bcnt); - ep->xfer_buff += status.b.bcnt; - ep->xfer_count += status.b.bcnt; - } - break; - case STS_XFER_COMP: - break; - case STS_SETUP_COMP: - break; - case STS_SETUP_UPDT: - /* Copy the setup packet received in FIFO into the setup buffer in RAM */ - USB_OTG_ReadPacket(pdev , pdev->dev.setup_packet, 8); - ep->xfer_count += status.b.bcnt; - break; - default: - break; - } - - /* Enable the Rx Status Queue Level interrupt */ - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, int_mask.d32); - - return 1; -} - -/** -* @brief DCD_WriteEmptyTxFifo -* check FIFO for the next packet to be loaded -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_WriteEmptyTxFifo(USB_OTG_CORE_HANDLE *pdev, uint32_t epnum) -{ - USB_OTG_DTXFSTSn_TypeDef txstatus; - USB_OTG_EP *ep; - uint32_t len = 0; - uint32_t len32b; - txstatus.d32 = 0; - - ep = &pdev->dev.in_ep[epnum]; - - len = ep->xfer_len - ep->xfer_count; - - if (len > ep->maxpacket) - { - len = ep->maxpacket; - } - - len32b = (len + 3) / 4; - txstatus.d32 = USB_OTG_READ_REG32( &pdev->regs.INEP_REGS[epnum]->DTXFSTS); - - - - while (txstatus.b.txfspcavail > len32b && - ep->xfer_count < ep->xfer_len && - ep->xfer_len != 0) - { - /* Write the FIFO */ - len = ep->xfer_len - ep->xfer_count; - - if (len > ep->maxpacket) - { - len = ep->maxpacket; - } - len32b = (len + 3) / 4; - - USB_OTG_WritePacket (pdev , ep->xfer_buff, epnum, len); - - ep->xfer_buff += len; - ep->xfer_count += len; - - // this code turns off the "empty interrupt" - // without it the USB is subject to perpetual interrupts - // see my.st.com, "Yet another STM32F105/7 USB OTG driver issue (VCP device)" - // this code might also work if put in DCD_HandleInEP_ISR - if (ep->xfer_count >= ep->xfer_len) { - uint32_t fifoemptymsk = 1 << ep->num; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, fifoemptymsk, 0); - break; - } - - txstatus.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[epnum]->DTXFSTS); - } - - return 1; -} - -/** -* @brief DCD_HandleUsbReset_ISR -* This interrupt occurs when a USB Reset is detected -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_HandleUsbReset_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_DAINT_TypeDef daintmsk; - USB_OTG_DOEPMSK_TypeDef doepmsk; - USB_OTG_DIEPMSK_TypeDef diepmsk; - USB_OTG_DCFG_TypeDef dcfg; - USB_OTG_DCTL_TypeDef dctl; - USB_OTG_GINTSTS_TypeDef gintsts; - uint32_t i; - - dctl.d32 = 0; - daintmsk.d32 = 0; - doepmsk.d32 = 0; - diepmsk.d32 = 0; - dcfg.d32 = 0; - gintsts.d32 = 0; - - /* Clear the Remote Wake-up Signaling */ - dctl.b.rmtwkupsig = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, 0 ); - - /* Flush the Tx FIFO */ - USB_OTG_FlushTxFifo(pdev , 0 ); - - for (i = 0; i < pdev->cfg.dev_endpoints ; i++) - { - USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF); - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF); - } - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF ); - - daintmsk.ep.in = 1; - daintmsk.ep.out = 1; - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, daintmsk.d32 ); - - doepmsk.b.setup = 1; - doepmsk.b.xfercompl = 1; - doepmsk.b.epdisabled = 1; - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, doepmsk.d32 ); -#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOUTEP1MSK, doepmsk.d32 ); -#endif - diepmsk.b.xfercompl = 1; - diepmsk.b.timeout = 1; - diepmsk.b.epdisabled = 1; - - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, diepmsk.d32 ); -#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DINEP1MSK, diepmsk.d32 ); -#endif - /* Reset Device Address */ - dcfg.d32 = USB_OTG_READ_REG32( &pdev->regs.DREGS->DCFG); - dcfg.b.devaddr = 0; - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DCFG, dcfg.d32); - - - /* setup EP0 to receive SETUP packets */ - USB_OTG_EP0_OutStart(pdev); - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.usbreset = 1; - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32); - - /*Reset internal state machine */ - USBD_DCD_INT_fops->Reset(pdev); - return 1; -} - -/** -* @brief DCD_HandleEnumDone_ISR -* Read the device status register and set the device speed -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_HandleEnumDone_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintsts; - USB_OTG_GUSBCFG_TypeDef gusbcfg; - - USB_OTG_EP0Activate(pdev); - - /* Set USB turn-around time based on device speed and PHY interface. */ - gusbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG); - - /* Full or High speed */ - if ( USB_OTG_GetDeviceSpeed(pdev) == USB_SPEED_HIGH) - { - pdev->cfg.speed = USB_OTG_SPEED_HIGH; - pdev->cfg.mps = USB_OTG_HS_MAX_PACKET_SIZE ; - gusbcfg.b.usbtrdtim = 9; - } - else - { - pdev->cfg.speed = USB_OTG_SPEED_FULL; - pdev->cfg.mps = USB_OTG_FS_MAX_PACKET_SIZE ; - gusbcfg.b.usbtrdtim = 5; - } - - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, gusbcfg.d32); - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.enumdone = 1; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, gintsts.d32 ); - return 1; -} - - -/** -* @brief DCD_IsoINIncomplete_ISR -* handle the ISO IN incomplete interrupt -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_IsoINIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintsts; - - gintsts.d32 = 0; - - USBD_DCD_INT_fops->IsoINIncomplete (pdev); - - /* Clear interrupt */ - gintsts.b.incomplisoin = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); - - return 1; -} - -/** -* @brief DCD_IsoOUTIncomplete_ISR -* handle the ISO OUT incomplete interrupt -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_IsoOUTIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintsts; - - gintsts.d32 = 0; - - USBD_DCD_INT_fops->IsoOUTIncomplete (pdev); - - /* Clear interrupt */ - gintsts.b.incomplisoout = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); - return 1; -} -/** -* @brief DCD_ReadDevInEP -* Reads ep flags -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_ReadDevInEP (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum) -{ - uint32_t v, msk, emp; - msk = USB_OTG_READ_REG32(&pdev->regs.DREGS->DIEPMSK); - emp = USB_OTG_READ_REG32(&pdev->regs.DREGS->DIEPEMPMSK); - msk |= ((emp >> epnum) & 0x1) << 7; - v = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[epnum]->DIEPINT) & msk; - return v; -} - - - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmusb/usb_dcd_int.h b/stm/stmusb/usb_dcd_int.h deleted file mode 100644 index e2369e5dd..000000000 --- a/stm/stmusb/usb_dcd_int.h +++ /dev/null @@ -1,127 +0,0 @@ -/** - ****************************************************************************** - * @file usb_dcd_int.h - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief Peripheral Device Interface Layer - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef USB_DCD_INT_H__ -#define USB_DCD_INT_H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_dcd.h" - - - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_DCD_INT - * @brief This file is the - * @{ - */ - - -/** @defgroup USB_DCD_INT_Exported_Defines - * @{ - */ - -typedef struct _USBD_DCD_INT -{ - uint8_t (* DataOutStage) (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum); - uint8_t (* DataInStage) (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum); - uint8_t (* SetupStage) (USB_OTG_CORE_HANDLE *pdev); - uint8_t (* SOF) (USB_OTG_CORE_HANDLE *pdev); - uint8_t (* Reset) (USB_OTG_CORE_HANDLE *pdev); - uint8_t (* Suspend) (USB_OTG_CORE_HANDLE *pdev); - uint8_t (* Resume) (USB_OTG_CORE_HANDLE *pdev); - uint8_t (* IsoINIncomplete) (USB_OTG_CORE_HANDLE *pdev); - uint8_t (* IsoOUTIncomplete) (USB_OTG_CORE_HANDLE *pdev); - - uint8_t (* DevConnected) (USB_OTG_CORE_HANDLE *pdev); - uint8_t (* DevDisconnected) (USB_OTG_CORE_HANDLE *pdev); - -}USBD_DCD_INT_cb_TypeDef; - -extern USBD_DCD_INT_cb_TypeDef *USBD_DCD_INT_fops; -/** - * @} - */ - - -/** @defgroup USB_DCD_INT_Exported_Types - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_DCD_INT_Exported_Macros - * @{ - */ - -#define CLEAR_IN_EP_INTR(epnum,intr) \ - diepint.d32=0; \ - diepint.b.intr = 1; \ - USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[epnum]->DIEPINT,diepint.d32); - -#define CLEAR_OUT_EP_INTR(epnum,intr) \ - doepint.d32=0; \ - doepint.b.intr = 1; \ - USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[epnum]->DOEPINT,doepint.d32); - -/** - * @} - */ - -/** @defgroup USB_DCD_INT_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_DCD_INT_Exported_FunctionsPrototype - * @{ - */ - -uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev); - -/** - * @} - */ - - -#endif // USB_DCD_INT_H__ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/stm/stmusb/usb_defines.h b/stm/stmusb/usb_defines.h deleted file mode 100644 index 28e6d1687..000000000 --- a/stm/stmusb/usb_defines.h +++ /dev/null @@ -1,249 +0,0 @@ -/** - ****************************************************************************** - * @file usb_defines.h - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief Header of the Core Layer - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_DEF_H__ -#define __USB_DEF_H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_conf.h" - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_DEFINES - * @brief This file is the - * @{ - */ - - -/** @defgroup USB_DEFINES_Exported_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup _CORE_DEFINES_ - * @{ - */ - -#define USB_OTG_SPEED_PARAM_HIGH 0 -#define USB_OTG_SPEED_PARAM_HIGH_IN_FULL 1 -#define USB_OTG_SPEED_PARAM_FULL 3 - -#define USB_OTG_SPEED_HIGH 0 -#define USB_OTG_SPEED_FULL 1 - -#define USB_OTG_ULPI_PHY 1 -#define USB_OTG_EMBEDDED_PHY 2 - -/** - * @} - */ - - -/** @defgroup _GLOBAL_DEFINES_ - * @{ - */ -#define GAHBCFG_TXFEMPTYLVL_EMPTY 1 -#define GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0 -#define GAHBCFG_GLBINT_ENABLE 1 -#define GAHBCFG_INT_DMA_BURST_SINGLE 0 -#define GAHBCFG_INT_DMA_BURST_INCR 1 -#define GAHBCFG_INT_DMA_BURST_INCR4 3 -#define GAHBCFG_INT_DMA_BURST_INCR8 5 -#define GAHBCFG_INT_DMA_BURST_INCR16 7 -#define GAHBCFG_DMAENABLE 1 -#define GAHBCFG_TXFEMPTYLVL_EMPTY 1 -#define GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0 -#define GRXSTS_PKTSTS_IN 2 -#define GRXSTS_PKTSTS_IN_XFER_COMP 3 -#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5 -#define GRXSTS_PKTSTS_CH_HALTED 7 -/** - * @} - */ - - -/** @defgroup _OnTheGo_DEFINES_ - * @{ - */ -#define MODE_HNP_SRP_CAPABLE 0 -#define MODE_SRP_ONLY_CAPABLE 1 -#define MODE_NO_HNP_SRP_CAPABLE 2 -#define MODE_SRP_CAPABLE_DEVICE 3 -#define MODE_NO_SRP_CAPABLE_DEVICE 4 -#define MODE_SRP_CAPABLE_HOST 5 -#define MODE_NO_SRP_CAPABLE_HOST 6 -#define A_HOST 1 -#define A_SUSPEND 2 -#define A_PERIPHERAL 3 -#define B_PERIPHERAL 4 -#define B_HOST 5 -#define DEVICE_MODE 0 -#define HOST_MODE 1 -#define OTG_MODE 2 -/** - * @} - */ - - -/** @defgroup __DEVICE_DEFINES_ - * @{ - */ -#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0 -#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1 -#define DSTS_ENUMSPD_LS_PHY_6MHZ 2 -#define DSTS_ENUMSPD_FS_PHY_48MHZ 3 - -#define DCFG_FRAME_INTERVAL_80 0 -#define DCFG_FRAME_INTERVAL_85 1 -#define DCFG_FRAME_INTERVAL_90 2 -#define DCFG_FRAME_INTERVAL_95 3 - -#define DEP0CTL_MPS_64 0 -#define DEP0CTL_MPS_32 1 -#define DEP0CTL_MPS_16 2 -#define DEP0CTL_MPS_8 3 - -#define EP_SPEED_LOW 0 -#define EP_SPEED_FULL 1 -#define EP_SPEED_HIGH 2 - -#define EP_TYPE_CTRL 0 -#define EP_TYPE_ISOC 1 -#define EP_TYPE_BULK 2 -#define EP_TYPE_INTR 3 -#define EP_TYPE_MSK 3 - -#define STS_GOUT_NAK 1 -#define STS_DATA_UPDT 2 -#define STS_XFER_COMP 3 -#define STS_SETUP_COMP 4 -#define STS_SETUP_UPDT 6 -/** - * @} - */ - - -/** @defgroup __HOST_DEFINES_ - * @{ - */ -#define HC_PID_DATA0 0 -#define HC_PID_DATA2 1 -#define HC_PID_DATA1 2 -#define HC_PID_SETUP 3 - -#define HPRT0_PRTSPD_HIGH_SPEED 0 -#define HPRT0_PRTSPD_FULL_SPEED 1 -#define HPRT0_PRTSPD_LOW_SPEED 2 - -#define HCFG_30_60_MHZ 0 -#define HCFG_48_MHZ 1 -#define HCFG_6_MHZ 2 - -#define HCCHAR_CTRL 0 -#define HCCHAR_ISOC 1 -#define HCCHAR_BULK 2 -#define HCCHAR_INTR 3 - -#define MIN(a, b) (((a) < (b)) ? (a) : (b)) - -/** - * @} - */ - - -/** @defgroup USB_DEFINES_Exported_Types - * @{ - */ - -typedef enum -{ - USB_OTG_HS_CORE_ID = 0, - USB_OTG_FS_CORE_ID = 1 -}USB_OTG_CORE_ID_TypeDef; -/** - * @} - */ - - -/** @defgroup USB_DEFINES_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_DEFINES_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_DEFINES_Exported_FunctionsPrototype - * @{ - */ -/** - * @} - */ - - -/** @defgroup Internal_Macro's - * @{ - */ -#define USB_OTG_READ_REG32(reg) (*(__IO uint32_t *)reg) -#define USB_OTG_WRITE_REG32(reg,value) (*(__IO uint32_t *)reg = value) -#define USB_OTG_MODIFY_REG32(reg,clear_mask,set_mask) \ - USB_OTG_WRITE_REG32(reg, (((USB_OTG_READ_REG32(reg)) & ~clear_mask) | set_mask ) ) - -/******************************************************************************** - ENUMERATION TYPE -********************************************************************************/ -enum USB_OTG_SPEED { - USB_SPEED_UNKNOWN = 0, - USB_SPEED_LOW, - USB_SPEED_FULL, - USB_SPEED_HIGH -}; - -#endif //__USB_DEFINES__H__ - - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/stm/stmusb/usb_hcd.c b/stm/stmusb/usb_hcd.c deleted file mode 100644 index 060e12329..000000000 --- a/stm/stmusb/usb_hcd.c +++ /dev/null @@ -1,265 +0,0 @@ -/** - ****************************************************************************** - * @file usb_hcd.c - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief Host Interface Layer - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_core.h" -#include "usb_hcd.h" -#include "usb_conf.h" -#include "usb_bsp.h" - -#ifdef USE_HOST_MODE - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_HCD - * @brief This file is the interface between EFSL ans Host mass-storage class - * @{ - */ - - -/** @defgroup USB_HCD_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_HCD_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - - -/** @defgroup USB_HCD_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_HCD_Private_Variables - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_HCD_Private_FunctionPrototypes - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_HCD_Private_Functions - * @{ - */ - -/** - * @brief HCD_Init - * Initialize the HOST portion of the driver. - * @param pdev: Selected device - * @param base_address: OTG base address - * @retval Status - */ -uint32_t HCD_Init(USB_OTG_CORE_HANDLE *pdev , - USB_OTG_CORE_ID_TypeDef coreID) -{ - uint8_t i = 0; - pdev->host.ConnSts = 0; - - for (i= 0; i< USB_OTG_MAX_TX_FIFOS; i++) - { - pdev->host.ErrCnt[i] = 0; - pdev->host.XferCnt[i] = 0; - pdev->host.HC_Status[i] = HC_IDLE; - } - pdev->host.hc[0].max_packet = 8; - - USB_OTG_SelectCore(pdev, coreID); -#ifndef DUAL_ROLE_MODE_ENABLED - USB_OTG_DisableGlobalInt(pdev); - USB_OTG_CoreInit(pdev); - - /* Force Host Mode*/ - USB_OTG_SetCurrentMode(pdev , HOST_MODE); - USB_OTG_CoreInitHost(pdev); - USB_OTG_EnableGlobalInt(pdev); -#endif - - return 0; -} - - -/** - * @brief HCD_GetCurrentSpeed - * Get Current device Speed. - * @param pdev : Selected device - * @retval Status - */ - -uint32_t HCD_GetCurrentSpeed (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_HPRT0_TypeDef HPRT0; - HPRT0.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0); - - return HPRT0.b.prtspd; -} - -/** - * @brief HCD_ResetPort - * Issues the reset command to device - * @param pdev : Selected device - * @retval Status - */ -uint32_t HCD_ResetPort(USB_OTG_CORE_HANDLE *pdev) -{ - /* - Before starting to drive a USB reset, the application waits for the OTG - interrupt triggered by the debounce done bit (DBCDNE bit in OTG_FS_GOTGINT), - which indicates that the bus is stable again after the electrical debounce - caused by the attachment of a pull-up resistor on DP (FS) or DM (LS). - */ - - USB_OTG_ResetPort(pdev); - return 0; -} - -/** - * @brief HCD_IsDeviceConnected - * Check if the device is connected. - * @param pdev : Selected device - * @retval Device connection status. 1 -> connected and 0 -> disconnected - * - */ -uint32_t HCD_IsDeviceConnected(USB_OTG_CORE_HANDLE *pdev) -{ - return (pdev->host.ConnSts); -} - -/** - * @brief HCD_GetCurrentFrame - * This function returns the frame number for sof packet - * @param pdev : Selected device - * @retval Frame number - * - */ -uint32_t HCD_GetCurrentFrame (USB_OTG_CORE_HANDLE *pdev) -{ - return (USB_OTG_READ_REG32(&pdev->regs.HREGS->HFNUM) & 0xFFFF) ; -} - -/** - * @brief HCD_GetURB_State - * This function returns the last URBstate - * @param pdev: Selected device - * @retval URB_STATE - * - */ -URB_STATE HCD_GetURB_State (USB_OTG_CORE_HANDLE *pdev , uint8_t ch_num) -{ - return pdev->host.URB_State[ch_num] ; -} - -/** - * @brief HCD_GetXferCnt - * This function returns the last URBstate - * @param pdev: Selected device - * @retval No. of data bytes transferred - * - */ -uint32_t HCD_GetXferCnt (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num) -{ - return pdev->host.XferCnt[ch_num] ; -} - - - -/** - * @brief HCD_GetHCState - * This function returns the HC Status - * @param pdev: Selected device - * @retval HC_STATUS - * - */ -HC_STATUS HCD_GetHCState (USB_OTG_CORE_HANDLE *pdev , uint8_t ch_num) -{ - return pdev->host.HC_Status[ch_num] ; -} - -/** - * @brief HCD_HC_Init - * This function prepare a HC and start a transfer - * @param pdev: Selected device - * @param hc_num: Channel number - * @retval status - */ -uint32_t HCD_HC_Init (USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) -{ - return USB_OTG_HC_Init(pdev, hc_num); -} - -/** - * @brief HCD_SubmitRequest - * This function prepare a HC and start a transfer - * @param pdev: Selected device - * @param hc_num: Channel number - * @retval status - */ -uint32_t HCD_SubmitRequest (USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) -{ - - pdev->host.URB_State[hc_num] = URB_IDLE; - pdev->host.hc[hc_num].xfer_count = 0 ; - return USB_OTG_HC_StartXfer(pdev, hc_num); -} - - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -#endif // USE_HOST_MODE - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmusb/usb_hcd.h b/stm/stmusb/usb_hcd.h deleted file mode 100644 index ca2ba3c37..000000000 --- a/stm/stmusb/usb_hcd.h +++ /dev/null @@ -1,108 +0,0 @@ -/** - ****************************************************************************** - * @file usb_hcd.h - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief Host layer Header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_HCD_H__ -#define __USB_HCD_H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_regs.h" -#include "usb_core.h" - - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_HCD - * @brief This file is the - * @{ - */ - - -/** @defgroup USB_HCD_Exported_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_HCD_Exported_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_HCD_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_HCD_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_HCD_Exported_FunctionsPrototype - * @{ - */ -uint32_t HCD_Init (USB_OTG_CORE_HANDLE *pdev , - USB_OTG_CORE_ID_TypeDef coreID); -uint32_t HCD_HC_Init (USB_OTG_CORE_HANDLE *pdev , - uint8_t hc_num); -uint32_t HCD_SubmitRequest (USB_OTG_CORE_HANDLE *pdev , - uint8_t hc_num) ; -uint32_t HCD_GetCurrentSpeed (USB_OTG_CORE_HANDLE *pdev); -uint32_t HCD_ResetPort (USB_OTG_CORE_HANDLE *pdev); -uint32_t HCD_IsDeviceConnected (USB_OTG_CORE_HANDLE *pdev); -uint32_t HCD_GetCurrentFrame (USB_OTG_CORE_HANDLE *pdev) ; -URB_STATE HCD_GetURB_State (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num); -uint32_t HCD_GetXferCnt (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num); -HC_STATUS HCD_GetHCState (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num) ; -/** - * @} - */ - -#endif //__USB_HCD_H__ - - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/stm/stmusb/usb_hcd_int.c b/stm/stmusb/usb_hcd_int.c deleted file mode 100644 index 545818d46..000000000 --- a/stm/stmusb/usb_hcd_int.c +++ /dev/null @@ -1,863 +0,0 @@ -/** - ****************************************************************************** - * @file usb_hcd_int.c - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief Host driver interrupt subroutines - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_core.h" -#include "usb_defines.h" -#include "usb_hcd_int.h" - -#ifdef USE_HOST_MODE - -#if defined (__CC_ARM) /*!< ARM Compiler */ -#pragma O0 -#elif defined (__GNUC__) /*!< GNU Compiler */ -#pragma GCC optimize ("O0") -#elif defined (__TASKING__) /*!< TASKING Compiler */ -#pragma optimize=0 - -#endif /* __CC_ARM */ - -/** @addtogroup USB_OTG_DRIVER -* @{ -*/ - -/** @defgroup USB_HCD_INT -* @brief This file contains the interrupt subroutines for the Host mode. -* @{ -*/ - - -/** @defgroup USB_HCD_INT_Private_Defines -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_HCD_INT_Private_TypesDefinitions -* @{ -*/ -/** -* @} -*/ - - - -/** @defgroup USB_HCD_INT_Private_Macros -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_HCD_INT_Private_Variables -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_HCD_INT_Private_FunctionPrototypes -* @{ -*/ - -static uint32_t USB_OTG_USBH_handle_sof_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t USB_OTG_USBH_handle_port_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t USB_OTG_USBH_handle_hc_ISR (USB_OTG_CORE_HANDLE *pdev); -static uint32_t USB_OTG_USBH_handle_hc_n_In_ISR (USB_OTG_CORE_HANDLE *pdev , - uint32_t num); -static uint32_t USB_OTG_USBH_handle_hc_n_Out_ISR (USB_OTG_CORE_HANDLE *pdev , - uint32_t num); -static uint32_t USB_OTG_USBH_handle_rx_qlvl_ISR (USB_OTG_CORE_HANDLE *pdev); -static uint32_t USB_OTG_USBH_handle_nptxfempty_ISR (USB_OTG_CORE_HANDLE *pdev); -static uint32_t USB_OTG_USBH_handle_ptxfempty_ISR (USB_OTG_CORE_HANDLE *pdev); -static uint32_t USB_OTG_USBH_handle_Disconnect_ISR (USB_OTG_CORE_HANDLE *pdev); -static uint32_t USB_OTG_USBH_handle_IncompletePeriodicXfer_ISR (USB_OTG_CORE_HANDLE *pdev); - -/** -* @} -*/ - - -/** @defgroup USB_HCD_INT_Private_Functions -* @{ -*/ - -/** -* @brief HOST_Handle_ISR -* This function handles all USB Host Interrupts -* @param pdev: Selected device -* @retval status -*/ - -uint32_t USBH_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintsts; - uint32_t retval = 0; - - gintsts.d32 = 0; - - /* Check if HOST Mode */ - if (USB_OTG_IsHostMode(pdev)) - { - gintsts.d32 = USB_OTG_ReadCoreItr(pdev); - if (!gintsts.d32) - { - return 0; - } - - if (gintsts.b.sofintr) - { - retval |= USB_OTG_USBH_handle_sof_ISR (pdev); - } - - if (gintsts.b.rxstsqlvl) - { - retval |= USB_OTG_USBH_handle_rx_qlvl_ISR (pdev); - } - - if (gintsts.b.nptxfempty) - { - retval |= USB_OTG_USBH_handle_nptxfempty_ISR (pdev); - } - - if (gintsts.b.ptxfempty) - { - retval |= USB_OTG_USBH_handle_ptxfempty_ISR (pdev); - } - - if (gintsts.b.hcintr) - { - retval |= USB_OTG_USBH_handle_hc_ISR (pdev); - } - - if (gintsts.b.portintr) - { - retval |= USB_OTG_USBH_handle_port_ISR (pdev); - } - - if (gintsts.b.disconnect) - { - retval |= USB_OTG_USBH_handle_Disconnect_ISR (pdev); - - } - - if (gintsts.b.incomplisoout) - { - retval |= USB_OTG_USBH_handle_IncompletePeriodicXfer_ISR (pdev); - } - - - } - - return retval; -} - -/** -* @brief USB_OTG_USBH_handle_hc_ISR -* This function indicates that one or more host channels has a pending -* @param pdev: Selected device -* @retval status -*/ -static uint32_t USB_OTG_USBH_handle_hc_ISR (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_HAINT_TypeDef haint; - USB_OTG_HCCHAR_TypeDef hcchar; - uint32_t i = 0; - uint32_t retval = 0; - - /* Clear appropriate bits in HCINTn to clear the interrupt bit in - * GINTSTS */ - - haint.d32 = USB_OTG_ReadHostAllChannels_intr(pdev); - - for (i = 0; i < pdev->cfg.host_channels ; i++) - { - if (haint.b.chint & (1 << i)) - { - hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[i]->HCCHAR); - - if (hcchar.b.epdir) - { - retval |= USB_OTG_USBH_handle_hc_n_In_ISR (pdev, i); - } - else - { - retval |= USB_OTG_USBH_handle_hc_n_Out_ISR (pdev, i); - } - } - } - - return retval; -} - -/** -* @brief USB_OTG_otg_hcd_handle_sof_intr -* Handles the start-of-frame interrupt in host mode. -* @param pdev: Selected device -* @retval status -*/ -static uint32_t USB_OTG_USBH_handle_sof_ISR (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintsts; - gintsts.d32 = 0; - - USBH_HCD_INT_fops->SOF(pdev); - - /* Clear interrupt */ - gintsts.b.sofintr = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); - - return 1; -} - -/** -* @brief USB_OTG_USBH_handle_Disconnect_ISR -* Handles disconnect event. -* @param pdev: Selected device -* @retval status -*/ -static uint32_t USB_OTG_USBH_handle_Disconnect_ISR (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintsts; - - gintsts.d32 = 0; - - USBH_HCD_INT_fops->DevDisconnected(pdev); - - /* Clear interrupt */ - gintsts.b.disconnect = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); - - return 1; -} -#if defined ( __ICCARM__ ) /*!< IAR Compiler */ -#pragma optimize = none -#endif /* __CC_ARM */ -/** -* @brief USB_OTG_USBH_handle_nptxfempty_ISR -* Handles non periodic tx fifo empty. -* @param pdev: Selected device -* @retval status -*/ -static uint32_t USB_OTG_USBH_handle_nptxfempty_ISR (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTMSK_TypeDef intmsk; - USB_OTG_HNPTXSTS_TypeDef hnptxsts; - uint16_t len_words , len; - - hnptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS); - - len_words = (pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len + 3) / 4; - - while ((hnptxsts.b.nptxfspcavail > len_words)&& - (pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len != 0)) - { - - len = hnptxsts.b.nptxfspcavail * 4; - - if (len > pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len) - { - /* Last packet */ - len = pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len; - - intmsk.d32 = 0; - intmsk.b.nptxfempty = 1; - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, 0); - } - - len_words = (pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len + 3) / 4; - - USB_OTG_WritePacket (pdev , pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_buff, hnptxsts.b.nptxqtop.chnum, len); - - pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_buff += len; - pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len -= len; - pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_count += len; - - hnptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS); - } - - return 1; -} -#if defined ( __ICCARM__ ) /*!< IAR Compiler */ -#pragma optimize = none -#endif /* __CC_ARM */ -/** -* @brief USB_OTG_USBH_handle_ptxfempty_ISR -* Handles periodic tx fifo empty -* @param pdev: Selected device -* @retval status -*/ -static uint32_t USB_OTG_USBH_handle_ptxfempty_ISR (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTMSK_TypeDef intmsk; - USB_OTG_HPTXSTS_TypeDef hptxsts; - uint16_t len_words , len; - - hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS); - - len_words = (pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len + 3) / 4; - - while ((hptxsts.b.ptxfspcavail > len_words)&& - (pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len != 0)) - { - - len = hptxsts.b.ptxfspcavail * 4; - - if (len > pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len) - { - len = pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len; - /* Last packet */ - intmsk.d32 = 0; - intmsk.b.ptxfempty = 1; - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, 0); - } - - len_words = (pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len + 3) / 4; - - USB_OTG_WritePacket (pdev , pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_buff, hptxsts.b.ptxqtop.chnum, len); - - pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_buff += len; - pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len -= len; - pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_count += len; - - hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS); - } - - return 1; -} - -/** -* @brief USB_OTG_USBH_handle_port_ISR -* This function determines which interrupt conditions have occurred -* @param pdev: Selected device -* @retval status -*/ -#if defined ( __ICCARM__ ) /*!< IAR Compiler */ -#pragma optimize = none -#endif /* __CC_ARM */ -static uint32_t USB_OTG_USBH_handle_port_ISR (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_HPRT0_TypeDef hprt0; - USB_OTG_HPRT0_TypeDef hprt0_dup; - USB_OTG_HCFG_TypeDef hcfg; - uint32_t do_reset = 0; - uint32_t retval = 0; - - hcfg.d32 = 0; - hprt0.d32 = 0; - hprt0_dup.d32 = 0; - - hprt0.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0); - hprt0_dup.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0); - - /* Clear the interrupt bits in GINTSTS */ - - hprt0_dup.b.prtena = 0; - hprt0_dup.b.prtconndet = 0; - hprt0_dup.b.prtenchng = 0; - hprt0_dup.b.prtovrcurrchng = 0; - - /* Port Connect Detected */ - if (hprt0.b.prtconndet) - { - - hprt0_dup.b.prtconndet = 1; - USBH_HCD_INT_fops->DevConnected(pdev); - retval |= 1; - } - - /* Port Enable Changed */ - if (hprt0.b.prtenchng) - { - hprt0_dup.b.prtenchng = 1; - - if (hprt0.b.prtena == 1) - { - - USBH_HCD_INT_fops->DevConnected(pdev); - - if ((hprt0.b.prtspd == HPRT0_PRTSPD_LOW_SPEED) || - (hprt0.b.prtspd == HPRT0_PRTSPD_FULL_SPEED)) - { - - hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG); - - if (hprt0.b.prtspd == HPRT0_PRTSPD_LOW_SPEED) - { - USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HFIR, 6000 ); - if (hcfg.b.fslspclksel != HCFG_6_MHZ) - { - if(pdev->cfg.phy_itface == USB_OTG_EMBEDDED_PHY) - { - USB_OTG_InitFSLSPClkSel(pdev ,HCFG_6_MHZ ); - } - do_reset = 1; - } - } - else - { - - USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HFIR, 48000 ); - if (hcfg.b.fslspclksel != HCFG_48_MHZ) - { - USB_OTG_InitFSLSPClkSel(pdev ,HCFG_48_MHZ ); - do_reset = 1; - } - } - } - else - { - do_reset = 1; - } - } - } - /* Overcurrent Change Interrupt */ - if (hprt0.b.prtovrcurrchng) - { - hprt0_dup.b.prtovrcurrchng = 1; - retval |= 1; - } - if (do_reset) - { - USB_OTG_ResetPort(pdev); - } - /* Clear Port Interrupts */ - USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0_dup.d32); - - return retval; -} -#if defined ( __ICCARM__ ) /*!< IAR Compiler */ -#pragma optimize = none -#endif /* __CC_ARM */ -/** -* @brief USB_OTG_USBH_handle_hc_n_Out_ISR -* Handles interrupt for a specific Host Channel -* @param pdev: Selected device -* @param hc_num: Channel number -* @retval status -*/ -uint32_t USB_OTG_USBH_handle_hc_n_Out_ISR (USB_OTG_CORE_HANDLE *pdev , uint32_t num) -{ - - USB_OTG_HCINTn_TypeDef hcint; - USB_OTG_HCINTMSK_TypeDef hcintmsk; - USB_OTG_HC_REGS *hcreg; - USB_OTG_HCCHAR_TypeDef hcchar; - - hcreg = pdev->regs.HC_REGS[num]; - hcint.d32 = USB_OTG_READ_REG32(&hcreg->HCINT); - hcintmsk.d32 = USB_OTG_READ_REG32(&hcreg->HCINTMSK); - hcint.d32 = hcint.d32 & hcintmsk.d32; - - hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[num]->HCCHAR); - - if (hcint.b.ahberr) - { - CLEAR_HC_INT(hcreg ,ahberr); - UNMASK_HOST_INT_CHH (num); - } - else if (hcint.b.ack) - { - CLEAR_HC_INT(hcreg , ack); - } - else if (hcint.b.frmovrun) - { - UNMASK_HOST_INT_CHH (num); - USB_OTG_HC_Halt(pdev, num); - CLEAR_HC_INT(hcreg ,frmovrun); - } - else if (hcint.b.xfercompl) - { - pdev->host.ErrCnt[num] = 0; - UNMASK_HOST_INT_CHH (num); - USB_OTG_HC_Halt(pdev, num); - CLEAR_HC_INT(hcreg , xfercompl); - pdev->host.HC_Status[num] = HC_XFRC; - } - - else if (hcint.b.stall) - { - CLEAR_HC_INT(hcreg , stall); - UNMASK_HOST_INT_CHH (num); - USB_OTG_HC_Halt(pdev, num); - pdev->host.HC_Status[num] = HC_STALL; - } - - else if (hcint.b.nak) - { - pdev->host.ErrCnt[num] = 0; - UNMASK_HOST_INT_CHH (num); - USB_OTG_HC_Halt(pdev, num); - CLEAR_HC_INT(hcreg , nak); - pdev->host.HC_Status[num] = HC_NAK; - } - - else if (hcint.b.xacterr) - { - UNMASK_HOST_INT_CHH (num); - USB_OTG_HC_Halt(pdev, num); - pdev->host.ErrCnt[num] ++; - pdev->host.HC_Status[num] = HC_XACTERR; - CLEAR_HC_INT(hcreg , xacterr); - } - else if (hcint.b.nyet) - { - pdev->host.ErrCnt[num] = 0; - UNMASK_HOST_INT_CHH (num); - USB_OTG_HC_Halt(pdev, num); - CLEAR_HC_INT(hcreg , nyet); - pdev->host.HC_Status[num] = HC_NYET; - } - else if (hcint.b.datatglerr) - { - - UNMASK_HOST_INT_CHH (num); - USB_OTG_HC_Halt(pdev, num); - CLEAR_HC_INT(hcreg , nak); - pdev->host.HC_Status[num] = HC_DATATGLERR; - - CLEAR_HC_INT(hcreg , datatglerr); - } - else if (hcint.b.chhltd) - { - MASK_HOST_INT_CHH (num); - - if(pdev->host.HC_Status[num] == HC_XFRC) - { - pdev->host.URB_State[num] = URB_DONE; - - if (hcchar.b.eptype == EP_TYPE_BULK) - { - pdev->host.hc[num].toggle_out ^= 1; - } - } - else if(pdev->host.HC_Status[num] == HC_NAK) - { - pdev->host.URB_State[num] = URB_NOTREADY; - } - else if(pdev->host.HC_Status[num] == HC_NYET) - { - if(pdev->host.hc[num].do_ping == 1) - { - USB_OTG_HC_DoPing(pdev, num); - } - pdev->host.URB_State[num] = URB_NOTREADY; - } - else if(pdev->host.HC_Status[num] == HC_STALL) - { - pdev->host.URB_State[num] = URB_STALL; - } - else if(pdev->host.HC_Status[num] == HC_XACTERR) - { - if (pdev->host.ErrCnt[num] == 3) - { - pdev->host.URB_State[num] = URB_ERROR; - pdev->host.ErrCnt[num] = 0; - } - } - CLEAR_HC_INT(hcreg , chhltd); - } - - - return 1; -} -#if defined ( __ICCARM__ ) /*!< IAR Compiler */ -#pragma optimize = none -#endif /* __CC_ARM */ -/** -* @brief USB_OTG_USBH_handle_hc_n_In_ISR -* Handles interrupt for a specific Host Channel -* @param pdev: Selected device -* @param hc_num: Channel number -* @retval status -*/ -uint32_t USB_OTG_USBH_handle_hc_n_In_ISR (USB_OTG_CORE_HANDLE *pdev , uint32_t num) -{ - USB_OTG_HCINTn_TypeDef hcint; - USB_OTG_HCINTMSK_TypeDef hcintmsk; - USB_OTG_HCCHAR_TypeDef hcchar; - USB_OTG_HCTSIZn_TypeDef hctsiz; - USB_OTG_HC_REGS *hcreg; - - - hcreg = pdev->regs.HC_REGS[num]; - hcint.d32 = USB_OTG_READ_REG32(&hcreg->HCINT); - hcintmsk.d32 = USB_OTG_READ_REG32(&hcreg->HCINTMSK); - hcint.d32 = hcint.d32 & hcintmsk.d32; - hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[num]->HCCHAR); - hcintmsk.d32 = 0; - - - if (hcint.b.ahberr) - { - CLEAR_HC_INT(hcreg ,ahberr); - UNMASK_HOST_INT_CHH (num); - } - else if (hcint.b.ack) - { - CLEAR_HC_INT(hcreg ,ack); - } - - else if (hcint.b.stall) - { - UNMASK_HOST_INT_CHH (num); - pdev->host.HC_Status[num] = HC_STALL; - CLEAR_HC_INT(hcreg , nak); /* Clear the NAK Condition */ - CLEAR_HC_INT(hcreg , stall); /* Clear the STALL Condition */ - hcint.b.nak = 0; /* NOTE: When there is a 'stall', reset also nak, - else, the pdev->host.HC_Status = HC_STALL - will be overwritten by 'nak' in code below */ - USB_OTG_HC_Halt(pdev, num); - } - else if (hcint.b.datatglerr) - { - - UNMASK_HOST_INT_CHH (num); - USB_OTG_HC_Halt(pdev, num); - CLEAR_HC_INT(hcreg , nak); - pdev->host.HC_Status[num] = HC_DATATGLERR; - CLEAR_HC_INT(hcreg , datatglerr); - } - - if (hcint.b.frmovrun) - { - UNMASK_HOST_INT_CHH (num); - USB_OTG_HC_Halt(pdev, num); - CLEAR_HC_INT(hcreg ,frmovrun); - } - - else if (hcint.b.xfercompl) - { - - if (pdev->cfg.dma_enable == 1) - { - hctsiz.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[num]->HCTSIZ); - pdev->host.XferCnt[num] = pdev->host.hc[num].xfer_len - hctsiz.b.xfersize; - } - - pdev->host.HC_Status[num] = HC_XFRC; - pdev->host.ErrCnt [num]= 0; - CLEAR_HC_INT(hcreg , xfercompl); - - if ((hcchar.b.eptype == EP_TYPE_CTRL)|| - (hcchar.b.eptype == EP_TYPE_BULK)) - { - UNMASK_HOST_INT_CHH (num); - USB_OTG_HC_Halt(pdev, num); - CLEAR_HC_INT(hcreg , nak); - pdev->host.hc[num].toggle_in ^= 1; - - } - else if(hcchar.b.eptype == EP_TYPE_INTR) - { - hcchar.b.oddfrm = 1; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[num]->HCCHAR, hcchar.d32); - pdev->host.URB_State[num] = URB_DONE; - } - - } - else if (hcint.b.chhltd) - { - MASK_HOST_INT_CHH (num); - - if(pdev->host.HC_Status[num] == HC_XFRC) - { - pdev->host.URB_State[num] = URB_DONE; - } - - else if (pdev->host.HC_Status[num] == HC_STALL) - { - pdev->host.URB_State[num] = URB_STALL; - } - - else if((pdev->host.HC_Status[num] == HC_XACTERR) || - (pdev->host.HC_Status[num] == HC_DATATGLERR)) - { - pdev->host.ErrCnt[num] = 0; - pdev->host.URB_State[num] = URB_ERROR; - - } - else if(hcchar.b.eptype == EP_TYPE_INTR) - { - pdev->host.hc[num].toggle_in ^= 1; - } - - CLEAR_HC_INT(hcreg , chhltd); - - } - else if (hcint.b.xacterr) - { - UNMASK_HOST_INT_CHH (num); - pdev->host.ErrCnt[num] ++; - pdev->host.HC_Status[num] = HC_XACTERR; - USB_OTG_HC_Halt(pdev, num); - CLEAR_HC_INT(hcreg , xacterr); - - } - else if (hcint.b.nak) - { - if(hcchar.b.eptype == EP_TYPE_INTR) - { - UNMASK_HOST_INT_CHH (num); - USB_OTG_HC_Halt(pdev, num); - } - else if ((hcchar.b.eptype == EP_TYPE_CTRL)|| - (hcchar.b.eptype == EP_TYPE_BULK)) - { - /* re-activate the channel */ - hcchar.b.chen = 1; - hcchar.b.chdis = 0; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[num]->HCCHAR, hcchar.d32); - } - pdev->host.HC_Status[num] = HC_NAK; - CLEAR_HC_INT(hcreg , nak); - } - - - return 1; - -} - -/** -* @brief USB_OTG_USBH_handle_rx_qlvl_ISR -* Handles the Rx Status Queue Level Interrupt -* @param pdev: Selected device -* @retval status -*/ -#if defined ( __ICCARM__ ) /*!< IAR Compiler */ -#pragma optimize = none -#endif /* __CC_ARM */ -static uint32_t USB_OTG_USBH_handle_rx_qlvl_ISR (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GRXFSTS_TypeDef grxsts; - USB_OTG_GINTMSK_TypeDef intmsk; - USB_OTG_HCTSIZn_TypeDef hctsiz; - USB_OTG_HCCHAR_TypeDef hcchar; - __IO uint8_t channelnum =0; - uint32_t count; - - /* Disable the Rx Status Queue Level interrupt */ - intmsk.d32 = 0; - intmsk.b.rxstsqlvl = 1; - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, 0); - - grxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GRXSTSP); - channelnum = grxsts.b.chnum; - hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[channelnum]->HCCHAR); - - switch (grxsts.b.pktsts) - { - case GRXSTS_PKTSTS_IN: - /* Read the data into the host buffer. */ - if ((grxsts.b.bcnt > 0) && (pdev->host.hc[channelnum].xfer_buff != (void *)0)) - { - - USB_OTG_ReadPacket(pdev, pdev->host.hc[channelnum].xfer_buff, grxsts.b.bcnt); - /*manage multiple Xfer */ - pdev->host.hc[grxsts.b.chnum].xfer_buff += grxsts.b.bcnt; - pdev->host.hc[grxsts.b.chnum].xfer_count += grxsts.b.bcnt; - - - count = pdev->host.hc[channelnum].xfer_count; - pdev->host.XferCnt[channelnum] = count; - - hctsiz.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[channelnum]->HCTSIZ); - if(hctsiz.b.pktcnt > 0) - { - /* re-activate the channel when more packets are expected */ - hcchar.b.chen = 1; - hcchar.b.chdis = 0; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[channelnum]->HCCHAR, hcchar.d32); - } - } - break; - - case GRXSTS_PKTSTS_IN_XFER_COMP: - - case GRXSTS_PKTSTS_DATA_TOGGLE_ERR: - case GRXSTS_PKTSTS_CH_HALTED: - default: - break; - } - - /* Enable the Rx Status Queue Level interrupt */ - intmsk.b.rxstsqlvl = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, 0, intmsk.d32); - return 1; -} - -/** -* @brief USB_OTG_USBH_handle_IncompletePeriodicXfer_ISR -* Handles the incomplete Periodic transfer Interrupt -* @param pdev: Selected device -* @retval status -*/ -#if defined ( __ICCARM__ ) /*!< IAR Compiler */ -#pragma optimize = none -#endif /* __CC_ARM */ -static uint32_t USB_OTG_USBH_handle_IncompletePeriodicXfer_ISR (USB_OTG_CORE_HANDLE *pdev) -{ - - USB_OTG_GINTSTS_TypeDef gintsts; - USB_OTG_HCCHAR_TypeDef hcchar; - - - - - hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[0]->HCCHAR); - hcchar.b.chen = 1; - hcchar.b.chdis = 1; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[0]->HCCHAR, hcchar.d32); - - gintsts.d32 = 0; - /* Clear interrupt */ - gintsts.b.incomplisoout = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); - - return 1; -} - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -#endif // USE_HOST_MODE - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/stm/stmusb/usb_hcd_int.h b/stm/stmusb/usb_hcd_int.h deleted file mode 100644 index 5bc5b8a88..000000000 --- a/stm/stmusb/usb_hcd_int.h +++ /dev/null @@ -1,141 +0,0 @@ -/** - ****************************************************************************** - * @file usb_hcd_int.h - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief Peripheral Device Interface Layer - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __HCD_INT_H__ -#define __HCD_INT_H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_hcd.h" - - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_HCD_INT - * @brief This file is the - * @{ - */ - - -/** @defgroup USB_HCD_INT_Exported_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_HCD_INT_Exported_Types - * @{ - */ - -typedef struct _USBH_HCD_INT -{ - uint8_t (* SOF) (USB_OTG_CORE_HANDLE *pdev); - uint8_t (* DevConnected) (USB_OTG_CORE_HANDLE *pdev); - uint8_t (* DevDisconnected) (USB_OTG_CORE_HANDLE *pdev); - -}USBH_HCD_INT_cb_TypeDef; - -extern USBH_HCD_INT_cb_TypeDef *USBH_HCD_INT_fops; -/** - * @} - */ - - -/** @defgroup USB_HCD_INT_Exported_Macros - * @{ - */ - -#define CLEAR_HC_INT(HC_REGS, intr) \ - {\ - USB_OTG_HCINTn_TypeDef hcint_clear; \ - hcint_clear.d32 = 0; \ - hcint_clear.b.intr = 1; \ - USB_OTG_WRITE_REG32(&((HC_REGS)->HCINT), hcint_clear.d32);\ - }\ - -#define MASK_HOST_INT_CHH(hc_num) { USB_OTG_HCINTMSK_TypeDef INTMSK; \ - INTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK); \ - INTMSK.b.chhltd = 0; \ - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK, INTMSK.d32);} - -#define UNMASK_HOST_INT_CHH(hc_num) { USB_OTG_HCINTMSK_TypeDef INTMSK; \ - INTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK); \ - INTMSK.b.chhltd = 1; \ - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK, INTMSK.d32);} - -#define MASK_HOST_INT_ACK(hc_num) { USB_OTG_HCINTMSK_TypeDef INTMSK; \ - INTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK); \ - INTMSK.b.ack = 0; \ - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK, GINTMSK.d32);} - -#define UNMASK_HOST_INT_ACK(hc_num) { USB_OTG_HCGINTMSK_TypeDef INTMSK; \ - INTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK); \ - INTMSK.b.ack = 1; \ - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK, INTMSK.d32);} - -/** - * @} - */ - -/** @defgroup USB_HCD_INT_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_HCD_INT_Exported_FunctionsPrototype - * @{ - */ -/* Callbacks handler */ -void ConnectCallback_Handler(USB_OTG_CORE_HANDLE *pdev); -void Disconnect_Callback_Handler(USB_OTG_CORE_HANDLE *pdev); -void Overcurrent_Callback_Handler(USB_OTG_CORE_HANDLE *pdev); -uint32_t USBH_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev); - -/** - * @} - */ - - - -#endif //__HCD_INT_H__ - - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/stm/stmusb/usb_otg.c b/stm/stmusb/usb_otg.c deleted file mode 100644 index bb421ae91..000000000 --- a/stm/stmusb/usb_otg.c +++ /dev/null @@ -1,418 +0,0 @@ -/** - ****************************************************************************** - * @file usb_otg.c - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief OTG Core Layer - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_defines.h" -#include "usb_regs.h" -#include "usb_core.h" -#include "usb_otg.h" - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_OTG - * @brief This file is the interface between EFSL ans Host mass-storage class - * @{ - */ - - -/** @defgroup USB_OTG_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_OTG_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - - -/** @defgroup USB_OTG_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_OTG_Private_Variables - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_OTG_Private_FunctionPrototypes - * @{ - */ - -static uint32_t USB_OTG_HandleOTG_ISR(USB_OTG_CORE_HANDLE *pdev); - -static uint32_t USB_OTG_HandleConnectorIDStatusChange_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t USB_OTG_HandleSessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t USB_OTG_Read_itr(USB_OTG_CORE_HANDLE *pdev); - -/** - * @} - */ - - -/** @defgroup USB_OTG_Private_Functions - * @{ - */ - - -/* OTG Interrupt Handler */ - - -/** - * @brief STM32_USBO_OTG_ISR_Handler - * - * @param None - * @retval : None - */ -uint32_t STM32_USBO_OTG_ISR_Handler(USB_OTG_CORE_HANDLE *pdev) -{ - uint32_t retval = 0; - USB_OTG_GINTSTS_TypeDef gintsts ; - gintsts.d32 = 0; - - gintsts.d32 = USB_OTG_Read_itr(pdev); - if (gintsts.d32 == 0) - { - return 0; - } - if (gintsts.b.otgintr) - { - retval |= USB_OTG_HandleOTG_ISR(pdev); - } - if (gintsts.b.conidstschng) - { - retval |= USB_OTG_HandleConnectorIDStatusChange_ISR(pdev); - } - if (gintsts.b.sessreqintr) - { - retval |= USB_OTG_HandleSessionRequest_ISR(pdev); - } - return retval; -} - - -/** - * @brief USB_OTG_Read_itr - * returns the Core Interrupt register - * @param None - * @retval : status - */ -static uint32_t USB_OTG_Read_itr(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintsts; - USB_OTG_GINTMSK_TypeDef gintmsk; - USB_OTG_GINTMSK_TypeDef gintmsk_common; - - - gintsts.d32 = 0; - gintmsk.d32 = 0; - gintmsk_common.d32 = 0; - - /* OTG interrupts */ - gintmsk_common.b.sessreqintr = 1; - gintmsk_common.b.conidstschng = 1; - gintmsk_common.b.otgintr = 1; - - gintsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTSTS); - gintmsk.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTMSK); - return ((gintsts.d32 & gintmsk.d32 ) & gintmsk_common.d32); -} - - -/** - * @brief USB_OTG_HandleOTG_ISR - * handles the OTG Interrupts - * @param None - * @retval : status - */ -static uint32_t USB_OTG_HandleOTG_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GOTGINT_TypeDef gotgint; - USB_OTG_GOTGCTL_TypeDef gotgctl; - - - gotgint.d32 = 0; - gotgctl.d32 = 0; - - gotgint.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGINT); - gotgctl.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGCTL); - - if (gotgint.b.sesenddet) - { - gotgctl.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGCTL); - - - if (USB_OTG_IsDeviceMode(pdev)) - { - - } - else if (USB_OTG_IsHostMode(pdev)) - { - - } - } - - /* ----> SRP SUCCESS or FAILURE INTERRUPT <---- */ - if (gotgint.b.sesreqsucstschng) - { - gotgctl.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGCTL); - if (gotgctl.b.sesreqscs) /* Session request success */ - { - if (USB_OTG_IsDeviceMode(pdev)) - { - - } - /* Clear Session Request */ - gotgctl.d32 = 0; - gotgctl.b.sesreq = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GOTGCTL, gotgctl.d32, 0); - } - else /* Session request failure */ - { - if (USB_OTG_IsDeviceMode(pdev)) - { - - } - } - } - /* ----> HNP SUCCESS or FAILURE INTERRUPT <---- */ - if (gotgint.b.hstnegsucstschng) - { - gotgctl.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGCTL); - - if (gotgctl.b.hstnegscs) /* Host negotiation success */ - { - if (USB_OTG_IsHostMode(pdev)) /* The core AUTOMATICALLY sets the Host mode */ - { - - } - } - else /* Host negotiation failure */ - { - - } - gotgint.b.hstnegsucstschng = 1; /* Ack "Host Negotiation Success Status Change" interrupt. */ - } - /* ----> HOST NEGOTIATION DETECTED INTERRUPT <---- */ - if (gotgint.b.hstnegdet) - { - if (USB_OTG_IsDeviceMode(pdev)) /* The core AUTOMATICALLY sets the Host mode */ - { - - } - else - { - - } - } - if (gotgint.b.adevtoutchng) - {} - if (gotgint.b.debdone) - { - USB_OTG_ResetPort(pdev); - } - /* Clear OTG INT */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGINT, gotgint.d32); - return 1; -} - - -/** - * @brief USB_OTG_HandleConnectorIDStatusChange_ISR - * handles the Connector ID Status Change Interrupt - * @param None - * @retval : status - */ -static uint32_t USB_OTG_HandleConnectorIDStatusChange_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTMSK_TypeDef gintmsk; - USB_OTG_GOTGCTL_TypeDef gotgctl; - USB_OTG_GINTSTS_TypeDef gintsts; - - gintsts.d32 = 0 ; - gintmsk.d32 = 0 ; - gotgctl.d32 = 0 ; - gintmsk.b.sofintr = 1; - - USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, gintmsk.d32, 0); - gotgctl.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGCTL); - - /* B-Device connector (Device Mode) */ - if (gotgctl.b.conidsts) - { - USB_OTG_DisableGlobalInt(pdev); - USB_OTG_CoreInitDev(pdev); - USB_OTG_EnableGlobalInt(pdev); - pdev->otg.OTG_State = B_PERIPHERAL; - } - else - { - USB_OTG_DisableGlobalInt(pdev); - USB_OTG_CoreInitHost(pdev); - USB_OTG_EnableGlobalInt(pdev); - pdev->otg.OTG_State = A_HOST; - } - /* Set flag and clear interrupt */ - gintsts.b.conidstschng = 1; - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32); - return 1; -} - - -/** - * @brief USB_OTG_HandleSessionRequest_ISR - * Initiating the Session Request Protocol - * @param None - * @retval : status - */ -static uint32_t USB_OTG_HandleSessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintsts; - USB_OTG_GOTGCTL_TypeDef gotgctl; - - - gotgctl.d32 = 0; - gintsts.d32 = 0; - - gotgctl.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GOTGCTL ); - if (USB_OTG_IsDeviceMode(pdev) && (gotgctl.b.bsesvld)) - { - } - else if (gotgctl.b.asesvld) - { - - } - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.sessreqintr = 1; - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32); - return 1; -} - - -/** - * @brief USB_OTG_InitiateSRP - * Initiate an srp session - * @param None - * @retval : None - */ -void USB_OTG_InitiateSRP(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GOTGCTL_TypeDef otgctl; - - otgctl.d32 = 0; - - otgctl.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GOTGCTL ); - if (otgctl.b.sesreq) - { - return; /* SRP in progress */ - } - otgctl.b.sesreq = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGCTL, otgctl.d32); -} - - -/** - * @brief USB_OTG_InitiateHNP - * Initiate HNP - * @param None - * @retval : None - */ -void USB_OTG_InitiateHNP(USB_OTG_CORE_HANDLE *pdev , uint8_t state, uint8_t mode) -{ - USB_OTG_GOTGCTL_TypeDef otgctl; - USB_OTG_HPRT0_TypeDef hprt0; - - otgctl.d32 = 0; - hprt0.d32 = 0; - - otgctl.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GOTGCTL ); - if (mode) - { /* Device mode */ - if (state) - { - - otgctl.b.devhnpen = 1; /* B-Dev has been enabled to perform HNP */ - otgctl.b.hnpreq = 1; /* Initiate an HNP req. to the connected USB host*/ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGCTL, otgctl.d32); - } - } - else - { /* Host mode */ - if (state) - { - otgctl.b.hstsethnpen = 1; /* A-Dev has enabled B-device for HNP */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGCTL, otgctl.d32); - /* Suspend the bus so that B-dev will disconnect indicating the initial condition for HNP to DWC_Core */ - hprt0.d32 = USB_OTG_ReadHPRT0(pdev); - hprt0.b.prtsusp = 1; /* The core clear this bit when disconnect interrupt generated (GINTSTS.DisconnInt = '1') */ - USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32); - } - } -} - - -/** - * @brief USB_OTG_GetCurrentState - * Return current OTG State - * @param None - * @retval : None - */ -uint32_t USB_OTG_GetCurrentState (USB_OTG_CORE_HANDLE *pdev) -{ - return pdev->otg.OTG_State; -} - - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmusb/usb_otg.h b/stm/stmusb/usb_otg.h deleted file mode 100644 index 2f378dc16..000000000 --- a/stm/stmusb/usb_otg.h +++ /dev/null @@ -1,99 +0,0 @@ -/** - ****************************************************************************** - * @file usb_otg.h - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief OTG Core Header - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_OTG__ -#define __USB_OTG__ - - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_OTG - * @brief This file is the - * @{ - */ - - -/** @defgroup USB_OTG_Exported_Defines - * @{ - */ - - -void USB_OTG_InitiateSRP(USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_InitiateHNP(USB_OTG_CORE_HANDLE *pdev, uint8_t state, uint8_t mode); -void USB_OTG_Switchback (USB_OTG_CORE_HANDLE *pdev); -uint32_t USB_OTG_GetCurrentState (USB_OTG_CORE_HANDLE *pdev); - -/** - * @} - */ - - -/** @defgroup USB_OTG_Exported_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_OTG_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_OTG_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_OTG_Exported_FunctionsPrototype - * @{ - */ -/** - * @} - */ - - -#endif //__USB_OTG__ - - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/stm/stmusb/usb_regs.h b/stm/stmusb/usb_regs.h deleted file mode 100644 index 323e87056..000000000 --- a/stm/stmusb/usb_regs.h +++ /dev/null @@ -1,1188 +0,0 @@ -/** - ****************************************************************************** - * @file usb_regs.h - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief hardware registers - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_OTG_REGS_H__ -#define __USB_OTG_REGS_H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_conf.h" - - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_REGS - * @brief This file is the - * @{ - */ - - -/** @defgroup USB_REGS_Exported_Defines - * @{ - */ - -#define USB_OTG_HS_BASE_ADDR 0x40040000 -#define USB_OTG_FS_BASE_ADDR 0x50000000 - -#define USB_OTG_CORE_GLOBAL_REGS_OFFSET 0x000 -#define USB_OTG_DEV_GLOBAL_REG_OFFSET 0x800 -#define USB_OTG_DEV_IN_EP_REG_OFFSET 0x900 -#define USB_OTG_EP_REG_OFFSET 0x20 -#define USB_OTG_DEV_OUT_EP_REG_OFFSET 0xB00 -#define USB_OTG_HOST_GLOBAL_REG_OFFSET 0x400 -#define USB_OTG_HOST_PORT_REGS_OFFSET 0x440 -#define USB_OTG_HOST_CHAN_REGS_OFFSET 0x500 -#define USB_OTG_CHAN_REGS_OFFSET 0x20 -#define USB_OTG_PCGCCTL_OFFSET 0xE00 -#define USB_OTG_DATA_FIFO_OFFSET 0x1000 -#define USB_OTG_DATA_FIFO_SIZE 0x1000 - - -#define USB_OTG_MAX_TX_FIFOS 15 - -#define USB_OTG_HS_MAX_PACKET_SIZE 512 -#define USB_OTG_FS_MAX_PACKET_SIZE 64 -#define USB_OTG_MAX_EP0_SIZE 64 -/** - * @} - */ - -/** @defgroup USB_REGS_Exported_Types - * @{ - */ - -/** @defgroup __USB_OTG_Core_register - * @{ - */ -typedef struct _USB_OTG_GREGS //000h -{ - __IO uint32_t GOTGCTL; /* USB_OTG Control and Status Register 000h*/ - __IO uint32_t GOTGINT; /* USB_OTG Interrupt Register 004h*/ - __IO uint32_t GAHBCFG; /* Core AHB Configuration Register 008h*/ - __IO uint32_t GUSBCFG; /* Core USB Configuration Register 00Ch*/ - __IO uint32_t GRSTCTL; /* Core Reset Register 010h*/ - __IO uint32_t GINTSTS; /* Core Interrupt Register 014h*/ - __IO uint32_t GINTMSK; /* Core Interrupt Mask Register 018h*/ - __IO uint32_t GRXSTSR; /* Receive Sts Q Read Register 01Ch*/ - __IO uint32_t GRXSTSP; /* Receive Sts Q Read & POP Register 020h*/ - __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/ - __IO uint32_t DIEPTXF0_HNPTXFSIZ; /* EP0 / Non Periodic Tx FIFO Size Register 028h*/ - __IO uint32_t HNPTXSTS; /* Non Periodic Tx FIFO/Queue Sts reg 02Ch*/ - uint32_t Reserved30[2]; /* Reserved 030h*/ - __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/ - __IO uint32_t CID; /* User ID Register 03Ch*/ - uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/ - __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/ - __IO uint32_t DIEPTXF[USB_OTG_MAX_TX_FIFOS];/* dev Periodic Transmit FIFO */ -} -USB_OTG_GREGS; -/** - * @} - */ - - -/** @defgroup __device_Registers - * @{ - */ -typedef struct _USB_OTG_DREGS // 800h -{ - __IO uint32_t DCFG; /* dev Configuration Register 800h*/ - __IO uint32_t DCTL; /* dev Control Register 804h*/ - __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/ - uint32_t Reserved0C; /* Reserved 80Ch*/ - __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/ - __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/ - __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/ - __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/ - uint32_t Reserved20; /* Reserved 820h*/ - uint32_t Reserved9; /* Reserved 824h*/ - __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/ - __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/ - __IO uint32_t DTHRCTL; /* dev thr 830h*/ - __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/ - __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/ - __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/ - uint32_t Reserved40; /* dedicated EP mask 840h*/ - __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/ - uint32_t Reserved44[15]; /* Reserved 844-87Ch*/ - __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/ -} -USB_OTG_DREGS; -/** - * @} - */ - - -/** @defgroup __IN_Endpoint-Specific_Register - * @{ - */ -typedef struct _USB_OTG_INEPREGS -{ - __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/ - uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/ - __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/ - uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/ - __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/ - __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/ - __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/ - uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/ -} -USB_OTG_INEPREGS; -/** - * @} - */ - - -/** @defgroup __OUT_Endpoint-Specific_Registers - * @{ - */ -typedef struct _USB_OTG_OUTEPREGS -{ - __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ - uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/ - __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ - uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/ - __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ - __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/ - uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/ -} -USB_OTG_OUTEPREGS; -/** - * @} - */ - - -/** @defgroup __Host_Mode_Register_Structures - * @{ - */ -typedef struct _USB_OTG_HREGS -{ - __IO uint32_t HCFG; /* Host Configuration Register 400h*/ - __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/ - __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/ - uint32_t Reserved40C; /* Reserved 40Ch*/ - __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/ - __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/ - __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/ -} -USB_OTG_HREGS; -/** - * @} - */ - - -/** @defgroup __Host_Channel_Specific_Registers - * @{ - */ -typedef struct _USB_OTG_HC_REGS -{ - __IO uint32_t HCCHAR; - __IO uint32_t HCSPLT; - __IO uint32_t HCINT; - __IO uint32_t HCINTMSK; - __IO uint32_t HCTSIZ; - __IO uint32_t HCDMA; - uint32_t Reserved[2]; -} -USB_OTG_HC_REGS; -/** - * @} - */ - - -/** @defgroup __otg_Core_registers - * @{ - */ -typedef struct USB_OTG_core_regs //000h -{ - USB_OTG_GREGS *GREGS; - USB_OTG_DREGS *DREGS; - USB_OTG_HREGS *HREGS; - USB_OTG_INEPREGS *INEP_REGS[USB_OTG_MAX_TX_FIFOS]; - USB_OTG_OUTEPREGS *OUTEP_REGS[USB_OTG_MAX_TX_FIFOS]; - USB_OTG_HC_REGS *HC_REGS[USB_OTG_MAX_TX_FIFOS]; - __IO uint32_t *HPRT0; - __IO uint32_t *DFIFO[USB_OTG_MAX_TX_FIFOS]; - __IO uint32_t *PCGCCTL; -} -USB_OTG_CORE_REGS , *PUSB_OTG_CORE_REGS; -typedef union _USB_OTG_GOTGCTL_TypeDef -{ - uint32_t d32; - struct - { -uint32_t sesreqscs : - 1; -uint32_t sesreq : - 1; -uint32_t Reserved2_7 : - 6; -uint32_t hstnegscs : - 1; -uint32_t hnpreq : - 1; -uint32_t hstsethnpen : - 1; -uint32_t devhnpen : - 1; -uint32_t Reserved12_15 : - 4; -uint32_t conidsts : - 1; -uint32_t dbct : - 1; -uint32_t asesvld : - 1; -uint32_t bsesvld : - 1; -uint32_t Reserved20_31 : - 12; - } - b; -} USB_OTG_GOTGCTL_TypeDef ; - -typedef union _USB_OTG_GOTGINT_TypeDef -{ - uint32_t d32; - struct - { -uint32_t Reserved0_1 : - 2; -uint32_t sesenddet : - 1; -uint32_t Reserved3_7 : - 5; -uint32_t sesreqsucstschng : - 1; -uint32_t hstnegsucstschng : - 1; -uint32_t reserver10_16 : - 7; -uint32_t hstnegdet : - 1; -uint32_t adevtoutchng : - 1; -uint32_t debdone : - 1; -uint32_t Reserved31_20 : - 12; - } - b; -} USB_OTG_GOTGINT_TypeDef ; -typedef union _USB_OTG_GAHBCFG_TypeDef -{ - uint32_t d32; - struct - { -uint32_t glblintrmsk : - 1; -uint32_t hburstlen : - 4; -uint32_t dmaenable : - 1; -uint32_t Reserved : - 1; -uint32_t nptxfemplvl_txfemplvl : - 1; -uint32_t ptxfemplvl : - 1; -uint32_t Reserved9_31 : - 23; - } - b; -} USB_OTG_GAHBCFG_TypeDef ; -typedef union _USB_OTG_GUSBCFG_TypeDef -{ - uint32_t d32; - struct - { -uint32_t toutcal : - 3; -uint32_t Reserved3_5 : - 3; -uint32_t physel : - 1; -uint32_t Reserved7 : - 1; -uint32_t srpcap : - 1; -uint32_t hnpcap : - 1; -uint32_t usbtrdtim : - 4; -uint32_t Reserved14 : - 1; -uint32_t phylpwrclksel : - 1; -uint32_t Reserved16 : - 1; -uint32_t ulpi_fsls : - 1; -uint32_t ulpi_auto_res : - 1; -uint32_t ulpi_clk_sus_m : - 1; -uint32_t ulpi_ext_vbus_drv : - 1; -uint32_t ulpi_int_vbus_ind : - 1; -uint32_t term_sel_dl_pulse : - 1; -uint32_t ulpi_ind_cpl : - 1; -uint32_t ulpi_passthrough : - 1; -uint32_t ulpi_protect_disable : - 1; -uint32_t Reserved26_28 : - 3; -uint32_t force_host : - 1; -uint32_t force_dev : - 1; -uint32_t corrupt_tx : - 1; - } - b; -} USB_OTG_GUSBCFG_TypeDef ; -typedef union _USB_OTG_GRSTCTL_TypeDef -{ - uint32_t d32; - struct - { -uint32_t csftrst : - 1; -uint32_t hsftrst : - 1; -uint32_t hstfrm : - 1; -uint32_t Reserved3 : - 1; -uint32_t rxfflsh : - 1; -uint32_t txfflsh : - 1; -uint32_t txfnum : - 5; -uint32_t Reserved11_29 : - 19; -uint32_t dmareq : - 1; -uint32_t ahbidle : - 1; - } - b; -} USB_OTG_GRSTCTL_TypeDef ; -typedef union _USB_OTG_GINTMSK_TypeDef -{ - uint32_t d32; - struct - { -uint32_t Reserved0 : - 1; -uint32_t modemismatch : - 1; -uint32_t otgintr : - 1; -uint32_t sofintr : - 1; -uint32_t rxstsqlvl : - 1; -uint32_t nptxfempty : - 1; -uint32_t ginnakeff : - 1; -uint32_t goutnakeff : - 1; -uint32_t Reserved8_9 : - 2; -uint32_t erlysuspend : - 1; -uint32_t usbsuspend : - 1; -uint32_t usbreset : - 1; -uint32_t enumdone : - 1; -uint32_t isooutdrop : - 1; -uint32_t eopframe : - 1; -uint32_t Reserved16 : - 1; -uint32_t epmismatch : - 1; -uint32_t inepintr : - 1; -uint32_t outepintr : - 1; -uint32_t incomplisoin : - 1; -uint32_t incomplisoout : - 1; -uint32_t Reserved22_23 : - 2; -uint32_t portintr : - 1; -uint32_t hcintr : - 1; -uint32_t ptxfempty : - 1; -uint32_t Reserved27 : - 1; -uint32_t conidstschng : - 1; -uint32_t disconnect : - 1; -uint32_t sessreqintr : - 1; -uint32_t wkupintr : - 1; - } - b; -} USB_OTG_GINTMSK_TypeDef ; -typedef union _USB_OTG_GINTSTS_TypeDef -{ - uint32_t d32; - struct - { -uint32_t curmode : - 1; -uint32_t modemismatch : - 1; -uint32_t otgintr : - 1; -uint32_t sofintr : - 1; -uint32_t rxstsqlvl : - 1; -uint32_t nptxfempty : - 1; -uint32_t ginnakeff : - 1; -uint32_t goutnakeff : - 1; -uint32_t Reserved8_9 : - 2; -uint32_t erlysuspend : - 1; -uint32_t usbsuspend : - 1; -uint32_t usbreset : - 1; -uint32_t enumdone : - 1; -uint32_t isooutdrop : - 1; -uint32_t eopframe : - 1; -uint32_t Reserved16_17 : - 2; -uint32_t inepint: - 1; -uint32_t outepintr : - 1; -uint32_t incomplisoin : - 1; -uint32_t incomplisoout : - 1; -uint32_t Reserved22_23 : - 2; -uint32_t portintr : - 1; -uint32_t hcintr : - 1; -uint32_t ptxfempty : - 1; -uint32_t Reserved27 : - 1; -uint32_t conidstschng : - 1; -uint32_t disconnect : - 1; -uint32_t sessreqintr : - 1; -uint32_t wkupintr : - 1; - } - b; -} USB_OTG_GINTSTS_TypeDef ; -typedef union _USB_OTG_DRXSTS_TypeDef -{ - uint32_t d32; - struct - { -uint32_t epnum : - 4; -uint32_t bcnt : - 11; -uint32_t dpid : - 2; -uint32_t pktsts : - 4; -uint32_t fn : - 4; -uint32_t Reserved : - 7; - } - b; -} USB_OTG_DRXSTS_TypeDef ; -typedef union _USB_OTG_GRXSTS_TypeDef -{ - uint32_t d32; - struct - { -uint32_t chnum : - 4; -uint32_t bcnt : - 11; -uint32_t dpid : - 2; -uint32_t pktsts : - 4; -uint32_t Reserved : - 11; - } - b; -} USB_OTG_GRXFSTS_TypeDef ; -typedef union _USB_OTG_FSIZ_TypeDef -{ - uint32_t d32; - struct - { -uint32_t startaddr : - 16; -uint32_t depth : - 16; - } - b; -} USB_OTG_FSIZ_TypeDef ; -typedef union _USB_OTG_HNPTXSTS_TypeDef -{ - uint32_t d32; - struct - { - uint32_t nptxfspcavail : - 16; - uint32_t nptxqspcavail : - 8; - struct - { - uint32_t terminate : - 1; - uint32_t token : - 2; - uint32_t chnum : - 4; - } nptxqtop; - uint32_t Reserved : - 1; - } - b; -} USB_OTG_HNPTXSTS_TypeDef ; -typedef union _USB_OTG_DTXFSTSn_TypeDef -{ - uint32_t d32; - struct - { -uint32_t txfspcavail : - 16; -uint32_t Reserved : - 16; - } - b; -} USB_OTG_DTXFSTSn_TypeDef ; - -typedef union _USB_OTG_GCCFG_TypeDef -{ - uint32_t d32; - struct - { -uint32_t Reserved_in : - 16; -uint32_t pwdn : - 1; -uint32_t Reserved_17 : - 1; -uint32_t vbussensingA : - 1; -uint32_t vbussensingB : - 1; -uint32_t sofouten : - 1; -uint32_t disablevbussensing : - 1; -uint32_t Reserved_out : - 10; - } - b; -} USB_OTG_GCCFG_TypeDef ; - -typedef union _USB_OTG_DCFG_TypeDef -{ - uint32_t d32; - struct - { -uint32_t devspd : - 2; -uint32_t nzstsouthshk : - 1; -uint32_t Reserved3 : - 1; -uint32_t devaddr : - 7; -uint32_t perfrint : - 2; -uint32_t Reserved12_31 : - 19; - } - b; -} USB_OTG_DCFG_TypeDef ; -typedef union _USB_OTG_DCTL_TypeDef -{ - uint32_t d32; - struct - { -uint32_t rmtwkupsig : - 1; -uint32_t sftdiscon : - 1; -uint32_t gnpinnaksts : - 1; -uint32_t goutnaksts : - 1; -uint32_t tstctl : - 3; -uint32_t sgnpinnak : - 1; -uint32_t cgnpinnak : - 1; -uint32_t sgoutnak : - 1; -uint32_t cgoutnak : - 1; -uint32_t poprg_done : - 1; -uint32_t Reserved : - 20; - } - b; -} USB_OTG_DCTL_TypeDef ; -typedef union _USB_OTG_DSTS_TypeDef -{ - uint32_t d32; - struct - { -uint32_t suspsts : - 1; -uint32_t enumspd : - 2; -uint32_t errticerr : - 1; -uint32_t Reserved4_7: - 4; -uint32_t soffn : - 14; -uint32_t Reserved22_31 : - 10; - } - b; -} USB_OTG_DSTS_TypeDef ; -typedef union _USB_OTG_DIEPINTn_TypeDef -{ - uint32_t d32; - struct - { -uint32_t xfercompl : - 1; -uint32_t epdisabled : - 1; -uint32_t Reserved2 : - 1; -uint32_t timeout : - 1; -uint32_t intktxfemp : - 1; -uint32_t Reserved5 : - 1; -uint32_t inepnakeff : - 1; -uint32_t emptyintr : - 1; -uint32_t txfifoundrn : - 1; -uint32_t Reserved14_31 : - 23; - } - b; -} USB_OTG_DIEPINTn_TypeDef ; -typedef union _USB_OTG_DIEPINTn_TypeDef USB_OTG_DIEPMSK_TypeDef ; -typedef union _USB_OTG_DOEPINTn_TypeDef -{ - uint32_t d32; - struct - { -uint32_t xfercompl : - 1; -uint32_t epdisabled : - 1; -uint32_t Reserved2 : - 1; -uint32_t setup : - 1; -uint32_t Reserved04_31 : - 28; - } - b; -} USB_OTG_DOEPINTn_TypeDef ; -typedef union _USB_OTG_DOEPINTn_TypeDef USB_OTG_DOEPMSK_TypeDef ; - -typedef union _USB_OTG_DAINT_TypeDef -{ - uint32_t d32; - struct - { -uint32_t in : - 16; -uint32_t out : - 16; - } - ep; -} USB_OTG_DAINT_TypeDef ; - -typedef union _USB_OTG_DTHRCTL_TypeDef -{ - uint32_t d32; - struct - { -uint32_t non_iso_thr_en : - 1; -uint32_t iso_thr_en : - 1; -uint32_t tx_thr_len : - 9; -uint32_t Reserved11_15 : - 5; -uint32_t rx_thr_en : - 1; -uint32_t rx_thr_len : - 9; -uint32_t Reserved26 : - 1; -uint32_t arp_en : - 1; -uint32_t Reserved28_31 : - 4; - } - b; -} USB_OTG_DTHRCTL_TypeDef ; -typedef union _USB_OTG_DEPCTL_TypeDef -{ - uint32_t d32; - struct - { -uint32_t mps : - 11; -uint32_t reserved : - 4; -uint32_t usbactep : - 1; -uint32_t dpid : - 1; -uint32_t naksts : - 1; -uint32_t eptype : - 2; -uint32_t snp : - 1; -uint32_t stall : - 1; -uint32_t txfnum : - 4; -uint32_t cnak : - 1; -uint32_t snak : - 1; -uint32_t setd0pid : - 1; -uint32_t setd1pid : - 1; -uint32_t epdis : - 1; -uint32_t epena : - 1; - } - b; -} USB_OTG_DEPCTL_TypeDef ; -typedef union _USB_OTG_DEPXFRSIZ_TypeDef -{ - uint32_t d32; - struct - { -uint32_t xfersize : - 19; -uint32_t pktcnt : - 10; -uint32_t mc : - 2; -uint32_t Reserved : - 1; - } - b; -} USB_OTG_DEPXFRSIZ_TypeDef ; -typedef union _USB_OTG_DEP0XFRSIZ_TypeDef -{ - uint32_t d32; - struct - { -uint32_t xfersize : - 7; -uint32_t Reserved7_18 : - 12; -uint32_t pktcnt : - 2; -uint32_t Reserved20_28 : - 9; -uint32_t supcnt : - 2; - uint32_t Reserved31; - } - b; -} USB_OTG_DEP0XFRSIZ_TypeDef ; -typedef union _USB_OTG_HCFG_TypeDef -{ - uint32_t d32; - struct - { -uint32_t fslspclksel : - 2; -uint32_t fslssupp : - 1; - } - b; -} USB_OTG_HCFG_TypeDef ; -typedef union _USB_OTG_HFRMINTRVL_TypeDef -{ - uint32_t d32; - struct - { -uint32_t frint : - 16; -uint32_t Reserved : - 16; - } - b; -} USB_OTG_HFRMINTRVL_TypeDef ; - -typedef union _USB_OTG_HFNUM_TypeDef -{ - uint32_t d32; - struct - { -uint32_t frnum : - 16; -uint32_t frrem : - 16; - } - b; -} USB_OTG_HFNUM_TypeDef ; -typedef union _USB_OTG_HPTXSTS_TypeDef -{ - uint32_t d32; - struct - { -uint32_t ptxfspcavail : - 16; -uint32_t ptxqspcavail : - 8; - struct - { - uint32_t terminate : - 1; - uint32_t token : - 2; - uint32_t chnum : - 4; - uint32_t odd_even : - 1; - } ptxqtop; - } - b; -} USB_OTG_HPTXSTS_TypeDef ; -typedef union _USB_OTG_HPRT0_TypeDef -{ - uint32_t d32; - struct - { -uint32_t prtconnsts : - 1; -uint32_t prtconndet : - 1; -uint32_t prtena : - 1; -uint32_t prtenchng : - 1; -uint32_t prtovrcurract : - 1; -uint32_t prtovrcurrchng : - 1; -uint32_t prtres : - 1; -uint32_t prtsusp : - 1; -uint32_t prtrst : - 1; -uint32_t Reserved9 : - 1; -uint32_t prtlnsts : - 2; -uint32_t prtpwr : - 1; -uint32_t prttstctl : - 4; -uint32_t prtspd : - 2; -uint32_t Reserved19_31 : - 13; - } - b; -} USB_OTG_HPRT0_TypeDef ; -typedef union _USB_OTG_HAINT_TypeDef -{ - uint32_t d32; - struct - { -uint32_t chint : - 16; -uint32_t Reserved : - 16; - } - b; -} USB_OTG_HAINT_TypeDef ; -typedef union _USB_OTG_HAINTMSK_TypeDef -{ - uint32_t d32; - struct - { -uint32_t chint : - 16; -uint32_t Reserved : - 16; - } - b; -} USB_OTG_HAINTMSK_TypeDef ; -typedef union _USB_OTG_HCCHAR_TypeDef -{ - uint32_t d32; - struct - { -uint32_t mps : - 11; -uint32_t epnum : - 4; -uint32_t epdir : - 1; -uint32_t Reserved : - 1; -uint32_t lspddev : - 1; -uint32_t eptype : - 2; -uint32_t multicnt : - 2; -uint32_t devaddr : - 7; -uint32_t oddfrm : - 1; -uint32_t chdis : - 1; -uint32_t chen : - 1; - } - b; -} USB_OTG_HCCHAR_TypeDef ; -typedef union _USB_OTG_HCSPLT_TypeDef -{ - uint32_t d32; - struct - { -uint32_t prtaddr : - 7; -uint32_t hubaddr : - 7; -uint32_t xactpos : - 2; -uint32_t compsplt : - 1; -uint32_t Reserved : - 14; -uint32_t spltena : - 1; - } - b; -} USB_OTG_HCSPLT_TypeDef ; -typedef union _USB_OTG_HCINTn_TypeDef -{ - uint32_t d32; - struct - { -uint32_t xfercompl : - 1; -uint32_t chhltd : - 1; -uint32_t ahberr : - 1; -uint32_t stall : - 1; -uint32_t nak : - 1; -uint32_t ack : - 1; -uint32_t nyet : - 1; -uint32_t xacterr : - 1; -uint32_t bblerr : - 1; -uint32_t frmovrun : - 1; -uint32_t datatglerr : - 1; -uint32_t Reserved : - 21; - } - b; -} USB_OTG_HCINTn_TypeDef ; -typedef union _USB_OTG_HCTSIZn_TypeDef -{ - uint32_t d32; - struct - { -uint32_t xfersize : - 19; -uint32_t pktcnt : - 10; -uint32_t pid : - 2; -uint32_t dopng : - 1; - } - b; -} USB_OTG_HCTSIZn_TypeDef ; -typedef union _USB_OTG_HCINTMSK_TypeDef -{ - uint32_t d32; - struct - { -uint32_t xfercompl : - 1; -uint32_t chhltd : - 1; -uint32_t ahberr : - 1; -uint32_t stall : - 1; -uint32_t nak : - 1; -uint32_t ack : - 1; -uint32_t nyet : - 1; -uint32_t xacterr : - 1; -uint32_t bblerr : - 1; -uint32_t frmovrun : - 1; -uint32_t datatglerr : - 1; -uint32_t Reserved : - 21; - } - b; -} USB_OTG_HCINTMSK_TypeDef ; - -typedef union _USB_OTG_PCGCCTL_TypeDef -{ - uint32_t d32; - struct - { -uint32_t stoppclk : - 1; -uint32_t gatehclk : - 1; -uint32_t Reserved2_3 : - 2; -uint32_t phy_susp : - 1; -uint32_t Reserved5_31 : - 27; - } - b; -} USB_OTG_PCGCCTL_TypeDef ; - -/** - * @} - */ - - -/** @defgroup USB_REGS_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_REGS_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_REGS_Exported_FunctionsPrototype - * @{ - */ -/** - * @} - */ - - -#endif //__USB_OTG_REGS_H__ - - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/stm/stmusbd/usbd_cdc_core.h b/stm/stmusbd/usbd_cdc_core.h deleted file mode 100644 index 026462143..000000000 --- a/stm/stmusbd/usbd_cdc_core.h +++ /dev/null @@ -1,143 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_cdc_core.h - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief header file for the usbd_cdc_core.c file. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ - -#ifndef __USB_CDC_CORE_H_ -#define __USB_CDC_CORE_H_ - -#include "usbd_ioreq.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup usbd_cdc - * @brief This file is the Header file for USBD_cdc.c - * @{ - */ - - -/** @defgroup usbd_cdc_Exported_Defines - * @{ - */ -#define USB_CDC_CONFIG_DESC_SIZ (98) -#define USB_CDC_DESC_SIZ (98-9) - -#define CDC_DESCRIPTOR_TYPE 0x21 - -#define DEVICE_CLASS_CDC 0x02 -#define DEVICE_SUBCLASS_CDC 0x00 - - -#define USB_DEVICE_DESCRIPTOR_TYPE 0x01 -#define USB_CONFIGURATION_DESCRIPTOR_TYPE 0x02 -#define USB_STRING_DESCRIPTOR_TYPE 0x03 -#define USB_INTERFACE_DESCRIPTOR_TYPE 0x04 -#define USB_ENDPOINT_DESCRIPTOR_TYPE 0x05 - -#define STANDARD_ENDPOINT_DESC_SIZE 0x09 - -#define CDC_DATA_IN_PACKET_SIZE CDC_DATA_MAX_PACKET_SIZE - -#define CDC_DATA_OUT_PACKET_SIZE CDC_DATA_MAX_PACKET_SIZE - -/*---------------------------------------------------------------------*/ -/* CDC definitions */ -/*---------------------------------------------------------------------*/ - -/**************************************************/ -/* CDC Requests */ -/**************************************************/ -#define SEND_ENCAPSULATED_COMMAND 0x00 -#define GET_ENCAPSULATED_RESPONSE 0x01 -#define SET_COMM_FEATURE 0x02 -#define GET_COMM_FEATURE 0x03 -#define CLEAR_COMM_FEATURE 0x04 -#define SET_LINE_CODING 0x20 -#define GET_LINE_CODING 0x21 -#define SET_CONTROL_LINE_STATE 0x22 -#define SEND_BREAK 0x23 -#define NO_CMD 0xFF - -/** - * @} - */ - - -/** @defgroup USBD_CORE_Exported_TypesDefinitions - * @{ - */ -typedef struct _CDC_IF_PROP -{ - uint16_t (*pIf_Init) (void); - uint16_t (*pIf_DeInit) (void); - uint16_t (*pIf_Ctrl) (uint32_t Cmd, uint8_t* Buf, uint32_t Len); - uint16_t (*pIf_DataTx) (const uint8_t* Buf, uint32_t Len); - uint16_t (*pIf_DataRx) (uint8_t* Buf, uint32_t Len); -} -CDC_IF_Prop_TypeDef; -/** - * @} - */ - - - -/** @defgroup USBD_CORE_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_CORE_Exported_Variables - * @{ - */ - -extern USBD_Class_cb_TypeDef USBD_CDC_cb; -/** - * @} - */ - -/** @defgroup USB_CORE_Exported_Functions - * @{ - */ -/** - * @} - */ - -#endif // __USB_CDC_CORE_H_ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmusbd/usbd_cdc_vcp.c b/stm/stmusbd/usbd_cdc_vcp.c deleted file mode 100644 index cb16b58f1..000000000 --- a/stm/stmusbd/usbd_cdc_vcp.c +++ /dev/null @@ -1,222 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_cdc_vcp.c - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief Generic media access Layer. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED -#pragma data_alignment = 4 -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_conf.h" -#include "usbd_cdc_vcp.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -LINE_CODING linecoding = - { - 115200, /* baud rate*/ - 0x00, /* stop bits-1*/ - 0x00, /* parity - none*/ - 0x08 /* nb. of bits 8*/ - }; - - -/* These are external variables imported from CDC core to be used for IN - transfer management. */ - -extern uint32_t APP_dev_is_connected; // set if CDC device is connected - -extern uint8_t APP_Rx_Buffer []; /* Write CDC received data in this buffer. - These data will be sent over USB IN endpoint - in the CDC core functions. */ -extern uint32_t APP_Rx_ptr_in; /* Increment this pointer or roll it back to - start address when writing received data - in the buffer APP_Rx_Buffer. */ - -/* Private function prototypes -----------------------------------------------*/ -static uint16_t VCP_Init (void); -static uint16_t VCP_DeInit (void); -static uint16_t VCP_Ctrl (uint32_t Cmd, uint8_t* Buf, uint32_t Len); -static uint16_t VCP_DataTx (const uint8_t* Buf, uint32_t Len); -static uint16_t VCP_DataRx (uint8_t* Buf, uint32_t Len); - -CDC_IF_Prop_TypeDef VCP_fops = -{ - VCP_Init, - VCP_DeInit, - VCP_Ctrl, - VCP_DataTx, - VCP_DataRx -}; - -/* Private functions ---------------------------------------------------------*/ -/** - * @brief VCP_Init - * Initializes the Media on the STM32 - * @param None - * @retval Result of the opeartion (USBD_OK in all cases) - */ -static uint16_t VCP_Init(void) { - return USBD_OK; -} - -/** - * @brief VCP_DeInit - * DeInitializes the Media on the STM32 - * @param None - * @retval Result of the opeartion (USBD_OK in all cases) - */ -static uint16_t VCP_DeInit(void) -{ - - return USBD_OK; -} - - -/** - * @brief VCP_Ctrl - * Manage the CDC class requests - * @param Cmd: Command code - * @param Buf: Buffer containing command data (request parameters) - * @param Len: Number of data to be sent (in bytes) - * @retval Result of the opeartion (USBD_OK in all cases) - */ -static uint16_t VCP_Ctrl (uint32_t Cmd, uint8_t* Buf, uint32_t Len) -{ - switch (Cmd) - { - case SEND_ENCAPSULATED_COMMAND: - /* Not needed for this driver */ - break; - - case GET_ENCAPSULATED_RESPONSE: - /* Not needed for this driver */ - break; - - case SET_COMM_FEATURE: - /* Not needed for this driver */ - break; - - case GET_COMM_FEATURE: - /* Not needed for this driver */ - break; - - case CLEAR_COMM_FEATURE: - /* Not needed for this driver */ - break; - - case SET_LINE_CODING: - /* - linecoding.bitrate = (uint32_t)(Buf[0] | (Buf[1] << 8) | (Buf[2] << 16) | (Buf[3] << 24)); - linecoding.format = Buf[4]; - linecoding.paritytype = Buf[5]; - linecoding.datatype = Buf[6]; - // Set the new configuration - VCP_COMConfig(OTHER_CONFIG); - */ - break; - - case GET_LINE_CODING: - /* - Buf[0] = (uint8_t)(linecoding.bitrate); - Buf[1] = (uint8_t)(linecoding.bitrate >> 8); - Buf[2] = (uint8_t)(linecoding.bitrate >> 16); - Buf[3] = (uint8_t)(linecoding.bitrate >> 24); - Buf[4] = linecoding.format; - Buf[5] = linecoding.paritytype; - Buf[6] = linecoding.datatype; - */ - Buf[0] = 0; - Buf[1] = 0; - Buf[2] = 0; - Buf[3] = 0; - Buf[4] = 0; - Buf[5] = 0; - Buf[6] = 0; - break; - - case SET_CONTROL_LINE_STATE: - APP_dev_is_connected = Len & 0x1; // wValue is passed in Len (bit of a hack) - break; - - case SEND_BREAK: - /* Not needed for this driver */ - break; - - default: - break; - } - - return USBD_OK; -} - -/** - * @brief VCP_DataTx - * CDC received data to be send over USB IN endpoint are managed in - * this function. - * @param Buf: Buffer of data to be sent - * @param Len: Number of data to be sent (in bytes) - * @retval Result of the opeartion: USBD_OK if all operations are OK else VCP_FAIL - */ -static uint16_t VCP_DataTx (const uint8_t* Buf, uint32_t Len) -{ - for (int i = 0; i < Len; i++) { - APP_Rx_Buffer[APP_Rx_ptr_in] = Buf[i]; - APP_Rx_ptr_in++; - - /* To avoid buffer overflow */ - if(APP_Rx_ptr_in == APP_RX_DATA_SIZE) { - APP_Rx_ptr_in = 0; - } - } - - return USBD_OK; -} - -/** - * @brief VCP_DataRx - * Data received over USB OUT endpoint are sent over CDC interface - * through this function. - * - * @note - * This function will block any OUT packet reception on USB endpoint - * untill exiting this function. If you exit this function before transfer - * is complete on CDC interface (ie. using DMA controller) it will result - * in receiving more data while previous ones are still not sent. - * - * @param Buf: Buffer of data to be received - * @param Len: Number of data received (in bytes) - * @retval Result of the opeartion: USBD_OK if all operations are OK else VCP_FAIL - */ -static uint16_t VCP_DataRx (uint8_t* Buf, uint32_t Len) { - extern void usb_vcp_receive(uint8_t *buf, uint32_t len); - usb_vcp_receive(Buf, Len); - return USBD_OK; -} - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmusbd/usbd_cdc_vcp.h b/stm/stmusbd/usbd_cdc_vcp.h deleted file mode 100644 index a80e287fa..000000000 --- a/stm/stmusbd/usbd_cdc_vcp.h +++ /dev/null @@ -1,52 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_cdc_vcp.h - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief Header for usbd_cdc_vcp.c file. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_CDC_VCP_H -#define __USBD_CDC_VCP_H - -#include "usbd_cdc_core.h" -#include "usbd_conf.h" - -/* Exported typef ------------------------------------------------------------*/ -/* The following structures groups all needed parameters to be configured for the - ComPort. These parameters can modified on the fly by the host through CDC class - command class requests. */ -typedef struct -{ - uint32_t bitrate; - uint8_t format; - uint8_t paritytype; - uint8_t datatype; -} LINE_CODING; - -#define DEFAULT_CONFIG 0 -#define OTHER_CONFIG 1 - -#endif /* __USBD_CDC_VCP_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmusbd/usbd_conf.h b/stm/stmusbd/usbd_conf.h deleted file mode 100644 index ad4cd73c8..000000000 --- a/stm/stmusbd/usbd_conf.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef __USBD_CONF__H__ -#define __USBD_CONF__H__ - -#define USBD_CFG_MAX_NUM 1 -#define USBD_ITF_MAX_NUM 1 // TODO need more than 1? - -// CDC Endpoints parameters -#define CDC_IN_EP 0x81 /* EP1 for data IN */ -#define CDC_OUT_EP 0x01 /* EP1 for data OUT */ -#define CDC_CMD_EP 0x82 /* EP2 for CDC commands */ -#define CDC_DATA_MAX_PACKET_SIZE 64 /* Endpoint IN & OUT Packet size */ -#define CDC_CMD_PACKET_SZE 8 /* Control Endpoint Packet size */ -#define CDC_IN_FRAME_INTERVAL 5 /* Number of frames between IN transfers */ -#define APP_RX_DATA_SIZE 2048 /* Total size of IN buffer: - APP_RX_DATA_SIZE*8/MAX_BAUDARATE*1000 should be > CDC_IN_FRAME_INTERVAL */ - -// MSC parameters -#define MSC_IN_EP 0x83 -#define MSC_OUT_EP 0x03 -#define MSC_MAX_PACKET 64 -#define MSC_MEDIA_PACKET 2048 /* XXX was 4096; how small can we make it? */ - -#endif //__USBD_CONF__H__ diff --git a/stm/stmusbd/usbd_core.c b/stm/stmusbd/usbd_core.c deleted file mode 100644 index fa647eb0f..000000000 --- a/stm/stmusbd/usbd_core.c +++ /dev/null @@ -1,506 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_core.c - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief This file provides all the USBD core functions. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_core.h" -#include "usbd_req.h" -#include "usbd_ioreq.h" -#include "usb_dcd_int.h" -#include "usb_bsp.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY -* @{ -*/ - - -/** @defgroup USBD_CORE -* @brief usbd core module -* @{ -*/ - -/** @defgroup USBD_CORE_Private_TypesDefinitions -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USBD_CORE_Private_Defines -* @{ -*/ - -/** -* @} -*/ - - -/** @defgroup USBD_CORE_Private_Macros -* @{ -*/ -/** -* @} -*/ - - - - -/** @defgroup USBD_CORE_Private_FunctionPrototypes -* @{ -*/ -static uint8_t USBD_SetupStage(USB_OTG_CORE_HANDLE *pdev); -static uint8_t USBD_DataOutStage(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum); -static uint8_t USBD_DataInStage(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum); -static uint8_t USBD_SOF(USB_OTG_CORE_HANDLE *pdev); -static uint8_t USBD_Reset(USB_OTG_CORE_HANDLE *pdev); -static uint8_t USBD_Suspend(USB_OTG_CORE_HANDLE *pdev); -static uint8_t USBD_Resume(USB_OTG_CORE_HANDLE *pdev); -#ifdef VBUS_SENSING_ENABLED -static uint8_t USBD_DevConnected(USB_OTG_CORE_HANDLE *pdev); -static uint8_t USBD_DevDisconnected(USB_OTG_CORE_HANDLE *pdev); -#endif -static uint8_t USBD_IsoINIncomplete(USB_OTG_CORE_HANDLE *pdev); -static uint8_t USBD_IsoOUTIncomplete(USB_OTG_CORE_HANDLE *pdev); -static uint8_t USBD_RunTestMode (USB_OTG_CORE_HANDLE *pdev) ; -/** -* @} -*/ - -/** @defgroup USBD_CORE_Private_Variables -* @{ -*/ - -__IO USB_OTG_DCTL_TypeDef SET_TEST_MODE; - -USBD_DCD_INT_cb_TypeDef USBD_DCD_INT_cb = -{ - USBD_DataOutStage, - USBD_DataInStage, - USBD_SetupStage, - USBD_SOF, - USBD_Reset, - USBD_Suspend, - USBD_Resume, - USBD_IsoINIncomplete, - USBD_IsoOUTIncomplete, -#ifdef VBUS_SENSING_ENABLED -USBD_DevConnected, -USBD_DevDisconnected, -#endif -}; - -USBD_DCD_INT_cb_TypeDef *USBD_DCD_INT_fops = &USBD_DCD_INT_cb; -/** -* @} -*/ - -/** @defgroup USBD_CORE_Private_Functions -* @{ -*/ - -/** -* @brief USBD_Init -* Initailizes the device stack and load the class driver -* @param pdev: device instance -* @param core_address: USB OTG core ID -* @param class_cb: Class callback structure address -* @param usr_cb: User callback structure address -* @retval None -*/ -void USBD_Init(USB_OTG_CORE_HANDLE *pdev, - USB_OTG_CORE_ID_TypeDef coreID, - USBD_DEVICE *pDevice, - USBD_Class_cb_TypeDef *class_cb, - USBD_Usr_cb_TypeDef *usr_cb) -{ - /* Hardware Init */ - USB_OTG_BSP_Init(pdev); - - USBD_DeInit(pdev); - - /*Register class and user callbacks */ - pdev->dev.class_cb = class_cb; - pdev->dev.usr_cb = usr_cb; - pdev->dev.usr_device = pDevice; - - /* set USB OTG core params */ - DCD_Init(pdev , coreID); - - /* Upon Init call usr callback */ - pdev->dev.usr_cb->Init(); - - /* Enable Interrupts */ - USB_OTG_BSP_EnableInterrupt(pdev); -} - -/** -* @brief USBD_DeInit -* Re-Initialize th device library -* @param pdev: device instance -* @retval status: status -*/ -USBD_Status USBD_DeInit(USB_OTG_CORE_HANDLE *pdev) -{ - /* Software Init */ - - return USBD_OK; -} - -/** -* @brief USBD_SetupStage -* Handle the setup stage -* @param pdev: device instance -* @retval status -*/ -static uint8_t USBD_SetupStage(USB_OTG_CORE_HANDLE *pdev) -{ - USB_SETUP_REQ req; - - USBD_ParseSetupRequest(pdev , &req); - - switch (req.bmRequest & 0x1F) - { - case USB_REQ_RECIPIENT_DEVICE: - USBD_StdDevReq (pdev, &req); - break; - - case USB_REQ_RECIPIENT_INTERFACE: - USBD_StdItfReq(pdev, &req); - break; - - case USB_REQ_RECIPIENT_ENDPOINT: - USBD_StdEPReq(pdev, &req); - break; - - default: - DCD_EP_Stall(pdev , req.bmRequest & 0x80); - break; - } - return USBD_OK; -} - -/** -* @brief USBD_DataOutStage -* Handle data out stage -* @param pdev: device instance -* @param epnum: endpoint index -* @retval status -*/ -static uint8_t USBD_DataOutStage(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum) -{ - USB_OTG_EP *ep; - - if(epnum == 0) - { - ep = &pdev->dev.out_ep[0]; - if ( pdev->dev.device_state == USB_OTG_EP0_DATA_OUT) - { - if(ep->rem_data_len > ep->maxpacket) - { - ep->rem_data_len -= ep->maxpacket; - - if(pdev->cfg.dma_enable == 1) - { - /* in slave mode this, is handled by the RxSTSQLvl ISR */ - ep->xfer_buff += ep->maxpacket; - } - USBD_CtlContinueRx (pdev, - ep->xfer_buff, - MIN(ep->rem_data_len ,ep->maxpacket)); - } - else - { - if((pdev->dev.class_cb->EP0_RxReady != NULL)&& - (pdev->dev.device_status == USB_OTG_CONFIGURED)) - { - pdev->dev.class_cb->EP0_RxReady(pdev); - } - USBD_CtlSendStatus(pdev); - } - } - } - else if((pdev->dev.class_cb->DataOut != NULL)&& - (pdev->dev.device_status == USB_OTG_CONFIGURED)) - { - pdev->dev.class_cb->DataOut(pdev, epnum); - } - return USBD_OK; -} - -/** -* @brief USBD_DataInStage -* Handle data in stage -* @param pdev: device instance -* @param epnum: endpoint index -* @retval status -*/ -static uint8_t USBD_DataInStage(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum) -{ - USB_OTG_EP *ep; - - if(epnum == 0) - { - ep = &pdev->dev.in_ep[0]; - if ( pdev->dev.device_state == USB_OTG_EP0_DATA_IN) - { - if(ep->rem_data_len > ep->maxpacket) - { - ep->rem_data_len -= ep->maxpacket; - if(pdev->cfg.dma_enable == 1) - { - /* in slave mode this, is handled by the TxFifoEmpty ISR */ - ep->xfer_buff += ep->maxpacket; - } - USBD_CtlContinueSendData (pdev, - ep->xfer_buff, - ep->rem_data_len); - } - else - { /* last packet is MPS multiple, so send ZLP packet */ - if((ep->total_data_len % ep->maxpacket == 0) && - (ep->total_data_len >= ep->maxpacket) && - (ep->total_data_len < ep->ctl_data_len )) - { - - USBD_CtlContinueSendData(pdev , NULL, 0); - ep->ctl_data_len = 0; - } - else - { - if((pdev->dev.class_cb->EP0_TxSent != NULL)&& - (pdev->dev.device_status == USB_OTG_CONFIGURED)) - { - pdev->dev.class_cb->EP0_TxSent(pdev); - } - USBD_CtlReceiveStatus(pdev); - } - } - } - if (pdev->dev.test_mode == 1) - { - USBD_RunTestMode(pdev); - pdev->dev.test_mode = 0; - } - } - else if((pdev->dev.class_cb->DataIn != NULL)&& - (pdev->dev.device_status == USB_OTG_CONFIGURED)) - { - pdev->dev.class_cb->DataIn(pdev, epnum); - } - return USBD_OK; -} - - - - -/** -* @brief USBD_RunTestMode -* Launch test mode process -* @param pdev: device instance -* @retval status -*/ -static uint8_t USBD_RunTestMode (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCTL, SET_TEST_MODE.d32); - return USBD_OK; -} - -/** -* @brief USBD_Reset -* Handle Reset event -* @param pdev: device instance -* @retval status -*/ - -static uint8_t USBD_Reset(USB_OTG_CORE_HANDLE *pdev) -{ - /* Open EP0 OUT */ - DCD_EP_Open(pdev, - 0x00, - USB_OTG_MAX_EP0_SIZE, - EP_TYPE_CTRL); - - /* Open EP0 IN */ - DCD_EP_Open(pdev, - 0x80, - USB_OTG_MAX_EP0_SIZE, - EP_TYPE_CTRL); - - /* Upon Reset call usr call back */ - pdev->dev.device_status = USB_OTG_DEFAULT; - pdev->dev.usr_cb->DeviceReset(pdev->cfg.speed); - - return USBD_OK; -} - -/** -* @brief USBD_Resume -* Handle Resume event -* @param pdev: device instance -* @retval status -*/ - -static uint8_t USBD_Resume(USB_OTG_CORE_HANDLE *pdev) -{ - /* Upon Resume call usr call back */ - pdev->dev.usr_cb->DeviceResumed(); - pdev->dev.device_status = pdev->dev.device_old_status; - pdev->dev.device_status = USB_OTG_CONFIGURED; - return USBD_OK; -} - - -/** -* @brief USBD_Suspend -* Handle Suspend event -* @param pdev: device instance -* @retval status -*/ - -static uint8_t USBD_Suspend(USB_OTG_CORE_HANDLE *pdev) -{ - pdev->dev.device_old_status = pdev->dev.device_status; - pdev->dev.device_status = USB_OTG_SUSPENDED; - /* Upon Resume call usr call back */ - pdev->dev.usr_cb->DeviceSuspended(); - return USBD_OK; -} - - -/** -* @brief USBD_SOF -* Handle SOF event -* @param pdev: device instance -* @retval status -*/ - -static uint8_t USBD_SOF(USB_OTG_CORE_HANDLE *pdev) -{ - if(pdev->dev.class_cb->SOF) - { - pdev->dev.class_cb->SOF(pdev); - } - return USBD_OK; -} -/** -* @brief USBD_SetCfg -* Configure device and start the interface -* @param pdev: device instance -* @param cfgidx: configuration index -* @retval status -*/ - -USBD_Status USBD_SetCfg(USB_OTG_CORE_HANDLE *pdev, uint8_t cfgidx) -{ - pdev->dev.class_cb->Init(pdev, cfgidx); - - /* Upon set config call usr call back */ - pdev->dev.usr_cb->DeviceConfigured(); - return USBD_OK; -} - -/** -* @brief USBD_ClrCfg -* Clear current configuration -* @param pdev: device instance -* @param cfgidx: configuration index -* @retval status: USBD_Status -*/ -USBD_Status USBD_ClrCfg(USB_OTG_CORE_HANDLE *pdev, uint8_t cfgidx) -{ - pdev->dev.class_cb->DeInit(pdev, cfgidx); - return USBD_OK; -} - -/** -* @brief USBD_IsoINIncomplete -* Handle iso in incomplete event -* @param pdev: device instance -* @retval status -*/ -static uint8_t USBD_IsoINIncomplete(USB_OTG_CORE_HANDLE *pdev) -{ - pdev->dev.class_cb->IsoINIncomplete(pdev); - return USBD_OK; -} - -/** -* @brief USBD_IsoOUTIncomplete -* Handle iso out incomplete event -* @param pdev: device instance -* @retval status -*/ -static uint8_t USBD_IsoOUTIncomplete(USB_OTG_CORE_HANDLE *pdev) -{ - pdev->dev.class_cb->IsoOUTIncomplete(pdev); - return USBD_OK; -} - -#ifdef VBUS_SENSING_ENABLED -/** -* @brief USBD_DevConnected -* Handle device connection event -* @param pdev: device instance -* @retval status -*/ -static uint8_t USBD_DevConnected(USB_OTG_CORE_HANDLE *pdev) -{ - pdev->dev.usr_cb->DeviceConnected(); - pdev->dev.connection_status = 1; - return USBD_OK; -} - -/** -* @brief USBD_DevDisconnected -* Handle device disconnection event -* @param pdev: device instance -* @retval status -*/ -static uint8_t USBD_DevDisconnected(USB_OTG_CORE_HANDLE *pdev) -{ - pdev->dev.usr_cb->DeviceDisconnected(); - pdev->dev.class_cb->DeInit(pdev, 0); - pdev->dev.connection_status = 0; - return USBD_OK; -} -#endif -/** -* @} -*/ - - -/** -* @} -*/ - - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/stm/stmusbd/usbd_core.h b/stm/stmusbd/usbd_core.h deleted file mode 100644 index 60d185b78..000000000 --- a/stm/stmusbd/usbd_core.h +++ /dev/null @@ -1,120 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_core.h - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief Header file for usbd_core.c - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_CORE_H -#define __USBD_CORE_H - -/* Includes ------------------------------------------------------------------*/ -#include "usb_dcd.h" -#include "usbd_def.h" -//#include "usbd_conf.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USBD_CORE - * @brief This file is the Header file for usbd_core.c file - * @{ - */ - - -/** @defgroup USBD_CORE_Exported_Defines - * @{ - */ - -typedef enum { - USBD_OK = 0, - USBD_BUSY, - USBD_FAIL, -}USBD_Status; -/** - * @} - */ - - -/** @defgroup USBD_CORE_Exported_TypesDefinitions - * @{ - */ - - -/** - * @} - */ - - - -/** @defgroup USBD_CORE_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_CORE_Exported_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_CORE_Exported_FunctionsPrototype - * @{ - */ -void USBD_Init(USB_OTG_CORE_HANDLE *pdev, - USB_OTG_CORE_ID_TypeDef coreID, - USBD_DEVICE *pDevice, - USBD_Class_cb_TypeDef *class_cb, - USBD_Usr_cb_TypeDef *usr_cb); - -USBD_Status USBD_DeInit(USB_OTG_CORE_HANDLE *pdev); - -USBD_Status USBD_ClrCfg(USB_OTG_CORE_HANDLE *pdev, uint8_t cfgidx); - -USBD_Status USBD_SetCfg(USB_OTG_CORE_HANDLE *pdev, uint8_t cfgidx); - -/** - * @} - */ - -#endif /* __USBD_CORE_H */ - -/** - * @} - */ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - - diff --git a/stm/stmusbd/usbd_def.h b/stm/stmusbd/usbd_def.h deleted file mode 100644 index bdf72d249..000000000 --- a/stm/stmusbd/usbd_def.h +++ /dev/null @@ -1,157 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_def.h - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief general defines for the usb device library - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ - -#ifndef __USBD_DEF_H -#define __USBD_DEF_H - -/* Includes ------------------------------------------------------------------*/ -//#include "usbd_conf.h" -#define USB_MAX_STR_DESC_SIZ 255 - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USB_DEF - * @brief general defines for the usb device library file - * @{ - */ - -/** @defgroup USB_DEF_Exported_Defines - * @{ - */ - -#ifndef NULL -#define NULL 0 -#endif - -#define USB_LEN_DEV_QUALIFIER_DESC 0x0A -#define USB_LEN_DEV_DESC 0x12 -#define USB_LEN_CFG_DESC 0x09 -#define USB_LEN_IF_DESC 0x09 -#define USB_LEN_EP_DESC 0x07 -#define USB_LEN_OTG_DESC 0x03 - -#define USBD_IDX_LANGID_STR 0x00 -#define USBD_IDX_MFC_STR 0x01 -#define USBD_IDX_PRODUCT_STR 0x02 -#define USBD_IDX_SERIAL_STR 0x03 -#define USBD_IDX_CONFIG_STR 0x04 -#define USBD_IDX_INTERFACE_STR 0x05 - -#define USB_REQ_TYPE_STANDARD 0x00 -#define USB_REQ_TYPE_CLASS 0x20 -#define USB_REQ_TYPE_VENDOR 0x40 -#define USB_REQ_TYPE_MASK 0x60 - -#define USB_REQ_RECIPIENT_DEVICE 0x00 -#define USB_REQ_RECIPIENT_INTERFACE 0x01 -#define USB_REQ_RECIPIENT_ENDPOINT 0x02 -#define USB_REQ_RECIPIENT_MASK 0x03 - -#define USB_REQ_GET_STATUS 0x00 -#define USB_REQ_CLEAR_FEATURE 0x01 -#define USB_REQ_SET_FEATURE 0x03 -#define USB_REQ_SET_ADDRESS 0x05 -#define USB_REQ_GET_DESCRIPTOR 0x06 -#define USB_REQ_SET_DESCRIPTOR 0x07 -#define USB_REQ_GET_CONFIGURATION 0x08 -#define USB_REQ_SET_CONFIGURATION 0x09 -#define USB_REQ_GET_INTERFACE 0x0A -#define USB_REQ_SET_INTERFACE 0x0B -#define USB_REQ_SYNCH_FRAME 0x0C - -#define USB_DESC_TYPE_DEVICE 1 -#define USB_DESC_TYPE_CONFIGURATION 2 -#define USB_DESC_TYPE_STRING 3 -#define USB_DESC_TYPE_INTERFACE 4 -#define USB_DESC_TYPE_ENDPOINT 5 -#define USB_DESC_TYPE_DEVICE_QUALIFIER 6 -#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION 7 - - -#define USB_CONFIG_REMOTE_WAKEUP 2 -#define USB_CONFIG_SELF_POWERED 1 - -#define USB_FEATURE_EP_HALT 0 -#define USB_FEATURE_REMOTE_WAKEUP 1 -#define USB_FEATURE_TEST_MODE 2 - -/** - * @} - */ - - -/** @defgroup USBD_DEF_Exported_TypesDefinitions - * @{ - */ -/** - * @} - */ - - - -/** @defgroup USBD_DEF_Exported_Macros - * @{ - */ -#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ - (((uint16_t)(*(((uint8_t *)(addr)) + 1))) << 8)) - -#define LOBYTE(x) ((uint8_t)(x & 0x00FF)) -#define HIBYTE(x) ((uint8_t)((x & 0xFF00) >>8)) -/** - * @} - */ - -/** @defgroup USBD_DEF_Exported_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_DEF_Exported_FunctionsPrototype - * @{ - */ - -/** - * @} - */ - -#endif /* __USBD_DEF_H */ - -/** - * @} - */ - -/** -* @} -*/ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmusbd/usbd_desc.c b/stm/stmusbd/usbd_desc.c deleted file mode 100644 index 1edbdbfac..000000000 --- a/stm/stmusbd/usbd_desc.c +++ /dev/null @@ -1,331 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_desc.c - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief This file provides the USBD descriptors and string formating method. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_core.h" -#include "usbd_desc.h" -#include "usbd_req.h" -#include "usb_regs.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup USBD_DESC - * @brief USBD descriptors module - * @{ - */ - -/** @defgroup USBD_DESC_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_DESC_Private_Defines - * @{ - */ -/* -#define USBD_VID 0x0483 // TODO set VID -#define USBD_PID 0x5720 // TODO set PID - -#define USBD_LANGID_STRING 0x409 -#define USBD_MANUFACTURER_STRING "STMicroelectronics" // TODO set -#define USBD_PRODUCT_HS_STRING "VCP/MSC in HS Mode" // TODO set -#define USBD_SERIALNUMBER_HS_STRING "00000000001A" // TODO set -#define USBD_PRODUCT_FS_STRING "VCP/MSC in FS Mode" // TODO set -#define USBD_SERIALNUMBER_FS_STRING "00000000001B" // TODO set -#define USBD_CONFIGURATION_HS_STRING "VCP/MSC Config" // TODO set -#define USBD_INTERFACE_HS_STRING "VCP/MSC Interface" // TODO set -#define USBD_CONFIGURATION_FS_STRING "VCP/MSC Config" // TODO set -#define USBD_INTERFACE_FS_STRING "VCP/MSC Interface" // TODO set -*/ -/** - * @} - */ - -// seems we need to use this VID/PID to get it to work on windows - -#define USBD_VID 0x0483 -#define USBD_PID 0x5740 - -#define USBD_LANGID_STRING 0x409 -#define USBD_MANUFACTURER_STRING "STMicroelectronics" -#define USBD_PRODUCT_HS_STRING "STM32 Virtual ComPort in HS mode" -#define USBD_SERIALNUMBER_HS_STRING "00000000050B" -#define USBD_PRODUCT_FS_STRING "STM32 Virtual ComPort in FS Mode" -#define USBD_SERIALNUMBER_FS_STRING "00000000050C" -#define USBD_CONFIGURATION_HS_STRING "VCP Config" -#define USBD_INTERFACE_HS_STRING "VCP Interface" -#define USBD_CONFIGURATION_FS_STRING "VCP Config" -#define USBD_INTERFACE_FS_STRING "VCP Interface" - - -/** @defgroup USBD_DESC_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_DESC_Private_Variables - * @{ - */ - -USBD_DEVICE USR_desc = -{ - USBD_USR_DeviceDescriptor, - USBD_USR_LangIDStrDescriptor, - USBD_USR_ManufacturerStrDescriptor, - USBD_USR_ProductStrDescriptor, - USBD_USR_SerialStrDescriptor, - USBD_USR_ConfigStrDescriptor, - USBD_USR_InterfaceStrDescriptor, - -}; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -/* USB Standard Device Descriptor */ -__ALIGN_BEGIN static uint8_t USBD_DeviceDesc[USB_SIZ_DEVICE_DESC] __ALIGN_END = -{ - 0x12, // bLength - USB_DEVICE_DESCRIPTOR_TYPE, // bDescriptorType - 0x00, // bcdUSB: v2.0 - 0x02, - 0xef, // bDeviceClass: Miscellaneous Device Class - 0x02, // bDeviceSubClass: Common Class - 0x01, // bDeviceProtocol: Interface Association Descriptor - USB_OTG_MAX_EP0_SIZE, // bMaxPacketSize - LOBYTE(USBD_VID), // idVendor - HIBYTE(USBD_VID), // idVendor - LOBYTE(USBD_PID), // idVendor - HIBYTE(USBD_PID), // idVendor - 0x00, // bcdDevice: rel. 2.00 - 0x02, - USBD_IDX_MFC_STR, /*Index of manufacturer string*/ - USBD_IDX_PRODUCT_STR, /*Index of product string*/ - USBD_IDX_SERIAL_STR, /*Index of serial number string*/ - USBD_CFG_MAX_NUM // bNumConfigurations: 1 - } ; /* USB_DeviceDescriptor */ - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -/* USB Standard Device Descriptor */ -__ALIGN_BEGIN uint8_t USBD_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END = -{ - USB_LEN_DEV_QUALIFIER_DESC, - USB_DESC_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x01, - 0x00, -}; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -/* USB Standard Device Descriptor */ -__ALIGN_BEGIN uint8_t USBD_LangIDDesc[USB_SIZ_STRING_LANGID] __ALIGN_END = -{ - USB_SIZ_STRING_LANGID, - USB_DESC_TYPE_STRING, - LOBYTE(USBD_LANGID_STRING), - HIBYTE(USBD_LANGID_STRING), -}; -/** - * @} - */ - - -/** @defgroup USBD_DESC_Private_FunctionPrototypes - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_DESC_Private_Functions - * @{ - */ - -/** -* @brief USBD_USR_DeviceDescriptor -* return the device descriptor -* @param speed : current device speed -* @param length : pointer to data length variable -* @retval pointer to descriptor buffer -*/ -uint8_t * USBD_USR_DeviceDescriptor( uint8_t speed , uint16_t *length) -{ - *length = sizeof(USBD_DeviceDesc); - return USBD_DeviceDesc; -} - -/** -* @brief USBD_USR_LangIDStrDescriptor -* return the LangID string descriptor -* @param speed : current device speed -* @param length : pointer to data length variable -* @retval pointer to descriptor buffer -*/ -uint8_t * USBD_USR_LangIDStrDescriptor( uint8_t speed , uint16_t *length) -{ - *length = sizeof(USBD_LangIDDesc); - return USBD_LangIDDesc; -} - - -/** -* @brief USBD_USR_ProductStrDescriptor -* return the product string descriptor -* @param speed : current device speed -* @param length : pointer to data length variable -* @retval pointer to descriptor buffer -*/ -uint8_t * USBD_USR_ProductStrDescriptor( uint8_t speed , uint16_t *length) -{ - - - if(speed == 0) - { - USBD_GetString (USBD_PRODUCT_HS_STRING, USBD_StrDesc, length); - } - else - { - USBD_GetString (USBD_PRODUCT_FS_STRING, USBD_StrDesc, length); - } - return USBD_StrDesc; -} - -/** -* @brief USBD_USR_ManufacturerStrDescriptor -* return the manufacturer string descriptor -* @param speed : current device speed -* @param length : pointer to data length variable -* @retval pointer to descriptor buffer -*/ -uint8_t * USBD_USR_ManufacturerStrDescriptor( uint8_t speed , uint16_t *length) -{ - USBD_GetString (USBD_MANUFACTURER_STRING, USBD_StrDesc, length); - return USBD_StrDesc; -} - -/** -* @brief USBD_USR_SerialStrDescriptor -* return the serial number string descriptor -* @param speed : current device speed -* @param length : pointer to data length variable -* @retval pointer to descriptor buffer -*/ -uint8_t * USBD_USR_SerialStrDescriptor( uint8_t speed , uint16_t *length) -{ - if(speed == USB_OTG_SPEED_HIGH) - { - USBD_GetString (USBD_SERIALNUMBER_HS_STRING, USBD_StrDesc, length); - } - else - { - USBD_GetString (USBD_SERIALNUMBER_FS_STRING, USBD_StrDesc, length); - } - return USBD_StrDesc; -} - -/** -* @brief USBD_USR_ConfigStrDescriptor -* return the configuration string descriptor -* @param speed : current device speed -* @param length : pointer to data length variable -* @retval pointer to descriptor buffer -*/ -uint8_t * USBD_USR_ConfigStrDescriptor( uint8_t speed , uint16_t *length) -{ - if(speed == USB_OTG_SPEED_HIGH) - { - USBD_GetString (USBD_CONFIGURATION_HS_STRING, USBD_StrDesc, length); - } - else - { - USBD_GetString (USBD_CONFIGURATION_FS_STRING, USBD_StrDesc, length); - } - return USBD_StrDesc; -} - - -/** -* @brief USBD_USR_InterfaceStrDescriptor -* return the interface string descriptor -* @param speed : current device speed -* @param length : pointer to data length variable -* @retval pointer to descriptor buffer -*/ -uint8_t * USBD_USR_InterfaceStrDescriptor( uint8_t speed , uint16_t *length) -{ - if(speed == 0) - { - USBD_GetString (USBD_INTERFACE_HS_STRING, USBD_StrDesc, length); - } - else - { - USBD_GetString (USBD_INTERFACE_FS_STRING, USBD_StrDesc, length); - } - return USBD_StrDesc; -} - -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/stm/stmusbd/usbd_desc.h b/stm/stmusbd/usbd_desc.h deleted file mode 100644 index c6da3158b..000000000 --- a/stm/stmusbd/usbd_desc.h +++ /dev/null @@ -1,121 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_desc.h - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief header file for the usbd_desc.c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ - -#ifndef __USB_DESC_H -#define __USB_DESC_H - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_def.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USB_DESC - * @brief general defines for the usb device library file - * @{ - */ - -/** @defgroup USB_DESC_Exported_Defines - * @{ - */ -#define USB_DEVICE_DESCRIPTOR_TYPE 0x01 -#define USB_CONFIGURATION_DESCRIPTOR_TYPE 0x02 -#define USB_STRING_DESCRIPTOR_TYPE 0x03 -#define USB_INTERFACE_DESCRIPTOR_TYPE 0x04 -#define USB_ENDPOINT_DESCRIPTOR_TYPE 0x05 -#define USB_INTERFACE_ASSOCIATION_TYPE 0x0b -#define USB_SIZ_DEVICE_DESC 18 -#define USB_SIZ_STRING_LANGID 4 - -/** - * @} - */ - - -/** @defgroup USBD_DESC_Exported_TypesDefinitions - * @{ - */ -/** - * @} - */ - - - -/** @defgroup USBD_DESC_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USBD_DESC_Exported_Variables - * @{ - */ -//extern uint8_t USBD_DeviceDesc [USB_SIZ_DEVICE_DESC]; -extern uint8_t USBD_StrDesc[USB_MAX_STR_DESC_SIZ]; -extern uint8_t USBD_OtherSpeedCfgDesc[USB_LEN_CFG_DESC]; -extern uint8_t USBD_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC]; -extern uint8_t USBD_LangIDDesc[USB_SIZ_STRING_LANGID]; -extern USBD_DEVICE USR_desc; -/** - * @} - */ - -/** @defgroup USBD_DESC_Exported_FunctionsPrototype - * @{ - */ - - -uint8_t * USBD_USR_DeviceDescriptor( uint8_t speed , uint16_t *length); -uint8_t * USBD_USR_LangIDStrDescriptor( uint8_t speed , uint16_t *length); -uint8_t * USBD_USR_ManufacturerStrDescriptor ( uint8_t speed , uint16_t *length); -uint8_t * USBD_USR_ProductStrDescriptor ( uint8_t speed , uint16_t *length); -uint8_t * USBD_USR_SerialStrDescriptor( uint8_t speed , uint16_t *length); -uint8_t * USBD_USR_ConfigStrDescriptor( uint8_t speed , uint16_t *length); -uint8_t * USBD_USR_InterfaceStrDescriptor( uint8_t speed , uint16_t *length); - -#ifdef USB_SUPPORT_USER_STRING_DESC -uint8_t * USBD_USR_USRStringDesc (uint8_t speed, uint8_t idx , uint16_t *length); -#endif /* USB_SUPPORT_USER_STRING_DESC */ - -/** - * @} - */ - -#endif /* __USBD_DESC_H */ - -/** - * @} - */ - -/** -* @} -*/ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmusbd/usbd_ioreq.c b/stm/stmusbd/usbd_ioreq.c deleted file mode 100644 index a9e4a8636..000000000 --- a/stm/stmusbd/usbd_ioreq.c +++ /dev/null @@ -1,244 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_ioreq.c - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief This file provides the IO requests APIs for control endpoints. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_ioreq.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup USBD_IOREQ - * @brief control I/O requests module - * @{ - */ - -/** @defgroup USBD_IOREQ_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Private_Defines - * @{ - */ - -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Private_Variables - * @{ - */ - -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Private_FunctionPrototypes - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Private_Functions - * @{ - */ - -/** -* @brief USBD_CtlSendData -* send data on the ctl pipe -* @param pdev: device instance -* @param buff: pointer to data buffer -* @param len: length of data to be sent -* @retval status -*/ -USBD_Status USBD_CtlSendData (USB_OTG_CORE_HANDLE *pdev, - uint8_t *pbuf, - uint16_t len) -{ - USBD_Status ret = USBD_OK; - - pdev->dev.in_ep[0].total_data_len = len; - pdev->dev.in_ep[0].rem_data_len = len; - pdev->dev.device_state = USB_OTG_EP0_DATA_IN; - - DCD_EP_Tx (pdev, 0, pbuf, len); - - return ret; -} - -/** -* @brief USBD_CtlContinueSendData -* continue sending data on the ctl pipe -* @param pdev: device instance -* @param buff: pointer to data buffer -* @param len: length of data to be sent -* @retval status -*/ -USBD_Status USBD_CtlContinueSendData (USB_OTG_CORE_HANDLE *pdev, - uint8_t *pbuf, - uint16_t len) -{ - USBD_Status ret = USBD_OK; - - DCD_EP_Tx (pdev, 0, pbuf, len); - - - return ret; -} - -/** -* @brief USBD_CtlPrepareRx -* receive data on the ctl pipe -* @param pdev: USB OTG device instance -* @param buff: pointer to data buffer -* @param len: length of data to be received -* @retval status -*/ -USBD_Status USBD_CtlPrepareRx (USB_OTG_CORE_HANDLE *pdev, - uint8_t *pbuf, - uint16_t len) -{ - USBD_Status ret = USBD_OK; - - pdev->dev.out_ep[0].total_data_len = len; - pdev->dev.out_ep[0].rem_data_len = len; - pdev->dev.device_state = USB_OTG_EP0_DATA_OUT; - - DCD_EP_PrepareRx (pdev, - 0, - pbuf, - len); - - - return ret; -} - -/** -* @brief USBD_CtlContinueRx -* continue receive data on the ctl pipe -* @param pdev: USB OTG device instance -* @param buff: pointer to data buffer -* @param len: length of data to be received -* @retval status -*/ -USBD_Status USBD_CtlContinueRx (USB_OTG_CORE_HANDLE *pdev, - uint8_t *pbuf, - uint16_t len) -{ - USBD_Status ret = USBD_OK; - - DCD_EP_PrepareRx (pdev, - 0, - pbuf, - len); - return ret; -} -/** -* @brief USBD_CtlSendStatus -* send zero lzngth packet on the ctl pipe -* @param pdev: USB OTG device instance -* @retval status -*/ -USBD_Status USBD_CtlSendStatus (USB_OTG_CORE_HANDLE *pdev) -{ - USBD_Status ret = USBD_OK; - pdev->dev.device_state = USB_OTG_EP0_STATUS_IN; - DCD_EP_Tx (pdev, - 0, - NULL, - 0); - - USB_OTG_EP0_OutStart(pdev); - - return ret; -} - -/** -* @brief USBD_CtlReceiveStatus -* receive zero lzngth packet on the ctl pipe -* @param pdev: USB OTG device instance -* @retval status -*/ -USBD_Status USBD_CtlReceiveStatus (USB_OTG_CORE_HANDLE *pdev) -{ - USBD_Status ret = USBD_OK; - pdev->dev.device_state = USB_OTG_EP0_STATUS_OUT; - DCD_EP_PrepareRx ( pdev, - 0, - NULL, - 0); - - USB_OTG_EP0_OutStart(pdev); - - return ret; -} - - -/** -* @brief USBD_GetRxCount -* returns the received data length -* @param pdev: USB OTG device instance -* epnum: endpoint index -* @retval Rx Data blength -*/ -uint16_t USBD_GetRxCount (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum) -{ - return pdev->dev.out_ep[epnum].xfer_count; -} - -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmusbd/usbd_ioreq.h b/stm/stmusbd/usbd_ioreq.h deleted file mode 100644 index 3f6aea1a9..000000000 --- a/stm/stmusbd/usbd_ioreq.h +++ /dev/null @@ -1,121 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_ioreq.h - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief header file for the usbd_ioreq.c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ - -#ifndef __USBD_IOREQ_H_ -#define __USBD_IOREQ_H_ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_def.h" -#include "usbd_core.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USBD_IOREQ - * @brief header file for the usbd_ioreq.c file - * @{ - */ - -/** @defgroup USBD_IOREQ_Exported_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Exported_Types - * @{ - */ - - -/** - * @} - */ - - - -/** @defgroup USBD_IOREQ_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_IOREQ_Exported_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_IOREQ_Exported_FunctionsPrototype - * @{ - */ - -USBD_Status USBD_CtlSendData (USB_OTG_CORE_HANDLE *pdev, - uint8_t *buf, - uint16_t len); - -USBD_Status USBD_CtlContinueSendData (USB_OTG_CORE_HANDLE *pdev, - uint8_t *pbuf, - uint16_t len); - -USBD_Status USBD_CtlPrepareRx (USB_OTG_CORE_HANDLE *pdev, - uint8_t *pbuf, - uint16_t len); - -USBD_Status USBD_CtlContinueRx (USB_OTG_CORE_HANDLE *pdev, - uint8_t *pbuf, - uint16_t len); - -USBD_Status USBD_CtlSendStatus (USB_OTG_CORE_HANDLE *pdev); - -USBD_Status USBD_CtlReceiveStatus (USB_OTG_CORE_HANDLE *pdev); - -uint16_t USBD_GetRxCount (USB_OTG_CORE_HANDLE *pdev , - uint8_t epnum); - -/** - * @} - */ - -#endif /* __USBD_IOREQ_H_ */ - -/** - * @} - */ - -/** -* @} -*/ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmusbd/usbd_msc_bot.c b/stm/stmusbd/usbd_msc_bot.c deleted file mode 100644 index 20dbc4863..000000000 --- a/stm/stmusbd/usbd_msc_bot.c +++ /dev/null @@ -1,401 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_msc_bot.c - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief This file provides all the BOT protocol core functions. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_msc_bot.h" -#include "usbd_msc_scsi.h" -#include "usbd_ioreq.h" -#include "usbd_msc_mem.h" -#include "usbd_conf.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup MSC_BOT - * @brief BOT protocol module - * @{ - */ - -/** @defgroup MSC_BOT_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_BOT_Private_Defines - * @{ - */ - -/** - * @} - */ - - -/** @defgroup MSC_BOT_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_BOT_Private_Variables - * @{ - */ -uint16_t MSC_BOT_DataLen; -uint8_t MSC_BOT_State; -uint8_t MSC_BOT_Status; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN uint8_t MSC_BOT_Data[MSC_MEDIA_PACKET] __ALIGN_END ; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN MSC_BOT_CBW_TypeDef MSC_BOT_cbw __ALIGN_END ; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN MSC_BOT_CSW_TypeDef MSC_BOT_csw __ALIGN_END ; -/** - * @} - */ - - -/** @defgroup MSC_BOT_Private_FunctionPrototypes - * @{ - */ -static void MSC_BOT_CBW_Decode (USB_OTG_CORE_HANDLE *pdev); - -static void MSC_BOT_SendData (USB_OTG_CORE_HANDLE *pdev, - uint8_t* pbuf, - uint16_t len); - -static void MSC_BOT_Abort(USB_OTG_CORE_HANDLE *pdev); -/** - * @} - */ - - -/** @defgroup MSC_BOT_Private_Functions - * @{ - */ - - - -/** -* @brief MSC_BOT_Init -* Initialize the BOT Process -* @param pdev: device instance -* @retval None -*/ -void MSC_BOT_Init (USB_OTG_CORE_HANDLE *pdev) -{ - MSC_BOT_State = BOT_IDLE; - MSC_BOT_Status = BOT_STATE_NORMAL; - USBD_STORAGE_fops->Init(0); - - DCD_EP_Flush(pdev, MSC_OUT_EP); - DCD_EP_Flush(pdev, MSC_IN_EP); - /* Prapare EP to Receive First BOT Cmd */ - DCD_EP_PrepareRx (pdev, - MSC_OUT_EP, - (uint8_t *)&MSC_BOT_cbw, - BOT_CBW_LENGTH); -} - -/** -* @brief MSC_BOT_Reset -* Reset the BOT Machine -* @param pdev: device instance -* @retval None -*/ -void MSC_BOT_Reset (USB_OTG_CORE_HANDLE *pdev) -{ - MSC_BOT_State = BOT_IDLE; - MSC_BOT_Status = BOT_STATE_RECOVERY; - /* Prapare EP to Receive First BOT Cmd */ - DCD_EP_PrepareRx (pdev, - MSC_OUT_EP, - (uint8_t *)&MSC_BOT_cbw, - BOT_CBW_LENGTH); -} - -/** -* @brief MSC_BOT_DeInit -* Uninitialize the BOT Machine -* @param pdev: device instance -* @retval None -*/ -void MSC_BOT_DeInit (USB_OTG_CORE_HANDLE *pdev) -{ - MSC_BOT_State = BOT_IDLE; -} - -/** -* @brief MSC_BOT_DataIn -* Handle BOT IN data stage -* @param pdev: device instance -* @param epnum: endpoint index -* @retval None -*/ -void MSC_BOT_DataIn (USB_OTG_CORE_HANDLE *pdev, - uint8_t epnum) -{ - - switch (MSC_BOT_State) - { - case BOT_DATA_IN: - if(SCSI_ProcessCmd(pdev, - MSC_BOT_cbw.bLUN, - &MSC_BOT_cbw.CB[0]) < 0) - { - MSC_BOT_SendCSW (pdev, CSW_CMD_FAILED); - } - break; - - case BOT_SEND_DATA: - case BOT_LAST_DATA_IN: - MSC_BOT_SendCSW (pdev, CSW_CMD_PASSED); - - break; - - default: - break; - } -} -/** -* @brief MSC_BOT_DataOut -* Proccess MSC OUT data -* @param pdev: device instance -* @param epnum: endpoint index -* @retval None -*/ -void MSC_BOT_DataOut (USB_OTG_CORE_HANDLE *pdev, - uint8_t epnum) -{ - switch (MSC_BOT_State) - { - case BOT_IDLE: - MSC_BOT_CBW_Decode(pdev); - break; - - case BOT_DATA_OUT: - - if(SCSI_ProcessCmd(pdev, - MSC_BOT_cbw.bLUN, - &MSC_BOT_cbw.CB[0]) < 0) - { - MSC_BOT_SendCSW (pdev, CSW_CMD_FAILED); - } - - break; - - default: - break; - } - -} - -/** -* @brief MSC_BOT_CBW_Decode -* Decode the CBW command and set the BOT state machine accordingtly -* @param pdev: device instance -* @retval None -*/ -static void MSC_BOT_CBW_Decode (USB_OTG_CORE_HANDLE *pdev) -{ - - MSC_BOT_csw.dTag = MSC_BOT_cbw.dTag; - MSC_BOT_csw.dDataResidue = MSC_BOT_cbw.dDataLength; - - if ((USBD_GetRxCount (pdev ,MSC_OUT_EP) != BOT_CBW_LENGTH) || - (MSC_BOT_cbw.dSignature != BOT_CBW_SIGNATURE)|| - (MSC_BOT_cbw.bLUN > 1) || - (MSC_BOT_cbw.bCBLength < 1) || - (MSC_BOT_cbw.bCBLength > 16)) - { - - SCSI_SenseCode(MSC_BOT_cbw.bLUN, - ILLEGAL_REQUEST, - INVALID_CDB); - MSC_BOT_Status = BOT_STATE_ERROR; - MSC_BOT_Abort(pdev); - - } - else - { - if(SCSI_ProcessCmd(pdev, - MSC_BOT_cbw.bLUN, - &MSC_BOT_cbw.CB[0]) < 0) - { - MSC_BOT_Abort(pdev); - } - /*Burst xfer handled internally*/ - else if ((MSC_BOT_State != BOT_DATA_IN) && - (MSC_BOT_State != BOT_DATA_OUT) && - (MSC_BOT_State != BOT_LAST_DATA_IN)) - { - if (MSC_BOT_DataLen > 0) - { - MSC_BOT_SendData(pdev, - MSC_BOT_Data, - MSC_BOT_DataLen); - } - else if (MSC_BOT_DataLen == 0) - { - MSC_BOT_SendCSW (pdev, - CSW_CMD_PASSED); - } - } - } -} - -/** -* @brief MSC_BOT_SendData -* Send the requested data -* @param pdev: device instance -* @param buf: pointer to data buffer -* @param len: Data Length -* @retval None -*/ -static void MSC_BOT_SendData(USB_OTG_CORE_HANDLE *pdev, - uint8_t* buf, - uint16_t len) -{ - - len = MIN (MSC_BOT_cbw.dDataLength, len); - MSC_BOT_csw.dDataResidue -= len; - MSC_BOT_csw.bStatus = CSW_CMD_PASSED; - MSC_BOT_State = BOT_SEND_DATA; - - DCD_EP_Tx (pdev, MSC_IN_EP, buf, len); -} - -/** -* @brief MSC_BOT_SendCSW -* Send the Command Status Wrapper -* @param pdev: device instance -* @param status : CSW status -* @retval None -*/ -void MSC_BOT_SendCSW (USB_OTG_CORE_HANDLE *pdev, - uint8_t CSW_Status) -{ - MSC_BOT_csw.dSignature = BOT_CSW_SIGNATURE; - MSC_BOT_csw.bStatus = CSW_Status; - MSC_BOT_State = BOT_IDLE; - - DCD_EP_Tx (pdev, - MSC_IN_EP, - (uint8_t *)&MSC_BOT_csw, - BOT_CSW_LENGTH); - - /* Prapare EP to Receive next Cmd */ - DCD_EP_PrepareRx (pdev, - MSC_OUT_EP, - (uint8_t *)&MSC_BOT_cbw, - BOT_CBW_LENGTH); - -} - -/** -* @brief MSC_BOT_Abort -* Abort the current transfer -* @param pdev: device instance -* @retval status -*/ - -static void MSC_BOT_Abort (USB_OTG_CORE_HANDLE *pdev) -{ - - if ((MSC_BOT_cbw.bmFlags == 0) && - (MSC_BOT_cbw.dDataLength != 0) && - (MSC_BOT_Status == BOT_STATE_NORMAL) ) - { - DCD_EP_Stall(pdev, MSC_OUT_EP ); - } - DCD_EP_Stall(pdev, MSC_IN_EP); - - if(MSC_BOT_Status == BOT_STATE_ERROR) - { - DCD_EP_PrepareRx (pdev, - MSC_OUT_EP, - (uint8_t *)&MSC_BOT_cbw, - BOT_CBW_LENGTH); - } -} - -/** -* @brief MSC_BOT_CplClrFeature -* Complete the clear feature request -* @param pdev: device instance -* @param epnum: endpoint index -* @retval None -*/ - -void MSC_BOT_CplClrFeature (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum) -{ - if(MSC_BOT_Status == BOT_STATE_ERROR )/* Bad CBW Signature */ - { - DCD_EP_Stall(pdev, MSC_IN_EP); - MSC_BOT_Status = BOT_STATE_NORMAL; - } - else if(((epnum & 0x80) == 0x80) && ( MSC_BOT_Status != BOT_STATE_RECOVERY)) - { - MSC_BOT_SendCSW (pdev, CSW_CMD_FAILED); - } - -} -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmusbd/usbd_msc_bot.h b/stm/stmusbd/usbd_msc_bot.h deleted file mode 100644 index 53c95fbe4..000000000 --- a/stm/stmusbd/usbd_msc_bot.h +++ /dev/null @@ -1,153 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_msc_bot.h - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief header for the usbd_msc_bot.c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ - -#include "usbd_core.h" - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_MSC_BOT_H -#define __USBD_MSC_BOT_H - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup MSC_BOT - * @brief This file is the Header file for usbd_bot.c - * @{ - */ - - -/** @defgroup USBD_CORE_Exported_Defines - * @{ - */ -#define BOT_IDLE 0 /* Idle state */ -#define BOT_DATA_OUT 1 /* Data Out state */ -#define BOT_DATA_IN 2 /* Data In state */ -#define BOT_LAST_DATA_IN 3 /* Last Data In Last */ -#define BOT_SEND_DATA 4 /* Send Immediate data */ - -#define BOT_CBW_SIGNATURE 0x43425355 -#define BOT_CSW_SIGNATURE 0x53425355 -#define BOT_CBW_LENGTH 31 -#define BOT_CSW_LENGTH 13 - -/* CSW Status Definitions */ -#define CSW_CMD_PASSED 0x00 -#define CSW_CMD_FAILED 0x01 -#define CSW_PHASE_ERROR 0x02 - -/* BOT Status */ -#define BOT_STATE_NORMAL 0 -#define BOT_STATE_RECOVERY 1 -#define BOT_STATE_ERROR 2 - - -#define DIR_IN 0 -#define DIR_OUT 1 -#define BOTH_DIR 2 - -/** - * @} - */ - -/** @defgroup MSC_CORE_Private_TypesDefinitions - * @{ - */ - -typedef struct _MSC_BOT_CBW -{ - uint32_t dSignature; - uint32_t dTag; - uint32_t dDataLength; - uint8_t bmFlags; - uint8_t bLUN; - uint8_t bCBLength; - uint8_t CB[16]; -} -MSC_BOT_CBW_TypeDef; - - -typedef struct _MSC_BOT_CSW -{ - uint32_t dSignature; - uint32_t dTag; - uint32_t dDataResidue; - uint8_t bStatus; -} -MSC_BOT_CSW_TypeDef; - -/** - * @} - */ - - -/** @defgroup USBD_CORE_Exported_Types - * @{ - */ - -extern uint8_t MSC_BOT_Data[]; -extern uint16_t MSC_BOT_DataLen; -extern uint8_t MSC_BOT_State; -extern uint8_t MSC_BOT_BurstMode; -extern MSC_BOT_CBW_TypeDef MSC_BOT_cbw; -extern MSC_BOT_CSW_TypeDef MSC_BOT_csw; -/** - * @} - */ -/** @defgroup USBD_CORE_Exported_FunctionsPrototypes - * @{ - */ -void MSC_BOT_Init (USB_OTG_CORE_HANDLE *pdev); -void MSC_BOT_Reset (USB_OTG_CORE_HANDLE *pdev); -void MSC_BOT_DeInit (USB_OTG_CORE_HANDLE *pdev); -void MSC_BOT_DataIn (USB_OTG_CORE_HANDLE *pdev, - uint8_t epnum); - -void MSC_BOT_DataOut (USB_OTG_CORE_HANDLE *pdev, - uint8_t epnum); - -void MSC_BOT_SendCSW (USB_OTG_CORE_HANDLE *pdev, - uint8_t CSW_Status); - -void MSC_BOT_CplClrFeature (USB_OTG_CORE_HANDLE *pdev, - uint8_t epnum); -/** - * @} - */ - -#endif /* __USBD_MSC_BOT_H */ -/** - * @} - */ - -/** -* @} -*/ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/stm/stmusbd/usbd_msc_data.c b/stm/stmusbd/usbd_msc_data.c deleted file mode 100644 index 1dc7d22e7..000000000 --- a/stm/stmusbd/usbd_msc_data.c +++ /dev/null @@ -1,134 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_msc_data.c - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief This file provides all the vital inquiry pages and sense data. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_msc_data.h" - - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup MSC_DATA - * @brief Mass storage info/data module - * @{ - */ - -/** @defgroup MSC_DATA_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_DATA_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_DATA_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_DATA_Private_Variables - * @{ - */ - - -/* USB Mass storage Page 0 Inquiry Data */ -const uint8_t MSC_Page00_Inquiry_Data[] = {//7 - 0x00, - 0x00, - 0x00, - (LENGTH_INQUIRY_PAGE00 - 4), - 0x00, - 0x80, - 0x83 -}; -/* USB Mass storage sense 6 Data */ -const uint8_t MSC_Mode_Sense6_data[] = { - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00 -}; -/* USB Mass storage sense 10 Data */ -const uint8_t MSC_Mode_Sense10_data[] = { - 0x00, - 0x06, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00 -}; -/** - * @} - */ - - -/** @defgroup MSC_DATA_Private_FunctionPrototypes - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_DATA_Private_Functions - * @{ - */ - -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmusbd/usbd_msc_data.h b/stm/stmusbd/usbd_msc_data.h deleted file mode 100644 index 7c0d13679..000000000 --- a/stm/stmusbd/usbd_msc_data.h +++ /dev/null @@ -1,105 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_msc_data.h - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief header for the usbd_msc_data.c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ - -#ifndef _USBD_MSC_DATA_H_ -#define _USBD_MSC_DATA_H_ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_conf.h" -//#include "usbd_conf.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USB_INFO - * @brief general defines for the usb device library file - * @{ - */ - -/** @defgroup USB_INFO_Exported_Defines - * @{ - */ -#define MODE_SENSE6_LEN 8 -#define MODE_SENSE10_LEN 8 -#define LENGTH_INQUIRY_PAGE00 7 -#define LENGTH_FORMAT_CAPACITIES 20 - -/** - * @} - */ - - -/** @defgroup USBD_INFO_Exported_TypesDefinitions - * @{ - */ -/** - * @} - */ - - - -/** @defgroup USBD_INFO_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_INFO_Exported_Variables - * @{ - */ -extern const uint8_t MSC_Page00_Inquiry_Data[]; -extern const uint8_t MSC_Mode_Sense6_data[]; -extern const uint8_t MSC_Mode_Sense10_data[] ; - -/** - * @} - */ - -/** @defgroup USBD_INFO_Exported_FunctionsPrototype - * @{ - */ - -/** - * @} - */ - -#endif /* _USBD_MSC_DATA_H_ */ - -/** - * @} - */ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmusbd/usbd_msc_mem.h b/stm/stmusbd/usbd_msc_mem.h deleted file mode 100644 index 888c79674..000000000 --- a/stm/stmusbd/usbd_msc_mem.h +++ /dev/null @@ -1,113 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_msc_mem.h - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief header for the STORAGE DISK file file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ - -#ifndef __USBD_MEM_H -#define __USBD_MEM_H -/* Includes ------------------------------------------------------------------*/ -#include "usb_conf.h" -#include "usbd_def.h" - - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USBD_MEM - * @brief header file for the storage disk file - * @{ - */ - -/** @defgroup USBD_MEM_Exported_Defines - * @{ - */ -#define USBD_STD_INQUIRY_LENGTH 36 -/** - * @} - */ - - -/** @defgroup USBD_MEM_Exported_TypesDefinitions - * @{ - */ - -typedef struct _USBD_STORAGE -{ - int8_t (* Init) (uint8_t lun); - int8_t (* GetCapacity) (uint8_t lun, uint32_t *block_num, uint32_t *block_size); - int8_t (* IsReady) (uint8_t lun); - int8_t (* IsWriteProtected) (uint8_t lun); - int8_t (* Read) (uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len); - int8_t (* Write)(uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len); - int8_t (* GetMaxLun)(void); - int8_t *pInquiry; - -}USBD_STORAGE_cb_TypeDef; -/** - * @} - */ - - - -/** @defgroup USBD_MEM_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_MEM_Exported_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_MEM_Exported_FunctionsPrototype - * @{ - */ -extern USBD_STORAGE_cb_TypeDef *USBD_STORAGE_fops; -/** - * @} - */ - -#endif /* __USBD_MEM_H */ -/** - * @} - */ - -/** - * @} - */ - -/** -* @} -*/ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmusbd/usbd_msc_scsi.c b/stm/stmusbd/usbd_msc_scsi.c deleted file mode 100644 index e1e557f54..000000000 --- a/stm/stmusbd/usbd_msc_scsi.c +++ /dev/null @@ -1,729 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_msc_scsi.c - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief This file provides all the USBD SCSI layer functions. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_msc_bot.h" -#include "usbd_msc_scsi.h" -#include "usbd_msc_mem.h" -#include "usbd_msc_data.h" -#include "usbd_conf.h" - - - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup MSC_SCSI - * @brief Mass storage SCSI layer module - * @{ - */ - -/** @defgroup MSC_SCSI_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_SCSI_Private_Defines - * @{ - */ - -/** - * @} - */ - - -/** @defgroup MSC_SCSI_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_SCSI_Private_Variables - * @{ - */ - -SCSI_Sense_TypeDef SCSI_Sense [SENSE_LIST_DEEPTH]; -uint8_t SCSI_Sense_Head; -uint8_t SCSI_Sense_Tail; - -uint32_t SCSI_blk_size; -uint32_t SCSI_blk_nbr; - -uint32_t SCSI_blk_addr; -uint32_t SCSI_blk_len; - -USB_OTG_CORE_HANDLE *cdev; -/** - * @} - */ - - -/** @defgroup MSC_SCSI_Private_FunctionPrototypes - * @{ - */ -static int8_t SCSI_TestUnitReady(uint8_t lun, uint8_t *params); -static int8_t SCSI_Inquiry(uint8_t lun, uint8_t *params); -static int8_t SCSI_ReadFormatCapacity(uint8_t lun, uint8_t *params); -static int8_t SCSI_ReadCapacity10(uint8_t lun, uint8_t *params); -static int8_t SCSI_RequestSense (uint8_t lun, uint8_t *params); -static int8_t SCSI_StartStopUnit(uint8_t lun, uint8_t *params); -static int8_t SCSI_ModeSense6 (uint8_t lun, uint8_t *params); -static int8_t SCSI_ModeSense10 (uint8_t lun, uint8_t *params); -static int8_t SCSI_Write10(uint8_t lun , uint8_t *params); -static int8_t SCSI_Read10(uint8_t lun , uint8_t *params); -static int8_t SCSI_Verify10(uint8_t lun, uint8_t *params); -static int8_t SCSI_CheckAddressRange (uint8_t lun , - uint32_t blk_offset , - uint16_t blk_nbr); -static int8_t SCSI_ProcessRead (uint8_t lun); - -static int8_t SCSI_ProcessWrite (uint8_t lun); -/** - * @} - */ - - -/** @defgroup MSC_SCSI_Private_Functions - * @{ - */ - - -/** -* @brief SCSI_ProcessCmd -* Process SCSI commands -* @param pdev: device instance -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ -int8_t SCSI_ProcessCmd(USB_OTG_CORE_HANDLE *pdev, - uint8_t lun, - uint8_t *params) -{ - cdev = pdev; - - switch (params[0]) - { - case SCSI_TEST_UNIT_READY: - return SCSI_TestUnitReady(lun, params); - - case SCSI_REQUEST_SENSE: - return SCSI_RequestSense (lun, params); - case SCSI_INQUIRY: - return SCSI_Inquiry(lun, params); - - case SCSI_START_STOP_UNIT: - return SCSI_StartStopUnit(lun, params); - - case SCSI_ALLOW_MEDIUM_REMOVAL: - return SCSI_StartStopUnit(lun, params); - - case SCSI_MODE_SENSE6: - return SCSI_ModeSense6 (lun, params); - - case SCSI_MODE_SENSE10: - return SCSI_ModeSense10 (lun, params); - - case SCSI_READ_FORMAT_CAPACITIES: - return SCSI_ReadFormatCapacity(lun, params); - - case SCSI_READ_CAPACITY10: - return SCSI_ReadCapacity10(lun, params); - - case SCSI_READ10: - return SCSI_Read10(lun, params); - - case SCSI_WRITE10: - return SCSI_Write10(lun, params); - - case SCSI_VERIFY10: - return SCSI_Verify10(lun, params); - - default: - SCSI_SenseCode(lun, - ILLEGAL_REQUEST, - INVALID_CDB); - return -1; - } -} - - -/** -* @brief SCSI_TestUnitReady -* Process SCSI Test Unit Ready Command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ -static int8_t SCSI_TestUnitReady(uint8_t lun, uint8_t *params) -{ - - /* case 9 : Hi > D0 */ - if (MSC_BOT_cbw.dDataLength != 0) - { - SCSI_SenseCode(MSC_BOT_cbw.bLUN, - ILLEGAL_REQUEST, - INVALID_CDB); - return -1; - } - - if(USBD_STORAGE_fops->IsReady(lun) !=0 ) - { - SCSI_SenseCode(lun, - NOT_READY, - MEDIUM_NOT_PRESENT); - return -1; - } - MSC_BOT_DataLen = 0; - return 0; -} - -/** -* @brief SCSI_Inquiry -* Process Inquiry command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ -static int8_t SCSI_Inquiry(uint8_t lun, uint8_t *params) -{ - uint8_t* pPage; - uint16_t len; - - if (params[1] & 0x01)/*Evpd is set*/ - { - pPage = (uint8_t *)MSC_Page00_Inquiry_Data; - len = LENGTH_INQUIRY_PAGE00; - } - else - { - - pPage = (uint8_t *)&USBD_STORAGE_fops->pInquiry[lun * USBD_STD_INQUIRY_LENGTH]; - len = pPage[4] + 5; - - if (params[4] <= len) - { - len = params[4]; - } - } - MSC_BOT_DataLen = len; - - while (len) - { - len--; - MSC_BOT_Data[len] = pPage[len]; - } - return 0; -} - -/** -* @brief SCSI_ReadCapacity10 -* Process Read Capacity 10 command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ -static int8_t SCSI_ReadCapacity10(uint8_t lun, uint8_t *params) -{ - - if(USBD_STORAGE_fops->GetCapacity(lun, &SCSI_blk_nbr, &SCSI_blk_size) != 0) - { - SCSI_SenseCode(lun, - NOT_READY, - MEDIUM_NOT_PRESENT); - return -1; - } - else - { - - MSC_BOT_Data[0] = (uint8_t)((SCSI_blk_nbr - 1) >> 24); // dpgeorge added paren - MSC_BOT_Data[1] = (uint8_t)((SCSI_blk_nbr - 1) >> 16); // dpgeorge added paren - MSC_BOT_Data[2] = (uint8_t)((SCSI_blk_nbr - 1) >> 8); // dpgeorge added paren - MSC_BOT_Data[3] = (uint8_t)(SCSI_blk_nbr - 1); - - MSC_BOT_Data[4] = (uint8_t)(SCSI_blk_size >> 24); - MSC_BOT_Data[5] = (uint8_t)(SCSI_blk_size >> 16); - MSC_BOT_Data[6] = (uint8_t)(SCSI_blk_size >> 8); - MSC_BOT_Data[7] = (uint8_t)(SCSI_blk_size); - - MSC_BOT_DataLen = 8; - return 0; - } -} -/** -* @brief SCSI_ReadFormatCapacity -* Process Read Format Capacity command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ -static int8_t SCSI_ReadFormatCapacity(uint8_t lun, uint8_t *params) -{ - - uint32_t blk_size; - uint32_t blk_nbr; - uint16_t i; - - for(i=0 ; i < 12 ; i++) - { - MSC_BOT_Data[i] = 0; - } - - if(USBD_STORAGE_fops->GetCapacity(lun, &blk_nbr, &blk_size) != 0) - { - SCSI_SenseCode(lun, - NOT_READY, - MEDIUM_NOT_PRESENT); - return -1; - } - else - { - MSC_BOT_Data[3] = 0x08; - MSC_BOT_Data[4] = (uint8_t)((blk_nbr - 1) >> 24); // dpgeorge added paren - MSC_BOT_Data[5] = (uint8_t)((blk_nbr - 1) >> 16); // dpgeorge added paren - MSC_BOT_Data[6] = (uint8_t)((blk_nbr - 1) >> 8); // dpgeorge added paren - MSC_BOT_Data[7] = (uint8_t)(blk_nbr - 1); - - MSC_BOT_Data[8] = 0x02; - MSC_BOT_Data[9] = (uint8_t)(blk_size >> 16); - MSC_BOT_Data[10] = (uint8_t)(blk_size >> 8); - MSC_BOT_Data[11] = (uint8_t)(blk_size); - - MSC_BOT_DataLen = 12; - return 0; - } -} -/** -* @brief SCSI_ModeSense6 -* Process Mode Sense6 command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ -static int8_t SCSI_ModeSense6 (uint8_t lun, uint8_t *params) -{ - - uint16_t len = 8 ; - MSC_BOT_DataLen = len; - - while (len) - { - len--; - MSC_BOT_Data[len] = MSC_Mode_Sense6_data[len]; - } - return 0; -} - -/** -* @brief SCSI_ModeSense10 -* Process Mode Sense10 command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ -static int8_t SCSI_ModeSense10 (uint8_t lun, uint8_t *params) -{ - uint16_t len = 8; - - MSC_BOT_DataLen = len; - - while (len) - { - len--; - MSC_BOT_Data[len] = MSC_Mode_Sense10_data[len]; - } - return 0; -} - -/** -* @brief SCSI_RequestSense -* Process Request Sense command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ - -static int8_t SCSI_RequestSense (uint8_t lun, uint8_t *params) -{ - uint8_t i; - - for(i=0 ; i < REQUEST_SENSE_DATA_LEN ; i++) - { - MSC_BOT_Data[i] = 0; - } - - MSC_BOT_Data[0] = 0x70; - MSC_BOT_Data[7] = REQUEST_SENSE_DATA_LEN - 6; - - if((SCSI_Sense_Head != SCSI_Sense_Tail)) { - - MSC_BOT_Data[2] = SCSI_Sense[SCSI_Sense_Head].Skey; - MSC_BOT_Data[12] = SCSI_Sense[SCSI_Sense_Head].w.b.ASCQ; - MSC_BOT_Data[13] = SCSI_Sense[SCSI_Sense_Head].w.b.ASC; - SCSI_Sense_Head++; - - if (SCSI_Sense_Head == SENSE_LIST_DEEPTH) - { - SCSI_Sense_Head = 0; - } - } - MSC_BOT_DataLen = REQUEST_SENSE_DATA_LEN; - - if (params[4] <= REQUEST_SENSE_DATA_LEN) - { - MSC_BOT_DataLen = params[4]; - } - return 0; -} - -/** -* @brief SCSI_SenseCode -* Load the last error code in the error list -* @param lun: Logical unit number -* @param sKey: Sense Key -* @param ASC: Additional Sense Key -* @retval none - -*/ -void SCSI_SenseCode(uint8_t lun, uint8_t sKey, uint8_t ASC) -{ - SCSI_Sense[SCSI_Sense_Tail].Skey = sKey; - SCSI_Sense[SCSI_Sense_Tail].w.ASC = ASC << 8; - SCSI_Sense_Tail++; - if (SCSI_Sense_Tail == SENSE_LIST_DEEPTH) - { - SCSI_Sense_Tail = 0; - } -} -/** -* @brief SCSI_StartStopUnit -* Process Start Stop Unit command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ -static int8_t SCSI_StartStopUnit(uint8_t lun, uint8_t *params) -{ - MSC_BOT_DataLen = 0; - return 0; -} - -/** -* @brief SCSI_Read10 -* Process Read10 command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ -static int8_t SCSI_Read10(uint8_t lun , uint8_t *params) -{ - if(MSC_BOT_State == BOT_IDLE) /* Idle */ - { - - /* case 10 : Ho <> Di */ - - if ((MSC_BOT_cbw.bmFlags & 0x80) != 0x80) - { - SCSI_SenseCode(MSC_BOT_cbw.bLUN, - ILLEGAL_REQUEST, - INVALID_CDB); - return -1; - } - - if(USBD_STORAGE_fops->IsReady(lun) !=0 ) - { - SCSI_SenseCode(lun, - NOT_READY, - MEDIUM_NOT_PRESENT); - return -1; - } - - SCSI_blk_addr = (params[2] << 24) | \ - (params[3] << 16) | \ - (params[4] << 8) | \ - params[5]; - - SCSI_blk_len = (params[7] << 8) | \ - params[8]; - - - - if( SCSI_CheckAddressRange(lun, SCSI_blk_addr, SCSI_blk_len) < 0) - { - return -1; /* error */ - } - - MSC_BOT_State = BOT_DATA_IN; - SCSI_blk_addr *= SCSI_blk_size; - SCSI_blk_len *= SCSI_blk_size; - - /* cases 4,5 : Hi <> Dn */ - if (MSC_BOT_cbw.dDataLength != SCSI_blk_len) - { - SCSI_SenseCode(MSC_BOT_cbw.bLUN, - ILLEGAL_REQUEST, - INVALID_CDB); - return -1; - } - } - MSC_BOT_DataLen = MSC_MEDIA_PACKET; - - return SCSI_ProcessRead(lun); -} - -/** -* @brief SCSI_Write10 -* Process Write10 command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ - -static int8_t SCSI_Write10 (uint8_t lun , uint8_t *params) -{ - if (MSC_BOT_State == BOT_IDLE) /* Idle */ - { - - /* case 8 : Hi <> Do */ - - if ((MSC_BOT_cbw.bmFlags & 0x80) == 0x80) - { - SCSI_SenseCode(MSC_BOT_cbw.bLUN, - ILLEGAL_REQUEST, - INVALID_CDB); - return -1; - } - - /* Check whether Media is ready */ - if(USBD_STORAGE_fops->IsReady(lun) !=0 ) - { - SCSI_SenseCode(lun, - NOT_READY, - MEDIUM_NOT_PRESENT); - return -1; - } - - /* Check If media is write-protected */ - if(USBD_STORAGE_fops->IsWriteProtected(lun) !=0 ) - { - SCSI_SenseCode(lun, - NOT_READY, - WRITE_PROTECTED); - return -1; - } - - - SCSI_blk_addr = (params[2] << 24) | \ - (params[3] << 16) | \ - (params[4] << 8) | \ - params[5]; - SCSI_blk_len = (params[7] << 8) | \ - params[8]; - - /* check if LBA address is in the right range */ - if(SCSI_CheckAddressRange(lun, SCSI_blk_addr, SCSI_blk_len) < 0) - { - return -1; /* error */ - } - - SCSI_blk_addr *= SCSI_blk_size; - SCSI_blk_len *= SCSI_blk_size; - - /* cases 3,11,13 : Hn,Ho <> D0 */ - if (MSC_BOT_cbw.dDataLength != SCSI_blk_len) - { - SCSI_SenseCode(MSC_BOT_cbw.bLUN, - ILLEGAL_REQUEST, - INVALID_CDB); - return -1; - } - - /* Prepare EP to receive first data packet */ - MSC_BOT_State = BOT_DATA_OUT; - DCD_EP_PrepareRx (cdev, - MSC_OUT_EP, - MSC_BOT_Data, - MIN (SCSI_blk_len, MSC_MEDIA_PACKET)); - } - else /* Write Process ongoing */ - { - return SCSI_ProcessWrite(lun); - } - return 0; -} - - -/** -* @brief SCSI_Verify10 -* Process Verify10 command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ - -static int8_t SCSI_Verify10(uint8_t lun , uint8_t *params){ - if ((params[1]& 0x02) == 0x02) - { - SCSI_SenseCode (lun, ILLEGAL_REQUEST, INVALID_FIELED_IN_COMMAND); - return -1; /* Error, Verify Mode Not supported*/ - } - - if(SCSI_CheckAddressRange(lun, SCSI_blk_addr, SCSI_blk_len) < 0) - { - return -1; /* error */ - } - MSC_BOT_DataLen = 0; - return 0; -} - -/** -* @brief SCSI_CheckAddressRange -* Check address range -* @param lun: Logical unit number -* @param blk_offset: first block address -* @param blk_nbr: number of block to be processed -* @retval status -*/ -static int8_t SCSI_CheckAddressRange (uint8_t lun , uint32_t blk_offset , uint16_t blk_nbr) -{ - - if ((blk_offset + blk_nbr) > SCSI_blk_nbr ) - { - SCSI_SenseCode(lun, ILLEGAL_REQUEST, ADDRESS_OUT_OF_RANGE); - return -1; - } - return 0; -} - -/** -* @brief SCSI_ProcessRead -* Handle Read Process -* @param lun: Logical unit number -* @retval status -*/ -static int8_t SCSI_ProcessRead (uint8_t lun) -{ - uint32_t len; - - len = MIN(SCSI_blk_len , MSC_MEDIA_PACKET); - - if( USBD_STORAGE_fops->Read(lun , - MSC_BOT_Data, - SCSI_blk_addr / SCSI_blk_size, - len / SCSI_blk_size) < 0) - { - - SCSI_SenseCode(lun, HARDWARE_ERROR, UNRECOVERED_READ_ERROR); - return -1; - } - - - DCD_EP_Tx (cdev, - MSC_IN_EP, - MSC_BOT_Data, - len); - - - SCSI_blk_addr += len; - SCSI_blk_len -= len; - - /* case 6 : Hi = Di */ - MSC_BOT_csw.dDataResidue -= len; - - if (SCSI_blk_len == 0) - { - MSC_BOT_State = BOT_LAST_DATA_IN; - } - return 0; -} - -/** -* @brief SCSI_ProcessWrite -* Handle Write Process -* @param lun: Logical unit number -* @retval status -*/ - -static int8_t SCSI_ProcessWrite (uint8_t lun) -{ - uint32_t len; - - len = MIN(SCSI_blk_len , MSC_MEDIA_PACKET); - - if(USBD_STORAGE_fops->Write(lun , - MSC_BOT_Data, - SCSI_blk_addr / SCSI_blk_size, - len / SCSI_blk_size) < 0) - { - SCSI_SenseCode(lun, HARDWARE_ERROR, WRITE_FAULT); - return -1; - } - - - SCSI_blk_addr += len; - SCSI_blk_len -= len; - - /* case 12 : Ho = Do */ - MSC_BOT_csw.dDataResidue -= len; - - if (SCSI_blk_len == 0) - { - MSC_BOT_SendCSW (cdev, CSW_CMD_PASSED); - } - else - { - /* Prapare EP to Receive next packet */ - DCD_EP_PrepareRx (cdev, - MSC_OUT_EP, - MSC_BOT_Data, - MIN (SCSI_blk_len, MSC_MEDIA_PACKET)); - } - - return 0; -} -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmusbd/usbd_msc_scsi.h b/stm/stmusbd/usbd_msc_scsi.h deleted file mode 100644 index 1b8e35af1..000000000 --- a/stm/stmusbd/usbd_msc_scsi.h +++ /dev/null @@ -1,195 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_msc_scsi.h - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief header for the usbd_msc_scsi.c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_MSC_SCSI_H -#define __USBD_MSC_SCSI_H - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_def.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USBD_SCSI - * @brief header file for the storage disk file - * @{ - */ - -/** @defgroup USBD_SCSI_Exported_Defines - * @{ - */ - -#define SENSE_LIST_DEEPTH 4 - -/* SCSI Commands */ -#define SCSI_FORMAT_UNIT 0x04 -#define SCSI_INQUIRY 0x12 -#define SCSI_MODE_SELECT6 0x15 -#define SCSI_MODE_SELECT10 0x55 -#define SCSI_MODE_SENSE6 0x1A -#define SCSI_MODE_SENSE10 0x5A -#define SCSI_ALLOW_MEDIUM_REMOVAL 0x1E -#define SCSI_READ6 0x08 -#define SCSI_READ10 0x28 -#define SCSI_READ12 0xA8 -#define SCSI_READ16 0x88 - -#define SCSI_READ_CAPACITY10 0x25 -#define SCSI_READ_CAPACITY16 0x9E - -#define SCSI_REQUEST_SENSE 0x03 -#define SCSI_START_STOP_UNIT 0x1B -#define SCSI_TEST_UNIT_READY 0x00 -#define SCSI_WRITE6 0x0A -#define SCSI_WRITE10 0x2A -#define SCSI_WRITE12 0xAA -#define SCSI_WRITE16 0x8A - -#define SCSI_VERIFY10 0x2F -#define SCSI_VERIFY12 0xAF -#define SCSI_VERIFY16 0x8F - -#define SCSI_SEND_DIAGNOSTIC 0x1D -#define SCSI_READ_FORMAT_CAPACITIES 0x23 - -#define NO_SENSE 0 -#define RECOVERED_ERROR 1 -#define NOT_READY 2 -#define MEDIUM_ERROR 3 -#define HARDWARE_ERROR 4 -#define ILLEGAL_REQUEST 5 -#define UNIT_ATTENTION 6 -#define DATA_PROTECT 7 -#define BLANK_CHECK 8 -#define VENDOR_SPECIFIC 9 -#define COPY_ABORTED 10 -#define ABORTED_COMMAND 11 -#define VOLUME_OVERFLOW 13 -#define MISCOMPARE 14 - - -#define INVALID_CDB 0x20 -#define INVALID_FIELED_IN_COMMAND 0x24 -#define PARAMETER_LIST_LENGTH_ERROR 0x1A -#define INVALID_FIELD_IN_PARAMETER_LIST 0x26 -#define ADDRESS_OUT_OF_RANGE 0x21 -#define MEDIUM_NOT_PRESENT 0x3A -#define MEDIUM_HAVE_CHANGED 0x28 -#define WRITE_PROTECTED 0x27 -#define UNRECOVERED_READ_ERROR 0x11 -#define WRITE_FAULT 0x03 - -#define READ_FORMAT_CAPACITY_DATA_LEN 0x0C -#define READ_CAPACITY10_DATA_LEN 0x08 -#define MODE_SENSE10_DATA_LEN 0x08 -#define MODE_SENSE6_DATA_LEN 0x04 -#define REQUEST_SENSE_DATA_LEN 0x12 -#define STANDARD_INQUIRY_DATA_LEN 0x24 -#define BLKVFY 0x04 - -extern uint8_t Page00_Inquiry_Data[]; -extern uint8_t Standard_Inquiry_Data[]; -extern uint8_t Standard_Inquiry_Data2[]; -extern uint8_t Mode_Sense6_data[]; -extern uint8_t Mode_Sense10_data[]; -extern uint8_t Scsi_Sense_Data[]; -extern uint8_t ReadCapacity10_Data[]; -extern uint8_t ReadFormatCapacity_Data []; -/** - * @} - */ - - -/** @defgroup USBD_SCSI_Exported_TypesDefinitions - * @{ - */ - -typedef struct _SENSE_ITEM { - char Skey; - union { - struct _ASCs { - char ASC; - char ASCQ; - }b; - unsigned int ASC; - char *pData; - } w; -} SCSI_Sense_TypeDef; -/** - * @} - */ - -/** @defgroup USBD_SCSI_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_SCSI_Exported_Variables - * @{ - */ -extern SCSI_Sense_TypeDef SCSI_Sense [SENSE_LIST_DEEPTH]; -extern uint8_t SCSI_Sense_Head; -extern uint8_t SCSI_Sense_Tail; - -/** - * @} - */ -/** @defgroup USBD_SCSI_Exported_FunctionsPrototype - * @{ - */ -int8_t SCSI_ProcessCmd(USB_OTG_CORE_HANDLE *pdev, - uint8_t lun, - uint8_t *cmd); - -void SCSI_SenseCode(uint8_t lun, - uint8_t sKey, - uint8_t ASC); - -/** - * @} - */ - -#endif /* __USBD_MSC_SCSI_H */ -/** - * @} - */ - -/** - * @} - */ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/stm/stmusbd/usbd_pyb_core.c b/stm/stmusbd/usbd_pyb_core.c deleted file mode 100644 index 5fcf9bb18..000000000 --- a/stm/stmusbd/usbd_pyb_core.c +++ /dev/null @@ -1,958 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_cdc_core.c - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief This file provides the high layer firmware functions to manage the - * following functionalities of the USB CDC Class: - * - Initialization and Configuration of high and low layer - * - Enumeration as CDC Device (and enumeration for each implemented memory interface) - * - OUT/IN data transfer - * - Command IN transfer (class requests management) - * - Error management - * - * @verbatim - * - * =================================================================== - * CDC Class Driver Description - * =================================================================== - * This driver manages the "Universal Serial Bus Class Definitions for Communications Devices - * Revision 1.2 November 16, 2007" and the sub-protocol specification of "Universal Serial Bus - * Communications Class Subclass Specification for PSTN Devices Revision 1.2 February 9, 2007" - * This driver implements the following aspects of the specification: - * - Device descriptor management - * - Configuration descriptor management - * - Enumeration as CDC device with 2 data endpoints (IN and OUT) and 1 command endpoint (IN) - * - Requests management (as described in section 6.2 in specification) - * - Abstract Control Model compliant - * - Union Functional collection (using 1 IN endpoint for control) - * - Data interface class - - * @note - * For the Abstract Control Model, this core allows only transmitting the requests to - * lower layer dispatcher (ie. usbd_cdc_vcp.c/.h) which should manage each request and - * perform relative actions. - * - * These aspects may be enriched or modified for a specific user application. - * - * This driver doesn't implement the following aspects of the specification - * (but it is possible to manage these features with some modifications on this driver): - * - Any class-specific aspect relative to communication classes should be managed by user application. - * - All communication classes other than PSTN are not managed - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include - -#include "usbd_cdc_core.h" -#include "usbd_desc.h" -#include "usbd_req.h" -#include "usbd_conf.h" -#include "usbd_msc_bot.h" -#include "usbd_msc_mem.h" - -// CDC VCP is the first interface -// the option below is supposed to select between MSC (1) and HID (0) for the -// second USB interface, but it does not work (only VCP+MSC works) -// to use HID on its own (ie no VCP), the functions in usbd_pyb_core2.c can be -// used, and selected in the call to pyb_usb_dev_init(). -#define USB_PYB_USE_MSC (1) - -#if USB_PYB_USE_MSC -//#define USB_PYB_CONFIG_DESC_SIZ (67) // for only CDC VCP interfaces -#define USB_PYB_CONFIG_DESC_SIZ (98) // for both CDC VCP and MSC interfaces -#else // USE_HID -#define USB_PYB_CONFIG_DESC_SIZ (100) // for both CDC VCP and HID interfaces -#endif - -#define MSC_EPIN_SIZE MSC_MAX_PACKET -#define MSC_EPOUT_SIZE MSC_MAX_PACKET - -#define HID_MOUSE_REPORT_DESC_SIZE (74) - -#define HID_DESCRIPTOR_TYPE 0x21 -#define HID_REPORT_DESC 0x22 - -// HID parameters -#define HID_IN_EP (0x83) -#define HID_IN_PACKET (4) /* maximum, and actual, packet size */ - -/********************************************* - PYB Device library callbacks - *********************************************/ -static uint8_t usbd_pyb_Init (void *pdev, uint8_t cfgidx); -static uint8_t usbd_pyb_DeInit (void *pdev, uint8_t cfgidx); -static uint8_t usbd_pyb_Setup (void *pdev, USB_SETUP_REQ *req); -static uint8_t usbd_pyb_EP0_RxReady (void *pdev); -static uint8_t usbd_pyb_DataIn (void *pdev, uint8_t epnum); -static uint8_t usbd_pyb_DataOut (void *pdev, uint8_t epnum); -static uint8_t usbd_pyb_SOF (void *pdev); - -/********************************************* - PYB specific management functions - *********************************************/ -static void Handle_USBAsynchXfer (void *pdev); -static uint8_t *usbd_pyb_GetCfgDesc (uint8_t speed, uint16_t *length); - -/** @defgroup usbd_cdc_Private_Variables - * @{ - */ -extern CDC_IF_Prop_TypeDef VCP_fops; -extern uint8_t USBD_DeviceDesc [USB_SIZ_DEVICE_DESC]; - -__ALIGN_BEGIN static uint8_t usbd_cdc_AltSet __ALIGN_END = 0; -__ALIGN_BEGIN static uint8_t USB_Rx_Buffer[CDC_DATA_MAX_PACKET_SIZE] __ALIGN_END; -__ALIGN_BEGIN uint8_t APP_Rx_Buffer[APP_RX_DATA_SIZE] __ALIGN_END; - -__ALIGN_BEGIN static uint8_t CmdBuff[CDC_CMD_PACKET_SZE] __ALIGN_END; - -#if USB_PYB_USE_MSC -__ALIGN_BEGIN static uint8_t USBD_MSC_MaxLun __ALIGN_END = 0; -__ALIGN_BEGIN static uint8_t USBD_MSC_AltSet __ALIGN_END = 0; -#else -__ALIGN_BEGIN static uint8_t USBD_HID_AltSet __ALIGN_END = 0; -__ALIGN_BEGIN static uint8_t USBD_HID_Protocol __ALIGN_END = 0; -__ALIGN_BEGIN static uint8_t USBD_HID_IdleState __ALIGN_END = 0; -#endif - -uint32_t APP_Rx_ptr_in = 0; -uint32_t APP_Rx_ptr_out = 0; -uint32_t APP_Rx_length = 0; - -uint8_t USB_Tx_State = 0; - -static uint32_t cdcCmd = 0xFF; -static uint32_t cdcLen = 0; - -/* PYB interface class callbacks structure */ -USBD_Class_cb_TypeDef USBD_PYB_cb = -{ - usbd_pyb_Init, - usbd_pyb_DeInit, - usbd_pyb_Setup, - NULL, // EP0_TxSent - usbd_pyb_EP0_RxReady, - usbd_pyb_DataIn, - usbd_pyb_DataOut, - usbd_pyb_SOF, - NULL, // IsoINIncomplete - NULL, // IsoOUTIncomplete - usbd_pyb_GetCfgDesc, - // for OTG_HS support need to add other cfg desc here -}; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -/* USB PYB device Configuration Descriptor */ -__ALIGN_BEGIN static uint8_t usbd_pyb_CfgDesc[USB_PYB_CONFIG_DESC_SIZ] __ALIGN_END = -{ - //-------------------------------------------------------------------------- - // Configuration Descriptor - 0x09, // bLength: Configuration Descriptor size - USB_CONFIGURATION_DESCRIPTOR_TYPE, // bDescriptorType: Configuration - LOBYTE(USB_PYB_CONFIG_DESC_SIZ), // wTotalLength: no of returned bytes - HIBYTE(USB_PYB_CONFIG_DESC_SIZ), - 0x03, // bNumInterfaces: 3 interfaces - 0x01, // bConfigurationValue: Configuration value - 0x04, // iConfiguration: Index of string descriptor describing the configuration - 0x80, // bmAttributes: bus powered; 0xc0 for self powered - 0xfa, // bMaxPower: in units of 2mA - - //========================================================================== - // Interface Association for CDC VCP - 0x08, // bLength: 8 bytes - USB_INTERFACE_ASSOCIATION_TYPE, // bDescriptorType: IAD - 0x00, // bFirstInterface: first interface for this association - 0x02, // bInterfaceCount: nummber of interfaces for this association - 0x00, // bFunctionClass: ? - 0x00, // bFunctionSubClass: ? - 0x00, // bFunctionProtocol: ? - 0x04, // iFunction: index of string for this function - - //-------------------------------------------------------------------------- - // Interface Descriptor - 0x09, // bLength: Interface Descriptor size - USB_INTERFACE_DESCRIPTOR_TYPE, // bDescriptorType: Interface - 0x00, // bInterfaceNumber: Number of Interface - 0x00, // bAlternateSetting: Alternate setting - 0x01, // bNumEndpoints: One endpoints used - 0x02, // bInterfaceClass: Communication Interface Class - 0x02, // bInterfaceSubClass: Abstract Control Model - 0x01, // bInterfaceProtocol: Common AT commands - 0x00, // iInterface: - - // Header Functional Descriptor - 0x05, // bLength: Endpoint Descriptor size - 0x24, // bDescriptorType: CS_INTERFACE - 0x00, // bDescriptorSubtype: Header Func Desc - 0x10, // bcdCDC: spec release number - 0x01, // ? - - // Call Management Functional Descriptor - 0x05, // bFunctionLength - 0x24, // bDescriptorType: CS_INTERFACE - 0x01, // bDescriptorSubtype: Call Management Func Desc - 0x00, // bmCapabilities: D0+D1 - 0x01, // bDataInterface: 1 - - // ACM Functional Descriptor - 0x04, // bFunctionLength - 0x24, // bDescriptorType: CS_INTERFACE - 0x02, // bDescriptorSubtype: Abstract Control Management desc - 0x02, // bmCapabilities - - // Union Functional Descriptor - 0x05, // bFunctionLength - 0x24, // bDescriptorType: CS_INTERFACE - 0x06, // bDescriptorSubtype: Union func desc - 0x00, // bMasterInterface: Communication class interface - 0x01, // bSlaveInterface0: Data Class Interface - - // Endpoint 2 Descriptor - 0x07, // bLength: Endpoint Descriptor size - USB_ENDPOINT_DESCRIPTOR_TYPE, // bDescriptorType: Endpoint - CDC_CMD_EP, // bEndpointAddress - 0x03, // bmAttributes: Interrupt - LOBYTE(CDC_CMD_PACKET_SZE), // wMaxPacketSize: - HIBYTE(CDC_CMD_PACKET_SZE), - 0x80, // bInterval: polling interval in frames of 1ms - - //-------------------------------------------------------------------------- - // Data class interface descriptor - 0x09, // bLength: Endpoint Descriptor size - USB_INTERFACE_DESCRIPTOR_TYPE, // bDescriptorType: interface - 0x01, // bInterfaceNumber: Number of Interface - 0x00, // bAlternateSetting: Alternate setting - 0x02, // bNumEndpoints: Two endpoints used - 0x0A, // bInterfaceClass: CDC - 0x00, // bInterfaceSubClass: ? - 0x00, // bInterfaceProtocol: ? - 0x00, // iInterface: - - // Endpoint OUT Descriptor - 0x07, // bLength: Endpoint Descriptor size - USB_ENDPOINT_DESCRIPTOR_TYPE, // bDescriptorType: Endpoint - CDC_OUT_EP, // bEndpointAddress - 0x02, // bmAttributes: Bulk - LOBYTE(CDC_DATA_MAX_PACKET_SIZE), // wMaxPacketSize: - HIBYTE(CDC_DATA_MAX_PACKET_SIZE), - 0x00, // bInterval: ignore for Bulk transfer - - // Endpoint IN Descriptor - 0x07, // bLength: Endpoint Descriptor size - USB_ENDPOINT_DESCRIPTOR_TYPE, // bDescriptorType: Endpoint - CDC_IN_EP, // bEndpointAddress - 0x02, // bmAttributes: Bulk - LOBYTE(CDC_DATA_MAX_PACKET_SIZE), // wMaxPacketSize: - HIBYTE(CDC_DATA_MAX_PACKET_SIZE), - 0x00, // bInterval: ignore for Bulk transfer - -#if USB_PYB_USE_MSC - //========================================================================== - // MSC only has 1 interface so doesn't need an IAD - - //-------------------------------------------------------------------------- - // Interface Descriptor - 0x09, // bLength: Interface Descriptor size - USB_INTERFACE_DESCRIPTOR_TYPE, // bDescriptorType: interface descriptor - 0x02, // bInterfaceNumber: Number of Interface - 0x00, // bAlternateSetting: Alternate setting - 0x02, // bNumEndpoints - 0x08, // bInterfaceClass: MSC Class - 0x06, // bInterfaceSubClass : SCSI transparent - 0x50, // nInterfaceProtocol - 0x00, // iInterface: - - // Endpoint IN descriptor - 0x07, // bLength: Endpoint descriptor length - USB_ENDPOINT_DESCRIPTOR_TYPE, // bDescriptorType: Endpoint descriptor type - MSC_IN_EP, // bEndpointAddress: IN, address 3 - 0x02, // bmAttributes: Bulk endpoint type - LOBYTE(MSC_MAX_PACKET), // wMaxPacketSize - HIBYTE(MSC_MAX_PACKET), - 0x00, // bInterval: ignore for Bulk transfer - - // Endpoint OUT descriptor - 0x07, // bLength: Endpoint descriptor length - USB_ENDPOINT_DESCRIPTOR_TYPE, // bDescriptorType: Endpoint descriptor type - MSC_OUT_EP, // bEndpointAddress: OUT, address 3 - 0x02, // bmAttributes: Bulk endpoint type - LOBYTE(MSC_MAX_PACKET), // wMaxPacketSize - HIBYTE(MSC_MAX_PACKET), - 0x00, // bInterval: ignore for Bulk transfer - -#else - //========================================================================== - // HID only has 1 interface so doesn't need an IAD - - //-------------------------------------------------------------------------- - // Interface Descriptor - 0x09, // bLength: Interface Descriptor size - USB_INTERFACE_DESCRIPTOR_TYPE, // bDescriptorType: interface descriptor - 0x02, // bInterfaceNumber: Number of Interface - 0x00, // bAlternateSetting: Alternate setting - 0x01, // bNumEndpoints - 0x03, // bInterfaceClass: HID Class - 0x01, // bInterfaceSubClass: 0=no boot, 1=BOOT - 0x02, // nInterfaceProtocol: 0=none, 1=keyboard, 2=mouse - 0x00, // iInterface: - - // Descriptor of Joystick Mouse HID - 0x09, // bLength: HID Descriptor size - HID_DESCRIPTOR_TYPE, // bDescriptorType: HID - 0x11, // bcdHID: HID Class Spec release number, low byte - 0x01, // bcdHID: high byte - 0x00, // bCountryCode: Hardware target country (0=unsupported) - 0x01, // bNumDescriptors: Number of HID class descriptors to follow - HID_REPORT_DESC, // bDescriptorType: report - HID_MOUSE_REPORT_DESC_SIZE, // wItemLength: Total length of Report descriptor - 0x00, - - // Endpoint IN descriptor - 0x07, // bLength: Endpoint descriptor length - USB_ENDPOINT_DESCRIPTOR_TYPE, // bDescriptorType: Endpoint descriptor type - HID_IN_EP, // bEndpointAddress: IN, address of HID - 0x03, // bmAttributes: Interrupt endpoint type - LOBYTE(HID_IN_PACKET), // wMaxPacketSize - HIBYTE(HID_IN_PACKET), - 0x0a, // bInterval: polling interval, units of 1ms - -#endif -}; - -#if !USB_PYB_USE_MSC -__ALIGN_BEGIN static uint8_t HID_MOUSE_ReportDesc[HID_MOUSE_REPORT_DESC_SIZE] __ALIGN_END = -{ - 0x05, 0x01, - 0x09, 0x02, - 0xA1, 0x01, - 0x09, 0x01, - - 0xA1, 0x00, - 0x05, 0x09, - 0x19, 0x01, - 0x29, 0x03, - - 0x15, 0x00, - 0x25, 0x01, - 0x95, 0x03, - 0x75, 0x01, - - 0x81, 0x02, - 0x95, 0x01, - 0x75, 0x05, - 0x81, 0x01, - - 0x05, 0x01, - 0x09, 0x30, - 0x09, 0x31, - 0x09, 0x38, - - 0x15, 0x81, - 0x25, 0x7F, - 0x75, 0x08, - 0x95, 0x03, - - 0x81, 0x06, - 0xC0, 0x09, - 0x3c, 0x05, - 0xff, 0x09, - - 0x01, 0x15, - 0x00, 0x25, - 0x01, 0x75, - 0x01, 0x95, - - 0x02, 0xb1, - 0x22, 0x75, - 0x06, 0x95, - 0x01, 0xb1, - - 0x01, 0xc0 -}; -#endif - -/** @defgroup usbd_pyb_Private_Functions - * @{ - */ - -/** - * @brief usbd_pyb_Init - * Initilaize the PYB interface - * @param pdev: device instance - * @param cfgidx: Configuration index - * @retval status - */ -static uint8_t usbd_pyb_Init(void *pdev, uint8_t cfgidx) { - // deinit first to reset - usbd_pyb_DeInit(pdev, cfgidx); - - //---------------------------------- - // CDC VCP component - - // Open EP IN - DCD_EP_Open(pdev, - CDC_IN_EP, - CDC_DATA_IN_PACKET_SIZE, - USB_OTG_EP_BULK); - - // Open EP OUT - DCD_EP_Open(pdev, - CDC_OUT_EP, - CDC_DATA_OUT_PACKET_SIZE, - USB_OTG_EP_BULK); - - // Open Command IN EP - DCD_EP_Open(pdev, - CDC_CMD_EP, - CDC_CMD_PACKET_SZE, - USB_OTG_EP_INT); - - /* - // can use this to dynamically set the device class - uint8_t *pbuf = USBD_DeviceDesc; - pbuf[4] = DEVICE_CLASS_CDC; - pbuf[5] = DEVICE_SUBCLASS_CDC; - */ - - // Initialize the Interface physical components - VCP_fops.pIf_Init(); - - // Prepare Out endpoint to receive next packet */ - DCD_EP_PrepareRx(pdev, - CDC_OUT_EP, - (uint8_t*)(USB_Rx_Buffer), - CDC_DATA_OUT_PACKET_SIZE); - -#if USB_PYB_USE_MSC - //---------------------------------- - // MSC component - - // Open EP IN - DCD_EP_Open(pdev, - MSC_IN_EP, - MSC_EPIN_SIZE, - USB_OTG_EP_BULK); - - // Open EP OUT - DCD_EP_Open(pdev, - MSC_OUT_EP, - MSC_EPOUT_SIZE, - USB_OTG_EP_BULK); - - // Init the BOT layer - MSC_BOT_Init(pdev); - -#else - //---------------------------------- - // HID component - - // Open EP IN - DCD_EP_Open(pdev, - HID_IN_EP, - HID_IN_PACKET, - USB_OTG_EP_INT); -#endif - - return USBD_OK; -} - -/** - * @brief usbd_pyb_Init - * DeInitialize the CDC layer - * @param pdev: device instance - * @param cfgidx: Configuration index - * @retval status - */ -static uint8_t usbd_pyb_DeInit(void *pdev, uint8_t cfgidx) { - //---------------------------------- - // CDC VCP component - // close CDC EPs - DCD_EP_Close(pdev, CDC_IN_EP); - DCD_EP_Close(pdev, CDC_OUT_EP); - DCD_EP_Close(pdev, CDC_CMD_EP); - - // Restore default state of the Interface physical components - VCP_fops.pIf_DeInit(); - -#if USB_PYB_USE_MSC - //---------------------------------- - // MSC component - - // Close MSC EPs - DCD_EP_Close(pdev, MSC_IN_EP); - DCD_EP_Close(pdev, MSC_OUT_EP); - - // Un Init the BOT layer - MSC_BOT_DeInit(pdev); - -#else - //---------------------------------- - // HID component - - // Close HID EP - DCD_EP_Close(pdev, HID_IN_EP); -#endif - - return USBD_OK; -} - -#define BOT_GET_MAX_LUN 0xFE -#define BOT_RESET 0xFF - -#define HID_REQ_SET_PROTOCOL (0x0B) -#define HID_REQ_GET_PROTOCOL (0x03) -#define HID_REQ_SET_IDLE (0x0A) -#define HID_REQ_GET_IDLE (0x02) -#define HID_REQ_SET_REPORT (0x09) // used? -#define HID_REQ_GET_REPORT (0x01) // used? - -/** - * @brief usbd_pyb_Setup - * Handle the CDC specific requests - * @param pdev: instance - * @param req: usb requests - * @retval status - */ -static uint8_t usbd_pyb_Setup(void *pdev, USB_SETUP_REQ *req) { - switch (req->bmRequest & (USB_REQ_TYPE_MASK | USB_REQ_RECIPIENT_MASK)) { - - // Standard Device Request --------------------------------------------- - case (USB_REQ_TYPE_STANDARD | USB_REQ_RECIPIENT_DEVICE): - /* - switch (req->bRequest) { - case USB_REQ_GET_DESCRIPTOR: - { - uint16_t len = USB_CDC_DESC_SIZ; // XXX WRONG! - uint8_t *pbuf = usbd_pyb_CfgDesc + 9; - if ((req->wValue >> 8) == CDC_DESCRIPTOR_TYPE) { - pbuf = usbd_pyb_CfgDesc + 9 + (9 * USBD_ITF_MAX_NUM); // TODO - len = MIN(USB_CDC_DESC_SIZ, req->wLength); // TODO - } - return USBD_CtlSendData(pdev, pbuf, len); - // TODO stuff here for HID, using HID_MOUSE_ReportDesc - } - } - */ - break; - - // Standard Interface Request ------------------------------------------ - case (USB_REQ_TYPE_STANDARD | USB_REQ_RECIPIENT_INTERFACE): - switch (req->bRequest) { - case USB_REQ_GET_DESCRIPTOR: // needed for HID; SU 0x81 0x06 0x2200 0x00 request - // wIndex & 0xff is the interface - if ((req->wIndex & 0xff) <= 1) { - // CDC VCP - } else { -#if USB_PYB_USE_MSC -#else - uint16_t len = 0; - uint8_t *pbuf = NULL; - if (req->wValue >> 8 == HID_REPORT_DESC) { - len = MIN(HID_MOUSE_REPORT_DESC_SIZE , req->wLength); - pbuf = HID_MOUSE_ReportDesc; - return USBD_CtlSendData(pdev, pbuf, len); - } else if( req->wValue >> 8 == HID_DESCRIPTOR_TYPE) { - pbuf = usbd_pyb_CfgDesc + /* skip VCP */ 0x09 + 0x08 + 0x09 + 0x05 + 0x05 + 0x04 + 0x05 + 0x07 + 0x09 + 0x07 + 0x07 + /* skip iface descr */ 0x09; - len = MIN(0x09, req->wLength); - return USBD_CtlSendData(pdev, pbuf, len); - } -#endif - } - break; - - case USB_REQ_GET_INTERFACE: - // wIndex & 0xff is the interface - if ((req->wIndex & 0xff) <= 1) { - return USBD_CtlSendData(pdev, &usbd_cdc_AltSet, 1); - } else { -#if USB_PYB_USE_MSC - return USBD_CtlSendData(pdev, &USBD_MSC_AltSet, 1); -#else - return USBD_CtlSendData(pdev, &USBD_HID_AltSet, 1); -#endif - } - - case USB_REQ_SET_INTERFACE: - if ((uint8_t)(req->wValue) < USBD_ITF_MAX_NUM) { // TODO - if ((req->wIndex & 0xff) <= 1) { - usbd_cdc_AltSet = req->wValue; - } else { -#if USB_PYB_USE_MSC - USBD_MSC_AltSet = req->wValue; -#else - USBD_HID_AltSet = req->wValue; -#endif - } - return USBD_OK; - } - } - break; - - // Standard Endpoint Request ------------------------------------------- - case (USB_REQ_TYPE_STANDARD | USB_REQ_RECIPIENT_ENDPOINT): - // req->wIndex is the endpoint number, including direction -#if USB_PYB_USE_MSC - if (req->wIndex == MSC_IN_EP || req->wIndex == MSC_OUT_EP) { - // MSC component - switch (req->bRequest) { - case USB_REQ_CLEAR_FEATURE: - - // Flush the FIFO and Clear the stall status - DCD_EP_Flush(pdev, (uint8_t)req->wIndex); - - // Re-activate the EP - DCD_EP_Close(pdev, (uint8_t)req->wIndex); - - if ((((uint8_t)req->wIndex) & 0x80) == 0x80) { - DCD_EP_Open(pdev, ((uint8_t)req->wIndex), MSC_EPIN_SIZE, USB_OTG_EP_BULK); - } else { - DCD_EP_Open(pdev, ((uint8_t)req->wIndex), MSC_EPOUT_SIZE, USB_OTG_EP_BULK); - } - - // Handle BOT error - MSC_BOT_CplClrFeature(pdev, (uint8_t)req->wIndex); - return USBD_OK; - } - } -#endif - break; - - // CDC Class Requests ------------------------------ - case (USB_REQ_TYPE_CLASS | USB_REQ_RECIPIENT_INTERFACE): - // req->wIndex is the recipient interface number - if (req->wIndex == 0) { - // CDC component, communications interface (TODO do we need to handle if#1?) - - // Check if the request is a data setup packet - if (req->wLength) { - if (req->bmRequest & 0x80) { - // Device-to-Host request - - // Get the data to be sent to Host from interface layer - VCP_fops.pIf_Ctrl(req->bRequest, CmdBuff, req->wLength); - - // Send the data to the host - return USBD_CtlSendData(pdev, CmdBuff, req->wLength); - - } else { - // Host-to-Device requeset - - // Set the value of the current command to be processed */ - cdcCmd = req->bRequest; - cdcLen = req->wLength; - - // Prepare the reception of the buffer over EP0 - // Next step: the received data will be managed in usbd_cdc_EP0_TxSent() function. - return USBD_CtlPrepareRx(pdev, CmdBuff, req->wLength); - } - } else { - // Not a Data request - - // Transfer the command to the interface layer */ - return VCP_fops.pIf_Ctrl(req->bRequest, NULL, req->wValue); - } - - } else if (req->wIndex == 2) { -#if USB_PYB_USE_MSC - // MSC component - switch (req->bRequest) { - case BOT_GET_MAX_LUN: - if ((req->wValue == 0) && (req->wLength == 1) && ((req->bmRequest & 0x80) == 0x80)) { - USBD_MSC_MaxLun = USBD_STORAGE_fops->GetMaxLun(); - if (USBD_MSC_MaxLun > 0) { - return USBD_CtlSendData(pdev, &USBD_MSC_MaxLun, 1); - } - } - break; - - case BOT_RESET: - if ((req->wValue == 0) && (req->wLength == 0) && ((req->bmRequest & 0x80) != 0x80)) { - MSC_BOT_Reset(pdev); - return USBD_OK; - } - break; - } -#else - // HID component - switch (req->bRequest) { - case HID_REQ_SET_PROTOCOL: - USBD_HID_Protocol = req->wValue; - return USBD_OK; - - case HID_REQ_GET_PROTOCOL: - return USBD_CtlSendData(pdev, &USBD_HID_Protocol, 1); - - case HID_REQ_SET_IDLE: - USBD_HID_IdleState = (req->wValue >> 8); - return USBD_OK; - - case HID_REQ_GET_IDLE: - return USBD_CtlSendData(pdev, &USBD_HID_IdleState, 1); - } -#endif - } - break; - } - - printf("SU %x %x %x %x\n", req->bmRequest, req->bRequest, req->wValue, req->wIndex); - - // invalid command - USBD_CtlError(pdev, req); - return USBD_FAIL; -} - -/** - * @brief usbd_pyb_EP0_RxReady - * Data received on control endpoint - * @param pdev: device device instance - * @retval status - */ -static uint8_t usbd_pyb_EP0_RxReady(void *pdev) { - if (cdcCmd != NO_CMD) { - // Process the data - VCP_fops.pIf_Ctrl(cdcCmd, CmdBuff, cdcLen); - - // Reset the command variable to default value - cdcCmd = NO_CMD; - } - - return USBD_OK; -} - -/** - * @brief usbd_pyb_DataIn - * Data sent on non-control IN endpoint - * @param pdev: device instance - * @param epnum: endpoint number - * @retval status - */ -static uint8_t usbd_pyb_DataIn(void *pdev, uint8_t epnum) { - uint16_t USB_Tx_ptr; - uint16_t USB_Tx_length; - - switch (epnum) { - case (CDC_IN_EP & 0x7f): // TODO is this correct? - case (CDC_CMD_EP & 0x7f): // TODO is this correct? - if (USB_Tx_State == 1) { - if (APP_Rx_length == 0) { - USB_Tx_State = 0; - } else { - if (APP_Rx_length > CDC_DATA_IN_PACKET_SIZE) { - USB_Tx_ptr = APP_Rx_ptr_out; - USB_Tx_length = CDC_DATA_IN_PACKET_SIZE; - - APP_Rx_ptr_out += CDC_DATA_IN_PACKET_SIZE; - APP_Rx_length -= CDC_DATA_IN_PACKET_SIZE; - } else { - USB_Tx_ptr = APP_Rx_ptr_out; - USB_Tx_length = APP_Rx_length; - - APP_Rx_ptr_out += APP_Rx_length; - APP_Rx_length = 0; - } - - // Prepare the available data buffer to be sent on IN endpoint - DCD_EP_Tx(pdev, - CDC_IN_EP, - (uint8_t*)&APP_Rx_Buffer[USB_Tx_ptr], - USB_Tx_length); - } - } - return USBD_OK; - -#if USB_PYB_USE_MSC - case (MSC_IN_EP & 0x7f): // TODO? - MSC_BOT_DataIn(pdev, epnum); - return USBD_OK; - -#else - case (HID_IN_EP & 0x7f): - /* Ensure that the FIFO is empty before a new transfer, this condition could - be caused by a new transfer before the end of the previous transfer */ - DCD_EP_Flush(pdev, HID_IN_EP); - return USBD_OK; -#endif - } - - printf("DI %x\n", epnum); - - return USBD_OK; -} - -/** - * @brief usbd_pyb_DataOut - * Data received on non-control Out endpoint - * @param pdev: device instance - * @param epnum: endpoint number - * @retval status - */ -static uint8_t usbd_pyb_DataOut(void *pdev, uint8_t epnum) { - uint16_t USB_Rx_Cnt; - - switch (epnum) { - case (CDC_OUT_EP & 0x7f): // TODO is this correct? - // Get the received data buffer and update the counter */ - USB_Rx_Cnt = ((USB_OTG_CORE_HANDLE*)pdev)->dev.out_ep[epnum].xfer_count; - - /* USB data will be immediately processed, this allow next USB traffic being - NAKed till the end of the application Xfer */ - VCP_fops.pIf_DataRx(USB_Rx_Buffer, USB_Rx_Cnt); - - // Prepare Out endpoint to receive next packet */ - DCD_EP_PrepareRx(pdev, - CDC_OUT_EP, - (uint8_t*)(USB_Rx_Buffer), - CDC_DATA_OUT_PACKET_SIZE); - return USBD_OK; - -#if USB_PYB_USE_MSC - case (MSC_OUT_EP & 0x7f): // TODO is this correct? - MSC_BOT_DataOut(pdev, epnum); - return USBD_OK; -#endif - } - - printf("DO %x\n", epnum); - - return USBD_OK; -} - -/** - * @brief usbd_pyb_SOF - * Start Of Frame event management - * @param pdev: instance - * @retval status - */ -static uint8_t usbd_pyb_SOF(void *pdev) { - static uint32_t FrameCount = 0; - - // TODO do we need to check that this is for CDC/VCP? can we even do that? - - if (FrameCount++ == CDC_IN_FRAME_INTERVAL) { - // Reset the frame counter */ - FrameCount = 0; - - // Check the data to be sent through IN pipe */ - Handle_USBAsynchXfer(pdev); - } - - return USBD_OK; -} - -/** - * @brief Handle_USBAsynchXfer - * Send data to USB - * @param pdev: instance - * @retval None - */ -static void Handle_USBAsynchXfer (void *pdev) -{ - uint16_t USB_Tx_ptr; - uint16_t USB_Tx_length; - - if(USB_Tx_State != 1) - { - if (APP_Rx_ptr_out == APP_RX_DATA_SIZE) - { - APP_Rx_ptr_out = 0; - } - - if(APP_Rx_ptr_out == APP_Rx_ptr_in) - { - USB_Tx_State = 0; - return; - } - - if(APP_Rx_ptr_out > APP_Rx_ptr_in) // rollback */ - { - APP_Rx_length = APP_RX_DATA_SIZE - APP_Rx_ptr_out; - - } - else - { - APP_Rx_length = APP_Rx_ptr_in - APP_Rx_ptr_out; - - } -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - APP_Rx_length &= ~0x03; -#endif // USB_OTG_HS_INTERNAL_DMA_ENABLED */ - - if (APP_Rx_length > CDC_DATA_IN_PACKET_SIZE) - { - USB_Tx_ptr = APP_Rx_ptr_out; - USB_Tx_length = CDC_DATA_IN_PACKET_SIZE; - - APP_Rx_ptr_out += CDC_DATA_IN_PACKET_SIZE; - APP_Rx_length -= CDC_DATA_IN_PACKET_SIZE; - } - else - { - USB_Tx_ptr = APP_Rx_ptr_out; - USB_Tx_length = APP_Rx_length; - - APP_Rx_ptr_out += APP_Rx_length; - APP_Rx_length = 0; - } - USB_Tx_State = 1; - - DCD_EP_Tx (pdev, - CDC_IN_EP, - (uint8_t*)&APP_Rx_Buffer[USB_Tx_ptr], - USB_Tx_length); - } - -} - -/** - * @brief usbd_pyb_GetCfgDesc - * Return configuration descriptor - * @param speed : current device speed - * @param length : pointer data length - * @retval pointer to descriptor buffer - */ -static uint8_t *usbd_pyb_GetCfgDesc(uint8_t speed, uint16_t *length) { - *length = sizeof(usbd_pyb_CfgDesc); - return usbd_pyb_CfgDesc; -} - -/** - * @brief USBD_HID_SendReport - * Send HID Report - * @param pdev: device instance - * @param buff: pointer to report (4 bytes: ?, x, y, ?) - * @retval status - */ -/* -uint8_t USBD_HID_SendReport(USB_OTG_CORE_HANDLE *pdev, uint8_t *report, uint16_t len) { - if (pdev->dev.device_status == USB_OTG_CONFIGURED) { - DCD_EP_Tx(pdev, HID_IN_EP, report, len); - } - return USBD_OK; -} -*/ diff --git a/stm/stmusbd/usbd_pyb_core.h b/stm/stmusbd/usbd_pyb_core.h deleted file mode 100644 index 761ca2253..000000000 --- a/stm/stmusbd/usbd_pyb_core.h +++ /dev/null @@ -1,4 +0,0 @@ -extern USBD_Class_cb_TypeDef USBD_PYB_cb; -extern USBD_Class_cb_TypeDef USBD_PYB_HID_cb; - -uint8_t USBD_HID_SendReport(USB_OTG_CORE_HANDLE *pdev, uint8_t *report, uint16_t len); diff --git a/stm/stmusbd/usbd_pyb_core2.c b/stm/stmusbd/usbd_pyb_core2.c deleted file mode 100644 index c1abda3e7..000000000 --- a/stm/stmusbd/usbd_pyb_core2.c +++ /dev/null @@ -1,323 +0,0 @@ -#include - -#include "usbd_ioreq.h" -#include "usbd_desc.h" -#include "usbd_req.h" -#include "usbd_pyb_core.h" - -#define USB_PYB_CONFIG_DESC_SIZ (34) - -#define HID_MOUSE_REPORT_DESC_SIZE (74) - -#define HID_DESCRIPTOR_TYPE (0x21) -#define HID_REPORT_DESC (0x22) - -#define HID_IN_EP (0x81) -#define HID_IN_PACKET (4) /* maximum, and actual, packet size */ - -/********************************************* - PYB Device library callbacks - *********************************************/ - -static uint8_t usbd_pyb_Init (void *pdev, uint8_t cfgidx); -static uint8_t usbd_pyb_DeInit (void *pdev, uint8_t cfgidx); -static uint8_t usbd_pyb_Setup (void *pdev, USB_SETUP_REQ *req); -static uint8_t usbd_pyb_DataIn (void *pdev, uint8_t epnum); - -/********************************************* - PYB specific management functions - *********************************************/ - -static uint8_t *usbd_pyb_GetCfgDesc(uint8_t speed, uint16_t *length); - -__ALIGN_BEGIN static uint8_t USBD_HID_AltSet __ALIGN_END = 0; -__ALIGN_BEGIN static uint8_t USBD_HID_Protocol __ALIGN_END = 0; -__ALIGN_BEGIN static uint8_t USBD_HID_IdleState __ALIGN_END = 0; - -/* PYB interface class callbacks structure */ -USBD_Class_cb_TypeDef USBD_PYB_HID_cb = -{ - usbd_pyb_Init, - usbd_pyb_DeInit, - usbd_pyb_Setup, - NULL, // EP0_TxSent - NULL, // usbd_pyb_EP0_RxReady, - usbd_pyb_DataIn, - NULL, // usbd_pyb_DataOut, - NULL, // usbd_pyb_SOF, - NULL, // IsoINIncomplete - NULL, // IsoOUTIncomplete - usbd_pyb_GetCfgDesc, - // for OTG_HS support need to add other cfg desc here -}; - -/* USB PYB device Configuration Descriptor */ -__ALIGN_BEGIN static uint8_t usbd_pyb_CfgDesc[USB_PYB_CONFIG_DESC_SIZ] __ALIGN_END = -{ - //-------------------------------------------------------------------------- - // Configuration Descriptor - 0x09, // bLength: Configuration Descriptor size - USB_CONFIGURATION_DESCRIPTOR_TYPE, // bDescriptorType: Configuration - LOBYTE(USB_PYB_CONFIG_DESC_SIZ), // wTotalLength: no of returned bytes - HIBYTE(USB_PYB_CONFIG_DESC_SIZ), - 0x01, // bNumInterfaces: 1 interfaces - 0x01, // bConfigurationValue: Configuration value - 0x04, // iConfiguration: Index of string descriptor describing the configuration - 0x80, // bmAttributes: bus powered; 0xc0 for self powered - 0xfa, // bMaxPower: in units of 2mA - - //-------------------------------------------------------------------------- - // Interface Descriptor - 0x09, // bLength: Interface Descriptor size - USB_INTERFACE_DESCRIPTOR_TYPE, // bDescriptorType: interface descriptor - 0x00, // bInterfaceNumber: Number of Interface - 0x00, // bAlternateSetting: Alternate setting - 0x01, // bNumEndpoints - 0x03, // bInterfaceClass: HID Class - 0x01, // bInterfaceSubClass: 0=no boot, 1=BOOT - 0x02, // nInterfaceProtocol: 0=none, 1=keyboard, 2=mouse - 0x00, // iInterface: - - // Descriptor of Joystick Mouse HID - 0x09, // bLength: HID Descriptor size - HID_DESCRIPTOR_TYPE, // bDescriptorType: HID - 0x11, // bcdHID: HID Class Spec release number, low byte - 0x01, // bcdHID: high byte - 0x00, // bCountryCode: Hardware target country (0=unsupported) - 0x01, // bNumDescriptors: Number of HID class descriptors to follow - HID_REPORT_DESC, // bDescriptorType: report - HID_MOUSE_REPORT_DESC_SIZE, // wItemLength: Total length of Report descriptor - 0x00, - - // Endpoint IN descriptor - 0x07, // bLength: Endpoint descriptor length - USB_ENDPOINT_DESCRIPTOR_TYPE, // bDescriptorType: Endpoint descriptor type - HID_IN_EP, // bEndpointAddress: IN, address of HID - 0x03, // bmAttributes: Interrupt endpoint type - LOBYTE(HID_IN_PACKET), // wMaxPacketSize - HIBYTE(HID_IN_PACKET), - 0x0a, // bInterval: polling interval, units of 1ms -}; - -__ALIGN_BEGIN static uint8_t HID_MOUSE_ReportDesc[HID_MOUSE_REPORT_DESC_SIZE] __ALIGN_END = -{ - 0x05, 0x01, - 0x09, 0x02, - 0xA1, 0x01, - 0x09, 0x01, - - 0xA1, 0x00, - 0x05, 0x09, - 0x19, 0x01, - 0x29, 0x03, - - 0x15, 0x00, - 0x25, 0x01, - 0x95, 0x03, - 0x75, 0x01, - - 0x81, 0x02, - 0x95, 0x01, - 0x75, 0x05, - 0x81, 0x01, - - 0x05, 0x01, - 0x09, 0x30, - 0x09, 0x31, - 0x09, 0x38, - - 0x15, 0x81, - 0x25, 0x7F, - 0x75, 0x08, - 0x95, 0x03, - - 0x81, 0x06, - 0xC0, 0x09, - 0x3c, 0x05, - 0xff, 0x09, - - 0x01, 0x15, - 0x00, 0x25, - 0x01, 0x75, - 0x01, 0x95, - - 0x02, 0xb1, - 0x22, 0x75, - 0x06, 0x95, - 0x01, 0xb1, - - 0x01, 0xc0 -}; - -/** - * @brief usbd_pyb_Init - * Initilaize the PYB interface - * @param pdev: device instance - * @param cfgidx: Configuration index - * @retval status - */ -static uint8_t usbd_pyb_Init(void *pdev, uint8_t cfgidx) { - // deinit first to reset - usbd_pyb_DeInit(pdev, cfgidx); - - // Open EP IN - DCD_EP_Open(pdev, - HID_IN_EP, - HID_IN_PACKET, - USB_OTG_EP_INT); - - return USBD_OK; -} - -/** - * @brief usbd_pyb_Init - * DeInitialize the CDC layer - * @param pdev: device instance - * @param cfgidx: Configuration index - * @retval status - */ -static uint8_t usbd_pyb_DeInit(void *pdev, uint8_t cfgidx) { - // Close HID EP - DCD_EP_Close(pdev, HID_IN_EP); - - return USBD_OK; -} - -#define HID_REQ_SET_PROTOCOL (0x0B) -#define HID_REQ_GET_PROTOCOL (0x03) -#define HID_REQ_SET_IDLE (0x0A) -#define HID_REQ_GET_IDLE (0x02) -#define HID_REQ_SET_REPORT (0x09) // used? -#define HID_REQ_GET_REPORT (0x01) // used? - -/** - * @brief usbd_pyb_Setup - * Handle the CDC specific requests - * @param pdev: instance - * @param req: usb requests - * @retval status - */ -static uint8_t usbd_pyb_Setup(void *pdev, USB_SETUP_REQ *req) { - switch (req->bmRequest & (USB_REQ_TYPE_MASK | USB_REQ_RECIPIENT_MASK)) { - - // Standard Device Request --------------------------------------------- - case (USB_REQ_TYPE_STANDARD | USB_REQ_RECIPIENT_DEVICE): - break; - - // Standard Interface Request ------------------------------------------ - case (USB_REQ_TYPE_STANDARD | USB_REQ_RECIPIENT_INTERFACE): - switch (req->bRequest) { - case USB_REQ_GET_DESCRIPTOR: // needed for HID; SU 0x81 0x06 0x2200 0x00 request - // wIndex & 0xff is the interface - if ((req->wIndex & 0xff) == 0) { - uint16_t len = 0; - uint8_t *pbuf = NULL; - if( req->wValue >> 8 == HID_REPORT_DESC) { - len = MIN(HID_MOUSE_REPORT_DESC_SIZE , req->wLength); - pbuf = HID_MOUSE_ReportDesc; - return USBD_CtlSendData (pdev, pbuf, len); - } else if( req->wValue >> 8 == HID_DESCRIPTOR_TYPE) { - pbuf = usbd_pyb_CfgDesc + 0x09 + 0x09; - len = MIN(0x09 , req->wLength); - return USBD_CtlSendData (pdev, pbuf, len); - } - } - - case USB_REQ_GET_INTERFACE: - // wIndex & 0xff is the interface - if ((req->wIndex & 0xff) == 0) { - return USBD_CtlSendData(pdev, &USBD_HID_AltSet, 1); - } - - case USB_REQ_SET_INTERFACE: - if ((uint8_t)(req->wValue) < USBD_ITF_MAX_NUM) { // TODO - if ((req->wIndex & 0xff) == 0) { - USBD_HID_AltSet = req->wValue; - } - return USBD_OK; - } - } - break; - - // Standard Endpoint Request ------------------------------------------- - case (USB_REQ_TYPE_STANDARD | USB_REQ_RECIPIENT_ENDPOINT): - // req->wIndex is the endpoint number, including direction - break; - - // CDC Class Requests ------------------------------ - case (USB_REQ_TYPE_CLASS | USB_REQ_RECIPIENT_INTERFACE): - // req->wIndex is the recipient interface number - if (req->wIndex == 0) { - // HID component - switch (req->bRequest) { - case HID_REQ_SET_PROTOCOL: - USBD_HID_Protocol = req->wValue; - return USBD_OK; - - case HID_REQ_GET_PROTOCOL: - return USBD_CtlSendData(pdev, &USBD_HID_Protocol, 1); - - case HID_REQ_SET_IDLE: - USBD_HID_IdleState = (req->wValue >> 8); - return USBD_OK; - - case HID_REQ_GET_IDLE: - return USBD_CtlSendData(pdev, &USBD_HID_IdleState, 1); - } - } - break; - } - - printf("SU %x %x %x %x\n", req->bmRequest, req->bRequest, req->wValue, req->wIndex); - - // invalid command - USBD_CtlError(pdev, req); - return USBD_FAIL; -} - -/** - * @brief usbd_pyb_DataIn - * Data sent on non-control IN endpoint - * @param pdev: device instance - * @param epnum: endpoint number - * @retval status - */ -static uint8_t usbd_pyb_DataIn(void *pdev, uint8_t epnum) { - switch (epnum) { - case (HID_IN_EP & 0x7f): - /* Ensure that the FIFO is empty before a new transfer, this condition could - be caused by a new transfer before the end of the previous transfer */ - DCD_EP_Flush(pdev, HID_IN_EP); - return USBD_OK; - } - - printf("DI %x\n", epnum); - - return USBD_OK; -} - -/** - * @brief usbd_pyb_GetCfgDesc - * Return configuration descriptor - * @param speed : current device speed - * @param length : pointer data length - * @retval pointer to descriptor buffer - */ -static uint8_t *usbd_pyb_GetCfgDesc(uint8_t speed, uint16_t *length) { - *length = sizeof(usbd_pyb_CfgDesc); - return usbd_pyb_CfgDesc; -} - -/** - * @brief USBD_HID_SendReport - * Send HID Report - * @param pdev: device instance - * @param buff: pointer to report (4 bytes: ?, x, y, ?) - * @retval status - */ -uint8_t USBD_HID_SendReport(USB_OTG_CORE_HANDLE *pdev, uint8_t *report, uint16_t len) { - if (pdev->dev.device_status == USB_OTG_CONFIGURED) { - DCD_EP_Tx(pdev, HID_IN_EP, report, len); - } - return USBD_OK; -} diff --git a/stm/stmusbd/usbd_req.c b/stm/stmusbd/usbd_req.c deleted file mode 100644 index 02217cdcc..000000000 --- a/stm/stmusbd/usbd_req.c +++ /dev/null @@ -1,868 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_req.c - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief This file provides the standard USB requests following chapter 9. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_req.h" -#include "usbd_ioreq.h" -#include "usbd_desc.h" - - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup USBD_REQ - * @brief USB standard requests module - * @{ - */ - -/** @defgroup USBD_REQ_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_REQ_Private_Defines - * @{ - */ - -/** - * @} - */ - - -/** @defgroup USBD_REQ_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_REQ_Private_Variables - * @{ - */ -extern __IO USB_OTG_DCTL_TypeDef SET_TEST_MODE; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN uint32_t USBD_ep_status __ALIGN_END = 0; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN uint32_t USBD_default_cfg __ALIGN_END = 0; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN uint32_t USBD_cfg_status __ALIGN_END = 0; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN uint8_t USBD_StrDesc[USB_MAX_STR_DESC_SIZ] __ALIGN_END ; -/** - * @} - */ - - -/** @defgroup USBD_REQ_Private_FunctionPrototypes - * @{ - */ -static void USBD_GetDescriptor(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req); - -static void USBD_SetAddress(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req); - -static void USBD_SetConfig(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req); - -static void USBD_GetConfig(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req); - -static void USBD_GetStatus(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req); - -static void USBD_SetFeature(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req); - -static void USBD_ClrFeature(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req); - -static uint8_t USBD_GetLen(const char *buf); -/** - * @} - */ - - -/** @defgroup USBD_REQ_Private_Functions - * @{ - */ - - -/** -* @brief USBD_StdDevReq -* Handle standard usb device requests -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -USBD_Status USBD_StdDevReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req) -{ - USBD_Status ret = USBD_OK; - - switch (req->bRequest) - { - case USB_REQ_GET_DESCRIPTOR: - - USBD_GetDescriptor (pdev, req) ; - break; - - case USB_REQ_SET_ADDRESS: - USBD_SetAddress(pdev, req); - break; - - case USB_REQ_SET_CONFIGURATION: - USBD_SetConfig (pdev , req); - break; - - case USB_REQ_GET_CONFIGURATION: - USBD_GetConfig (pdev , req); - break; - - case USB_REQ_GET_STATUS: - USBD_GetStatus (pdev , req); - break; - - - case USB_REQ_SET_FEATURE: - USBD_SetFeature (pdev , req); - break; - - case USB_REQ_CLEAR_FEATURE: - USBD_ClrFeature (pdev , req); - break; - - default: - USBD_CtlError(pdev , req); - break; - } - - return ret; -} - -/** -* @brief USBD_StdItfReq -* Handle standard usb interface requests -* @param pdev: USB OTG device instance -* @param req: usb request -* @retval status -*/ -USBD_Status USBD_StdItfReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req) -{ - USBD_Status ret = USBD_OK; - - switch (pdev->dev.device_status) - { - case USB_OTG_CONFIGURED: - - if (LOBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) - { - pdev->dev.class_cb->Setup (pdev, req); - - if((req->wLength == 0)&& (ret == USBD_OK)) - { - USBD_CtlSendStatus(pdev); - } - } - else - { - USBD_CtlError(pdev , req); - } - break; - - default: - USBD_CtlError(pdev , req); - break; - } - return ret; -} - -/** -* @brief USBD_StdEPReq -* Handle standard usb endpoint requests -* @param pdev: USB OTG device instance -* @param req: usb request -* @retval status -*/ -USBD_Status USBD_StdEPReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req) -{ - - uint8_t ep_addr; - USBD_Status ret = USBD_OK; - - ep_addr = LOBYTE(req->wIndex); - - switch (req->bRequest) - { - - case USB_REQ_SET_FEATURE : - - switch (pdev->dev.device_status) - { - case USB_OTG_ADDRESSED: - if ((ep_addr != 0x00) && (ep_addr != 0x80)) - { - DCD_EP_Stall(pdev , ep_addr); - } - break; - - case USB_OTG_CONFIGURED: - if (req->wValue == USB_FEATURE_EP_HALT) - { - if ((ep_addr != 0x00) && (ep_addr != 0x80)) - { - DCD_EP_Stall(pdev , ep_addr); - - } - } - pdev->dev.class_cb->Setup (pdev, req); - USBD_CtlSendStatus(pdev); - - break; - - default: - USBD_CtlError(pdev , req); - break; - } - break; - - case USB_REQ_CLEAR_FEATURE : - - switch (pdev->dev.device_status) - { - case USB_OTG_ADDRESSED: - if ((ep_addr != 0x00) && (ep_addr != 0x80)) - { - DCD_EP_Stall(pdev , ep_addr); - } - break; - - case USB_OTG_CONFIGURED: - if (req->wValue == USB_FEATURE_EP_HALT) - { - if ((ep_addr != 0x00) && (ep_addr != 0x80)) - { - DCD_EP_ClrStall(pdev , ep_addr); - pdev->dev.class_cb->Setup (pdev, req); - } - USBD_CtlSendStatus(pdev); - } - break; - - default: - USBD_CtlError(pdev , req); - break; - } - break; - - case USB_REQ_GET_STATUS: - switch (pdev->dev.device_status) - { - case USB_OTG_ADDRESSED: - if ((ep_addr != 0x00) && (ep_addr != 0x80)) - { - DCD_EP_Stall(pdev , ep_addr); - } - break; - - case USB_OTG_CONFIGURED: - - - if ((ep_addr & 0x80)== 0x80) - { - if(pdev->dev.in_ep[ep_addr & 0x7F].is_stall) - { - USBD_ep_status = 0x0001; - } - else - { - USBD_ep_status = 0x0000; - } - } - else if ((ep_addr & 0x80)== 0x00) - { - if(pdev->dev.out_ep[ep_addr].is_stall) - { - USBD_ep_status = 0x0001; - } - - else - { - USBD_ep_status = 0x0000; - } - } - USBD_CtlSendData (pdev, - (uint8_t *)&USBD_ep_status, - 2); - break; - - default: - USBD_CtlError(pdev , req); - break; - } - break; - - default: - break; - } - return ret; -} -/** -* @brief USBD_GetDescriptor -* Handle Get Descriptor requests -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_GetDescriptor(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req) -{ - uint16_t len; - uint8_t *pbuf; - - - switch (req->wValue >> 8) - { - case USB_DESC_TYPE_DEVICE: - pbuf = pdev->dev.usr_device->GetDeviceDescriptor(pdev->cfg.speed, &len); - if ((req->wLength == 64) ||( pdev->dev.device_status == USB_OTG_DEFAULT)) - { - len = 8; - } - break; - - case USB_DESC_TYPE_CONFIGURATION: - pbuf = (uint8_t *)pdev->dev.class_cb->GetConfigDescriptor(pdev->cfg.speed, &len); -#ifdef USB_OTG_HS_CORE - if((pdev->cfg.speed == USB_OTG_SPEED_FULL )&& - (pdev->cfg.phy_itface == USB_OTG_ULPI_PHY)) - { - pbuf = (uint8_t *)pdev->dev.class_cb->GetOtherConfigDescriptor(pdev->cfg.speed, &len); - } -#endif - pbuf[1] = USB_DESC_TYPE_CONFIGURATION; - pdev->dev.pConfig_descriptor = pbuf; - break; - - case USB_DESC_TYPE_STRING: - switch ((uint8_t)(req->wValue)) - { - case USBD_IDX_LANGID_STR: - pbuf = pdev->dev.usr_device->GetLangIDStrDescriptor(pdev->cfg.speed, &len); - break; - - case USBD_IDX_MFC_STR: - pbuf = pdev->dev.usr_device->GetManufacturerStrDescriptor(pdev->cfg.speed, &len); - break; - - case USBD_IDX_PRODUCT_STR: - pbuf = pdev->dev.usr_device->GetProductStrDescriptor(pdev->cfg.speed, &len); - break; - - case USBD_IDX_SERIAL_STR: - pbuf = pdev->dev.usr_device->GetSerialStrDescriptor(pdev->cfg.speed, &len); - break; - - case USBD_IDX_CONFIG_STR: - pbuf = pdev->dev.usr_device->GetConfigurationStrDescriptor(pdev->cfg.speed, &len); - break; - - case USBD_IDX_INTERFACE_STR: - pbuf = pdev->dev.usr_device->GetInterfaceStrDescriptor(pdev->cfg.speed, &len); - break; - - default: -#ifdef USB_SUPPORT_USER_STRING_DESC - pbuf = pdev->dev.class_cb->GetUsrStrDescriptor(pdev->cfg.speed, (req->wValue) , &len); - break; -#else - USBD_CtlError(pdev , req); - return; -#endif /* USBD_CtlError(pdev , req); */ - } - break; - case USB_DESC_TYPE_DEVICE_QUALIFIER: -#ifdef USB_OTG_HS_CORE - if(pdev->cfg.speed == USB_OTG_SPEED_HIGH ) - { - - pbuf = (uint8_t *)pdev->dev.class_cb->GetConfigDescriptor(pdev->cfg.speed, &len); - - USBD_DeviceQualifierDesc[4]= pbuf[14]; - USBD_DeviceQualifierDesc[5]= pbuf[15]; - USBD_DeviceQualifierDesc[6]= pbuf[16]; - - pbuf = USBD_DeviceQualifierDesc; - len = USB_LEN_DEV_QUALIFIER_DESC; - break; - } - else - { - USBD_CtlError(pdev , req); - return; - } -#else - USBD_CtlError(pdev , req); - return; -#endif - - case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: -#ifdef USB_OTG_HS_CORE - - if(pdev->cfg.speed == USB_OTG_SPEED_HIGH ) - { - pbuf = (uint8_t *)pdev->dev.class_cb->GetOtherConfigDescriptor(pdev->cfg.speed, &len); - pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; - break; - } - else - { - USBD_CtlError(pdev , req); - return; - } -#else - USBD_CtlError(pdev , req); - return; -#endif - - - default: - USBD_CtlError(pdev , req); - return; - } - - if((len != 0)&& (req->wLength != 0)) - { - - len = MIN(len , req->wLength); - - USBD_CtlSendData (pdev, - pbuf, - len); - } - -} - -/** -* @brief USBD_SetAddress -* Set device address -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_SetAddress(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req) -{ - uint8_t dev_addr; - - if ((req->wIndex == 0) && (req->wLength == 0)) - { - dev_addr = (uint8_t)(req->wValue) & 0x7F; - - if (pdev->dev.device_status == USB_OTG_CONFIGURED) - { - USBD_CtlError(pdev , req); - } - else - { - pdev->dev.device_address = dev_addr; - DCD_EP_SetAddress(pdev, dev_addr); - USBD_CtlSendStatus(pdev); - - if (dev_addr != 0) - { - pdev->dev.device_status = USB_OTG_ADDRESSED; - } - else - { - pdev->dev.device_status = USB_OTG_DEFAULT; - } - } - } - else - { - USBD_CtlError(pdev , req); - } -} - -/** -* @brief USBD_SetConfig -* Handle Set device configuration request -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_SetConfig(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req) -{ - - static uint8_t cfgidx; - - cfgidx = (uint8_t)(req->wValue); - - if (cfgidx > USBD_CFG_MAX_NUM ) - { - USBD_CtlError(pdev , req); - } - else - { - switch (pdev->dev.device_status) - { - case USB_OTG_ADDRESSED: - if (cfgidx) - { - pdev->dev.device_config = cfgidx; - pdev->dev.device_status = USB_OTG_CONFIGURED; - USBD_SetCfg(pdev , cfgidx); - USBD_CtlSendStatus(pdev); - } - else - { - USBD_CtlSendStatus(pdev); - } - break; - - case USB_OTG_CONFIGURED: - if (cfgidx == 0) - { - pdev->dev.device_status = USB_OTG_ADDRESSED; - pdev->dev.device_config = cfgidx; - USBD_ClrCfg(pdev , cfgidx); - USBD_CtlSendStatus(pdev); - - } - else if (cfgidx != pdev->dev.device_config) - { - /* Clear old configuration */ - USBD_ClrCfg(pdev , pdev->dev.device_config); - - /* set new configuration */ - pdev->dev.device_config = cfgidx; - USBD_SetCfg(pdev , cfgidx); - USBD_CtlSendStatus(pdev); - } - else - { - USBD_CtlSendStatus(pdev); - } - break; - - default: - USBD_CtlError(pdev , req); - break; - } - } -} - -/** -* @brief USBD_GetConfig -* Handle Get device configuration request -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_GetConfig(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req) -{ - - if (req->wLength != 1) - { - USBD_CtlError(pdev , req); - } - else - { - switch (pdev->dev.device_status ) - { - case USB_OTG_ADDRESSED: - - USBD_CtlSendData (pdev, - (uint8_t *)&USBD_default_cfg, - 1); - break; - - case USB_OTG_CONFIGURED: - - USBD_CtlSendData (pdev, - &pdev->dev.device_config, - 1); - break; - - default: - USBD_CtlError(pdev , req); - break; - } - } -} - -/** -* @brief USBD_GetStatus -* Handle Get Status request -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_GetStatus(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req) -{ - - - switch (pdev->dev.device_status) - { - case USB_OTG_ADDRESSED: - case USB_OTG_CONFIGURED: - -#ifdef USBD_SELF_POWERED - USBD_cfg_status = USB_CONFIG_SELF_POWERED; -#else - USBD_cfg_status = 0x00; -#endif - - if (pdev->dev.DevRemoteWakeup) - { - USBD_cfg_status |= USB_CONFIG_REMOTE_WAKEUP; - } - - USBD_CtlSendData (pdev, - (uint8_t *)&USBD_cfg_status, - 2); - break; - - default : - USBD_CtlError(pdev , req); - break; - } -} - - -/** -* @brief USBD_SetFeature -* Handle Set device feature request -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_SetFeature(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req) -{ - - USB_OTG_DCTL_TypeDef dctl; - uint8_t test_mode = 0; - - if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) - { - pdev->dev.DevRemoteWakeup = 1; - pdev->dev.class_cb->Setup (pdev, req); - USBD_CtlSendStatus(pdev); - } - - else if ((req->wValue == USB_FEATURE_TEST_MODE) && - ((req->wIndex & 0xFF) == 0)) - { - dctl.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCTL); - - test_mode = req->wIndex >> 8; - switch (test_mode) - { - case 1: // TEST_J - dctl.b.tstctl = 1; - break; - - case 2: // TEST_K - dctl.b.tstctl = 2; - break; - - case 3: // TEST_SE0_NAK - dctl.b.tstctl = 3; - break; - - case 4: // TEST_PACKET - dctl.b.tstctl = 4; - break; - - case 5: // TEST_FORCE_ENABLE - dctl.b.tstctl = 5; - break; - } - SET_TEST_MODE = dctl; - pdev->dev.test_mode = 1; - USBD_CtlSendStatus(pdev); - } - -} - - -/** -* @brief USBD_ClrFeature -* Handle clear device feature request -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_ClrFeature(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req) -{ - switch (pdev->dev.device_status) - { - case USB_OTG_ADDRESSED: - case USB_OTG_CONFIGURED: - if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) - { - pdev->dev.DevRemoteWakeup = 0; - pdev->dev.class_cb->Setup (pdev, req); - USBD_CtlSendStatus(pdev); - } - break; - - default : - USBD_CtlError(pdev , req); - break; - } -} - -/** -* @brief USBD_ParseSetupRequest -* Copy buffer into setup structure -* @param pdev: device instance -* @param req: usb request -* @retval None -*/ - -void USBD_ParseSetupRequest( USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req) -{ - req->bmRequest = *(uint8_t *) (pdev->dev.setup_packet); - req->bRequest = *(uint8_t *) (pdev->dev.setup_packet + 1); - req->wValue = SWAPBYTE (pdev->dev.setup_packet + 2); - req->wIndex = SWAPBYTE (pdev->dev.setup_packet + 4); - req->wLength = SWAPBYTE (pdev->dev.setup_packet + 6); - - pdev->dev.in_ep[0].ctl_data_len = req->wLength ; - pdev->dev.device_state = USB_OTG_EP0_SETUP; -} - -/** -* @brief USBD_CtlError -* Handle USB low level Error -* @param pdev: device instance -* @param req: usb request -* @retval None -*/ - -void USBD_CtlError( USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req) -{ - - DCD_EP_Stall(pdev , 0x80); - DCD_EP_Stall(pdev , 0); - USB_OTG_EP0_OutStart(pdev); -} - - -/** - * @brief USBD_GetString - * Convert Ascii string into unicode one - * @param desc : descriptor buffer - * @param unicode : Formatted string buffer (unicode) - * @param len : descriptor length - * @retval None - */ -void USBD_GetString(const char *desc, uint8_t *unicode, uint16_t *len) -{ - uint8_t idx = 0; - - if (desc != NULL) - { - *len = USBD_GetLen(desc) * 2 + 2; - unicode[idx++] = *len; - unicode[idx++] = USB_DESC_TYPE_STRING; - - while (*desc != NULL) - { - unicode[idx++] = *desc++; - unicode[idx++] = 0x00; - } - } -} - -/** - * @brief USBD_GetLen - * return the string length - * @param buf : pointer to the ascii string buffer - * @retval string length - */ -static uint8_t USBD_GetLen(const char *buf) -{ - uint8_t len = 0; - - while (*buf != NULL) - { - len++; - buf++; - } - - return len; -} -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmusbd/usbd_req.h b/stm/stmusbd/usbd_req.h deleted file mode 100644 index 4853186c0..000000000 --- a/stm/stmusbd/usbd_req.h +++ /dev/null @@ -1,108 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_req.h - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief header file for the usbd_req.c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ - -#ifndef __USB_REQUEST_H_ -#define __USB_REQUEST_H_ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_def.h" -#include "usbd_core.h" -#include "usbd_conf.h" - - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USBD_REQ - * @brief header file for the usbd_ioreq.c file - * @{ - */ - -/** @defgroup USBD_REQ_Exported_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_REQ_Exported_Types - * @{ - */ -/** - * @} - */ - - - -/** @defgroup USBD_REQ_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USBD_REQ_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USBD_REQ_Exported_FunctionsPrototype - * @{ - */ - -USBD_Status USBD_StdDevReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req); -USBD_Status USBD_StdItfReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req); -USBD_Status USBD_StdEPReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req); -void USBD_ParseSetupRequest( USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req); - -void USBD_CtlError( USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req); - -void USBD_GetString(const char *desc, uint8_t *unicode, uint16_t *len); -/** - * @} - */ - -#endif /* __USB_REQUEST_H_ */ - -/** - * @} - */ - -/** -* @} -*/ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmusbd/usbd_storage_msd.c b/stm/stmusbd/usbd_storage_msd.c deleted file mode 100644 index d8650280c..000000000 --- a/stm/stmusbd/usbd_storage_msd.c +++ /dev/null @@ -1,363 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_storage_msd.c - * @author MCD application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief This file provides the disk operations functions. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Heavily modified by dpgeorge for Micro Python. - * - ****************************************************************************** - */ - -#include "usbd_msc_mem.h" -#include "usb_conf.h" -#include "usbd_storage_msd.h" - -#include "misc.h" -#include "storage.h" -#include "diskio.h" -#include "sdcard.h" - -/******************************************************************************/ -// Callback functions for when the internal flash is the mass storage device - -static const int8_t FLASH_STORAGE_Inquirydata[] = { // 36 bytes - /* LUN 0 */ - 0x00, - 0x00, // 0x00 for a fixed drive, 0x80 for a removable drive - 0x02, - 0x02, - (USBD_STD_INQUIRY_LENGTH - 5), - 0x00, - 0x00, - 0x00, - 'S', 'T', 'M', ' ', ' ', ' ', ' ', ' ', /* Manufacturer : 8 bytes */ - 'm', 'i', 'c', 'r', 'o', 'S', 'D', ' ', /* Product : 16 Bytes */ - 'F', 'l', 'a', 's', 'h', ' ', ' ', ' ', - '1', '.', '0' ,'0', /* Version : 4 Bytes */ -}; - -/** - * @brief Initialize the storage medium - * @param lun : logical unit number - * @retval Status - */ -int8_t FLASH_STORAGE_Init(uint8_t lun) { - storage_init(); - return 0; -} - -/** - * @brief return medium capacity and block size - * @param lun : logical unit number - * @param block_num : number of physical block - * @param block_size : size of a physical block - * @retval Status - */ -int8_t FLASH_STORAGE_GetCapacity(uint8_t lun, uint32_t *block_num, uint32_t *block_size) { - *block_size = storage_get_block_size(); - *block_num = storage_get_block_count(); - return 0; -} - -/** - * @brief check whether the medium is ready - * @param lun : logical unit number - * @retval Status - */ -int8_t FLASH_STORAGE_IsReady(uint8_t lun) { - return 0; -} - -/** - * @brief check whether the medium is write-protected - * @param lun : logical unit number - * @retval Status - */ -int8_t FLASH_STORAGE_IsWriteProtected(uint8_t lun) { - return 0; -} - -/** - * @brief Read data from the medium - * @param lun : logical unit number - * @param buf : Pointer to the buffer to save data - * @param blk_addr : address of 1st block to be read - * @param blk_len : nmber of blocks to be read - * @retval Status - */ -int8_t FLASH_STORAGE_Read(uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len) { - disk_read(0, buf, blk_addr, blk_len); - /* - for (int i = 0; i < blk_len; i++) { - if (!storage_read_block(buf + i * FLASH_BLOCK_SIZE, blk_addr + i)) { - return -1; - } - } - */ - return 0; -} - -/** - * @brief Write data to the medium - * @param lun : logical unit number - * @param buf : Pointer to the buffer to write from - * @param blk_addr : address of 1st block to be written - * @param blk_len : nmber of blocks to be read - * @retval Status - */ -int8_t FLASH_STORAGE_Write (uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len) { - disk_write(0, buf, blk_addr, blk_len); - /* - for (int i = 0; i < blk_len; i++) { - if (!storage_write_block(buf + i * FLASH_BLOCK_SIZE, blk_addr + i)) { - return -1; - } - } - */ - storage_flush(); // XXX hack for now so that the cache is always flushed - return 0; -} - -/** - * @brief Return number of supported logical unit - * @param None - * @retval number of logical unit - */ -int8_t FLASH_STORAGE_GetMaxLun(void) { - return 0; -} - -static const USBD_STORAGE_cb_TypeDef USBD_FLASH_STORAGE_fops = { - FLASH_STORAGE_Init, - FLASH_STORAGE_GetCapacity, - FLASH_STORAGE_IsReady, - FLASH_STORAGE_IsWriteProtected, - FLASH_STORAGE_Read, - FLASH_STORAGE_Write, - FLASH_STORAGE_GetMaxLun, - (int8_t *)FLASH_STORAGE_Inquirydata, -}; - -/******************************************************************************/ -// Callback functions for when the SD card is the mass storage device - -static const int8_t SDCARD_STORAGE_Inquirydata[] = { // 36 bytes - /* LUN 0 */ - 0x00, - 0x80, // 0x00 for a fixed drive, 0x80 for a removable drive - 0x02, - 0x02, - (USBD_STD_INQUIRY_LENGTH - 5), - 0x00, - 0x00, - 0x00, - 'S', 'T', 'M', ' ', ' ', ' ', ' ', ' ', /* Manufacturer : 8 bytes */ - 'm', 'i', 'c', 'r', 'o', 'S', 'D', ' ', /* Product : 16 Bytes */ - 'S', 'D', ' ', 'c', 'a', 'r', 'd', ' ', - '1', '.', '0' ,'0', /* Version : 4 Bytes */ -}; - -/** - * @brief Initialize the storage medium - * @param lun : logical unit number - * @retval Status - */ -int8_t SDCARD_STORAGE_Init(uint8_t lun) { - /* -#ifndef USE_STM3210C_EVAL - NVIC_InitTypeDef NVIC_InitStructure; - NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority =0; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); -#endif - if( SD_Init() != 0) - { - return (-1); - } - */ - if (!sdcard_power_on()) { - return -1; - } - - return 0; - -} - -/** - * @brief return medium capacity and block size - * @param lun : logical unit number - * @param block_num : number of physical block - * @param block_size : size of a physical block - * @retval Status - */ -int8_t SDCARD_STORAGE_GetCapacity(uint8_t lun, uint32_t *block_num, uint32_t *block_size) { -/* -#ifdef USE_STM3210C_EVAL - SD_CardInfo SDCardInfo; - SD_GetCardInfo(&SDCardInfo); -#else - if(SD_GetStatus() != 0 ) { - return (-1); - } -#endif - */ - - *block_size = SDCARD_BLOCK_SIZE; - *block_num = sdcard_get_capacity_in_bytes() / SDCARD_BLOCK_SIZE; - - return 0; -} - -/** - * @brief check whether the medium is ready - * @param lun : logical unit number - * @retval Status - */ -int8_t SDCARD_STORAGE_IsReady(uint8_t lun) { - /* -#ifndef USE_STM3210C_EVAL - - static int8_t last_status = 0; - - if(last_status < 0) - { - SD_Init(); - last_status = 0; - } - - if(SD_GetStatus() != 0) - { - last_status = -1; - return (-1); - } -#else - if( SD_Init() != 0) - { - return (-1); - } -#endif -*/ - return 0; -} - -/** - * @brief check whether the medium is write-protected - * @param lun : logical unit number - * @retval Status - */ -int8_t SDCARD_STORAGE_IsWriteProtected(uint8_t lun) { - return 0; -} - -/** - * @brief Read data from the medium - * @param lun : logical unit number - * @param buf : Pointer to the buffer to save data - * @param blk_addr : address of 1st block to be read - * @param blk_len : nmber of blocks to be read - * @retval Status - */ -int8_t SDCARD_STORAGE_Read(uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len) { - // TODO replace with call to sdcard_read_multi_blocks - for (int i = 0; i < blk_len; i++) { - if (!sdcard_read_block(buf + i * SDCARD_BLOCK_SIZE, blk_addr + i)) { - return -1; - } - } - /* - if (SD_ReadMultiBlocks(buf, blk_addr * 512, 512, blk_len) != 0) { - return -1; - } -#ifndef USE_STM3210C_EVAL - SD_WaitReadOperation(); - while (SD_GetStatus() != SD_TRANSFER_OK); -#endif -*/ - return 0; -} - -/** - * @brief Write data to the medium - * @param lun : logical unit number - * @param buf : Pointer to the buffer to write from - * @param blk_addr : address of 1st block to be written - * @param blk_len : nmber of blocks to be read - * @retval Status - */ -int8_t SDCARD_STORAGE_Write(uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len) { - // TODO replace with call to sdcard_write_multi_blocks - for (int i = 0; i < blk_len; i++) { - if (!sdcard_write_block(buf + i * SDCARD_BLOCK_SIZE, blk_addr + i)) { - return -1; - } - } - /* - if( SD_WriteMultiBlocks (buf, blk_addr * 512, 512, blk_len) != 0) { - return -1; - } -#ifndef USE_STM3210C_EVAL - SD_WaitWriteOperation(); - while (SD_GetStatus() != SD_TRANSFER_OK); -#endif -*/ - return 0; -} - -/** - * @brief Return number of supported logical unit - * @param None - * @retval number of logical unit - */ -int8_t SDCARD_STORAGE_GetMaxLun(void) { - return 0; -} - -static const USBD_STORAGE_cb_TypeDef USBD_SDCARD_STORAGE_fops = { - SDCARD_STORAGE_Init, - SDCARD_STORAGE_GetCapacity, - SDCARD_STORAGE_IsReady, - SDCARD_STORAGE_IsWriteProtected, - SDCARD_STORAGE_Read, - SDCARD_STORAGE_Write, - SDCARD_STORAGE_GetMaxLun, - (int8_t *)SDCARD_STORAGE_Inquirydata, -}; - -/******************************************************************************/ -// Callback functions for when the SD card is the mass storage device - -// default to flash as the storage device -USBD_STORAGE_cb_TypeDef *USBD_STORAGE_fops = (USBD_STORAGE_cb_TypeDef*)&USBD_FLASH_STORAGE_fops; - -void usbd_storage_select_medium(usbd_storage_medium_kind_t medium_kind) { - switch (medium_kind) { - case USBD_STORAGE_MEDIUM_FLASH: - USBD_STORAGE_fops = (USBD_STORAGE_cb_TypeDef*)&USBD_FLASH_STORAGE_fops; - break; - - case USBD_STORAGE_MEDIUM_SDCARD: - USBD_STORAGE_fops = (USBD_STORAGE_cb_TypeDef*)&USBD_SDCARD_STORAGE_fops; - break; - } -} diff --git a/stm/stmusbd/usbd_storage_msd.h b/stm/stmusbd/usbd_storage_msd.h deleted file mode 100644 index fac7b0469..000000000 --- a/stm/stmusbd/usbd_storage_msd.h +++ /dev/null @@ -1,6 +0,0 @@ -typedef enum { - USBD_STORAGE_MEDIUM_FLASH, - USBD_STORAGE_MEDIUM_SDCARD, -} usbd_storage_medium_kind_t; - -void usbd_storage_select_medium(usbd_storage_medium_kind_t medium_kind); diff --git a/stm/stmusbd/usbd_usr.c b/stm/stmusbd/usbd_usr.c deleted file mode 100644 index daa2ddbcb..000000000 --- a/stm/stmusbd/usbd_usr.c +++ /dev/null @@ -1,114 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_usr.c - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief This file includes the user application layer - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -#include "usbd_usr.h" -#include "usbd_ioreq.h" - -USBD_Usr_cb_TypeDef USR_cb = { - USBD_USR_Init, - USBD_USR_DeviceReset, - USBD_USR_DeviceConfigured, - USBD_USR_DeviceSuspended, - USBD_USR_DeviceResumed, - USBD_USR_DeviceConnected, - USBD_USR_DeviceDisconnected, -}; - -/** -* @brief USBD_USR_Init -* Displays the message on LCD for host lib initialization -* @param None -* @retval None -*/ -void USBD_USR_Init() { - //printf("USB OTG FS\n"); - //printf("USB device start\n"); -} - -/** -* @brief USBD_USR_DeviceReset -* Displays the message on LCD on device Reset Event -* @param speed : device speed -* @retval None -*/ -void USBD_USR_DeviceReset(uint8_t speed) { - //printf("USB reset %d\n", speed); -} - -/** -* @brief USBD_USR_DeviceConfigured -* Displays the message on LCD on device configuration Event -* @param None -* @retval Staus -*/ -void USBD_USR_DeviceConfigured() { - //printf("USB dev config\n"); -} - -/** -* @brief USBD_USR_DeviceSuspended -* Displays the message on LCD on device suspend Event -* @param None -* @retval None -*/ -void USBD_USR_DeviceSuspended() { - //printf("USB dev suspend\n"); -} - -/** -* @brief USBD_USR_DeviceResumed -* Displays the message on LCD on device resume Event -* @param None -* @retval None -*/ -void USBD_USR_DeviceResumed() { - //printf("USB dev resume\n"); -} - - -/** -* @brief USBD_USR_DeviceConnected -* Displays the message on LCD on device connection Event -* @param None -* @retval Staus -*/ -void USBD_USR_DeviceConnected() { - //printf("USB dev connect\n"); -} - - -/** -* @brief USBD_USR_DeviceDisonnected -* Displays the message on LCD on device disconnection Event -* @param None -* @retval Staus -*/ -void USBD_USR_DeviceDisconnected() { - //printf("USB dev disconn\n"); -} - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmusbd/usbd_usr.h b/stm/stmusbd/usbd_usr.h deleted file mode 100644 index bd5ff3e2e..000000000 --- a/stm/stmusbd/usbd_usr.h +++ /dev/null @@ -1,141 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_usr.h - * @author MCD Application Team - * @version V1.1.0 - * @date 19-March-2012 - * @brief Header file for usbd_usr.c - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_USR_H__ -#define __USBD_USR_H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_core.h" - - -/** @addtogroup USBD_USER - * @{ - */ - -/** @addtogroup USBD_MSC_DEMO_USER_CALLBACKS - * @{ - */ - -/** @defgroup USBD_USR - * @brief This file is the Header file for usbd_usr.c - * @{ - */ - - -/** @defgroup USBD_USR_Exported_Types - * @{ - */ - -extern USBD_Usr_cb_TypeDef USR_cb; -extern USBD_Usr_cb_TypeDef USR_FS_cb; -extern USBD_Usr_cb_TypeDef USR_HS_cb; - - - -/** - * @} - */ - - - -/** @defgroup USBD_USR_Exported_Defines - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_USR_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USBD_USR_Exported_Variables - * @{ - */ - -void USBD_USR_Init(void); -void USBD_USR_DeviceReset (uint8_t speed); -void USBD_USR_DeviceConfigured (void); -void USBD_USR_DeviceSuspended(void); -void USBD_USR_DeviceResumed(void); - -void USBD_USR_DeviceConnected(void); -void USBD_USR_DeviceDisconnected(void); - -void USBD_USR_FS_Init(void); -void USBD_USR_FS_DeviceReset (uint8_t speed); -void USBD_USR_FS_DeviceConfigured (void); -void USBD_USR_FS_DeviceSuspended(void); -void USBD_USR_FS_DeviceResumed(void); - -void USBD_USR_FS_DeviceConnected(void); -void USBD_USR_FS_DeviceDisconnected(void); - -void USBD_USR_HS_Init(void); -void USBD_USR_HS_DeviceReset (uint8_t speed); -void USBD_USR_HS_DeviceConfigured (void); -void USBD_USR_HS_DeviceSuspended(void); -void USBD_USR_HS_DeviceResumed(void); - -void USBD_USR_HS_DeviceConnected(void); -void USBD_USR_HS_DeviceDisconnected(void); - -/** - * @} - */ - -/** @defgroup USBD_USR_Exported_FunctionsPrototype - * @{ - */ -/** - * @} - */ - -#endif /*__USBD_USR_H__*/ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - - - diff --git a/stm/stmusbh/usbh_conf.h b/stm/stmusbh/usbh_conf.h deleted file mode 100644 index 51a780ae4..000000000 --- a/stm/stmusbh/usbh_conf.h +++ /dev/null @@ -1,97 +0,0 @@ -/** - ****************************************************************************** - * @file USBH_conf.h - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief General low level driver configuration - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBH_CONF__H__ -#define __USBH_CONF__H__ - -/* Includes ------------------------------------------------------------------*/ - -/** @addtogroup USBH_OTG_DRIVER - * @{ - */ - -/** @defgroup USBH_CONF - * @brief usb otg low level driver configuration file - * @{ - */ - -/** @defgroup USBH_CONF_Exported_Defines - * @{ - */ - -#define USBH_MAX_NUM_ENDPOINTS 2 -#define USBH_MAX_NUM_INTERFACES 2 -#define USBH_MSC_MPS_SIZE 0x200 - -/** - * @} - */ - - -/** @defgroup USBH_CONF_Exported_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBH_CONF_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USBH_CONF_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USBH_CONF_Exported_FunctionsPrototype - * @{ - */ -/** - * @} - */ - - -#endif //__USBH_CONF__H__ - - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/stm/stmusbh/usbh_core.c b/stm/stmusbh/usbh_core.c deleted file mode 100644 index a90851ccb..000000000 --- a/stm/stmusbh/usbh_core.c +++ /dev/null @@ -1,857 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_core.c - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief This file implements the functions for the core state machine process - * the enumeration and the control transfer process - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ - -#include "usbh_ioreq.h" -#include "usb_bsp.h" -#include "usbh_hcs.h" -#include "usbh_stdreq.h" -#include "usbh_core.h" -#include "usb_hcd_int.h" - - -/** @addtogroup USBH_LIB - * @{ - */ - -/** @addtogroup USBH_LIB_CORE -* @{ -*/ - -/** @defgroup USBH_CORE - * @brief TThis file handles the basic enumaration when a device is connected - * to the host. - * @{ - */ - -/** @defgroup USBH_CORE_Private_TypesDefinitions - * @{ - */ -uint8_t USBH_Disconnected (USB_OTG_CORE_HANDLE *pdev); -uint8_t USBH_Connected (USB_OTG_CORE_HANDLE *pdev); -uint8_t USBH_SOF (USB_OTG_CORE_HANDLE *pdev); - -USBH_HCD_INT_cb_TypeDef USBH_HCD_INT_cb = -{ - USBH_SOF, - USBH_Connected, - USBH_Disconnected, -}; - -USBH_HCD_INT_cb_TypeDef *USBH_HCD_INT_fops = &USBH_HCD_INT_cb; -/** - * @} - */ - - -/** @defgroup USBH_CORE_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBH_CORE_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBH_CORE_Private_Variables - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBH_CORE_Private_FunctionPrototypes - * @{ - */ -static USBH_Status USBH_HandleEnum(USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost); -USBH_Status USBH_HandleControl (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost); - -/** - * @} - */ - - -/** @defgroup USBH_CORE_Private_Functions - * @{ - */ - - -/** - * @brief USBH_Connected - * USB Connect callback function from the Interrupt. - * @param selected device - * @retval Status -*/ -uint8_t USBH_Connected (USB_OTG_CORE_HANDLE *pdev) -{ - pdev->host.ConnSts = 1; - return 0; -} - -/** -* @brief USBH_Disconnected -* USB Disconnect callback function from the Interrupt. -* @param selected device -* @retval Status -*/ - -uint8_t USBH_Disconnected (USB_OTG_CORE_HANDLE *pdev) -{ - pdev->host.ConnSts = 0; - return 0; -} - -/** - * @brief USBH_SOF - * USB SOF callback function from the Interrupt. - * @param selected device - * @retval Status - */ - -uint8_t USBH_SOF (USB_OTG_CORE_HANDLE *pdev) -{ - /* This callback could be used to implement a scheduler process */ - return 0; -} -/** - * @brief USBH_Init - * Host hardware and stack initializations - * @param class_cb: Class callback structure address - * @param usr_cb: User callback structure address - * @retval None - */ -void USBH_Init(USB_OTG_CORE_HANDLE *pdev, - USB_OTG_CORE_ID_TypeDef coreID, - USBH_HOST *phost, - USBH_Class_cb_TypeDef *class_cb, - USBH_Usr_cb_TypeDef *usr_cb) -{ - - /* Hardware Init */ - USB_OTG_BSP_Init(pdev); - - /* configure GPIO pin used for switching VBUS power */ - USB_OTG_BSP_ConfigVBUS(0); - - - /* Host de-initializations */ - USBH_DeInit(pdev, phost); - - /*Register class and user callbacks */ - phost->class_cb = class_cb; - phost->usr_cb = usr_cb; - - /* Start the USB OTG core */ - HCD_Init(pdev , coreID); - - /* Upon Init call usr call back */ - phost->usr_cb->Init(); - - /* Enable Interrupts */ - USB_OTG_BSP_EnableInterrupt(pdev); -} - -/** - * @brief USBH_DeInit - * Re-Initialize Host - * @param None - * @retval status: USBH_Status - */ -USBH_Status USBH_DeInit(USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost) -{ - /* Software Init */ - - phost->gState = HOST_IDLE; - phost->gStateBkp = HOST_IDLE; - phost->EnumState = ENUM_IDLE; - phost->RequestState = CMD_SEND; - - phost->Control.state = CTRL_SETUP; - phost->Control.ep0size = USB_OTG_MAX_EP0_SIZE; - - phost->device_prop.address = USBH_DEVICE_ADDRESS_DEFAULT; - phost->device_prop.speed = HPRT0_PRTSPD_FULL_SPEED; - - USBH_Free_Channel (pdev, phost->Control.hc_num_in); - USBH_Free_Channel (pdev, phost->Control.hc_num_out); - return USBH_OK; -} - -/** -* @brief USBH_Process -* USB Host core main state machine process -* @param None -* @retval None -*/ -void USBH_Process(USB_OTG_CORE_HANDLE *pdev , USBH_HOST *phost) -{ - volatile USBH_Status status = USBH_FAIL; - - - /* check for Host port events */ - if ((HCD_IsDeviceConnected(pdev) == 0)&& (phost->gState != HOST_IDLE)) - { - if(phost->gState != HOST_DEV_DISCONNECTED) - { - phost->gState = HOST_DEV_DISCONNECTED; - } - } - - switch (phost->gState) - { - - case HOST_IDLE : - - if (HCD_IsDeviceConnected(pdev)) - { - phost->gState = HOST_DEV_ATTACHED; - USB_OTG_BSP_mDelay(100); - } - break; - - case HOST_DEV_ATTACHED : - - phost->usr_cb->DeviceAttached(); - phost->Control.hc_num_out = USBH_Alloc_Channel(pdev, 0x00); - phost->Control.hc_num_in = USBH_Alloc_Channel(pdev, 0x80); - - /* Reset USB Device */ - if ( HCD_ResetPort(pdev) == 0) - { - phost->usr_cb->ResetDevice(); - /* Wait for USB USBH_ISR_PrtEnDisableChange() - Host is Now ready to start the Enumeration - */ - - phost->device_prop.speed = HCD_GetCurrentSpeed(pdev); - - phost->gState = HOST_ENUMERATION; - phost->usr_cb->DeviceSpeedDetected(phost->device_prop.speed); - - /* Open Control pipes */ - USBH_Open_Channel (pdev, - phost->Control.hc_num_in, - phost->device_prop.address, - phost->device_prop.speed, - EP_TYPE_CTRL, - phost->Control.ep0size); - - /* Open Control pipes */ - USBH_Open_Channel (pdev, - phost->Control.hc_num_out, - phost->device_prop.address, - phost->device_prop.speed, - EP_TYPE_CTRL, - phost->Control.ep0size); - } - break; - - case HOST_ENUMERATION: - /* Check for enumeration status */ - if ( USBH_HandleEnum(pdev , phost) == USBH_OK) - { - /* The function shall return USBH_OK when full enumeration is complete */ - - /* user callback for end of device basic enumeration */ - phost->usr_cb->EnumerationDone(); - - phost->gState = HOST_USR_INPUT; - } - break; - - case HOST_USR_INPUT: - /*The function should return user response true to move to class state */ - if ( phost->usr_cb->UserInput() == USBH_USR_RESP_OK) - { - if((phost->class_cb->Init(pdev, phost))\ - == USBH_OK) - { - phost->gState = HOST_CLASS_REQUEST; - } - } - break; - - case HOST_CLASS_REQUEST: - /* process class standard contol requests state machine */ - status = phost->class_cb->Requests(pdev, phost); - - if(status == USBH_OK) - { - phost->gState = HOST_CLASS; - } - - else - { - USBH_ErrorHandle(phost, status); - } - - - break; - case HOST_CLASS: - /* process class state machine */ - status = phost->class_cb->Machine(pdev, phost); - USBH_ErrorHandle(phost, status); - break; - - case HOST_CTRL_XFER: - /* process control transfer state machine */ - USBH_HandleControl(pdev, phost); - break; - - case HOST_SUSPENDED: - break; - - case HOST_ERROR_STATE: - /* Re-Initilaize Host for new Enumeration */ - USBH_DeInit(pdev, phost); - phost->usr_cb->DeInit(); - phost->class_cb->DeInit(pdev, &phost->device_prop); - break; - - case HOST_DEV_DISCONNECTED : - - /* Manage User disconnect operations*/ - phost->usr_cb->DeviceDisconnected(); - - /* Re-Initilaize Host for new Enumeration */ - USBH_DeInit(pdev, phost); - phost->usr_cb->DeInit(); - phost->class_cb->DeInit(pdev, &phost->device_prop); - USBH_DeAllocate_AllChannel(pdev); - phost->gState = HOST_IDLE; - - break; - - default : - break; - } - -} - - -/** - * @brief USBH_ErrorHandle - * This function handles the Error on Host side. - * @param errType : Type of Error or Busy/OK state - * @retval None - */ -void USBH_ErrorHandle(USBH_HOST *phost, USBH_Status errType) -{ - /* Error unrecovered or not supported device speed */ - if ( (errType == USBH_ERROR_SPEED_UNKNOWN) || - (errType == USBH_UNRECOVERED_ERROR) ) - { - phost->usr_cb->UnrecoveredError(); - phost->gState = HOST_ERROR_STATE; - } - /* USB host restart requested from application layer */ - else if(errType == USBH_APPLY_DEINIT) - { - phost->gState = HOST_ERROR_STATE; - /* user callback for initalization */ - phost->usr_cb->Init(); - } -} - - -/** - * @brief USBH_HandleEnum - * This function includes the complete enumeration process - * @param pdev: Selected device - * @retval USBH_Status - */ -static USBH_Status USBH_HandleEnum(USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost) -{ - USBH_Status Status = USBH_BUSY; - uint8_t Local_Buffer[64]; - - switch (phost->EnumState) - { - case ENUM_IDLE: - /* Get Device Desc for only 1st 8 bytes : To get EP0 MaxPacketSize */ - if ( USBH_Get_DevDesc(pdev , phost, 8) == USBH_OK) - { - phost->Control.ep0size = phost->device_prop.Dev_Desc.bMaxPacketSize; - - /* Issue Reset */ - HCD_ResetPort(pdev); - phost->EnumState = ENUM_GET_FULL_DEV_DESC; - - /* modify control channels configuration for MaxPacket size */ - USBH_Modify_Channel (pdev, - phost->Control.hc_num_out, - 0, - 0, - 0, - phost->Control.ep0size); - - USBH_Modify_Channel (pdev, - phost->Control.hc_num_in, - 0, - 0, - 0, - phost->Control.ep0size); - } - break; - - case ENUM_GET_FULL_DEV_DESC: - /* Get FULL Device Desc */ - if ( USBH_Get_DevDesc(pdev, phost, USB_DEVICE_DESC_SIZE)\ - == USBH_OK) - { - /* user callback for device descriptor available */ - phost->usr_cb->DeviceDescAvailable(&phost->device_prop.Dev_Desc); - phost->EnumState = ENUM_SET_ADDR; - } - break; - - case ENUM_SET_ADDR: - /* set address */ - if ( USBH_SetAddress(pdev, phost, USBH_DEVICE_ADDRESS) == USBH_OK) - { - USB_OTG_BSP_mDelay(2); - phost->device_prop.address = USBH_DEVICE_ADDRESS; - - /* user callback for device address assigned */ - phost->usr_cb->DeviceAddressAssigned(); - phost->EnumState = ENUM_GET_CFG_DESC; - - /* modify control channels to update device address */ - USBH_Modify_Channel (pdev, - phost->Control.hc_num_in, - phost->device_prop.address, - 0, - 0, - 0); - - USBH_Modify_Channel (pdev, - phost->Control.hc_num_out, - phost->device_prop.address, - 0, - 0, - 0); - } - break; - - case ENUM_GET_CFG_DESC: - /* get standard configuration descriptor */ - if ( USBH_Get_CfgDesc(pdev, - phost, - USB_CONFIGURATION_DESC_SIZE) == USBH_OK) - { - phost->EnumState = ENUM_GET_FULL_CFG_DESC; - } - break; - - case ENUM_GET_FULL_CFG_DESC: - /* get FULL config descriptor (config, interface, endpoints) */ - if (USBH_Get_CfgDesc(pdev, - phost, - phost->device_prop.Cfg_Desc.wTotalLength) == USBH_OK) - { - /* User callback for configuration descriptors available */ - phost->usr_cb->ConfigurationDescAvailable(&phost->device_prop.Cfg_Desc, - phost->device_prop.Itf_Desc, - phost->device_prop.Ep_Desc[0]); - - phost->EnumState = ENUM_GET_MFC_STRING_DESC; - } - break; - - case ENUM_GET_MFC_STRING_DESC: - if (phost->device_prop.Dev_Desc.iManufacturer != 0) - { /* Check that Manufacturer String is available */ - - if ( USBH_Get_StringDesc(pdev, - phost, - phost->device_prop.Dev_Desc.iManufacturer, - Local_Buffer , - 0xff) == USBH_OK) - { - /* User callback for Manufacturing string */ - phost->usr_cb->ManufacturerString(Local_Buffer); - phost->EnumState = ENUM_GET_PRODUCT_STRING_DESC; - } - } - else - { - phost->usr_cb->ManufacturerString("N/A"); - phost->EnumState = ENUM_GET_PRODUCT_STRING_DESC; - } - break; - - case ENUM_GET_PRODUCT_STRING_DESC: - if (phost->device_prop.Dev_Desc.iProduct != 0) - { /* Check that Product string is available */ - if ( USBH_Get_StringDesc(pdev, - phost, - phost->device_prop.Dev_Desc.iProduct, - Local_Buffer, - 0xff) == USBH_OK) - { - /* User callback for Product string */ - phost->usr_cb->ProductString(Local_Buffer); - phost->EnumState = ENUM_GET_SERIALNUM_STRING_DESC; - } - } - else - { - phost->usr_cb->ProductString("N/A"); - phost->EnumState = ENUM_GET_SERIALNUM_STRING_DESC; - } - break; - - case ENUM_GET_SERIALNUM_STRING_DESC: - if (phost->device_prop.Dev_Desc.iSerialNumber != 0) - { /* Check that Serial number string is available */ - if ( USBH_Get_StringDesc(pdev, - phost, - phost->device_prop.Dev_Desc.iSerialNumber, - Local_Buffer, - 0xff) == USBH_OK) - { - /* User callback for Serial number string */ - phost->usr_cb->SerialNumString(Local_Buffer); - phost->EnumState = ENUM_SET_CONFIGURATION; - } - } - else - { - phost->usr_cb->SerialNumString("N/A"); - phost->EnumState = ENUM_SET_CONFIGURATION; - } - break; - - case ENUM_SET_CONFIGURATION: - /* set configuration (default config) */ - if (USBH_SetCfg(pdev, - phost, - phost->device_prop.Cfg_Desc.bConfigurationValue) == USBH_OK) - { - phost->EnumState = ENUM_DEV_CONFIGURED; - } - break; - - - case ENUM_DEV_CONFIGURED: - /* user callback for enumeration done */ - Status = USBH_OK; - break; - - default: - break; - } - return Status; -} - - -/** - * @brief USBH_HandleControl - * Handles the USB control transfer state machine - * @param pdev: Selected device - * @retval Status - */ -USBH_Status USBH_HandleControl (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost) -{ - uint8_t direction; - static uint16_t timeout = 0; - USBH_Status status = USBH_OK; - URB_STATE URB_Status = URB_IDLE; - - phost->Control.status = CTRL_START; - - - switch (phost->Control.state) - { - case CTRL_SETUP: - /* send a SETUP packet */ - USBH_CtlSendSetup (pdev, - phost->Control.setup.d8 , - phost->Control.hc_num_out); - phost->Control.state = CTRL_SETUP_WAIT; - break; - - case CTRL_SETUP_WAIT: - - URB_Status = HCD_GetURB_State(pdev , phost->Control.hc_num_out); - /* case SETUP packet sent successfully */ - if(URB_Status == URB_DONE) - { - direction = (phost->Control.setup.b.bmRequestType & USB_REQ_DIR_MASK); - - /* check if there is a data stage */ - if (phost->Control.setup.b.wLength.w != 0 ) - { - timeout = DATA_STAGE_TIMEOUT; - if (direction == USB_D2H) - { - /* Data Direction is IN */ - phost->Control.state = CTRL_DATA_IN; - } - else - { - /* Data Direction is OUT */ - phost->Control.state = CTRL_DATA_OUT; - } - } - /* No DATA stage */ - else - { - timeout = NODATA_STAGE_TIMEOUT; - - /* If there is No Data Transfer Stage */ - if (direction == USB_D2H) - { - /* Data Direction is IN */ - phost->Control.state = CTRL_STATUS_OUT; - } - else - { - /* Data Direction is OUT */ - phost->Control.state = CTRL_STATUS_IN; - } - } - /* Set the delay timer to enable timeout for data stage completion */ - phost->Control.timer = HCD_GetCurrentFrame(pdev); - } - else if(URB_Status == URB_ERROR) - { - phost->Control.state = CTRL_ERROR; - phost->Control.status = CTRL_XACTERR; - } - break; - - case CTRL_DATA_IN: - /* Issue an IN token */ - USBH_CtlReceiveData(pdev, - phost->Control.buff, - phost->Control.length, - phost->Control.hc_num_in); - - phost->Control.state = CTRL_DATA_IN_WAIT; - break; - - case CTRL_DATA_IN_WAIT: - - URB_Status = HCD_GetURB_State(pdev , phost->Control.hc_num_in); - - /* check is DATA packet transfered successfully */ - if (URB_Status == URB_DONE) - { - phost->Control.state = CTRL_STATUS_OUT; - } - - /* manage error cases*/ - if (URB_Status == URB_STALL) - { - /* In stall case, return to previous machine state*/ - phost->gState = phost->gStateBkp; - } - else if (URB_Status == URB_ERROR) - { - /* Device error */ - phost->Control.state = CTRL_ERROR; - } - else if ((HCD_GetCurrentFrame(pdev)- phost->Control.timer) > timeout) - { - /* timeout for IN transfer */ - phost->Control.state = CTRL_ERROR; - } - break; - - case CTRL_DATA_OUT: - /* Start DATA out transfer (only one DATA packet)*/ - pdev->host.hc[phost->Control.hc_num_out].toggle_out = 1; - - USBH_CtlSendData (pdev, - phost->Control.buff, - phost->Control.length , - phost->Control.hc_num_out); - - - - - - phost->Control.state = CTRL_DATA_OUT_WAIT; - break; - - case CTRL_DATA_OUT_WAIT: - - URB_Status = HCD_GetURB_State(pdev , phost->Control.hc_num_out); - if (URB_Status == URB_DONE) - { /* If the Setup Pkt is sent successful, then change the state */ - phost->Control.state = CTRL_STATUS_IN; - } - - /* handle error cases */ - else if (URB_Status == URB_STALL) - { - /* In stall case, return to previous machine state*/ - phost->gState = phost->gStateBkp; - phost->Control.state = CTRL_STALLED; - } - else if (URB_Status == URB_NOTREADY) - { - /* Nack received from device */ - phost->Control.state = CTRL_DATA_OUT; - } - else if (URB_Status == URB_ERROR) - { - /* device error */ - phost->Control.state = CTRL_ERROR; - } - break; - - - case CTRL_STATUS_IN: - /* Send 0 bytes out packet */ - USBH_CtlReceiveData (pdev, - 0, - 0, - phost->Control.hc_num_in); - - phost->Control.state = CTRL_STATUS_IN_WAIT; - - break; - - case CTRL_STATUS_IN_WAIT: - - URB_Status = HCD_GetURB_State(pdev , phost->Control.hc_num_in); - - if ( URB_Status == URB_DONE) - { /* Control transfers completed, Exit the State Machine */ - phost->gState = phost->gStateBkp; - phost->Control.state = CTRL_COMPLETE; - } - - else if (URB_Status == URB_ERROR) - { - phost->Control.state = CTRL_ERROR; - } - - else if((HCD_GetCurrentFrame(pdev)\ - - phost->Control.timer) > timeout) - { - phost->Control.state = CTRL_ERROR; - } - else if(URB_Status == URB_STALL) - { - /* Control transfers completed, Exit the State Machine */ - phost->gState = phost->gStateBkp; - phost->Control.status = CTRL_STALL; - status = USBH_NOT_SUPPORTED; - } - break; - - case CTRL_STATUS_OUT: - pdev->host.hc[phost->Control.hc_num_out].toggle_out ^= 1; - USBH_CtlSendData (pdev, - 0, - 0, - phost->Control.hc_num_out); - - phost->Control.state = CTRL_STATUS_OUT_WAIT; - break; - - case CTRL_STATUS_OUT_WAIT: - - URB_Status = HCD_GetURB_State(pdev , phost->Control.hc_num_out); - if (URB_Status == URB_DONE) - { - phost->gState = phost->gStateBkp; - phost->Control.state = CTRL_COMPLETE; - } - else if (URB_Status == URB_NOTREADY) - { - phost->Control.state = CTRL_STATUS_OUT; - } - else if (URB_Status == URB_ERROR) - { - phost->Control.state = CTRL_ERROR; - } - break; - - case CTRL_ERROR: - /* - After a halt condition is encountered or an error is detected by the - host, a control endpoint is allowed to recover by accepting the next Setup - PID; i.e., recovery actions via some other pipe are not required for control - endpoints. For the Default Control Pipe, a device reset will ultimately be - required to clear the halt or error condition if the next Setup PID is not - accepted. - */ - if (++ phost->Control.errorcount <= USBH_MAX_ERROR_COUNT) - { - /* Do the transmission again, starting from SETUP Packet */ - phost->Control.state = CTRL_SETUP; - } - else - { - phost->Control.status = CTRL_FAIL; - phost->gState = phost->gStateBkp; - - status = USBH_FAIL; - } - break; - - default: - break; - } - return status; -} - - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - - - diff --git a/stm/stmusbh/usbh_core.h b/stm/stmusbh/usbh_core.h deleted file mode 100644 index c73ba612b..000000000 --- a/stm/stmusbh/usbh_core.h +++ /dev/null @@ -1,295 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_core.h - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief Header file for usbh_core.c - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive ----------------------------------------------*/ -#ifndef __USBH_CORE_H -#define __USBH_CORE_H - -/* Includes ------------------------------------------------------------------*/ -#include "usb_hcd.h" -#include "usbh_def.h" -#include "usbh_conf.h" - -/** @addtogroup USBH_LIB - * @{ - */ - -/** @addtogroup USBH_LIB_CORE -* @{ -*/ - -/** @defgroup USBH_CORE - * @brief This file is the Header file for usbh_core.c - * @{ - */ - - -/** @defgroup USBH_CORE_Exported_Defines - * @{ - */ - -#define MSC_CLASS 0x08 -#define HID_CLASS 0x03 -#define MSC_PROTOCOL 0x50 -#define CBI_PROTOCOL 0x01 - - -#define USBH_MAX_ERROR_COUNT 2 -#define USBH_DEVICE_ADDRESS_DEFAULT 0 -#define USBH_DEVICE_ADDRESS 1 - - -/** - * @} - */ - - -/** @defgroup USBH_CORE_Exported_Types - * @{ - */ - -typedef enum { - USBH_OK = 0, - USBH_BUSY, - USBH_FAIL, - USBH_NOT_SUPPORTED, - USBH_UNRECOVERED_ERROR, - USBH_ERROR_SPEED_UNKNOWN, - USBH_APPLY_DEINIT -}USBH_Status; - -/* Following states are used for gState */ -typedef enum { - HOST_IDLE =0, - HOST_DEV_ATTACHED, - HOST_DEV_DISCONNECTED, - HOST_DETECT_DEVICE_SPEED, - HOST_ENUMERATION, - HOST_CLASS_REQUEST, - HOST_CLASS, - HOST_CTRL_XFER, - HOST_USR_INPUT, - HOST_SUSPENDED, - HOST_ERROR_STATE -}HOST_State; - -/* Following states are used for EnumerationState */ -typedef enum { - ENUM_IDLE = 0, - ENUM_GET_FULL_DEV_DESC, - ENUM_SET_ADDR, - ENUM_GET_CFG_DESC, - ENUM_GET_FULL_CFG_DESC, - ENUM_GET_MFC_STRING_DESC, - ENUM_GET_PRODUCT_STRING_DESC, - ENUM_GET_SERIALNUM_STRING_DESC, - ENUM_SET_CONFIGURATION, - ENUM_DEV_CONFIGURED -} ENUM_State; - - - -/* Following states are used for CtrlXferStateMachine */ -typedef enum { - CTRL_IDLE =0, - CTRL_SETUP, - CTRL_SETUP_WAIT, - CTRL_DATA_IN, - CTRL_DATA_IN_WAIT, - CTRL_DATA_OUT, - CTRL_DATA_OUT_WAIT, - CTRL_STATUS_IN, - CTRL_STATUS_IN_WAIT, - CTRL_STATUS_OUT, - CTRL_STATUS_OUT_WAIT, - CTRL_ERROR, - CTRL_STALLED, - CTRL_COMPLETE -} -CTRL_State; - -typedef enum { - USBH_USR_NO_RESP = 0, - USBH_USR_RESP_OK = 1, -} -USBH_USR_Status; - -/* Following states are used for RequestState */ -typedef enum { - CMD_IDLE =0, - CMD_SEND, - CMD_WAIT -} CMD_State; - - - -typedef struct _Ctrl -{ - uint8_t hc_num_in; - uint8_t hc_num_out; - uint8_t ep0size; - uint8_t *buff; - uint16_t length; - uint8_t errorcount; - uint16_t timer; - CTRL_STATUS status; - USB_Setup_TypeDef setup; - CTRL_State state; - -} USBH_Ctrl_TypeDef; - - - -typedef struct _DeviceProp -{ - - uint8_t address; - uint8_t speed; - USBH_DevDesc_TypeDef Dev_Desc; - USBH_CfgDesc_TypeDef Cfg_Desc; - USBH_InterfaceDesc_TypeDef Itf_Desc[USBH_MAX_NUM_INTERFACES]; - USBH_EpDesc_TypeDef Ep_Desc[USBH_MAX_NUM_INTERFACES][USBH_MAX_NUM_ENDPOINTS]; - USBH_HIDDesc_TypeDef HID_Desc; - -}USBH_Device_TypeDef; - -typedef struct _USBH_Class_cb -{ - USBH_Status (*Init)\ - (USB_OTG_CORE_HANDLE *pdev , void *phost); - void (*DeInit)\ - (USB_OTG_CORE_HANDLE *pdev , void *phost); - USBH_Status (*Requests)\ - (USB_OTG_CORE_HANDLE *pdev , void *phost); - USBH_Status (*Machine)\ - (USB_OTG_CORE_HANDLE *pdev , void *phost); - -} USBH_Class_cb_TypeDef; - - -typedef struct _USBH_USR_PROP -{ - void (*Init)(void); /* HostLibInitialized */ - void (*DeInit)(void); /* HostLibInitialized */ - void (*DeviceAttached)(void); /* DeviceAttached */ - void (*ResetDevice)(void); - void (*DeviceDisconnected)(void); - void (*OverCurrentDetected)(void); - void (*DeviceSpeedDetected)(uint8_t DeviceSpeed); /* DeviceSpeed */ - void (*DeviceDescAvailable)(void *); /* DeviceDescriptor is available */ - void (*DeviceAddressAssigned)(void); /* Address is assigned to USB Device */ - void (*ConfigurationDescAvailable)(USBH_CfgDesc_TypeDef *, - USBH_InterfaceDesc_TypeDef *, - USBH_EpDesc_TypeDef *); - /* Configuration Descriptor available */ - void (*ManufacturerString)(void *); /* ManufacturerString*/ - void (*ProductString)(void *); /* ProductString*/ - void (*SerialNumString)(void *); /* SerialNubString*/ - void (*EnumerationDone)(void); /* Enumeration finished */ - USBH_USR_Status (*UserInput)(void); - int (*UserApplication) (void); - void (*DeviceNotSupported)(void); /* Device is not supported*/ - void (*UnrecoveredError)(void); - -} -USBH_Usr_cb_TypeDef; - -typedef struct _Host_TypeDef -{ - HOST_State gState; /* Host State Machine Value */ - HOST_State gStateBkp; /* backup of previous State machine value */ - ENUM_State EnumState; /* Enumeration state Machine */ - CMD_State RequestState; - USBH_Ctrl_TypeDef Control; - - USBH_Device_TypeDef device_prop; - - USBH_Class_cb_TypeDef *class_cb; - USBH_Usr_cb_TypeDef *usr_cb; - - -} USBH_HOST, *pUSBH_HOST; - -/** - * @} - */ - - - -/** @defgroup USBH_CORE_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBH_CORE_Exported_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBH_CORE_Exported_FunctionsPrototype - * @{ - */ -void USBH_Init(USB_OTG_CORE_HANDLE *pdev, - USB_OTG_CORE_ID_TypeDef coreID, - USBH_HOST *phost, - USBH_Class_cb_TypeDef *class_cb, - USBH_Usr_cb_TypeDef *usr_cb); - -USBH_Status USBH_DeInit(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost); -void USBH_Process(USB_OTG_CORE_HANDLE *pdev , - USBH_HOST *phost); -void USBH_ErrorHandle(USBH_HOST *phost, - USBH_Status errType); - -/** - * @} - */ - -#endif /* __USBH_CORE_H */ -/** - * @} - */ - -/** - * @} - */ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - - diff --git a/stm/stmusbh/usbh_def.h b/stm/stmusbh/usbh_def.h deleted file mode 100644 index 27a102a0e..000000000 --- a/stm/stmusbh/usbh_def.h +++ /dev/null @@ -1,288 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_def.h - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief Definitions used in the USB host library - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/** @addtogroup USBH_LIB - * @{ - */ - -/** @addtogroup USBH_LIB_CORE -* @{ -*/ - -/** @defgroup USBH_DEF - * @brief This file is includes USB descriptors - * @{ - */ - -#ifndef USBH_DEF_H -#define USBH_DEF_H - -#ifndef USBH_NULL -#define USBH_NULL ((void *)0) -#endif - -#ifndef FALSE -#define FALSE 0 -#endif - -#ifndef TRUE -#define TRUE 1 -#endif - - -#define ValBit(VAR,POS) (VAR & (1 << POS)) -#define SetBit(VAR,POS) (VAR |= (1 << POS)) -#define ClrBit(VAR,POS) (VAR &= ((1 << POS)^255)) - -#define LE16(addr) (((u16)(*((u8 *)(addr))))\ - + (((u16)(*(((u8 *)(addr)) + 1))) << 8)) - -#define USB_LEN_DESC_HDR 0x02 -#define USB_LEN_DEV_DESC 0x12 -#define USB_LEN_CFG_DESC 0x09 -#define USB_LEN_IF_DESC 0x09 -#define USB_LEN_EP_DESC 0x07 -#define USB_LEN_OTG_DESC 0x03 -#define USB_LEN_SETUP_PKT 0x08 - -/* bmRequestType :D7 Data Phase Transfer Direction */ -#define USB_REQ_DIR_MASK 0x80 -#define USB_H2D 0x00 -#define USB_D2H 0x80 - -/* bmRequestType D6..5 Type */ -#define USB_REQ_TYPE_STANDARD 0x00 -#define USB_REQ_TYPE_CLASS 0x20 -#define USB_REQ_TYPE_VENDOR 0x40 -#define USB_REQ_TYPE_RESERVED 0x60 - -/* bmRequestType D4..0 Recipient */ -#define USB_REQ_RECIPIENT_DEVICE 0x00 -#define USB_REQ_RECIPIENT_INTERFACE 0x01 -#define USB_REQ_RECIPIENT_ENDPOINT 0x02 -#define USB_REQ_RECIPIENT_OTHER 0x03 - -/* Table 9-4. Standard Request Codes */ -/* bRequest , Value */ -#define USB_REQ_GET_STATUS 0x00 -#define USB_REQ_CLEAR_FEATURE 0x01 -#define USB_REQ_SET_FEATURE 0x03 -#define USB_REQ_SET_ADDRESS 0x05 -#define USB_REQ_GET_DESCRIPTOR 0x06 -#define USB_REQ_SET_DESCRIPTOR 0x07 -#define USB_REQ_GET_CONFIGURATION 0x08 -#define USB_REQ_SET_CONFIGURATION 0x09 -#define USB_REQ_GET_INTERFACE 0x0A -#define USB_REQ_SET_INTERFACE 0x0B -#define USB_REQ_SYNCH_FRAME 0x0C - -/* Table 9-5. Descriptor Types of USB Specifications */ -#define USB_DESC_TYPE_DEVICE 1 -#define USB_DESC_TYPE_CONFIGURATION 2 -#define USB_DESC_TYPE_STRING 3 -#define USB_DESC_TYPE_INTERFACE 4 -#define USB_DESC_TYPE_ENDPOINT 5 -#define USB_DESC_TYPE_DEVICE_QUALIFIER 6 -#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION 7 -#define USB_DESC_TYPE_INTERFACE_POWER 8 -#define USB_DESC_TYPE_HID 0x21 -#define USB_DESC_TYPE_HID_REPORT 0x22 - - -#define USB_DEVICE_DESC_SIZE 18 -#define USB_CONFIGURATION_DESC_SIZE 9 -#define USB_HID_DESC_SIZE 9 -#define USB_INTERFACE_DESC_SIZE 9 -#define USB_ENDPOINT_DESC_SIZE 7 - -/* Descriptor Type and Descriptor Index */ -/* Use the following values when calling the function USBH_GetDescriptor */ -#define USB_DESC_DEVICE ((USB_DESC_TYPE_DEVICE << 8) & 0xFF00) -#define USB_DESC_CONFIGURATION ((USB_DESC_TYPE_CONFIGURATION << 8) & 0xFF00) -#define USB_DESC_STRING ((USB_DESC_TYPE_STRING << 8) & 0xFF00) -#define USB_DESC_INTERFACE ((USB_DESC_TYPE_INTERFACE << 8) & 0xFF00) -#define USB_DESC_ENDPOINT ((USB_DESC_TYPE_INTERFACE << 8) & 0xFF00) -#define USB_DESC_DEVICE_QUALIFIER ((USB_DESC_TYPE_DEVICE_QUALIFIER << 8) & 0xFF00) -#define USB_DESC_OTHER_SPEED_CONFIGURATION ((USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION << 8) & 0xFF00) -#define USB_DESC_INTERFACE_POWER ((USB_DESC_TYPE_INTERFACE_POWER << 8) & 0xFF00) -#define USB_DESC_HID_REPORT ((USB_DESC_TYPE_HID_REPORT << 8) & 0xFF00) -#define USB_DESC_HID ((USB_DESC_TYPE_HID << 8) & 0xFF00) - - -#define USB_EP_TYPE_CTRL 0x00 -#define USB_EP_TYPE_ISOC 0x01 -#define USB_EP_TYPE_BULK 0x02 -#define USB_EP_TYPE_INTR 0x03 - -#define USB_EP_DIR_OUT 0x00 -#define USB_EP_DIR_IN 0x80 -#define USB_EP_DIR_MSK 0x80 - -/* supported classes */ -#define USB_MSC_CLASS 0x08 -#define USB_HID_CLASS 0x03 - -/* Interface Descriptor field values for HID Boot Protocol */ -#define HID_BOOT_CODE 0x01 -#define HID_KEYBRD_BOOT_CODE 0x01 -#define HID_MOUSE_BOOT_CODE 0x02 - -/* As per USB specs 9.2.6.4 :Standard request with data request timeout: 5sec - Standard request with no data stage timeout : 50ms */ -#define DATA_STAGE_TIMEOUT 5000 -#define NODATA_STAGE_TIMEOUT 50 - -/** - * @} - */ - - -#define USBH_CONFIGURATION_DESCRIPTOR_SIZE (USB_CONFIGURATION_DESC_SIZE \ - + USB_INTERFACE_DESC_SIZE\ - + (USBH_MAX_NUM_ENDPOINTS * USB_ENDPOINT_DESC_SIZE)) - - -#define CONFIG_DESC_wTOTAL_LENGTH (ConfigurationDescriptorData.ConfigDescfield.\ - ConfigurationDescriptor.wTotalLength) - - -/* This Union is copied from usb_core.h */ -typedef union -{ - uint16_t w; - struct BW - { - uint8_t msb; - uint8_t lsb; - } - bw; -} -uint16_t_uint8_t; - - -typedef union _USB_Setup -{ - uint8_t d8[8]; - - struct _SetupPkt_Struc - { - uint8_t bmRequestType; - uint8_t bRequest; - uint16_t_uint8_t wValue; - uint16_t_uint8_t wIndex; - uint16_t_uint8_t wLength; - } b; -} -USB_Setup_TypeDef; - -typedef struct _DescHeader -{ - uint8_t bLength; - uint8_t bDescriptorType; -} -USBH_DescHeader_t; - -typedef struct _DeviceDescriptor -{ - uint8_t bLength; - uint8_t bDescriptorType; - uint16_t bcdUSB; /* USB Specification Number which device complies too */ - uint8_t bDeviceClass; - uint8_t bDeviceSubClass; - uint8_t bDeviceProtocol; - /* If equal to Zero, each interface specifies its own class - code if equal to 0xFF, the class code is vendor specified. - Otherwise field is valid Class Code.*/ - uint8_t bMaxPacketSize; - uint16_t idVendor; /* Vendor ID (Assigned by USB Org) */ - uint16_t idProduct; /* Product ID (Assigned by Manufacturer) */ - uint16_t bcdDevice; /* Device Release Number */ - uint8_t iManufacturer; /* Index of Manufacturer String Descriptor */ - uint8_t iProduct; /* Index of Product String Descriptor */ - uint8_t iSerialNumber; /* Index of Serial Number String Descriptor */ - uint8_t bNumConfigurations; /* Number of Possible Configurations */ -} -USBH_DevDesc_TypeDef; - - -typedef struct _ConfigurationDescriptor -{ - uint8_t bLength; - uint8_t bDescriptorType; - uint16_t wTotalLength; /* Total Length of Data Returned */ - uint8_t bNumInterfaces; /* Number of Interfaces */ - uint8_t bConfigurationValue; /* Value to use as an argument to select this configuration*/ - uint8_t iConfiguration; /*Index of String Descriptor Describing this configuration */ - uint8_t bmAttributes; /* D7 Bus Powered , D6 Self Powered, D5 Remote Wakeup , D4..0 Reserved (0)*/ - uint8_t bMaxPower; /*Maximum Power Consumption */ -} -USBH_CfgDesc_TypeDef; - - -typedef struct _HIDDescriptor -{ - uint8_t bLength; - uint8_t bDescriptorType; - uint16_t bcdHID; /* indicates what endpoint this descriptor is describing */ - uint8_t bCountryCode; /* specifies the transfer type. */ - uint8_t bNumDescriptors; /* specifies the transfer type. */ - uint8_t bReportDescriptorType; /* Maximum Packet Size this endpoint is capable of sending or receiving */ - uint16_t wItemLength; /* is used to specify the polling interval of certain transfers. */ -} -USBH_HIDDesc_TypeDef; - - -typedef struct _InterfaceDescriptor -{ - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bInterfaceNumber; - uint8_t bAlternateSetting; /* Value used to select alternative setting */ - uint8_t bNumEndpoints; /* Number of Endpoints used for this interface */ - uint8_t bInterfaceClass; /* Class Code (Assigned by USB Org) */ - uint8_t bInterfaceSubClass; /* Subclass Code (Assigned by USB Org) */ - uint8_t bInterfaceProtocol; /* Protocol Code */ - uint8_t iInterface; /* Index of String Descriptor Describing this interface */ - -} -USBH_InterfaceDesc_TypeDef; - - -typedef struct _EndpointDescriptor -{ - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bEndpointAddress; /* indicates what endpoint this descriptor is describing */ - uint8_t bmAttributes; /* specifies the transfer type. */ - uint16_t wMaxPacketSize; /* Maximum Packet Size this endpoint is capable of sending or receiving */ - uint8_t bInterval; /* is used to specify the polling interval of certain transfers. */ -} -USBH_EpDesc_TypeDef; -#endif - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/stm/stmusbh/usbh_hcs.c b/stm/stmusbh/usbh_hcs.c deleted file mode 100644 index fd53df6f6..000000000 --- a/stm/stmusbh/usbh_hcs.c +++ /dev/null @@ -1,259 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_hcs.c - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief This file implements functions for opening and closing host channels - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbh_hcs.h" - -/** @addtogroup USBH_LIB - * @{ - */ - -/** @addtogroup USBH_LIB_CORE -* @{ -*/ - -/** @defgroup USBH_HCS - * @brief This file includes opening and closing host channels - * @{ - */ - -/** @defgroup USBH_HCS_Private_Defines - * @{ - */ -/** - * @} - */ - -/** @defgroup USBH_HCS_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBH_HCS_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBH_HCS_Private_Variables - * @{ - */ - -/** - * @} - */ - - -/** @defgroup USBH_HCS_Private_FunctionPrototypes - * @{ - */ -static uint16_t USBH_GetFreeChannel (USB_OTG_CORE_HANDLE *pdev); -/** - * @} - */ - - -/** @defgroup USBH_HCS_Private_Functions - * @{ - */ - - - -/** - * @brief USBH_Open_Channel - * Open a pipe - * @param pdev : Selected device - * @param hc_num: Host channel Number - * @param dev_address: USB Device address allocated to attached device - * @param speed : USB device speed (Full/Low) - * @param ep_type: end point type (Bulk/int/ctl) - * @param mps: max pkt size - * @retval Status - */ -uint8_t USBH_Open_Channel (USB_OTG_CORE_HANDLE *pdev, - uint8_t hc_num, - uint8_t dev_address, - uint8_t speed, - uint8_t ep_type, - uint16_t mps) -{ - - pdev->host.hc[hc_num].ep_num = pdev->host.channel[hc_num]& 0x7F; - pdev->host.hc[hc_num].ep_is_in = (pdev->host.channel[hc_num] & 0x80 ) == 0x80; - pdev->host.hc[hc_num].dev_addr = dev_address; - pdev->host.hc[hc_num].ep_type = ep_type; - pdev->host.hc[hc_num].max_packet = mps; - pdev->host.hc[hc_num].speed = speed; - pdev->host.hc[hc_num].toggle_in = 0; - pdev->host.hc[hc_num].toggle_out = 0; - if(speed == HPRT0_PRTSPD_HIGH_SPEED) - { - pdev->host.hc[hc_num].do_ping = 1; - } - - USB_OTG_HC_Init(pdev, hc_num) ; - - return HC_OK; - -} - -/** - * @brief USBH_Modify_Channel - * Modify a pipe - * @param pdev : Selected device - * @param hc_num: Host channel Number - * @param dev_address: USB Device address allocated to attached device - * @param speed : USB device speed (Full/Low) - * @param ep_type: end point type (Bulk/int/ctl) - * @param mps: max pkt size - * @retval Status - */ -uint8_t USBH_Modify_Channel (USB_OTG_CORE_HANDLE *pdev, - uint8_t hc_num, - uint8_t dev_address, - uint8_t speed, - uint8_t ep_type, - uint16_t mps) -{ - - if(dev_address != 0) - { - pdev->host.hc[hc_num].dev_addr = dev_address; - } - - if((pdev->host.hc[hc_num].max_packet != mps) && (mps != 0)) - { - pdev->host.hc[hc_num].max_packet = mps; - } - - if((pdev->host.hc[hc_num].speed != speed ) && (speed != 0 )) - { - pdev->host.hc[hc_num].speed = speed; - } - - USB_OTG_HC_Init(pdev, hc_num); - return HC_OK; - -} - -/** - * @brief USBH_Alloc_Channel - * Allocate a new channel for the pipe - * @param ep_addr: End point for which the channel to be allocated - * @retval hc_num: Host channel number - */ -uint8_t USBH_Alloc_Channel (USB_OTG_CORE_HANDLE *pdev, uint8_t ep_addr) -{ - uint16_t hc_num; - - hc_num = USBH_GetFreeChannel(pdev); - - if (hc_num != HC_ERROR) - { - pdev->host.channel[hc_num] = HC_USED | ep_addr; - } - return hc_num; -} - -/** - * @brief USBH_Free_Pipe - * Free the USB host channel - * @param idx: Channel number to be freed - * @retval Status - */ -uint8_t USBH_Free_Channel (USB_OTG_CORE_HANDLE *pdev, uint8_t idx) -{ - if(idx < HC_MAX) - { - pdev->host.channel[idx] &= HC_USED_MASK; - } - return USBH_OK; -} - - -/** - * @brief USBH_DeAllocate_AllChannel - * Free all USB host channel -* @param pdev : core instance - * @retval Status - */ -uint8_t USBH_DeAllocate_AllChannel (USB_OTG_CORE_HANDLE *pdev) -{ - uint8_t idx; - - for (idx = 2; idx < HC_MAX ; idx ++) - { - pdev->host.channel[idx] = 0; - } - return USBH_OK; -} - -/** - * @brief USBH_GetFreeChannel - * Get a free channel number for allocation to a device endpoint - * @param None - * @retval idx: Free Channel number - */ -static uint16_t USBH_GetFreeChannel (USB_OTG_CORE_HANDLE *pdev) -{ - uint8_t idx = 0; - - for (idx = 0 ; idx < HC_MAX ; idx++) - { - if ((pdev->host.channel[idx] & HC_USED) == 0) - { - return idx; - } - } - return HC_ERROR; -} - - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - diff --git a/stm/stmusbh/usbh_hcs.h b/stm/stmusbh/usbh_hcs.h deleted file mode 100644 index af264017d..000000000 --- a/stm/stmusbh/usbh_hcs.h +++ /dev/null @@ -1,129 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_hcs.h - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief Header file for usbh_hcs.c - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive ----------------------------------------------*/ -#ifndef __USBH_HCS_H -#define __USBH_HCS_H - -/* Includes ------------------------------------------------------------------*/ -#include "usbh_core.h" - -/** @addtogroup USBH_LIB - * @{ - */ - -/** @addtogroup USBH_LIB_CORE -* @{ -*/ - -/** @defgroup USBH_HCS - * @brief This file is the header file for usbh_hcs.c - * @{ - */ - -/** @defgroup USBH_HCS_Exported_Defines - * @{ - */ -#define HC_MAX 8 - -#define HC_OK 0x0000 -#define HC_USED 0x8000 -#define HC_ERROR 0xFFFF -#define HC_USED_MASK 0x7FFF -/** - * @} - */ - -/** @defgroup USBH_HCS_Exported_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBH_HCS_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USBH_HCS_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USBH_HCS_Exported_FunctionsPrototype - * @{ - */ - -uint8_t USBH_Alloc_Channel(USB_OTG_CORE_HANDLE *pdev, uint8_t ep_addr); - -uint8_t USBH_Free_Channel (USB_OTG_CORE_HANDLE *pdev, uint8_t idx); - -uint8_t USBH_DeAllocate_AllChannel (USB_OTG_CORE_HANDLE *pdev); - -uint8_t USBH_Open_Channel (USB_OTG_CORE_HANDLE *pdev, - uint8_t ch_num, - uint8_t dev_address, - uint8_t speed, - uint8_t ep_type, - uint16_t mps); - -uint8_t USBH_Modify_Channel (USB_OTG_CORE_HANDLE *pdev, - uint8_t hc_num, - uint8_t dev_address, - uint8_t speed, - uint8_t ep_type, - uint16_t mps); -/** - * @} - */ - - - -#endif /* __USBH_HCS_H */ - - -/** - * @} - */ - -/** - * @} - */ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - diff --git a/stm/stmusbh/usbh_hid_core.c b/stm/stmusbh/usbh_hid_core.c deleted file mode 100644 index a60038d2b..000000000 --- a/stm/stmusbh/usbh_hid_core.c +++ /dev/null @@ -1,658 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_hid_core.c - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief This file is the HID Layer Handlers for USB Host HID class. - * - * @verbatim - * - * =================================================================== - * HID Class Description - * =================================================================== - * This module manages the MSC class V1.11 following the "Device Class Definition - * for Human Interface Devices (HID) Version 1.11 Jun 27, 2001". - * This driver implements the following aspects of the specification: - * - The Boot Interface Subclass - * - The Mouse and Keyboard protocols - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbh_hid_core.h" -#include "usbh_hid_mouse.h" -#include "usbh_hid_keybd.h" - -/** @addtogroup USBH_LIB -* @{ -*/ - -/** @addtogroup USBH_CLASS -* @{ -*/ - -/** @addtogroup USBH_HID_CLASS -* @{ -*/ - -/** @defgroup USBH_HID_CORE -* @brief This file includes HID Layer Handlers for USB Host HID class. -* @{ -*/ - -/** @defgroup USBH_HID_CORE_Private_TypesDefinitions -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USBH_HID_CORE_Private_Defines -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USBH_HID_CORE_Private_Macros -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USBH_HID_CORE_Private_Variables -* @{ -*/ -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN HID_Machine_TypeDef HID_Machine __ALIGN_END ; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN HID_Report_TypeDef HID_Report __ALIGN_END ; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN USB_Setup_TypeDef HID_Setup __ALIGN_END ; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN USBH_HIDDesc_TypeDef HID_Desc __ALIGN_END ; - -__IO uint8_t start_toggle = 0; -/** -* @} -*/ - - -/** @defgroup USBH_HID_CORE_Private_FunctionPrototypes -* @{ -*/ - -static USBH_Status USBH_HID_InterfaceInit (USB_OTG_CORE_HANDLE *pdev , - void *phost); - -static void USBH_ParseHIDDesc (USBH_HIDDesc_TypeDef *desc, uint8_t *buf); - -static void USBH_HID_InterfaceDeInit (USB_OTG_CORE_HANDLE *pdev , - void *phost); - -static USBH_Status USBH_HID_Handle(USB_OTG_CORE_HANDLE *pdev , - void *phost); - -static USBH_Status USBH_HID_ClassRequest(USB_OTG_CORE_HANDLE *pdev , - void *phost); - -static USBH_Status USBH_Get_HID_ReportDescriptor (USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint16_t length); - -static USBH_Status USBH_Get_HID_Descriptor (USB_OTG_CORE_HANDLE *pdev,\ - USBH_HOST *phost, - uint16_t length); - -static USBH_Status USBH_Set_Idle (USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t duration, - uint8_t reportId); - -static USBH_Status USBH_Set_Protocol (USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t protocol); - - -USBH_Class_cb_TypeDef HID_cb = -{ - USBH_HID_InterfaceInit, - USBH_HID_InterfaceDeInit, - USBH_HID_ClassRequest, - USBH_HID_Handle -}; -/** -* @} -*/ - - -/** @defgroup USBH_HID_CORE_Private_Functions -* @{ -*/ - -/** -* @brief USBH_HID_InterfaceInit -* The function init the HID class. -* @param pdev: Selected device -* @param hdev: Selected device property -* @retval USBH_Status :Response for USB HID driver intialization -*/ -static USBH_Status USBH_HID_InterfaceInit ( USB_OTG_CORE_HANDLE *pdev, - void *phost) -{ - uint8_t maxEP; - USBH_HOST *pphost = phost; - - uint8_t num =0; - USBH_Status status = USBH_BUSY ; - HID_Machine.state = HID_ERROR; - - //printf("USBH_HID_InterfaceInit\n"); - if(pphost->device_prop.Itf_Desc[0].bInterfaceSubClass == HID_BOOT_CODE) - { - /*Decode Bootclass Protocl: Mouse or Keyboard*/ - if(pphost->device_prop.Itf_Desc[0].bInterfaceProtocol == HID_KEYBRD_BOOT_CODE) - { - HID_Machine.cb = &HID_KEYBRD_cb; - } - else if(pphost->device_prop.Itf_Desc[0].bInterfaceProtocol == HID_MOUSE_BOOT_CODE) - { - HID_Machine.cb = &HID_MOUSE_cb; - } - //printf("USBH_HID_InterfaceInit %x %x\n", pphost->device_prop.Itf_Desc[0].bInterfaceSubClass, pphost->device_prop.Itf_Desc[0].bInterfaceProtocol); - - HID_Machine.state = HID_IDLE; - HID_Machine.ctl_state = HID_REQ_IDLE; - HID_Machine.ep_addr = pphost->device_prop.Ep_Desc[0][0].bEndpointAddress; - HID_Machine.length = pphost->device_prop.Ep_Desc[0][0].wMaxPacketSize; - HID_Machine.poll = pphost->device_prop.Ep_Desc[0][0].bInterval ; - - if (HID_Machine.poll < HID_MIN_POLL) - { - HID_Machine.poll = HID_MIN_POLL; - } - - - /* Check fo available number of endpoints */ - /* Find the number of EPs in the Interface Descriptor */ - /* Choose the lower number in order not to overrun the buffer allocated */ - maxEP = ( (pphost->device_prop.Itf_Desc[0].bNumEndpoints <= USBH_MAX_NUM_ENDPOINTS) ? - pphost->device_prop.Itf_Desc[0].bNumEndpoints : - USBH_MAX_NUM_ENDPOINTS); - - - /* Decode endpoint IN and OUT address from interface descriptor */ - for (num=0; num < maxEP; num++) - { - if(pphost->device_prop.Ep_Desc[0][num].bEndpointAddress & 0x80) - { - HID_Machine.HIDIntInEp = (pphost->device_prop.Ep_Desc[0][num].bEndpointAddress); - HID_Machine.hc_num_in =\ - USBH_Alloc_Channel(pdev, - pphost->device_prop.Ep_Desc[0][num].bEndpointAddress); - - /* Open channel for IN endpoint */ - USBH_Open_Channel (pdev, - HID_Machine.hc_num_in, - pphost->device_prop.address, - pphost->device_prop.speed, - EP_TYPE_INTR, - HID_Machine.length); - } - else - { - HID_Machine.HIDIntOutEp = (pphost->device_prop.Ep_Desc[0][num].bEndpointAddress); - HID_Machine.hc_num_out =\ - USBH_Alloc_Channel(pdev, - pphost->device_prop.Ep_Desc[0][num].bEndpointAddress); - - /* Open channel for OUT endpoint */ - USBH_Open_Channel (pdev, - HID_Machine.hc_num_out, - pphost->device_prop.address, - pphost->device_prop.speed, - EP_TYPE_INTR, - HID_Machine.length); - } - - } - - start_toggle =0; - status = USBH_OK; - } - else - { - pphost->usr_cb->DeviceNotSupported(); - } - - return status; - -} - - - -/** -* @brief USBH_HID_InterfaceDeInit -* The function DeInit the Host Channels used for the HID class. -* @param pdev: Selected device -* @param hdev: Selected device property -* @retval None -*/ -void USBH_HID_InterfaceDeInit ( USB_OTG_CORE_HANDLE *pdev, - void *phost) -{ - //USBH_HOST *pphost = phost; - - if(HID_Machine.hc_num_in != 0x00) - { - USB_OTG_HC_Halt(pdev, HID_Machine.hc_num_in); - USBH_Free_Channel (pdev, HID_Machine.hc_num_in); - HID_Machine.hc_num_in = 0; /* Reset the Channel as Free */ - } - - if(HID_Machine.hc_num_out != 0x00) - { - USB_OTG_HC_Halt(pdev, HID_Machine.hc_num_out); - USBH_Free_Channel (pdev, HID_Machine.hc_num_out); - HID_Machine.hc_num_out = 0; /* Reset the Channel as Free */ - } - - start_toggle = 0; -} - -/** -* @brief USBH_HID_ClassRequest -* The function is responsible for handling HID Class requests -* for HID class. -* @param pdev: Selected device -* @param hdev: Selected device property -* @retval USBH_Status :Response for USB Set Protocol request -*/ -static USBH_Status USBH_HID_ClassRequest(USB_OTG_CORE_HANDLE *pdev , - void *phost) -{ - USBH_HOST *pphost = phost; - - USBH_Status status = USBH_BUSY; - USBH_Status classReqStatus = USBH_BUSY; - - - /* Switch HID state machine */ - switch (HID_Machine.ctl_state) - { - case HID_IDLE: - case HID_REQ_GET_HID_DESC: - - /* Get HID Desc */ - if (USBH_Get_HID_Descriptor (pdev, pphost, USB_HID_DESC_SIZE)== USBH_OK) - { - - USBH_ParseHIDDesc(&HID_Desc, pdev->host.Rx_Buffer); - HID_Machine.ctl_state = HID_REQ_GET_REPORT_DESC; - } - - break; - case HID_REQ_GET_REPORT_DESC: - - - /* Get Report Desc */ - if (USBH_Get_HID_ReportDescriptor(pdev , pphost, HID_Desc.wItemLength) == USBH_OK) - { - HID_Machine.ctl_state = HID_REQ_SET_IDLE; - } - - break; - - case HID_REQ_SET_IDLE: - - classReqStatus = USBH_Set_Idle (pdev, pphost, 0, 0); - - /* set Idle */ - if (classReqStatus == USBH_OK) - { - HID_Machine.ctl_state = HID_REQ_SET_PROTOCOL; - } - else if(classReqStatus == USBH_NOT_SUPPORTED) - { - HID_Machine.ctl_state = HID_REQ_SET_PROTOCOL; - } - break; - - case HID_REQ_SET_PROTOCOL: - /* set protocol */ - if (USBH_Set_Protocol (pdev ,pphost, 0) == USBH_OK) - { - HID_Machine.ctl_state = HID_REQ_IDLE; - - /* all requests performed*/ - status = USBH_OK; - } - break; - - default: - break; - } - - return status; -} - - -/** -* @brief USBH_HID_Handle -* The function is for managing state machine for HID data transfers -* @param pdev: Selected device -* @param hdev: Selected device property -* @retval USBH_Status -*/ -static USBH_Status USBH_HID_Handle(USB_OTG_CORE_HANDLE *pdev , - void *phost) -{ - USBH_HOST *pphost = phost; - USBH_Status status = USBH_OK; - - switch (HID_Machine.state) - { - - case HID_IDLE: - HID_Machine.cb->Init(); - HID_Machine.state = HID_SYNC; - - case HID_SYNC: - - /* Sync with start of Even Frame */ - if(USB_OTG_IsEvenFrame(pdev) == TRUE) - { - HID_Machine.state = HID_GET_DATA; - } - break; - - case HID_GET_DATA: - - USBH_InterruptReceiveData(pdev, - HID_Machine.buff, - HID_Machine.length, - HID_Machine.hc_num_in); - start_toggle = 1; - - HID_Machine.state = HID_POLL; - HID_Machine.timer = HCD_GetCurrentFrame(pdev); - break; - - case HID_POLL: - if(( HCD_GetCurrentFrame(pdev) - HID_Machine.timer) >= HID_Machine.poll) - { - HID_Machine.state = HID_GET_DATA; - } - else if(HCD_GetURB_State(pdev , HID_Machine.hc_num_in) == URB_DONE) - { - if(start_toggle == 1) /* handle data once */ - { - start_toggle = 0; - HID_Machine.cb->Decode(HID_Machine.buff); - } - } - else if(HCD_GetURB_State(pdev, HID_Machine.hc_num_in) == URB_STALL) /* IN Endpoint Stalled */ - { - - /* Issue Clear Feature on interrupt IN endpoint */ - if( (USBH_ClrFeature(pdev, - pphost, - HID_Machine.ep_addr, - HID_Machine.hc_num_in)) == USBH_OK) - { - /* Change state to issue next IN token */ - HID_Machine.state = HID_GET_DATA; - - } - - } - break; - - default: - break; - } - return status; -} - - -/** -* @brief USBH_Get_HID_ReportDescriptor -* Issue report Descriptor command to the device. Once the response -* received, parse the report descriptor and update the status. -* @param pdev : Selected device -* @param Length : HID Report Descriptor Length -* @retval USBH_Status : Response for USB HID Get Report Descriptor Request -*/ -static USBH_Status USBH_Get_HID_ReportDescriptor (USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint16_t length) -{ - - USBH_Status status; - - status = USBH_GetDescriptor(pdev, - phost, - USB_REQ_RECIPIENT_INTERFACE - | USB_REQ_TYPE_STANDARD, - USB_DESC_HID_REPORT, - pdev->host.Rx_Buffer, - length); - - /* HID report descriptor is available in pdev->host.Rx_Buffer. - In case of USB Boot Mode devices for In report handling , - HID report descriptor parsing is not required. - In case, for supporting Non-Boot Protocol devices and output reports, - user may parse the report descriptor*/ - - - return status; -} - -/** -* @brief USBH_Get_HID_Descriptor -* Issue HID Descriptor command to the device. Once the response -* received, parse the report descriptor and update the status. -* @param pdev : Selected device -* @param Length : HID Descriptor Length -* @retval USBH_Status : Response for USB HID Get Report Descriptor Request -*/ -static USBH_Status USBH_Get_HID_Descriptor (USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint16_t length) -{ - - USBH_Status status; - - status = USBH_GetDescriptor(pdev, - phost, - USB_REQ_RECIPIENT_INTERFACE - | USB_REQ_TYPE_STANDARD, - USB_DESC_HID, - pdev->host.Rx_Buffer, - length); - - return status; -} - -/** -* @brief USBH_Set_Idle -* Set Idle State. -* @param pdev: Selected device -* @param duration: Duration for HID Idle request -* @param reportID : Targetted report ID for Set Idle request -* @retval USBH_Status : Response for USB Set Idle request -*/ -static USBH_Status USBH_Set_Idle (USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t duration, - uint8_t reportId) -{ - - phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_INTERFACE |\ - USB_REQ_TYPE_CLASS; - - - phost->Control.setup.b.bRequest = USB_HID_SET_IDLE; - phost->Control.setup.b.wValue.w = (duration << 8 ) | reportId; - - phost->Control.setup.b.wIndex.w = 0; - phost->Control.setup.b.wLength.w = 0; - - return USBH_CtlReq(pdev, phost, 0 , 0 ); -} - - -/** -* @brief USBH_Set_Report -* Issues Set Report -* @param pdev: Selected device -* @param reportType : Report type to be sent -* @param reportID : Targetted report ID for Set Report request -* @param reportLen : Length of data report to be send -* @param reportBuff : Report Buffer -* @retval USBH_Status : Response for USB Set Idle request -*/ -USBH_Status USBH_Set_Report (USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t reportType, - uint8_t reportId, - uint8_t reportLen, - uint8_t* reportBuff) -{ - - phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_INTERFACE |\ - USB_REQ_TYPE_CLASS; - - - phost->Control.setup.b.bRequest = USB_HID_SET_REPORT; - phost->Control.setup.b.wValue.w = (reportType << 8 ) | reportId; - - phost->Control.setup.b.wIndex.w = 0; - phost->Control.setup.b.wLength.w = reportLen; - - return USBH_CtlReq(pdev, phost, reportBuff , reportLen ); -} - - -/** -* @brief USBH_Set_Protocol -* Set protocol State. -* @param pdev: Selected device -* @param protocol : Set Protocol for HID : boot/report protocol -* @retval USBH_Status : Response for USB Set Protocol request -*/ -static USBH_Status USBH_Set_Protocol(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t protocol) -{ - - - phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_INTERFACE |\ - USB_REQ_TYPE_CLASS; - - - phost->Control.setup.b.bRequest = USB_HID_SET_PROTOCOL; - - if(protocol != 0) - { - /* Boot Protocol */ - phost->Control.setup.b.wValue.w = 0; - } - else - { - /*Report Protocol*/ - phost->Control.setup.b.wValue.w = 1; - } - - phost->Control.setup.b.wIndex.w = 0; - phost->Control.setup.b.wLength.w = 0; - - return USBH_CtlReq(pdev, phost, 0 , 0 ); - -} - -/** -* @brief USBH_ParseHIDDesc -* This function Parse the HID descriptor -* @param buf: Buffer where the source descriptor is available -* @retval None -*/ -static void USBH_ParseHIDDesc (USBH_HIDDesc_TypeDef *desc, uint8_t *buf) -{ - - desc->bLength = *(uint8_t *) (buf + 0); - desc->bDescriptorType = *(uint8_t *) (buf + 1); - desc->bcdHID = LE16 (buf + 2); - desc->bCountryCode = *(uint8_t *) (buf + 4); - desc->bNumDescriptors = *(uint8_t *) (buf + 5); - desc->bReportDescriptorType = *(uint8_t *) (buf + 6); - desc->wItemLength = LE16 (buf + 7); - -} -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - - -/** -* @} -*/ - - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmusbh/usbh_hid_core.h b/stm/stmusbh/usbh_hid_core.h deleted file mode 100644 index d2e8fb847..000000000 --- a/stm/stmusbh/usbh_hid_core.h +++ /dev/null @@ -1,203 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_hid_core.h - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief This file contains all the prototypes for the usbh_hid_core.c - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive ----------------------------------------------*/ -#ifndef __USBH_HID_CORE_H -#define __USBH_HID_CORE_H - -/* Includes ------------------------------------------------------------------*/ -#include "usbh_core.h" -#include "usbh_stdreq.h" -#include "usb_bsp.h" -#include "usbh_ioreq.h" -#include "usbh_hcs.h" - -/** @addtogroup USBH_LIB - * @{ - */ - -/** @addtogroup USBH_CLASS - * @{ - */ - -/** @addtogroup USBH_HID_CLASS - * @{ - */ - -/** @defgroup USBH_HID_CORE - * @brief This file is the Header file for USBH_HID_CORE.c - * @{ - */ - - -/** @defgroup USBH_HID_CORE_Exported_Types - * @{ - */ - -#define HID_MIN_POLL 10 - -/* States for HID State Machine */ -typedef enum -{ - HID_IDLE= 0, - HID_SEND_DATA, - HID_BUSY, - HID_GET_DATA, - HID_SYNC, - HID_POLL, - HID_ERROR, -} -HID_State; - -typedef enum -{ - HID_REQ_IDLE = 0, - HID_REQ_GET_REPORT_DESC, - HID_REQ_GET_HID_DESC, - HID_REQ_SET_IDLE, - HID_REQ_SET_PROTOCOL, - HID_REQ_SET_REPORT, - -} -HID_CtlState; - -typedef struct HID_cb -{ - void (*Init) (void); - void (*Decode) (uint8_t *data); - -} HID_cb_TypeDef; - -typedef struct _HID_Report -{ - uint8_t ReportID; - uint8_t ReportType; - uint16_t UsagePage; - uint32_t Usage[2]; - uint32_t NbrUsage; - uint32_t UsageMin; - uint32_t UsageMax; - int32_t LogMin; - int32_t LogMax; - int32_t PhyMin; - int32_t PhyMax; - int32_t UnitExp; - uint32_t Unit; - uint32_t ReportSize; - uint32_t ReportCnt; - uint32_t Flag; - uint32_t PhyUsage; - uint32_t AppUsage; - uint32_t LogUsage; -} -HID_Report_TypeDef; - -/* Structure for HID process */ -typedef struct _HID_Process -{ - uint8_t buff[64]; - uint8_t hc_num_in; - uint8_t hc_num_out; - HID_State state; - uint8_t HIDIntOutEp; - uint8_t HIDIntInEp; - HID_CtlState ctl_state; - uint16_t length; - uint8_t ep_addr; - uint16_t poll; - __IO uint16_t timer; - HID_cb_TypeDef *cb; -} -HID_Machine_TypeDef; - -/** - * @} - */ - -/** @defgroup USBH_HID_CORE_Exported_Defines - * @{ - */ - -#define USB_HID_REQ_GET_REPORT 0x01 -#define USB_HID_GET_IDLE 0x02 -#define USB_HID_GET_PROTOCOL 0x03 -#define USB_HID_SET_REPORT 0x09 -#define USB_HID_SET_IDLE 0x0A -#define USB_HID_SET_PROTOCOL 0x0B -/** - * @} - */ - -/** @defgroup USBH_HID_CORE_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USBH_HID_CORE_Exported_Variables - * @{ - */ -extern USBH_Class_cb_TypeDef HID_cb; -/** - * @} - */ - -/** @defgroup USBH_HID_CORE_Exported_FunctionsPrototype - * @{ - */ - -USBH_Status USBH_Set_Report (USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t reportType, - uint8_t reportId, - uint8_t reportLen, - uint8_t* reportBuff); -/** - * @} - */ - - -#endif /* __USBH_HID_CORE_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/stm/stmusbh/usbh_hid_keybd.c b/stm/stmusbh/usbh_hid_keybd.c deleted file mode 100644 index 089362a34..000000000 --- a/stm/stmusbh/usbh_hid_keybd.c +++ /dev/null @@ -1,367 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_hid_keybd.c - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief This file is the application layer for USB Host HID Keyboard handling - * QWERTY and AZERTY Keyboard are supported as per the selection in - * usbh_hid_keybd.h - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - - -/* Includes ------------------------------------------------------------------*/ -#include "usbh_hid_keybd.h" - -/** @addtogroup USBH_LIB -* @{ -*/ - -/** @addtogroup USBH_CLASS -* @{ -*/ - -/** @addtogroup USBH_HID_CLASS -* @{ -*/ - -/** @defgroup USBH_HID_KEYBD -* @brief This file includes HID Layer Handlers for USB Host HID class. -* @{ -*/ - -/** @defgroup USBH_HID_KEYBD_Private_TypesDefinitions -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USBH_HID_KEYBD_Private_Defines -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USBH_HID_KEYBD_Private_Macros -* @{ -*/ -/** -* @} -*/ - -/** @defgroup USBH_HID_KEYBD_Private_FunctionPrototypes -* @{ -*/ -static void KEYBRD_Init (void); -static void KEYBRD_Decode(uint8_t *data); - -/** -* @} -*/ - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined (__CC_ARM) /*!< ARM Compiler */ - __align(4) - #elif defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #elif defined (__GNUC__) /*!< GNU Compiler */ - #pragma pack(4) - #elif defined (__TASKING__) /*!< TASKING Compiler */ - __align(4) - #endif /* __CC_ARM */ -#endif - -/** @defgroup USBH_HID_KEYBD_Private_Variables -* @{ -*/ -HID_cb_TypeDef HID_KEYBRD_cb= -{ - KEYBRD_Init, - KEYBRD_Decode -}; - -/* -******************************************************************************* -* LOCAL CONSTANTS -******************************************************************************* -*/ - -static const uint8_t HID_KEYBRD_Codes[] = { - 0, 0, 0, 0, 31, 50, 48, 33, - 19, 34, 35, 36, 24, 37, 38, 39, /* 0x00 - 0x0F */ - 52, 51, 25, 26, 17, 20, 32, 21, - 23, 49, 18, 47, 22, 46, 2, 3, /* 0x10 - 0x1F */ - 4, 5, 6, 7, 8, 9, 10, 11, - 43, 110, 15, 16, 61, 12, 13, 27, /* 0x20 - 0x2F */ - 28, 29, 42, 40, 41, 1, 53, 54, - 55, 30, 112, 113, 114, 115, 116, 117, /* 0x30 - 0x3F */ - 118, 119, 120, 121, 122, 123, 124, 125, - 126, 75, 80, 85, 76, 81, 86, 89, /* 0x40 - 0x4F */ - 79, 84, 83, 90, 95, 100, 105, 106, - 108, 93, 98, 103, 92, 97, 102, 91, /* 0x50 - 0x5F */ - 96, 101, 99, 104, 45, 129, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, /* 0x60 - 0x6F */ - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, /* 0x70 - 0x7F */ - 0, 0, 0, 0, 0, 107, 0, 56, - 0, 0, 0, 0, 0, 0, 0, 0, /* 0x80 - 0x8F */ - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, /* 0x90 - 0x9F */ - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, /* 0xA0 - 0xAF */ - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, /* 0xB0 - 0xBF */ - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, /* 0xC0 - 0xCF */ - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, /* 0xD0 - 0xDF */ - 58, 44, 60, 127, 64, 57, 62, 128 /* 0xE0 - 0xE7 */ -}; - -#ifdef QWERTY_KEYBOARD -static const int8_t HID_KEYBRD_Key[] = { - '\0', '`', '1', '2', '3', '4', '5', '6', - '7', '8', '9', '0', '-', '=', '\0', 127, // dpgeorge 127 used to be \r (it's backspace) - '\t', 'q', 'w', 'e', 'r', 't', 'y', 'u', - 'i', 'o', 'p', '[', ']', '\\', - '\0', 'a', 's', 'd', 'f', 'g', 'h', 'j', - 'k', 'l', ';', '\'', '\0', '\r', // dpgeorge \r used to be \n (it's enter) - '\0', '\0', 'z', 'x', 'c', 'v', 'b', 'n', - 'm', ',', '.', '/', '\0', '\0', - '\0', '\0', '\0', ' ', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\r', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '7', '4', '1', - '\0', '/', '8', '5', '2', - '0', '*', '9', '6', '3', - '.', '-', '+', '\0', '\n', '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0' -}; - -static const int8_t HID_KEYBRD_ShiftKey[] = { - '\0', '~', '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', - '_', '+', '\0', '\0', '\0', 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', - 'I', 'O', 'P', '{', '}', '|', '\0', 'A', 'S', 'D', 'F', 'G', - 'H', 'J', 'K', 'L', ':', '"', '\0', '\r', '\0', '\0', 'Z', 'X', // dpgeorge \r used to be \n (it's enter) - 'C', 'V', 'B', 'N', 'M', '<', '>', '?', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0' -}; - -static const int8_t HID_KEYBRD_CtrlKey[] = { - '\0', '~', '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', - '_', '+', '\0', '\0', '\0', 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', - 'I', 'O', 'P', '{', '}', '|', '\0', 'A', 'S', 4, 'F', 'G', - 'H', 'J', 'K', 'L', ':', '"', '\0', '\r', '\0', '\0', 'Z', 'X', - 'C', 'V', 'B', 'N', 'M', '<', '>', '?', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0' -}; - -#else - -static const int8_t HID_KEYBRD_Key[] = { - '\0', '`', '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', - '-', '=', '\0', '\r', '\t', 'a', 'z', 'e', 'r', 't', 'y', 'u', - 'i', 'o', 'p', '[', ']', '\\', '\0', 'q', 's', 'd', 'f', 'g', - 'h', 'j', 'k', 'l', 'm', '\0', '\0', '\n', '\0', '\0', 'w', 'x', - 'c', 'v', 'b', 'n', ',', ';', ':', '!', '\0', '\0', '\0', '\0', - '\0', ' ', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\r', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '7', '4', '1','\0', '/', - '8', '5', '2', '0', '*', '9', '6', '3', '.', '-', '+', '\0', - '\n', '\0', '\0', '\0', '\0', '\0', '\0','\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0' -}; - -static const int8_t HID_KEYBRD_ShiftKey[] = { - '\0', '~', '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', '_', - '+', '\0', '\0', '\0', 'A', 'Z', 'E', 'R', 'T', 'Y', 'U', 'I', 'O', - 'P', '{', '}', '*', '\0', 'Q', 'S', 'D', 'F', 'G', 'H', 'J', 'K', - 'L', 'M', '%', '\0', '\n', '\0', '\0', 'W', 'X', 'C', 'V', 'B', 'N', - '?', '.', '/', '\0', '\0', '\0','\0', '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0' -}; -#endif - -/** -* @} -*/ - - -/** @defgroup USBH_HID_KEYBD_Private_Functions -* @{ -*/ - - -/** -* @brief KEYBRD_Init. -* Initialize the keyboard function. -* @param None -* @retval None -*/ -static void KEYBRD_Init (void) -{ - /* Call User Init*/ - USR_KEYBRD_Init(); -} - -/** -* @brief KEYBRD_ProcessData. -* The function is to decode the pressed keys. -* @param pbuf : Pointer to the HID IN report data buffer -* @retval None -*/ - -static void KEYBRD_Decode(uint8_t *pbuf) -{ - static uint8_t shift; - static uint8_t ctrl; - static uint8_t keys[KBR_MAX_NBR_PRESSED]; - static uint8_t keys_new[KBR_MAX_NBR_PRESSED]; - static uint8_t keys_last[KBR_MAX_NBR_PRESSED]; - static uint8_t key_newest; - static uint8_t nbr_keys; - static uint8_t nbr_keys_new; - static uint8_t nbr_keys_last; - uint8_t ix; - uint8_t jx; - uint8_t error; - uint8_t output; - - nbr_keys = 0; - nbr_keys_new = 0; - nbr_keys_last = 0; - key_newest = 0x00; - - - /* Check if Shift key is pressed */ - if ((pbuf[0] == KBD_LEFT_SHIFT) || (pbuf[0] == KBD_RIGHT_SHIFT)) { - shift = TRUE; - } else { - shift = FALSE; - } - /* Check if Ctrl key is pressed */ - if ((pbuf[0] == KBD_LEFT_CTRL) || (pbuf[0] == KBD_RIGHT_CTRL)) { - ctrl = TRUE; - } else { - ctrl = FALSE; - } - - error = FALSE; - - /* Check for the value of pressed key */ - for (ix = 2; ix < 2 + KBR_MAX_NBR_PRESSED; ix++) { - if ((pbuf[ix] == 0x01) || - (pbuf[ix] == 0x02) || - (pbuf[ix] == 0x03)) { - error = TRUE; - } - } - - if (error == TRUE) { - return; - } - - nbr_keys = 0; - nbr_keys_new = 0; - for (ix = 2; ix < 2 + KBR_MAX_NBR_PRESSED; ix++) { - if (pbuf[ix] != 0) { - keys[nbr_keys] = pbuf[ix]; - nbr_keys++; - for (jx = 0; jx < nbr_keys_last; jx++) { - if (pbuf[ix] == keys_last[jx]) { - break; - } - } - - if (jx == nbr_keys_last) { - keys_new[nbr_keys_new] = pbuf[ix]; - nbr_keys_new++; - } - } - } - - if (nbr_keys_new == 1) { - key_newest = keys_new[0]; - - if (ctrl == TRUE) { - output = HID_KEYBRD_CtrlKey[HID_KEYBRD_Codes[key_newest]]; - } else if (shift == TRUE) { - output = HID_KEYBRD_ShiftKey[HID_KEYBRD_Codes[key_newest]]; - } else { - output = HID_KEYBRD_Key[HID_KEYBRD_Codes[key_newest]]; - } - - /* call user process handle */ - USR_KEYBRD_ProcessData(output); - } else { - key_newest = 0x00; - } - - - nbr_keys_last = nbr_keys; - for (ix = 0; ix < KBR_MAX_NBR_PRESSED; ix++) { - keys_last[ix] = keys[ix]; - } -} - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/stm/stmusbh/usbh_hid_keybd.h b/stm/stmusbh/usbh_hid_keybd.h deleted file mode 100644 index a8b34dab2..000000000 --- a/stm/stmusbh/usbh_hid_keybd.h +++ /dev/null @@ -1,128 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_hid_keybd.h - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief This file contains all the prototypes for the usbh_hid_keybd.c - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive -----------------------------------------------*/ -#ifndef __USBH_HID_KEYBD_H -#define __USBH_HID_KEYBD_H - -/* Includes ------------------------------------------------------------------*/ -#include "usb_conf.h" -#include "usbh_hid_core.h" - -/** @addtogroup USBH_LIB - * @{ - */ - -/** @addtogroup USBH_CLASS - * @{ - */ - -/** @addtogroup USBH_HID_CLASS - * @{ - */ - -/** @defgroup USBH_HID_KEYBD - * @brief This file is the Header file for USBH_HID_KEYBD.c - * @{ - */ - - -/** @defgroup USBH_HID_KEYBD_Exported_Types - * @{ - */ - - -/** - * @} - */ - -/** @defgroup USBH_HID_KEYBD_Exported_Defines - * @{ - */ -#define QWERTY_KEYBOARD -//#define AZERTY_KEYBOARD - -#define KBD_LEFT_CTRL 0x01 -#define KBD_LEFT_SHIFT 0x02 -#define KBD_LEFT_ALT 0x04 -#define KBD_LEFT_GUI 0x08 -#define KBD_RIGHT_CTRL 0x10 -#define KBD_RIGHT_SHIFT 0x20 -#define KBD_RIGHT_ALT 0x40 -#define KBD_RIGHT_GUI 0x80 - -#define KBR_MAX_NBR_PRESSED 6 - -/** - * @} - */ - -/** @defgroup USBH_HID_KEYBD_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USBH_HID_KEYBD_Exported_Variables - * @{ - */ - -extern HID_cb_TypeDef HID_KEYBRD_cb; -/** - * @} - */ - -/** @defgroup USBH_HID_KEYBD_Exported_FunctionsPrototype - * @{ - */ -void USR_KEYBRD_Init (void); -void USR_KEYBRD_ProcessData (uint8_t pbuf); -/** - * @} - */ - -#endif /* __USBH_HID_KEYBD_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/stm/stmusbh/usbh_hid_mouse.c b/stm/stmusbh/usbh_hid_mouse.c deleted file mode 100644 index ffb9f5f26..000000000 --- a/stm/stmusbh/usbh_hid_mouse.c +++ /dev/null @@ -1,161 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_hid_mouse.c - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief This file is the application layer for USB Host HID Mouse Handling. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbh_hid_mouse.h" - - -/** @addtogroup USBH_LIB - * @{ - */ - -/** @addtogroup USBH_CLASS - * @{ - */ - -/** @addtogroup USBH_HID_CLASS - * @{ - */ - -/** @defgroup USBH_HID_MOUSE - * @brief This file includes HID Layer Handlers for USB Host HID class. - * @{ - */ - -/** @defgroup USBH_HID_MOUSE_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBH_HID_MOUSE_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBH_HID_MOUSE_Private_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USBH_HID_MOUSE_Private_FunctionPrototypes - * @{ - */ -static void MOUSE_Init (void); -static void MOUSE_Decode(uint8_t *data); -/** - * @} - */ - - -/** @defgroup USBH_HID_MOUSE_Private_Variables - * @{ - */ -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined (__CC_ARM) /*!< ARM Compiler */ - __align(4) - #elif defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #elif defined (__GNUC__) /*!< GNU Compiler */ - #pragma pack(4) - #elif defined (__TASKING__) /*!< TASKING Compiler */ - __align(4) - #endif /* __CC_ARM */ -#endif - - -HID_MOUSE_Data_TypeDef HID_MOUSE_Data; -HID_cb_TypeDef HID_MOUSE_cb = -{ - MOUSE_Init, - MOUSE_Decode, -}; -/** - * @} - */ - - -/** @defgroup USBH_HID_MOUSE_Private_Functions - * @{ - */ - -/** -* @brief MOUSE_Init -* Init Mouse State. -* @param None -* @retval None -*/ -static void MOUSE_Init ( void) -{ - /* Call User Init*/ - USR_MOUSE_Init(); -} - -/** -* @brief MOUSE_Decode -* Decode Mouse data -* @param data : Pointer to Mouse HID data buffer -* @retval None -*/ -static void MOUSE_Decode(uint8_t *data) -{ - HID_MOUSE_Data.button = data[0]; - - HID_MOUSE_Data.x = data[1]; - HID_MOUSE_Data.y = data[2]; - - USR_MOUSE_ProcessData(&HID_MOUSE_Data); - -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmusbh/usbh_hid_mouse.h b/stm/stmusbh/usbh_hid_mouse.h deleted file mode 100644 index 93ed6bed2..000000000 --- a/stm/stmusbh/usbh_hid_mouse.h +++ /dev/null @@ -1,120 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_hid_mouse.h - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief This file contains all the prototypes for the usbh_hid_mouse.c - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - - -/* Define to prevent recursive ----------------------------------------------*/ -#ifndef __USBH_HID_MOUSE_H -#define __USBH_HID_MOUSE_H - -/* Includes ------------------------------------------------------------------*/ -#include "usbh_hid_core.h" - -/** @addtogroup USBH_LIB - * @{ - */ - -/** @addtogroup USBH_CLASS - * @{ - */ - -/** @addtogroup USBH_HID_CLASS - * @{ - */ - -/** @defgroup USBH_HID_MOUSE - * @brief This file is the Header file for USBH_HID_MOUSE.c - * @{ - */ - - -/** @defgroup USBH_HID_MOUSE_Exported_Types - * @{ - */ -typedef struct _HID_MOUSE_Data -{ - uint8_t x; - uint8_t y; - uint8_t z; /* Not Supported */ - uint8_t button; -} -HID_MOUSE_Data_TypeDef; - -/** - * @} - */ - -/** @defgroup USBH_HID_MOUSE_Exported_Defines - * @{ - */ -/** - * @} - */ - -/** @defgroup USBH_HID_MOUSE_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USBH_HID_MOUSE_Exported_Variables - * @{ - */ - -extern HID_cb_TypeDef HID_MOUSE_cb; -extern HID_MOUSE_Data_TypeDef HID_MOUSE_Data; -/** - * @} - */ - -/** @defgroup USBH_HID_MOUSE_Exported_FunctionsPrototype - * @{ - */ -void USR_MOUSE_Init (void); -void USR_MOUSE_ProcessData (HID_MOUSE_Data_TypeDef *data); -/** - * @} - */ - -#endif /* __USBH_HID_MOUSE_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmusbh/usbh_ioreq.c b/stm/stmusbh/usbh_ioreq.c deleted file mode 100644 index 21f480d7b..000000000 --- a/stm/stmusbh/usbh_ioreq.c +++ /dev/null @@ -1,474 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_ioreq.c - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief This file handles the issuing of the USB transactions - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ - -#include "usbh_ioreq.h" - -/** @addtogroup USBH_LIB - * @{ - */ - -/** @addtogroup USBH_LIB_CORE -* @{ -*/ - -/** @defgroup USBH_IOREQ - * @brief This file handles the standard protocol processing (USB v2.0) - * @{ - */ - - -/** @defgroup USBH_IOREQ_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBH_IOREQ_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - - -/** @defgroup USBH_IOREQ_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBH_IOREQ_Private_Variables - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBH_IOREQ_Private_FunctionPrototypes - * @{ - */ -static USBH_Status USBH_SubmitSetupRequest(USBH_HOST *phost, - uint8_t* buff, - uint16_t length); - -/** - * @} - */ - - -/** @defgroup USBH_IOREQ_Private_Functions - * @{ - */ - - -/** - * @brief USBH_CtlReq - * USBH_CtlReq sends a control request and provide the status after - * completion of the request - * @param pdev: Selected device - * @param req: Setup Request Structure - * @param buff: data buffer address to store the response - * @param length: length of the response - * @retval Status - */ -USBH_Status USBH_CtlReq (USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t *buff, - uint16_t length) -{ - USBH_Status status; - status = USBH_BUSY; - - switch (phost->RequestState) - { - case CMD_SEND: - /* Start a SETUP transfer */ - USBH_SubmitSetupRequest(phost, buff, length); - phost->RequestState = CMD_WAIT; - status = USBH_BUSY; - break; - - case CMD_WAIT: - if (phost->Control.state == CTRL_COMPLETE ) - { - /* Commands successfully sent and Response Received */ - phost->RequestState = CMD_SEND; - phost->Control.state =CTRL_IDLE; - status = USBH_OK; - } - else if (phost->Control.state == CTRL_ERROR) - { - /* Failure Mode */ - phost->RequestState = CMD_SEND; - status = USBH_FAIL; - } - else if (phost->Control.state == CTRL_STALLED ) - { - /* Commands successfully sent and Response Received */ - phost->RequestState = CMD_SEND; - status = USBH_NOT_SUPPORTED; - } - break; - - default: - break; - } - return status; -} - -/** - * @brief USBH_CtlSendSetup - * Sends the Setup Packet to the Device - * @param pdev: Selected device - * @param buff: Buffer pointer from which the Data will be send to Device - * @param hc_num: Host channel Number - * @retval Status - */ -USBH_Status USBH_CtlSendSetup ( USB_OTG_CORE_HANDLE *pdev, - uint8_t *buff, - uint8_t hc_num){ - pdev->host.hc[hc_num].ep_is_in = 0; - pdev->host.hc[hc_num].data_pid = HC_PID_SETUP; - pdev->host.hc[hc_num].xfer_buff = buff; - pdev->host.hc[hc_num].xfer_len = USBH_SETUP_PKT_SIZE; - - return (USBH_Status)HCD_SubmitRequest (pdev , hc_num); -} - - -/** - * @brief USBH_CtlSendData - * Sends a data Packet to the Device - * @param pdev: Selected device - * @param buff: Buffer pointer from which the Data will be sent to Device - * @param length: Length of the data to be sent - * @param hc_num: Host channel Number - * @retval Status - */ -USBH_Status USBH_CtlSendData ( USB_OTG_CORE_HANDLE *pdev, - uint8_t *buff, - uint16_t length, - uint8_t hc_num) -{ - pdev->host.hc[hc_num].ep_is_in = 0; - pdev->host.hc[hc_num].xfer_buff = buff; - pdev->host.hc[hc_num].xfer_len = length; - - if ( length == 0 ) - { /* For Status OUT stage, Length==0, Status Out PID = 1 */ - pdev->host.hc[hc_num].toggle_out = 1; - } - - /* Set the Data Toggle bit as per the Flag */ - if ( pdev->host.hc[hc_num].toggle_out == 0) - { /* Put the PID 0 */ - pdev->host.hc[hc_num].data_pid = HC_PID_DATA0; - } - else - { /* Put the PID 1 */ - pdev->host.hc[hc_num].data_pid = HC_PID_DATA1 ; - } - - HCD_SubmitRequest (pdev , hc_num); - - return USBH_OK; -} - - -/** - * @brief USBH_CtlReceiveData - * Receives the Device Response to the Setup Packet - * @param pdev: Selected device - * @param buff: Buffer pointer in which the response needs to be copied - * @param length: Length of the data to be received - * @param hc_num: Host channel Number - * @retval Status. - */ -USBH_Status USBH_CtlReceiveData(USB_OTG_CORE_HANDLE *pdev, - uint8_t* buff, - uint16_t length, - uint8_t hc_num) -{ - - pdev->host.hc[hc_num].ep_is_in = 1; - pdev->host.hc[hc_num].data_pid = HC_PID_DATA1; - pdev->host.hc[hc_num].xfer_buff = buff; - pdev->host.hc[hc_num].xfer_len = length; - - HCD_SubmitRequest (pdev , hc_num); - - return USBH_OK; - -} - - -/** - * @brief USBH_BulkSendData - * Sends the Bulk Packet to the device - * @param pdev: Selected device - * @param buff: Buffer pointer from which the Data will be sent to Device - * @param length: Length of the data to be sent - * @param hc_num: Host channel Number - * @retval Status - */ -USBH_Status USBH_BulkSendData ( USB_OTG_CORE_HANDLE *pdev, - uint8_t *buff, - uint16_t length, - uint8_t hc_num) -{ - pdev->host.hc[hc_num].ep_is_in = 0; - pdev->host.hc[hc_num].xfer_buff = buff; - pdev->host.hc[hc_num].xfer_len = length; - - /* Set the Data Toggle bit as per the Flag */ - if ( pdev->host.hc[hc_num].toggle_out == 0) - { /* Put the PID 0 */ - pdev->host.hc[hc_num].data_pid = HC_PID_DATA0; - } - else - { /* Put the PID 1 */ - pdev->host.hc[hc_num].data_pid = HC_PID_DATA1 ; - } - - HCD_SubmitRequest (pdev , hc_num); - return USBH_OK; -} - - -/** - * @brief USBH_BulkReceiveData - * Receives IN bulk packet from device - * @param pdev: Selected device - * @param buff: Buffer pointer in which the received data packet to be copied - * @param length: Length of the data to be received - * @param hc_num: Host channel Number - * @retval Status. - */ -USBH_Status USBH_BulkReceiveData( USB_OTG_CORE_HANDLE *pdev, - uint8_t *buff, - uint16_t length, - uint8_t hc_num) -{ - pdev->host.hc[hc_num].ep_is_in = 1; - pdev->host.hc[hc_num].xfer_buff = buff; - pdev->host.hc[hc_num].xfer_len = length; - - - if( pdev->host.hc[hc_num].toggle_in == 0) - { - pdev->host.hc[hc_num].data_pid = HC_PID_DATA0; - } - else - { - pdev->host.hc[hc_num].data_pid = HC_PID_DATA1; - } - - HCD_SubmitRequest (pdev , hc_num); - return USBH_OK; -} - - -/** - * @brief USBH_InterruptReceiveData - * Receives the Device Response to the Interrupt IN token - * @param pdev: Selected device - * @param buff: Buffer pointer in which the response needs to be copied - * @param length: Length of the data to be received - * @param hc_num: Host channel Number - * @retval Status. - */ -USBH_Status USBH_InterruptReceiveData( USB_OTG_CORE_HANDLE *pdev, - uint8_t *buff, - uint8_t length, - uint8_t hc_num) -{ - - pdev->host.hc[hc_num].ep_is_in = 1; - pdev->host.hc[hc_num].xfer_buff = buff; - pdev->host.hc[hc_num].xfer_len = length; - - - - if(pdev->host.hc[hc_num].toggle_in == 0) - { - pdev->host.hc[hc_num].data_pid = HC_PID_DATA0; - } - else - { - pdev->host.hc[hc_num].data_pid = HC_PID_DATA1; - } - - /* toggle DATA PID */ - pdev->host.hc[hc_num].toggle_in ^= 1; - - HCD_SubmitRequest (pdev , hc_num); - - return USBH_OK; -} - -/** - * @brief USBH_InterruptSendData - * Sends the data on Interrupt OUT Endpoint - * @param pdev: Selected device - * @param buff: Buffer pointer from where the data needs to be copied - * @param length: Length of the data to be sent - * @param hc_num: Host channel Number - * @retval Status. - */ -USBH_Status USBH_InterruptSendData( USB_OTG_CORE_HANDLE *pdev, - uint8_t *buff, - uint8_t length, - uint8_t hc_num) -{ - - pdev->host.hc[hc_num].ep_is_in = 0; - pdev->host.hc[hc_num].xfer_buff = buff; - pdev->host.hc[hc_num].xfer_len = length; - - if(pdev->host.hc[hc_num].toggle_in == 0) - { - pdev->host.hc[hc_num].data_pid = HC_PID_DATA0; - } - else - { - pdev->host.hc[hc_num].data_pid = HC_PID_DATA1; - } - - pdev->host.hc[hc_num].toggle_in ^= 1; - - HCD_SubmitRequest (pdev , hc_num); - - return USBH_OK; -} - - -/** - * @brief USBH_SubmitSetupRequest - * Start a setup transfer by changing the state-machine and - * initializing the required variables needed for the Control Transfer - * @param pdev: Selected device - * @param setup: Setup Request Structure - * @param buff: Buffer used for setup request - * @param length: Length of the data - * @retval Status. -*/ -static USBH_Status USBH_SubmitSetupRequest(USBH_HOST *phost, - uint8_t* buff, - uint16_t length) -{ - - /* Save Global State */ - phost->gStateBkp = phost->gState; - - /* Prepare the Transactions */ - phost->gState = HOST_CTRL_XFER; - phost->Control.buff = buff; - phost->Control.length = length; - phost->Control.state = CTRL_SETUP; - - return USBH_OK; -} - - -/** - * @brief USBH_IsocReceiveData - * Receives the Device Response to the Isochronous IN token - * @param pdev: Selected device - * @param buff: Buffer pointer in which the response needs to be copied - * @param length: Length of the data to be received - * @param hc_num: Host channel Number - * @retval Status. - */ -USBH_Status USBH_IsocReceiveData( USB_OTG_CORE_HANDLE *pdev, - uint8_t *buff, - uint32_t length, - uint8_t hc_num) -{ - - pdev->host.hc[hc_num].ep_is_in = 1; - pdev->host.hc[hc_num].xfer_buff = buff; - pdev->host.hc[hc_num].xfer_len = length; - pdev->host.hc[hc_num].data_pid = HC_PID_DATA0; - - - HCD_SubmitRequest (pdev , hc_num); - - return USBH_OK; -} - -/** - * @brief USBH_IsocSendData - * Sends the data on Isochronous OUT Endpoint - * @param pdev: Selected device - * @param buff: Buffer pointer from where the data needs to be copied - * @param length: Length of the data to be sent - * @param hc_num: Host channel Number - * @retval Status. - */ -USBH_Status USBH_IsocSendData( USB_OTG_CORE_HANDLE *pdev, - uint8_t *buff, - uint32_t length, - uint8_t hc_num) -{ - - pdev->host.hc[hc_num].ep_is_in = 0; - pdev->host.hc[hc_num].xfer_buff = buff; - pdev->host.hc[hc_num].xfer_len = length; - pdev->host.hc[hc_num].data_pid = HC_PID_DATA0; - - HCD_SubmitRequest (pdev , hc_num); - - return USBH_OK; -} - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - - diff --git a/stm/stmusbh/usbh_ioreq.h b/stm/stmusbh/usbh_ioreq.h deleted file mode 100644 index aba253b84..000000000 --- a/stm/stmusbh/usbh_ioreq.h +++ /dev/null @@ -1,156 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_ioreq.h - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief Header file for usbh_ioreq.c - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive ----------------------------------------------*/ -#ifndef __USBH_IOREQ_H -#define __USBH_IOREQ_H - -/* Includes ------------------------------------------------------------------*/ -#include "usb_conf.h" -#include "usbh_core.h" -#include "usbh_def.h" - -/** @addtogroup USBH_LIB - * @{ - */ - -/** @addtogroup USBH_LIB_CORE -* @{ -*/ - -/** @defgroup USBH_IOREQ - * @brief This file is the header file for usbh_ioreq.c - * @{ - */ - - -/** @defgroup USBH_IOREQ_Exported_Defines - * @{ - */ -#define USBH_SETUP_PKT_SIZE 8 -#define USBH_EP0_EP_NUM 0 -#define USBH_MAX_PACKET_SIZE 0x40 -/** - * @} - */ - - -/** @defgroup USBH_IOREQ_Exported_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBH_IOREQ_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USBH_IOREQ_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USBH_IOREQ_Exported_FunctionsPrototype - * @{ - */ -USBH_Status USBH_CtlSendSetup ( USB_OTG_CORE_HANDLE *pdev, - uint8_t *buff, - uint8_t hc_num); - -USBH_Status USBH_CtlSendData ( USB_OTG_CORE_HANDLE *pdev, - uint8_t *buff, - uint16_t length, - uint8_t hc_num); - -USBH_Status USBH_CtlReceiveData( USB_OTG_CORE_HANDLE *pdev, - uint8_t *buff, - uint16_t length, - uint8_t hc_num); - -USBH_Status USBH_BulkReceiveData( USB_OTG_CORE_HANDLE *pdev, - uint8_t *buff, - uint16_t length, - uint8_t hc_num); - -USBH_Status USBH_BulkSendData ( USB_OTG_CORE_HANDLE *pdev, - uint8_t *buff, - uint16_t length, - uint8_t hc_num); - -USBH_Status USBH_InterruptReceiveData( USB_OTG_CORE_HANDLE *pdev, - uint8_t *buff, - uint8_t length, - uint8_t hc_num); - -USBH_Status USBH_InterruptSendData( USB_OTG_CORE_HANDLE *pdev, - uint8_t *buff, - uint8_t length, - uint8_t hc_num); - -USBH_Status USBH_CtlReq (USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t *buff, - uint16_t length); - -USBH_Status USBH_IsocReceiveData( USB_OTG_CORE_HANDLE *pdev, - uint8_t *buff, - uint32_t length, - uint8_t hc_num); - - -USBH_Status USBH_IsocSendData( USB_OTG_CORE_HANDLE *pdev, - uint8_t *buff, - uint32_t length, - uint8_t hc_num); -/** - * @} - */ - -#endif /* __USBH_IOREQ_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - diff --git a/stm/stmusbh/usbh_stdreq.c b/stm/stmusbh/usbh_stdreq.c deleted file mode 100644 index 9b134fa02..000000000 --- a/stm/stmusbh/usbh_stdreq.c +++ /dev/null @@ -1,607 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_stdreq.c - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief This file implements the standard requests for device enumeration - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ - -#include "usbh_ioreq.h" -#include "usbh_stdreq.h" - -/** @addtogroup USBH_LIB -* @{ -*/ - -/** @addtogroup USBH_LIB_CORE -* @{ -*/ - -/** @defgroup USBH_STDREQ -* @brief This file implements the standard requests for device enumeration -* @{ -*/ - - -/** @defgroup USBH_STDREQ_Private_Defines -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USBH_STDREQ_Private_TypesDefinitions -* @{ -*/ -/** -* @} -*/ - - - -/** @defgroup USBH_STDREQ_Private_Macros -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USBH_STDREQ_Private_Variables -* @{ -*/ -/** -* @} -*/ -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN uint8_t USBH_CfgDesc[512] __ALIGN_END ; - - -/** @defgroup USBH_STDREQ_Private_FunctionPrototypes -* @{ -*/ -static void USBH_ParseDevDesc (USBH_DevDesc_TypeDef* , uint8_t *buf, uint16_t length); - -static void USBH_ParseCfgDesc (USBH_CfgDesc_TypeDef* cfg_desc, - USBH_InterfaceDesc_TypeDef* itf_desc, - USBH_EpDesc_TypeDef ep_desc[][USBH_MAX_NUM_ENDPOINTS], - uint8_t *buf, - uint16_t length); - - -static void USBH_ParseInterfaceDesc (USBH_InterfaceDesc_TypeDef *if_descriptor, uint8_t *buf); -static void USBH_ParseEPDesc (USBH_EpDesc_TypeDef *ep_descriptor, uint8_t *buf); - -static void USBH_ParseStringDesc (uint8_t* psrc, uint8_t* pdest, uint16_t length); -/** -* @} -*/ - - -/** @defgroup USBH_STDREQ_Private_Functions -* @{ -*/ - - -/** -* @brief USBH_Get_DevDesc -* Issue Get Device Descriptor command to the device. Once the response -* received, it parses the device descriptor and updates the status. -* @param pdev: Selected device -* @param dev_desc: Device Descriptor buffer address -* @param pdev->host.Rx_Buffer: Receive Buffer address -* @param length: Length of the descriptor -* @retval Status -*/ -USBH_Status USBH_Get_DevDesc(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t length) -{ - - USBH_Status status; - - if((status = USBH_GetDescriptor(pdev, - phost, - USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD, - USB_DESC_DEVICE, - pdev->host.Rx_Buffer, - length)) == USBH_OK) - { - /* Commands successfully sent and Response Received */ - USBH_ParseDevDesc(&phost->device_prop.Dev_Desc, pdev->host.Rx_Buffer, length); - } - return status; -} - -/** -* @brief USBH_Get_CfgDesc -* Issues Configuration Descriptor to the device. Once the response -* received, it parses the configuartion descriptor and updates the -* status. -* @param pdev: Selected device -* @param cfg_desc: Configuration Descriptor address -* @param itf_desc: Interface Descriptor address -* @param ep_desc: Endpoint Descriptor address -* @param length: Length of the descriptor -* @retval Status -*/ -USBH_Status USBH_Get_CfgDesc(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint16_t length) - -{ - USBH_Status status; - uint16_t index = 0; - - if((status = USBH_GetDescriptor(pdev, - phost, - USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD, - USB_DESC_CONFIGURATION, - pdev->host.Rx_Buffer, - length)) == USBH_OK) - { - /*save Cfg descriptor for class parsing usage */ - for( ; index < length ; index ++) - { - USBH_CfgDesc[index] = pdev->host.Rx_Buffer[index]; - } - - /* Commands successfully sent and Response Received */ - USBH_ParseCfgDesc (&phost->device_prop.Cfg_Desc, - phost->device_prop.Itf_Desc, - phost->device_prop.Ep_Desc, - pdev->host.Rx_Buffer, - length); - - } - return status; -} - - -/** -* @brief USBH_Get_StringDesc -* Issues string Descriptor command to the device. Once the response -* received, it parses the string descriptor and updates the status. -* @param pdev: Selected device -* @param string_index: String index for the descriptor -* @param buff: Buffer address for the descriptor -* @param length: Length of the descriptor -* @retval Status -*/ -USBH_Status USBH_Get_StringDesc(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t string_index, - uint8_t *buff, - uint16_t length) -{ - USBH_Status status; - - if((status = USBH_GetDescriptor(pdev, - phost, - USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD, - USB_DESC_STRING | string_index, - pdev->host.Rx_Buffer, - length)) == USBH_OK) - { - /* Commands successfully sent and Response Received */ - USBH_ParseStringDesc(pdev->host.Rx_Buffer,buff, length); - } - return status; -} - -/** -* @brief USBH_GetDescriptor -* Issues Descriptor command to the device. Once the response received, -* it parses the descriptor and updates the status. -* @param pdev: Selected device -* @param req_type: Descriptor type -* @param value_idx: wValue for the GetDescriptr request -* @param buff: Buffer to store the descriptor -* @param length: Length of the descriptor -* @retval Status -*/ -USBH_Status USBH_GetDescriptor(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t req_type, - uint16_t value_idx, - uint8_t* buff, - uint16_t length ) -{ - phost->Control.setup.b.bmRequestType = USB_D2H | req_type; - phost->Control.setup.b.bRequest = USB_REQ_GET_DESCRIPTOR; - phost->Control.setup.b.wValue.w = value_idx; - - if ((value_idx & 0xff00) == USB_DESC_STRING) - { - phost->Control.setup.b.wIndex.w = 0x0409; - } - else - { - phost->Control.setup.b.wIndex.w = 0; - } - phost->Control.setup.b.wLength.w = length; - return USBH_CtlReq(pdev, phost, buff , length ); -} - -/** -* @brief USBH_SetAddress -* This command sets the address to the connected device -* @param pdev: Selected device -* @param DeviceAddress: Device address to assign -* @retval Status -*/ -USBH_Status USBH_SetAddress(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t DeviceAddress) -{ - phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_DEVICE | \ - USB_REQ_TYPE_STANDARD; - - phost->Control.setup.b.bRequest = USB_REQ_SET_ADDRESS; - - phost->Control.setup.b.wValue.w = (uint16_t)DeviceAddress; - phost->Control.setup.b.wIndex.w = 0; - phost->Control.setup.b.wLength.w = 0; - - return USBH_CtlReq(pdev, phost, 0 , 0 ); -} - -/** -* @brief USBH_SetCfg -* The command sets the configuration value to the connected device -* @param pdev: Selected device -* @param cfg_idx: Configuration value -* @retval Status -*/ -USBH_Status USBH_SetCfg(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint16_t cfg_idx) -{ - - phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_DEVICE |\ - USB_REQ_TYPE_STANDARD; - phost->Control.setup.b.bRequest = USB_REQ_SET_CONFIGURATION; - phost->Control.setup.b.wValue.w = cfg_idx; - phost->Control.setup.b.wIndex.w = 0; - phost->Control.setup.b.wLength.w = 0; - - return USBH_CtlReq(pdev, phost, 0 , 0 ); -} - -/** -* @brief USBH_SetInterface -* The command sets the Interface value to the connected device -* @param pdev: Selected device -* @param itf_idx: Interface value -* @retval Status -*/ -USBH_Status USBH_SetInterface(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t ep_num, uint8_t altSetting) -{ - - - phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_INTERFACE | \ - USB_REQ_TYPE_STANDARD; - - phost->Control.setup.b.bRequest = USB_REQ_SET_INTERFACE; - phost->Control.setup.b.wValue.w = altSetting; - phost->Control.setup.b.wIndex.w = ep_num; - phost->Control.setup.b.wLength.w = 0; - - return USBH_CtlReq(pdev, phost, 0 , 0 ); -} -/** -* @brief USBH_ClrFeature -* This request is used to clear or disable a specific feature. - -* @param pdev: Selected device -* @param ep_num: endpoint number -* @param hc_num: Host channel number -* @retval Status -*/ -USBH_Status USBH_ClrFeature(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t ep_num, - uint8_t hc_num) -{ - - phost->Control.setup.b.bmRequestType = USB_H2D | - USB_REQ_RECIPIENT_ENDPOINT | - USB_REQ_TYPE_STANDARD; - - phost->Control.setup.b.bRequest = USB_REQ_CLEAR_FEATURE; - phost->Control.setup.b.wValue.w = FEATURE_SELECTOR_ENDPOINT; - phost->Control.setup.b.wIndex.w = ep_num; - phost->Control.setup.b.wLength.w = 0; - - if ((ep_num & USB_REQ_DIR_MASK ) == USB_D2H) - { /* EP Type is IN */ - pdev->host.hc[hc_num].toggle_in = 0; - } - else - {/* EP Type is OUT */ - pdev->host.hc[hc_num].toggle_out = 0; - } - - return USBH_CtlReq(pdev, phost, 0 , 0 ); -} - -/** -* @brief USBH_ParseDevDesc -* This function Parses the device descriptor -* @param dev_desc: device_descriptor destinaton address -* @param buf: Buffer where the source descriptor is available -* @param length: Length of the descriptor -* @retval None -*/ -static void USBH_ParseDevDesc (USBH_DevDesc_TypeDef* dev_desc, - uint8_t *buf, - uint16_t length) -{ - dev_desc->bLength = *(uint8_t *) (buf + 0); - dev_desc->bDescriptorType = *(uint8_t *) (buf + 1); - dev_desc->bcdUSB = LE16 (buf + 2); - dev_desc->bDeviceClass = *(uint8_t *) (buf + 4); - dev_desc->bDeviceSubClass = *(uint8_t *) (buf + 5); - dev_desc->bDeviceProtocol = *(uint8_t *) (buf + 6); - dev_desc->bMaxPacketSize = *(uint8_t *) (buf + 7); - - if (length > 8) - { /* For 1st time after device connection, Host may issue only 8 bytes for - Device Descriptor Length */ - dev_desc->idVendor = LE16 (buf + 8); - dev_desc->idProduct = LE16 (buf + 10); - dev_desc->bcdDevice = LE16 (buf + 12); - dev_desc->iManufacturer = *(uint8_t *) (buf + 14); - dev_desc->iProduct = *(uint8_t *) (buf + 15); - dev_desc->iSerialNumber = *(uint8_t *) (buf + 16); - dev_desc->bNumConfigurations = *(uint8_t *) (buf + 17); - } -} - -/** -* @brief USBH_ParseCfgDesc -* This function Parses the configuration descriptor -* @param cfg_desc: Configuration Descriptor address -* @param itf_desc: Interface Descriptor address -* @param ep_desc: Endpoint Descriptor address -* @param buf: Buffer where the source descriptor is available -* @param length: Length of the descriptor -* @retval None -*/ -static void USBH_ParseCfgDesc (USBH_CfgDesc_TypeDef* cfg_desc, - USBH_InterfaceDesc_TypeDef* itf_desc, - USBH_EpDesc_TypeDef ep_desc[][USBH_MAX_NUM_ENDPOINTS], - uint8_t *buf, - uint16_t length) -{ - USBH_InterfaceDesc_TypeDef *pif ; - USBH_InterfaceDesc_TypeDef temp_pif ; - USBH_EpDesc_TypeDef *pep; - USBH_DescHeader_t *pdesc = (USBH_DescHeader_t *)buf; - uint16_t ptr; - int8_t if_ix = 0; - int8_t ep_ix = 0; - static uint16_t prev_ep_size = 0; - static uint8_t prev_itf = 0; - - - pdesc = (USBH_DescHeader_t *)buf; - - /* Parse configuration descriptor */ - cfg_desc->bLength = *(uint8_t *) (buf + 0); - cfg_desc->bDescriptorType = *(uint8_t *) (buf + 1); - cfg_desc->wTotalLength = LE16 (buf + 2); - cfg_desc->bNumInterfaces = *(uint8_t *) (buf + 4); - cfg_desc->bConfigurationValue = *(uint8_t *) (buf + 5); - cfg_desc->iConfiguration = *(uint8_t *) (buf + 6); - cfg_desc->bmAttributes = *(uint8_t *) (buf + 7); - cfg_desc->bMaxPower = *(uint8_t *) (buf + 8); - - - if (length > USB_CONFIGURATION_DESC_SIZE) - { - ptr = USB_LEN_CFG_DESC; - - if ( cfg_desc->bNumInterfaces <= USBH_MAX_NUM_INTERFACES) - { - pif = (USBH_InterfaceDesc_TypeDef *)0; - - while (ptr < cfg_desc->wTotalLength ) - { - pdesc = USBH_GetNextDesc((uint8_t *)pdesc, &ptr); - if (pdesc->bDescriptorType == USB_DESC_TYPE_INTERFACE) - { - if_ix = *(((uint8_t *)pdesc ) + 2); - pif = &itf_desc[if_ix]; - - if((*((uint8_t *)pdesc + 3)) < 3) - { - USBH_ParseInterfaceDesc (&temp_pif, (uint8_t *)pdesc); - ep_ix = 0; - - /* Parse Ep descriptors relative to the current interface */ - if(temp_pif.bNumEndpoints <= USBH_MAX_NUM_ENDPOINTS) - { - while (ep_ix < temp_pif.bNumEndpoints) - { - pdesc = USBH_GetNextDesc((void* )pdesc, &ptr); - if (pdesc->bDescriptorType == USB_DESC_TYPE_ENDPOINT) - { - pep = &ep_desc[if_ix][ep_ix]; - - if(prev_itf != if_ix) - { - prev_itf = if_ix; - USBH_ParseInterfaceDesc (pif, (uint8_t *)&temp_pif); - } - else - { - if(prev_ep_size > LE16((uint8_t *)pdesc + 4)) - { - break; - } - else - { - USBH_ParseInterfaceDesc (pif, (uint8_t *)&temp_pif); - } - } - USBH_ParseEPDesc (pep, (uint8_t *)pdesc); - prev_ep_size = LE16((uint8_t *)pdesc + 4); - ep_ix++; - } - } - } - } - } - } - } - prev_ep_size = 0; - prev_itf = 0; - } -} - - -/** -* @brief USBH_ParseInterfaceDesc -* This function Parses the interface descriptor -* @param if_descriptor : Interface descriptor destination -* @param buf: Buffer where the descriptor data is available -* @retval None -*/ -static void USBH_ParseInterfaceDesc (USBH_InterfaceDesc_TypeDef *if_descriptor, - uint8_t *buf) -{ - if_descriptor->bLength = *(uint8_t *) (buf + 0); - if_descriptor->bDescriptorType = *(uint8_t *) (buf + 1); - if_descriptor->bInterfaceNumber = *(uint8_t *) (buf + 2); - if_descriptor->bAlternateSetting = *(uint8_t *) (buf + 3); - if_descriptor->bNumEndpoints = *(uint8_t *) (buf + 4); - if_descriptor->bInterfaceClass = *(uint8_t *) (buf + 5); - if_descriptor->bInterfaceSubClass = *(uint8_t *) (buf + 6); - if_descriptor->bInterfaceProtocol = *(uint8_t *) (buf + 7); - if_descriptor->iInterface = *(uint8_t *) (buf + 8); -} - -/** -* @brief USBH_ParseEPDesc -* This function Parses the endpoint descriptor -* @param ep_descriptor: Endpoint descriptor destination address -* @param buf: Buffer where the parsed descriptor stored -* @retval None -*/ -static void USBH_ParseEPDesc (USBH_EpDesc_TypeDef *ep_descriptor, - uint8_t *buf) -{ - - ep_descriptor->bLength = *(uint8_t *) (buf + 0); - ep_descriptor->bDescriptorType = *(uint8_t *) (buf + 1); - ep_descriptor->bEndpointAddress = *(uint8_t *) (buf + 2); - ep_descriptor->bmAttributes = *(uint8_t *) (buf + 3); - ep_descriptor->wMaxPacketSize = LE16 (buf + 4); - ep_descriptor->bInterval = *(uint8_t *) (buf + 6); -} - -/** -* @brief USBH_ParseStringDesc -* This function Parses the string descriptor -* @param psrc: Source pointer containing the descriptor data -* @param pdest: Destination address pointer -* @param length: Length of the descriptor -* @retval None -*/ -static void USBH_ParseStringDesc (uint8_t* psrc, - uint8_t* pdest, - uint16_t length) -{ - uint16_t strlength; - uint16_t idx; - - /* The UNICODE string descriptor is not NULL-terminated. The string length is - computed by substracting two from the value of the first byte of the descriptor. - */ - - /* Check which is lower size, the Size of string or the length of bytes read - from the device */ - - if ( psrc[1] == USB_DESC_TYPE_STRING) - { /* Make sure the Descriptor is String Type */ - - /* psrc[0] contains Size of Descriptor, subtract 2 to get the length of string */ - strlength = ( ( (psrc[0]-2) <= length) ? (psrc[0]-2) :length); - psrc += 2; /* Adjust the offset ignoring the String Len and Descriptor type */ - - for (idx = 0; idx < strlength; idx+=2 ) - {/* Copy Only the string and ignore the UNICODE ID, hence add the src */ - *pdest = psrc[idx]; - pdest++; - } - *pdest = 0; /* mark end of string */ - } -} - -/** -* @brief USBH_GetNextDesc -* This function return the next descriptor header -* @param buf: Buffer where the cfg descriptor is available -* @param ptr: data popinter inside the cfg descriptor -* @retval next header -*/ -USBH_DescHeader_t *USBH_GetNextDesc (uint8_t *pbuf, uint16_t *ptr) -{ - USBH_DescHeader_t *pnext; - - *ptr += ((USBH_DescHeader_t *)pbuf)->bLength; - pnext = (USBH_DescHeader_t *)((uint8_t *)pbuf + \ - ((USBH_DescHeader_t *)pbuf)->bLength); - - return(pnext); -} - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - - - diff --git a/stm/stmusbh/usbh_stdreq.h b/stm/stmusbh/usbh_stdreq.h deleted file mode 100644 index ac96518f7..000000000 --- a/stm/stmusbh/usbh_stdreq.h +++ /dev/null @@ -1,161 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_stdreq.h - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief Header file for usbh_stdreq.c - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive ----------------------------------------------*/ -#ifndef __USBH_STDREQ_H -#define __USBH_STDREQ_H - -/* Includes ------------------------------------------------------------------*/ -#include "usb_conf.h" -#include "usb_hcd.h" -#include "usbh_core.h" -#include "usbh_def.h" - -/** @addtogroup USBH_LIB - * @{ - */ - -/** @addtogroup USBH_LIB_CORE -* @{ -*/ - -/** @defgroup USBH_STDREQ - * @brief This file is the - * @{ - */ - - -/** @defgroup USBH_STDREQ_Exported_Defines - * @{ - */ -/*Standard Feature Selector for clear feature command*/ -#define FEATURE_SELECTOR_ENDPOINT 0X00 -#define FEATURE_SELECTOR_DEVICE 0X01 - - -#define INTERFACE_DESC_TYPE 0x04 -#define ENDPOINT_DESC_TYPE 0x05 -#define INTERFACE_DESC_SIZE 0x09 - - -#define USBH_HID_CLASS 0x03 - -/** - * @} - */ - - -/** @defgroup USBH_STDREQ_Exported_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBH_STDREQ_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USBH_STDREQ_Exported_Variables - * @{ - */ -extern uint8_t USBH_CfgDesc[512]; -/** - * @} - */ - -/** @defgroup USBH_STDREQ_Exported_FunctionsPrototype - * @{ - */ -USBH_Status USBH_GetDescriptor(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t req_type, - uint16_t value_idx, - uint8_t* buff, - uint16_t length ); - -USBH_Status USBH_Get_DevDesc(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t length); - -USBH_Status USBH_Get_StringDesc(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t string_index, - uint8_t *buff, - uint16_t length); - -USBH_Status USBH_SetCfg(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint16_t configuration_value); - -USBH_Status USBH_Get_CfgDesc(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint16_t length); - -USBH_Status USBH_SetAddress(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t DeviceAddress); - -USBH_Status USBH_ClrFeature(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t ep_num, uint8_t hc_num); - -USBH_Status USBH_SetInterface(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t ep_num, uint8_t altSetting); - -USBH_Status USBH_Issue_ClrFeature(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t ep_num); - -USBH_DescHeader_t *USBH_GetNextDesc (uint8_t *pbuf, - uint16_t *ptr); -/** - * @} - */ - -#endif /* __USBH_STDREQ_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - diff --git a/stm/stmusbh/usbh_usr.c b/stm/stmusbh/usbh_usr.c deleted file mode 100644 index 19312c2e4..000000000 --- a/stm/stmusbh/usbh_usr.c +++ /dev/null @@ -1,386 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_usr.c - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief This file includes the user application layer - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include - -#include "usbh_usr.h" -#include "usbh_hid_mouse.h" -#include "usbh_hid_keybd.h" - -extern void led_state(int, int); - -/** @addtogroup USBH_USER -* @{ -*/ - -/** @addtogroup USBH_HID_DEMO_USER_CALLBACKS -* @{ -*/ - -/** @defgroup USBH_USR -* @brief This file is the Header file for usbh_usr.c -* @{ -*/ - - -/** -* @} -*/ - -/** @addtogroup USER -* @{ -*/ - -/** @defgroup USBH_USR -* @brief This file includes the user application layer -* @{ -*/ - -/** @defgroup USBH_CORE_Exported_Types -* @{ -*/ - - - -/** @defgroup USBH_USR_Private_Defines -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USBH_USR_Private_Macros -* @{ -*/ -/** -* @} -*/ - -/** @defgroup USBH_USR_Private_Variables -* @{ -*/ -/* Points to the DEVICE_PROP structure of current device */ -/* The purpose of this register is to speed up the execution */ - -USBH_Usr_cb_TypeDef USR_Callbacks = -{ - USBH_USR_Init, - USBH_USR_DeInit, - USBH_USR_DeviceAttached, - USBH_USR_ResetDevice, - USBH_USR_DeviceDisconnected, - USBH_USR_OverCurrentDetected, - USBH_USR_DeviceSpeedDetected, - USBH_USR_Device_DescAvailable, - USBH_USR_DeviceAddressAssigned, - USBH_USR_Configuration_DescAvailable, - USBH_USR_Manufacturer_String, - USBH_USR_Product_String, - USBH_USR_SerialNum_String, - USBH_USR_EnumerationDone, - USBH_USR_UserInput, - NULL, - USBH_USR_DeviceNotSupported, - USBH_USR_UnrecoveredError -}; - -/** -* @} -*/ - -/** @defgroup USBH_USR_Private_Constants -* @{ -*/ - -/** -* @} -*/ - - - -/** @defgroup USBH_USR_Private_FunctionPrototypes -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USBH_USR_Private_Functions -* @{ -*/ - - - - - -/** -* @brief USBH_USR_Init -* Displays the message on LCD for host lib initialization -* @param None -* @retval None -*/ -void USBH_USR_Init(void) -{ - static uint8_t startup = 0; - - if (startup == 0) { - startup = 1; - - printf("USB Host library started.\n"); - } -} - -/** -* @brief USBH_USR_DeviceAttached -* Displays the message on LCD on device attached -* @param None -* @retval None -*/ -void USBH_USR_DeviceAttached(void) { - led_state(1, 1); - USB_OTG_BSP_mDelay(900); -} - -/** -* @brief USBH_USR_UnrecoveredError -* @param None -* @retval None -*/ -void USBH_USR_UnrecoveredError(void) { -} - -/** -* @brief USBH_DisconnectEvent -* Device disconnect event -* @param None -* @retval None -*/ -void USBH_USR_DeviceDisconnected (void) -{ - led_state(1, 0); - led_state(2, 0); - led_state(3, 0); - led_state(4, 0); - USB_OTG_BSP_mDelay(100); -} - -/** -* @brief USBH_USR_ResetUSBDevice -* Reset USB Device -* @param None -* @retval None -*/ -void USBH_USR_ResetDevice(void) -{ - /* Users can do their application actions here for the USB-Reset */ - led_state(3, 1); - USB_OTG_BSP_mDelay(100); - led_state(3, 0); -} - - -/** -* @brief USBH_USR_DeviceSpeedDetected -* Displays the message on LCD for device speed -* @param Devicespeed : Device Speed -* @retval None -*/ -void USBH_USR_DeviceSpeedDetected(uint8_t DeviceSpeed) -{ - /* - if(DeviceSpeed == HPRT0_PRTSPD_HIGH_SPEED) - { - printf(MSG_DEV_HIGHSPEED); - } - else if(DeviceSpeed == HPRT0_PRTSPD_FULL_SPEED) - { - printf(MSG_DEV_FULLSPEED); - } - else if(DeviceSpeed == HPRT0_PRTSPD_LOW_SPEED) - { - printf(MSG_DEV_LOWSPEED); - } - else - { - printf(MSG_DEV_ERROR); - } - */ -} - -/** -* @brief USBH_USR_Device_DescAvailable -* Displays the message on LCD for device descriptor -* @param DeviceDesc : device descriptor -* @retval None -*/ -void USBH_USR_Device_DescAvailable(void *DeviceDesc) -{ - /* - USBH_DevDesc_TypeDef *hs; - hs = DeviceDesc; - - printf("VID : %04Xh\n" , (unsigned int)(*hs).idVendor); - printf("PID : %04Xh\n" , (unsigned int)(*hs).idProduct); - */ -} - -/** -* @brief USBH_USR_DeviceAddressAssigned -* USB device is successfully assigned the Address -* @param None -* @retval None -*/ -void USBH_USR_DeviceAddressAssigned(void) -{ - -} - - -/** -* @brief USBH_USR_Conf_Desc -* Displays the message on LCD for configuration descriptor -* @param ConfDesc : Configuration descriptor -* @retval None -*/ -void USBH_USR_Configuration_DescAvailable(USBH_CfgDesc_TypeDef * cfgDesc, - USBH_InterfaceDesc_TypeDef *itfDesc, - USBH_EpDesc_TypeDef *epDesc) -{ - /* - USBH_InterfaceDesc_TypeDef *id; - - id = itfDesc; - - if((*id).bInterfaceClass == 0x08) - { - printf(MSG_MSC_CLASS); - } - else if((*id).bInterfaceClass == 0x03) - { - printf(MSG_HID_CLASS); - } - */ -} - -/** -* @brief USBH_USR_Manufacturer_String -* Displays the message on LCD for Manufacturer String -* @param ManufacturerString : Manufacturer String of Device -* @retval None -*/ -void USBH_USR_Manufacturer_String(void *ManufacturerString) { -} - -/** -* @brief USBH_USR_Product_String -* Displays the message on LCD for Product String -* @param ProductString : Product String of Device -* @retval None -*/ -void USBH_USR_Product_String(void *ProductString) { -} - -/** -* @brief USBH_USR_SerialNum_String -* Displays the message on LCD for SerialNum_String -* @param SerialNumString : SerialNum_String of device -* @retval None -*/ -void USBH_USR_SerialNum_String(void *SerialNumString) { -} - -/** -* @brief EnumerationDone -* User response request is displayed to ask for -* application jump to class -* @param None -* @retval None -*/ -void USBH_USR_EnumerationDone(void) { - /* Enumeration complete */ - led_state(2, 1); - USB_OTG_BSP_mDelay(500); -} - -/** -* @brief USBH_USR_DeviceNotSupported -* Device is not supported -* @param None -* @retval None -*/ -void USBH_USR_DeviceNotSupported(void){ -} - - -/** -* @brief USBH_USR_UserInput -* User Action for application state entry -* @param None -* @retval USBH_USR_Status : User response for key button -*/ -USBH_USR_Status USBH_USR_UserInput(void) { - return USBH_USR_RESP_OK; -} - -/** -* @brief USBH_USR_OverCurrentDetected -* Device Overcurrent detection event -* @param None -* @retval None -*/ -void USBH_USR_OverCurrentDetected(void) { -} - -/** -* @brief USBH_USR_DeInit -* Deint User state and associated variables -* @param None -* @retval None -*/ -void USBH_USR_DeInit(void) -{ -} - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/stmusbh/usbh_usr.h b/stm/stmusbh/usbh_usr.h deleted file mode 100644 index fa8201ad3..000000000 --- a/stm/stmusbh/usbh_usr.h +++ /dev/null @@ -1,107 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_usr.h - * @author MCD Application Team - * @version V2.1.0 - * @date 19-March-2012 - * @brief This file is the header file for usb usr file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USH_USR_H__ -#define __USH_USR_H__ - - -/* Includes ------------------------------------------------------------------*/ -#include "usbh_core.h" -#include "usb_conf.h" -#include - -/** @addtogroup USBH_USER -* @{ -*/ - -/** @addtogroup USBH_HID_DEMO_USER_CALLBACKS -* @{ -*/ - -/** @defgroup USBH_USR - * @brief This file is the header file for user action - * @{ - */ - - -/** @defgroup USBH_CORE_Exported_Variables - * @{ - */ - - -extern USBH_Usr_cb_TypeDef USR_Callbacks; - - -/** - * @} - */ - - -/** @defgroup USBH_CORE_Exported_FunctionsPrototype - * @{ - */ - -void USBH_USR_ApplicationSelected(void); -void USBH_USR_Init(void); -void USBH_USR_DeInit(void); -void USBH_USR_DeviceAttached(void); -void USBH_USR_ResetDevice(void); -void USBH_USR_DeviceDisconnected (void); -void USBH_USR_OverCurrentDetected (void); -void USBH_USR_DeviceSpeedDetected(uint8_t DeviceSpeed); -void USBH_USR_Device_DescAvailable(void *); -void USBH_USR_DeviceAddressAssigned(void); -void USBH_USR_Configuration_DescAvailable(USBH_CfgDesc_TypeDef * cfgDesc, - USBH_InterfaceDesc_TypeDef *itfDesc, - USBH_EpDesc_TypeDef *epDesc); -void USBH_USR_Manufacturer_String(void *); -void USBH_USR_Product_String(void *); -void USBH_USR_SerialNum_String(void *); -void USBH_USR_EnumerationDone(void); -USBH_USR_Status USBH_USR_UserInput(void); -void USBH_USR_DeInit(void); -void USBH_USR_DeviceNotSupported(void); -void USBH_USR_UnrecoveredError(void); -/** - * @} - */ - -#endif /* __USBH_USR_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/storage.c b/stm/storage.c deleted file mode 100644 index 8eed6dfcd..000000000 --- a/stm/storage.c +++ /dev/null @@ -1,176 +0,0 @@ -#include -#include "std.h" - -#include "misc.h" -#include "systick.h" -#include "mpconfig.h" -#include "qstr.h" -#include "obj.h" -#include "led.h" -#include "flash.h" -#include "storage.h" - -#define CACHE_MEM_START_ADDR (0x10000000) // CCM data RAM, 64k -#define FLASH_PART1_START_BLOCK (0x100) -#define FLASH_PART1_NUM_BLOCKS (224) // 16k+16k+16k+64k=112k -#define FLASH_MEM_START_ADDR (0x08004000) // sector 1, 16k - -static bool flash_is_initialised = false; -static bool flash_cache_dirty; -static uint32_t flash_cache_sector_id; -static uint32_t flash_cache_sector_start; -static uint32_t flash_cache_sector_size; -static uint32_t flash_sys_tick_counter_last_write; - -static void flash_cache_flush(void) { - if (flash_cache_dirty) { - // sync the cache RAM buffer by writing it to the flash page - flash_write(flash_cache_sector_start, (const uint32_t*)CACHE_MEM_START_ADDR, flash_cache_sector_size / 4); - flash_cache_dirty = false; - // indicate a clean cache with LED off - led_state(PYB_LED_R1, 0); - } -} - -static uint8_t *flash_cache_get_addr_for_write(uint32_t flash_addr) { - uint32_t flash_sector_start; - uint32_t flash_sector_size; - uint32_t flash_sector_id = flash_get_sector_info(flash_addr, &flash_sector_start, &flash_sector_size); - if (flash_cache_sector_id != flash_sector_id) { - flash_cache_flush(); - memcpy((void*)CACHE_MEM_START_ADDR, (const void*)flash_sector_start, flash_sector_size); - flash_cache_sector_id = flash_sector_id; - flash_cache_sector_start = flash_sector_start; - flash_cache_sector_size = flash_sector_size; - } - flash_cache_dirty = true; - // indicate a dirty cache with LED on - led_state(PYB_LED_R1, 1); - return (uint8_t*)CACHE_MEM_START_ADDR + flash_addr - flash_sector_start; -} - -static uint8_t *flash_cache_get_addr_for_read(uint32_t flash_addr) { - uint32_t flash_sector_start; - uint32_t flash_sector_size; - uint32_t flash_sector_id = flash_get_sector_info(flash_addr, &flash_sector_start, &flash_sector_size); - if (flash_cache_sector_id == flash_sector_id) { - // in cache, copy from there - return (uint8_t*)CACHE_MEM_START_ADDR + flash_addr - flash_sector_start; - } - // not in cache, copy straight from flash - return (uint8_t*)flash_addr; -} - -void storage_init(void) { - if (!flash_is_initialised) { - flash_cache_dirty = false; - flash_cache_sector_id = 0; - flash_is_initialised = true; - flash_sys_tick_counter_last_write = 0; - } -} - -uint32_t storage_get_block_size(void) { - return FLASH_BLOCK_SIZE; -} - -uint32_t storage_get_block_count(void) { - return FLASH_PART1_START_BLOCK + FLASH_PART1_NUM_BLOCKS; -} - -bool storage_needs_flush(void) { - // wait 2 seconds after last write to flush - return flash_cache_dirty && sys_tick_has_passed(flash_sys_tick_counter_last_write, 2000); -} - -void storage_flush(void) { - flash_cache_flush(); -} - -static void build_partition(uint8_t *buf, int boot, int type, uint32_t start_block, uint32_t num_blocks) { - buf[0] = boot; - - if (num_blocks == 0) { - buf[1] = 0; - buf[2] = 0; - buf[3] = 0; - } else { - buf[1] = 0xff; - buf[2] = 0xff; - buf[3] = 0xff; - } - - buf[4] = type; - - if (num_blocks == 0) { - buf[5] = 0; - buf[6] = 0; - buf[7] = 0; - } else { - buf[5] = 0xff; - buf[6] = 0xff; - buf[7] = 0xff; - } - - buf[8] = start_block; - buf[9] = start_block >> 8; - buf[10] = start_block >> 16; - buf[11] = start_block >> 24; - - buf[12] = num_blocks; - buf[13] = num_blocks >> 8; - buf[14] = num_blocks >> 16; - buf[15] = num_blocks >> 24; -} - -bool storage_read_block(uint8_t *dest, uint32_t block) { - //printf("RD %u\n", block); - if (block == 0) { - // fake the MBR so we can decide on our own partition table - - for (int i = 0; i < 446; i++) { - dest[i] = 0; - } - - build_partition(dest + 446, 0, 0x01 /* FAT12 */, FLASH_PART1_START_BLOCK, FLASH_PART1_NUM_BLOCKS); - build_partition(dest + 462, 0, 0, 0, 0); - build_partition(dest + 478, 0, 0, 0, 0); - build_partition(dest + 494, 0, 0, 0, 0); - - dest[510] = 0x55; - dest[511] = 0xaa; - - return true; - - } else if (FLASH_PART1_START_BLOCK <= block && block < FLASH_PART1_START_BLOCK + FLASH_PART1_NUM_BLOCKS) { - // non-MBR block, get data from flash memory, possibly via cache - uint32_t flash_addr = FLASH_MEM_START_ADDR + (block - FLASH_PART1_START_BLOCK) * FLASH_BLOCK_SIZE; - uint8_t *src = flash_cache_get_addr_for_read(flash_addr); - memcpy(dest, src, FLASH_BLOCK_SIZE); - return true; - - } else { - // bad block number - return false; - } -} - -bool storage_write_block(const uint8_t *src, uint32_t block) { - //printf("WR %u\n", block); - if (block == 0) { - // can't write MBR, but pretend we did - return true; - - } else if (FLASH_PART1_START_BLOCK <= block && block < FLASH_PART1_START_BLOCK + FLASH_PART1_NUM_BLOCKS) { - // non-MBR block, copy to cache - uint32_t flash_addr = FLASH_MEM_START_ADDR + (block - FLASH_PART1_START_BLOCK) * FLASH_BLOCK_SIZE; - uint8_t *dest = flash_cache_get_addr_for_write(flash_addr); - memcpy(dest, src, FLASH_BLOCK_SIZE); - flash_sys_tick_counter_last_write = sys_tick_counter; - return true; - - } else { - // bad block number - return false; - } -} diff --git a/stm/storage.h b/stm/storage.h deleted file mode 100644 index 4d153d2f6..000000000 --- a/stm/storage.h +++ /dev/null @@ -1,9 +0,0 @@ -#define FLASH_BLOCK_SIZE (512) - -void storage_init(void); -uint32_t storage_get_block_size(void); -uint32_t storage_get_block_count(void); -bool storage_needs_flush(void); -void storage_flush(void); -bool storage_read_block(uint8_t *dest, uint32_t block); -bool storage_write_block(const uint8_t *src, uint32_t block); diff --git a/stm/string0.c b/stm/string0.c deleted file mode 100644 index 61350bd97..000000000 --- a/stm/string0.c +++ /dev/null @@ -1,137 +0,0 @@ -#include -#include "std.h" - -void *memcpy(void *dest, const void *src, size_t n) { - // TODO align and copy 32 bits at a time - uint8_t *d = dest; - const uint8_t *s = src; - for (; n > 0; n--) { - *d++ = *s++; - } - return dest; -} - -void *memmove(void *dest, const void *src, size_t n) { - if (src < dest && dest < src + n) { - // need to copy backwards - uint8_t *d = dest + n - 1; - const uint8_t *s = src + n - 1; - for (; n > 0; n--) { - *d-- = *s--; - } - return dest; - } else { - // can use normal memcpy - return memcpy(dest, src, n); - } -} - -void *memset(void *s, int c, size_t n) { - uint8_t *s2 = s; - for (; n > 0; n--) { - *s2++ = c; - } - return s; -} - -int memcmp(const char *s1, const char *s2, size_t n) { - while (n--) { - char c1 = *s1++; - char c2 = *s2++; - if (c1 < c2) return -1; - else if (c1 > c2) return 1; - } - return 0; -} - -size_t strlen(const char *str) { - int len = 0; - for (const char *s = str; *s; s++) { - len += 1; - } - return len; -} - -int strcmp(const char *s1, const char *s2) { - while (*s1 && *s2) { - char c1 = *s1++; // XXX UTF8 get char, next char - char c2 = *s2++; // XXX UTF8 get char, next char - if (c1 < c2) return -1; - else if (c1 > c2) return 1; - } - if (*s2) return -1; - else if (*s1) return 1; - else return 0; -} - -int strncmp(const char *s1, const char *s2, size_t n) { - while (*s1 && *s2 && n > 0) { - char c1 = *s1++; // XXX UTF8 get char, next char - char c2 = *s2++; // XXX UTF8 get char, next char - n--; - if (c1 < c2) return -1; - else if (c1 > c2) return 1; - } - if (n == 0) return 0; - else if (*s2) return -1; - else if (*s1) return 1; - else return 0; -} - -char *strcpy(char *dest, const char *src) { - char *d = dest; - while (*src) { - *d++ = *src++; - } - *d = '\0'; - return dest; -} - -// needed because gcc optimises strcpy + strcat to this -char *stpcpy(char *dest, const char *src) { - while (*src) { - *dest++ = *src++; - } - *dest = '\0'; - return dest; -} - -char *strcat(char *dest, const char *src) { - char *d = dest; - while (*d) { - d++; - } - while (*src) { - *d++ = *src++; - } - *d = '\0'; - return dest; -} - -// Public Domain implementation of strchr from: -// http://en.wikibooks.org/wiki/C_Programming/Strings#The_strchr_function -char *strchr(const char *s, int c) -{ - /* Scan s for the character. When this loop is finished, - s will either point to the end of the string or the - character we were looking for. */ - while (*s != '\0' && *s != (char)c) - s++; - return ((*s == c) ? (char *) s : 0); -} - - -// Public Domain implementation of strstr from: -// http://en.wikibooks.org/wiki/C_Programming/Strings#The_strstr_function -char *strstr(const char *haystack, const char *needle) -{ - size_t needlelen; - /* Check for the null needle case. */ - if (*needle == '\0') - return (char *) haystack; - needlelen = strlen(needle); - for (; (haystack = strchr(haystack, *needle)) != 0; haystack++) - if (strncmp(haystack, needle, needlelen) == 0) - return (char *) haystack; - return 0; -} diff --git a/stm/system_stm32f4xx.c b/stm/system_stm32f4xx.c deleted file mode 100644 index 12ac4d6b5..000000000 --- a/stm/system_stm32f4xx.c +++ /dev/null @@ -1,929 +0,0 @@ -/** - ****************************************************************************** - * @file Project/STM32F4xx_StdPeriph_Templates/system_stm32f4xx.c - * @author MCD Application Team - * @version V1.3.0 - * @date 13-November-2013 - * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. - * This file contains the system clock configuration for STM32F4xx devices. - * - * 1. This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier - * and Divider factors, AHB/APBx prescalers and Flash settings), - * depending on the configuration made in the clock xls tool. - * This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32f4xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * 2. After each device reset the HSI (16 MHz) is used as system clock source. - * Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to - * configure the system clock before to branch to main program. - * - * 3. If the system clock source selected by user fails to startup, the SystemInit() - * function will do nothing and HSI still used as system clock source. User can - * add some code to deal with this issue inside the SetSysClock() function. - * - * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define - * in "stm32f4xx.h" file. When HSE is used as system clock source, directly or - * through PLL, and you are using different crystal you have to adapt the HSE - * value to your own configuration. - * - * 5. This file configures the system clock as follows: - *============================================================================= - *============================================================================= - * Supported STM32F40xxx/41xxx devices - *----------------------------------------------------------------------------- - * System Clock source | PLL (HSE) - *----------------------------------------------------------------------------- - * SYSCLK(Hz) | 168000000 - *----------------------------------------------------------------------------- - * HCLK(Hz) | 168000000 - *----------------------------------------------------------------------------- - * AHB Prescaler | 1 - *----------------------------------------------------------------------------- - * APB1 Prescaler | 4 - *----------------------------------------------------------------------------- - * APB2 Prescaler | 2 - *----------------------------------------------------------------------------- - * HSE Frequency(Hz) | HSE_VALUE - *----------------------------------------------------------------------------- - * PLL_M | (HSE_VALUE/1000000) - *----------------------------------------------------------------------------- - * PLL_N | 336 - *----------------------------------------------------------------------------- - * PLL_P | 2 - *----------------------------------------------------------------------------- - * PLL_Q | 7 - *----------------------------------------------------------------------------- - * PLLI2S_N | NA - *----------------------------------------------------------------------------- - * PLLI2S_R | NA - *----------------------------------------------------------------------------- - * I2S input clock | NA - *----------------------------------------------------------------------------- - * VDD(V) | 3.3 - *----------------------------------------------------------------------------- - * Main regulator output voltage | Scale1 mode - *----------------------------------------------------------------------------- - * Flash Latency(WS) | 5 - *----------------------------------------------------------------------------- - * Prefetch Buffer | ON - *----------------------------------------------------------------------------- - * Instruction cache | ON - *----------------------------------------------------------------------------- - * Data cache | ON - *----------------------------------------------------------------------------- - * Require 48MHz for USB OTG FS, | Disabled - * SDIO and RNG clock | - *----------------------------------------------------------------------------- - *============================================================================= - *============================================================================= - * Supported STM32F42xxx/43xxx devices - *----------------------------------------------------------------------------- - * System Clock source | PLL (HSE) - *----------------------------------------------------------------------------- - * SYSCLK(Hz) | 180000000 - *----------------------------------------------------------------------------- - * HCLK(Hz) | 180000000 - *----------------------------------------------------------------------------- - * AHB Prescaler | 1 - *----------------------------------------------------------------------------- - * APB1 Prescaler | 4 - *----------------------------------------------------------------------------- - * APB2 Prescaler | 2 - *----------------------------------------------------------------------------- - * HSE Frequency(Hz) | 25000000 - *----------------------------------------------------------------------------- - * PLL_M | 25 - *----------------------------------------------------------------------------- - * PLL_N | 360 - *----------------------------------------------------------------------------- - * PLL_P | 2 - *----------------------------------------------------------------------------- - * PLL_Q | 7 - *----------------------------------------------------------------------------- - * PLLI2S_N | NA - *----------------------------------------------------------------------------- - * PLLI2S_R | NA - *----------------------------------------------------------------------------- - * I2S input clock | NA - *----------------------------------------------------------------------------- - * VDD(V) | 3.3 - *----------------------------------------------------------------------------- - * Main regulator output voltage | Scale1 mode - *----------------------------------------------------------------------------- - * Flash Latency(WS) | 5 - *----------------------------------------------------------------------------- - * Prefetch Buffer | ON - *----------------------------------------------------------------------------- - * Instruction cache | ON - *----------------------------------------------------------------------------- - * Data cache | ON - *----------------------------------------------------------------------------- - * Require 48MHz for USB OTG FS, | Disabled - * SDIO and RNG clock | - *----------------------------------------------------------------------------- - *============================================================================= - *============================================================================= - * Supported STM32F401xx devices - *----------------------------------------------------------------------------- - * System Clock source | PLL (HSE) - *----------------------------------------------------------------------------- - * SYSCLK(Hz) | 84000000 - *----------------------------------------------------------------------------- - * HCLK(Hz) | 84000000 - *----------------------------------------------------------------------------- - * AHB Prescaler | 1 - *----------------------------------------------------------------------------- - * APB1 Prescaler | 2 - *----------------------------------------------------------------------------- - * APB2 Prescaler | 1 - *----------------------------------------------------------------------------- - * HSE Frequency(Hz) | 25000000 - *----------------------------------------------------------------------------- - * PLL_M | 25 - *----------------------------------------------------------------------------- - * PLL_N | 336 - *----------------------------------------------------------------------------- - * PLL_P | 4 - *----------------------------------------------------------------------------- - * PLL_Q | 7 - *----------------------------------------------------------------------------- - * PLLI2S_N | NA - *----------------------------------------------------------------------------- - * PLLI2S_R | NA - *----------------------------------------------------------------------------- - * I2S input clock | NA - *----------------------------------------------------------------------------- - * VDD(V) | 3.3 - *----------------------------------------------------------------------------- - * Main regulator output voltage | Scale1 mode - *----------------------------------------------------------------------------- - * Flash Latency(WS) | 2 - *----------------------------------------------------------------------------- - * Prefetch Buffer | ON - *----------------------------------------------------------------------------- - * Instruction cache | ON - *----------------------------------------------------------------------------- - * Data cache | ON - *----------------------------------------------------------------------------- - * Require 48MHz for USB OTG FS, | Disabled - * SDIO and RNG clock | - *----------------------------------------------------------------------------- - *============================================================================= - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f4xx_system - * @{ - */ - -/** @addtogroup STM32F4xx_System_Private_Includes - * @{ - */ - -#include "stm32f4xx.h" - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Defines - * @{ - */ - -/************************* Miscellaneous Configuration ************************/ -/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted - on STM324xG_EVAL/STM324x7I_EVAL/STM324x9I_EVAL boards as data memory */ - -#if defined (STM32F40_41xxx) || defined (STM32F427_437xx) || defined (STM32F429_439xx) -/* #define DATA_IN_ExtSRAM */ -#endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx */ - -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) -/* #define DATA_IN_ExtSDRAM */ -#endif /* STM32F427_437x || STM32F429_439xx */ - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ -/******************************************************************************/ - -/************************* PLL Parameters *************************************/ -/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ -#define PLL_M (HSE_VALUE/1000000) -/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ -#define PLL_Q 7 - -#if defined (STM32F40_41xxx) -#define PLL_N 336 -/* SYSCLK = PLL_VCO / PLL_P */ -#define PLL_P 2 -#endif /* STM32F40_41xxx */ - -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) -#define PLL_N 360 -/* SYSCLK = PLL_VCO / PLL_P */ -#define PLL_P 2 -#endif /* STM32F427_437x || STM32F429_439xx */ - -#if defined (STM32F401xx) -#define PLL_N 336 -/* SYSCLK = PLL_VCO / PLL_P */ -#define PLL_P 4 -#endif /* STM32F401xx */ - -/******************************************************************************/ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Variables - * @{ - */ - -#if defined (STM32F40_41xxx) - uint32_t SystemCoreClock = 168000000; -#endif /* STM32F40_41xxx */ - -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) - uint32_t SystemCoreClock = 180000000; -#endif /* STM32F427_437x || STM32F429_439xx */ - -#if defined (STM32F401xx) - uint32_t SystemCoreClock = 84000000; -#endif /* STM32F401xx */ - - __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes - * @{ - */ - -static void SetSysClock(void); - -#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) -static void SystemInit_ExtMemCtl(void); -#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemFrequency variable. - * @param None - * @retval None - */ -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ - #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ - #endif - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x24003010; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000; - -#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) - SystemInit_ExtMemCtl(); -#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ - - /* Configure the System clock source, PLL Multiplier and Divider factors, - AHB/APBx prescalers and Flash settings ----------------------------------*/ - SetSysClock(); - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ -#endif -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value - * 25 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ - uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock source */ - SystemCoreClock = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock source */ - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N - SYSCLK = PLL_VCO / PLL_P - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; - pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - - if (pllsource != 0) - { - /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - else - { - /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - - pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; - SystemCoreClock = pllvco/pllp; - break; - default: - SystemCoreClock = HSI_VALUE; - break; - } - /* Compute HCLK frequency --------------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK frequency */ - SystemCoreClock >>= tmp; -} - -/** - * @brief Configures the System clock source, PLL Multiplier and Divider factors, - * AHB/APBx prescalers and Flash settings - * @Note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ -static void SetSysClock(void) -{ -/******************************************************************************/ -/* PLL (clocked by HSE) used as System clock source */ -/******************************************************************************/ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* Select regulator voltage output Scale 1 mode */ - RCC->APB1ENR |= RCC_APB1ENR_PWREN; - PWR->CR |= PWR_CR_VOS; - - /* HCLK = SYSCLK / 1*/ - RCC->CFGR |= RCC_CFGR_HPRE_DIV1; - -#if defined (STM32F40_41xxx) || defined (STM32F427_437xx) || defined (STM32F429_439xx) - /* PCLK2 = HCLK / 2*/ - RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; - - /* PCLK1 = HCLK / 4*/ - RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; -#endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx */ - -#if defined (STM32F401xx) - /* PCLK2 = HCLK / 2*/ - RCC->CFGR |= RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK / 4*/ - RCC->CFGR |= RCC_CFGR_PPRE1_DIV2; -#endif /* STM32F401xx */ - - /* Configure the main PLL */ - RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | - (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); - - /* Enable the main PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till the main PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) - /* Enable the Over-drive to extend the clock frequency to 180 Mhz */ - PWR->CR |= PWR_CR_ODEN; - while((PWR->CSR & PWR_CSR_ODRDY) == 0) - { - } - PWR->CR |= PWR_CR_ODSWEN; - while((PWR->CSR & PWR_CSR_ODSWRDY) == 0) - { - } - /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ - FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS; -#endif /* STM32F427_437x || STM32F429_439xx */ - -#if defined (STM32F40_41xxx) - /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ - FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS; -#endif /* STM32F40_41xxx */ - -#if defined (STM32F401xx) - /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ - FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS; -#endif /* STM32F401xx */ - - /* Select the main PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= RCC_CFGR_SW_PLL; - - /* Wait till the main PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } - -} - -/** - * @brief Setup the external memory controller. Called in startup_stm32f4xx.s - * before jump to __main - * @param None - * @retval None - */ -#ifdef DATA_IN_ExtSRAM -/** - * @brief Setup the external memory controller. - * Called in startup_stm32f4xx.s before jump to main. - * This function configures the external SRAM mounted on STM324xG_EVAL/STM324x7I boards - * This SRAM will be used as program data memory (including heap and stack). - * @param None - * @retval None - */ -void SystemInit_ExtMemCtl(void) -{ -/*-- GPIOs Configuration -----------------------------------------------------*/ -/* - +-------------------+--------------------+------------------+--------------+ - + SRAM pins assignment + - +-------------------+--------------------+------------------+--------------+ - | PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 | - | PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 | - | PD4 <-> FMC_NOE | PE3 <-> FMC_A19 | PF2 <-> FMC_A2 | PG2 <-> FMC_A12 | - | PD5 <-> FMC_NWE | PE4 <-> FMC_A20 | PF3 <-> FMC_A3 | PG3 <-> FMC_A13 | - | PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF4 <-> FMC_A4 | PG4 <-> FMC_A14 | - | PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF5 <-> FMC_A5 | PG5 <-> FMC_A15 | - | PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF12 <-> FMC_A6 | PG9 <-> FMC_NE2 | - | PD11 <-> FMC_A16 | PE10 <-> FMC_D7 | PF13 <-> FMC_A7 |-----------------+ - | PD12 <-> FMC_A17 | PE11 <-> FMC_D8 | PF14 <-> FMC_A8 | - | PD13 <-> FMC_A18 | PE12 <-> FMC_D9 | PF15 <-> FMC_A9 | - | PD14 <-> FMC_D0 | PE13 <-> FMC_D10 |-----------------+ - | PD15 <-> FMC_D1 | PE14 <-> FMC_D11 | - | | PE15 <-> FMC_D12 | - +------------------+------------------+ -*/ - /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ - RCC->AHB1ENR |= 0x00000078; - - /* Connect PDx pins to FMC Alternate function */ - GPIOD->AFR[0] = 0x00cc00cc; - GPIOD->AFR[1] = 0xcccccccc; - /* Configure PDx pins in Alternate function mode */ - GPIOD->MODER = 0xaaaa0a0a; - /* Configure PDx pins speed to 100 MHz */ - GPIOD->OSPEEDR = 0xffff0f0f; - /* Configure PDx pins Output type to push-pull */ - GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ - GPIOD->PUPDR = 0x00000000; - - /* Connect PEx pins to FMC Alternate function */ - GPIOE->AFR[0] = 0xcccccccc; - GPIOE->AFR[1] = 0xcccccccc; - /* Configure PEx pins in Alternate function mode */ - GPIOE->MODER = 0xaaaaaaaa; - /* Configure PEx pins speed to 100 MHz */ - GPIOE->OSPEEDR = 0xffffffff; - /* Configure PEx pins Output type to push-pull */ - GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ - GPIOE->PUPDR = 0x00000000; - - /* Connect PFx pins to FMC Alternate function */ - GPIOF->AFR[0] = 0x00cccccc; - GPIOF->AFR[1] = 0xcccc0000; - /* Configure PFx pins in Alternate function mode */ - GPIOF->MODER = 0xaa000aaa; - /* Configure PFx pins speed to 100 MHz */ - GPIOF->OSPEEDR = 0xff000fff; - /* Configure PFx pins Output type to push-pull */ - GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ - GPIOF->PUPDR = 0x00000000; - - /* Connect PGx pins to FMC Alternate function */ - GPIOG->AFR[0] = 0x00cccccc; - GPIOG->AFR[1] = 0x000000c0; - /* Configure PGx pins in Alternate function mode */ - GPIOG->MODER = 0x00080aaa; - /* Configure PGx pins speed to 100 MHz */ - GPIOG->OSPEEDR = 0x000c0fff; - /* Configure PGx pins Output type to push-pull */ - GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ - GPIOG->PUPDR = 0x00000000; - -/*-- FMC Configuration ------------------------------------------------------*/ - /* Enable the FMC/FSMC interface clock */ - RCC->AHB3ENR |= 0x00000001; - -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) - /* Configure and enable Bank1_SRAM2 */ - FMC_Bank1->BTCR[2] = 0x00001011; - FMC_Bank1->BTCR[3] = 0x00000201; - FMC_Bank1E->BWTR[2] = 0x0fffffff; -#endif /* STM32F427_437xx || STM32F429_439xx */ - -#if defined (STM32F40_41xxx) - /* Configure and enable Bank1_SRAM2 */ - FSMC_Bank1->BTCR[2] = 0x00001011; - FSMC_Bank1->BTCR[3] = 0x00000201; - FSMC_Bank1E->BWTR[2] = 0x0fffffff; -#endif /* STM32F40_41xxx */ - -/* - Bank1_SRAM2 is configured as follow: - In case of FSMC configuration - NORSRAMTimingStructure.FSMC_AddressSetupTime = 1; - NORSRAMTimingStructure.FSMC_AddressHoldTime = 0; - NORSRAMTimingStructure.FSMC_DataSetupTime = 2; - NORSRAMTimingStructure.FSMC_BusTurnAroundDuration = 0; - NORSRAMTimingStructure.FSMC_CLKDivision = 0; - NORSRAMTimingStructure.FSMC_DataLatency = 0; - NORSRAMTimingStructure.FSMC_AccessMode = FMC_AccessMode_A; - - FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; - FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; - FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM; - FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; - FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; - FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; - FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; - FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; - FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &NORSRAMTimingStructure; - FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &NORSRAMTimingStructure; - - In case of FMC configuration - NORSRAMTimingStructure.FMC_AddressSetupTime = 1; - NORSRAMTimingStructure.FMC_AddressHoldTime = 0; - NORSRAMTimingStructure.FMC_DataSetupTime = 2; - NORSRAMTimingStructure.FMC_BusTurnAroundDuration = 0; - NORSRAMTimingStructure.FMC_CLKDivision = 0; - NORSRAMTimingStructure.FMC_DataLatency = 0; - NORSRAMTimingStructure.FMC_AccessMode = FMC_AccessMode_A; - - FMC_NORSRAMInitStructure.FMC_Bank = FMC_Bank1_NORSRAM2; - FMC_NORSRAMInitStructure.FMC_DataAddressMux = FMC_DataAddressMux_Disable; - FMC_NORSRAMInitStructure.FMC_MemoryType = FMC_MemoryType_SRAM; - FMC_NORSRAMInitStructure.FMC_MemoryDataWidth = FMC_MemoryDataWidth_16b; - FMC_NORSRAMInitStructure.FMC_BurstAccessMode = FMC_BurstAccessMode_Disable; - FMC_NORSRAMInitStructure.FMC_AsynchronousWait = FMC_AsynchronousWait_Disable; - FMC_NORSRAMInitStructure.FMC_WaitSignalPolarity = FMC_WaitSignalPolarity_Low; - FMC_NORSRAMInitStructure.FMC_WrapMode = FMC_WrapMode_Disable; - FMC_NORSRAMInitStructure.FMC_WaitSignalActive = FMC_WaitSignalActive_BeforeWaitState; - FMC_NORSRAMInitStructure.FMC_WriteOperation = FMC_WriteOperation_Enable; - FMC_NORSRAMInitStructure.FMC_WaitSignal = FMC_WaitSignal_Disable; - FMC_NORSRAMInitStructure.FMC_ExtendedMode = FMC_ExtendedMode_Disable; - FMC_NORSRAMInitStructure.FMC_WriteBurst = FMC_WriteBurst_Disable; - FMC_NORSRAMInitStructure.FMC_ContinousClock = FMC_CClock_SyncOnly; - FMC_NORSRAMInitStructure.FMC_ReadWriteTimingStruct = &NORSRAMTimingStructure; - FMC_NORSRAMInitStructure.FMC_WriteTimingStruct = &NORSRAMTimingStructure; -*/ - -} -#endif /* DATA_IN_ExtSRAM */ - -#ifdef DATA_IN_ExtSDRAM -/** - * @brief Setup the external memory controller. - * Called in startup_stm32f4xx.s before jump to main. - * This function configures the external SDRAM mounted on STM324x9I_EVAL board - * This SDRAM will be used as program data memory (including heap and stack). - * @param None - * @retval None - */ -void SystemInit_ExtMemCtl(void) -{ - register uint32_t tmpreg = 0, timeout = 0xFFFF; - register uint32_t index; - - /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface - clock */ - RCC->AHB1ENR |= 0x000001FC; - - /* Connect PCx pins to FMC Alternate function */ - GPIOC->AFR[0] = 0x0000000c; - GPIOC->AFR[1] = 0x00007700; - /* Configure PCx pins in Alternate function mode */ - GPIOC->MODER = 0x00a00002; - /* Configure PCx pins speed to 50 MHz */ - GPIOC->OSPEEDR = 0x00a00002; - /* Configure PCx pins Output type to push-pull */ - GPIOC->OTYPER = 0x00000000; - /* No pull-up, pull-down for PCx pins */ - GPIOC->PUPDR = 0x00500000; - - /* Connect PDx pins to FMC Alternate function */ - GPIOD->AFR[0] = 0x000000CC; - GPIOD->AFR[1] = 0xCC000CCC; - /* Configure PDx pins in Alternate function mode */ - GPIOD->MODER = 0xA02A000A; - /* Configure PDx pins speed to 50 MHz */ - GPIOD->OSPEEDR = 0xA02A000A; - /* Configure PDx pins Output type to push-pull */ - GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ - GPIOD->PUPDR = 0x00000000; - - /* Connect PEx pins to FMC Alternate function */ - GPIOE->AFR[0] = 0xC00000CC; - GPIOE->AFR[1] = 0xCCCCCCCC; - /* Configure PEx pins in Alternate function mode */ - GPIOE->MODER = 0xAAAA800A; - /* Configure PEx pins speed to 50 MHz */ - GPIOE->OSPEEDR = 0xAAAA800A; - /* Configure PEx pins Output type to push-pull */ - GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ - GPIOE->PUPDR = 0x00000000; - - /* Connect PFx pins to FMC Alternate function */ - GPIOF->AFR[0] = 0xcccccccc; - GPIOF->AFR[1] = 0xcccccccc; - /* Configure PFx pins in Alternate function mode */ - GPIOF->MODER = 0xAA800AAA; - /* Configure PFx pins speed to 50 MHz */ - GPIOF->OSPEEDR = 0xAA800AAA; - /* Configure PFx pins Output type to push-pull */ - GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ - GPIOF->PUPDR = 0x00000000; - - /* Connect PGx pins to FMC Alternate function */ - GPIOG->AFR[0] = 0xcccccccc; - GPIOG->AFR[1] = 0xcccccccc; - /* Configure PGx pins in Alternate function mode */ - GPIOG->MODER = 0xaaaaaaaa; - /* Configure PGx pins speed to 50 MHz */ - GPIOG->OSPEEDR = 0xaaaaaaaa; - /* Configure PGx pins Output type to push-pull */ - GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ - GPIOG->PUPDR = 0x00000000; - - /* Connect PHx pins to FMC Alternate function */ - GPIOH->AFR[0] = 0x00C0CC00; - GPIOH->AFR[1] = 0xCCCCCCCC; - /* Configure PHx pins in Alternate function mode */ - GPIOH->MODER = 0xAAAA08A0; - /* Configure PHx pins speed to 50 MHz */ - GPIOH->OSPEEDR = 0xAAAA08A0; - /* Configure PHx pins Output type to push-pull */ - GPIOH->OTYPER = 0x00000000; - /* No pull-up, pull-down for PHx pins */ - GPIOH->PUPDR = 0x00000000; - - /* Connect PIx pins to FMC Alternate function */ - GPIOI->AFR[0] = 0xCCCCCCCC; - GPIOI->AFR[1] = 0x00000CC0; - /* Configure PIx pins in Alternate function mode */ - GPIOI->MODER = 0x0028AAAA; - /* Configure PIx pins speed to 50 MHz */ - GPIOI->OSPEEDR = 0x0028AAAA; - /* Configure PIx pins Output type to push-pull */ - GPIOI->OTYPER = 0x00000000; - /* No pull-up, pull-down for PIx pins */ - GPIOI->PUPDR = 0x00000000; - -/*-- FMC Configuration ------------------------------------------------------*/ - /* Enable the FMC interface clock */ - RCC->AHB3ENR |= 0x00000001; - - /* Configure and enable SDRAM bank1 */ - FMC_Bank5_6->SDCR[0] = 0x000039D0; - FMC_Bank5_6->SDTR[0] = 0x01115351; - - /* SDRAM initialization sequence */ - /* Clock enable command */ - FMC_Bank5_6->SDCMR = 0x00000011; - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - while((tmpreg != 0) & (timeout-- > 0)) - { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - - /* Delay */ - for (index = 0; index<1000; index++); - - /* PALL command */ - FMC_Bank5_6->SDCMR = 0x00000012; - timeout = 0xFFFF; - while((tmpreg != 0) & (timeout-- > 0)) - { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - - /* Auto refresh command */ - FMC_Bank5_6->SDCMR = 0x00000073; - timeout = 0xFFFF; - while((tmpreg != 0) & (timeout-- > 0)) - { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - - /* MRD register program */ - FMC_Bank5_6->SDCMR = 0x00046014; - timeout = 0xFFFF; - while((tmpreg != 0) & (timeout-- > 0)) - { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - - /* Set refresh count */ - tmpreg = FMC_Bank5_6->SDRTR; - FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); - - /* Disable write protection */ - tmpreg = FMC_Bank5_6->SDCR[0]; - FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); - -/* - Bank1_SDRAM is configured as follow: - - FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2; - FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 6; - FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4; - FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 6; - FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2; - FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2; - FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2; - - FMC_SDRAMInitStructure.FMC_Bank = SDRAM_BANK; - FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b; - FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_11b; - FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = FMC_SDMemory_Width_16b; - FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4; - FMC_SDRAMInitStructure.FMC_CASLatency = FMC_CAS_Latency_3; - FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable; - FMC_SDRAMInitStructure.FMC_SDClockPeriod = FMC_SDClock_Period_2; - FMC_SDRAMInitStructure.FMC_ReadBurst = FMC_Read_Burst_disable; - FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1; - FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure; -*/ - -} -#endif /* DATA_IN_ExtSDRAM */ - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm/systick.c b/stm/systick.c deleted file mode 100644 index 40ae53279..000000000 --- a/stm/systick.c +++ /dev/null @@ -1,56 +0,0 @@ -#include -#include "misc.h" -#include "systick.h" - -volatile uint32_t sys_tick_counter; - -void sys_tick_init(void) { - // sys-tick interrupt called at 1ms intervals - sys_tick_counter = 0; - SysTick_Config(SystemCoreClock / 1000); - NVIC_SetPriority(SysTick_IRQn, 0); // make it highest priority -} - -// called on SysTick interrupt -void SysTick_Handler(void) { - sys_tick_counter++; - // hack! - //void audio_drain(void); - //audio_drain(); -} - -void sys_tick_delay_ms(uint32_t delay_ms) { - sys_tick_wait_at_least(sys_tick_counter, delay_ms); -} - -// waits until at least delay_ms milliseconds have passed from the sampling of sys_tick_counter in stc -// handles overflow properl -// assumes stc was taken from sys_tick_counter some time before calling this function -// eg stc <= sys_tick_counter for the case of no wrap around of sys_tick_counter -void sys_tick_wait_at_least(uint32_t stc, uint32_t delay_ms) { - // stc_wait is the value of sys_tick_counter that we wait for - uint32_t stc_wait = stc + delay_ms; - if (stc_wait < stc) { - // stc_wait wrapped around - while (stc <= sys_tick_counter || sys_tick_counter < stc_wait) { - __WFI(); // enter sleep mode, waiting for interrupt - } - } else { - // stc_wait did not wrap around - while (stc <= sys_tick_counter && sys_tick_counter < stc_wait) { - __WFI(); // enter sleep mode, waiting for interrupt - } - } -} - -bool sys_tick_has_passed(uint32_t stc, uint32_t delay_ms) { - // stc_wait is the value of sys_tick_counter that we wait for - uint32_t stc_wait = stc + delay_ms; - if (stc_wait < stc) { - // stc_wait wrapped around - return !(stc <= sys_tick_counter || sys_tick_counter < stc_wait); - } else { - // stc_wait did not wrap around - return !(stc <= sys_tick_counter && sys_tick_counter < stc_wait); - } -} diff --git a/stm/systick.h b/stm/systick.h deleted file mode 100644 index 7d2deed11..000000000 --- a/stm/systick.h +++ /dev/null @@ -1,7 +0,0 @@ -extern volatile uint32_t sys_tick_counter; - -void sys_tick_init(void); -void SysTick_Handler(void); -void sys_tick_delay_ms(uint32_t delay_ms); -void sys_tick_wait_at_least(uint32_t stc, uint32_t delay_ms); -bool sys_tick_has_passed(uint32_t stc, uint32_t delay_ms); diff --git a/stm/timer.c b/stm/timer.c deleted file mode 100644 index 8d51de2cc..000000000 --- a/stm/timer.c +++ /dev/null @@ -1,98 +0,0 @@ -#include -#include -#include - -#include "stm_misc.h" -#include "stm32f4xx_rcc.h" -#include "stm32f4xx_tim.h" - -#include "mpconfig.h" -#include "nlr.h" -#include "misc.h" -#include "qstr.h" -#include "parse.h" -#include "obj.h" -#include "runtime.h" - -#include "timer.h" - -// TIM6 is used as an internal interrup to schedule something at a specific rate -mp_obj_t timer_py_callback; - -mp_obj_t timer_py_set_callback(mp_obj_t f) { - timer_py_callback = f; - return mp_const_none; -} - -mp_obj_t timer_py_set_period(mp_obj_t period) { - TIM6->ARR = mp_obj_get_int(period) & 0xffff; - return mp_const_none; -} - -mp_obj_t timer_py_set_prescaler(mp_obj_t prescaler) { - TIM6->PSC = mp_obj_get_int(prescaler) & 0xffff; - return mp_const_none; -} - -mp_obj_t timer_py_get_value(void) { - return mp_obj_new_int(TIM6->CNT & 0xfffff); -} - -void timer_init(void) { - timer_py_callback = mp_const_none; - - // TIM6 clock enable - RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM6, ENABLE); - - // Compute the prescaler value so TIM6 runs at 20kHz - uint16_t PrescalerValue = (uint16_t) ((SystemCoreClock / 2) / 20000) - 1; - - // Time base configuration - TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; - TIM_TimeBaseStructure.TIM_Period = 20000; // timer cycles at 1Hz - TIM_TimeBaseStructure.TIM_Prescaler = PrescalerValue; - TIM_TimeBaseStructure.TIM_ClockDivision = 0; // unused for TIM6 - TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; // unused for TIM6 - TIM_TimeBaseInit(TIM6, &TIM_TimeBaseStructure); - - // enable perhipheral preload register - TIM_ARRPreloadConfig(TIM6, ENABLE); - - // enable interrupt when counter overflows - TIM_ITConfig(TIM6, TIM_IT_Update, ENABLE); - - // set up interrupt - NVIC_InitTypeDef NVIC_InitStructure; - NVIC_InitStructure.NVIC_IRQChannel = TIM6_DAC_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0f; // lowest priority - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0f; // lowest priority - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); - - // TIM6 enable counter - TIM_Cmd(TIM6, ENABLE); - - // Python interface - mp_obj_t m = mp_obj_new_module(QSTR_FROM_STR_STATIC("timer")); - mp_store_attr(m, QSTR_FROM_STR_STATIC("callback"), mp_make_function_n(1, timer_py_set_callback)); - mp_store_attr(m, QSTR_FROM_STR_STATIC("period"), mp_make_function_n(1, timer_py_set_period)); - mp_store_attr(m, QSTR_FROM_STR_STATIC("prescaler"), mp_make_function_n(1, timer_py_set_prescaler)); - mp_store_attr(m, QSTR_FROM_STR_STATIC("value"), mp_make_function_n(0, timer_py_get_value)); - mp_store_name(QSTR_FROM_STR_STATIC("timer"), m); -} - -void timer_interrupt(void) { - if (timer_py_callback != mp_const_none) { - nlr_buf_t nlr; - if (nlr_push(&nlr) == 0) { - // XXX what to do if the GC is in the middle of running?? - mp_call_function_0(timer_py_callback); - nlr_pop(); - } else { - // uncaught exception - printf("exception in timer interrupt\n"); - mp_obj_print((mp_obj_t)nlr.ret_val, PRINT_REPR); - printf("\n"); - } - } -} diff --git a/stm/timer.h b/stm/timer.h deleted file mode 100644 index 117cff3c9..000000000 --- a/stm/timer.h +++ /dev/null @@ -1 +0,0 @@ -void timer_init(void); diff --git a/stm/usart.c b/stm/usart.c deleted file mode 100644 index 1dfbd433b..000000000 --- a/stm/usart.c +++ /dev/null @@ -1,269 +0,0 @@ -#include -#include -#include -#include - -#include "misc.h" -#include "mpconfig.h" -#include "qstr.h" -#include "obj.h" -#include "usart.h" - -pyb_usart_t pyb_usart_global_debug = PYB_USART_NONE; - -static USART_TypeDef *usart_get_base(pyb_usart_t usart_id) { - USART_TypeDef *USARTx=NULL; - - switch (usart_id) { - case PYB_USART_NONE: - break; - case PYB_USART_1: - USARTx = USART1; - break; - case PYB_USART_2: - USARTx = USART2; - break; - case PYB_USART_3: - USARTx = USART3; - break; - case PYB_USART_6: - USARTx = USART6; - break; - } - - return USARTx; -} - -void usart_init(pyb_usart_t usart_id, uint32_t baudrate) { - USART_TypeDef *USARTx=NULL; - - uint32_t GPIO_Pin=0; - uint8_t GPIO_AF_USARTx=0; - GPIO_TypeDef* GPIO_Port=NULL; - uint16_t GPIO_PinSource_TX=0; - uint16_t GPIO_PinSource_RX=0; - - uint32_t RCC_APBxPeriph=0; - void (*RCC_APBxPeriphClockCmd)(uint32_t, FunctionalState)=NULL; - - switch (usart_id) { - case PYB_USART_NONE: - return; - - case PYB_USART_1: - USARTx = USART1; - - GPIO_Port = GPIOA; - GPIO_AF_USARTx = GPIO_AF_USART1; - GPIO_Pin = GPIO_Pin_9 | GPIO_Pin_10; - GPIO_PinSource_TX = GPIO_PinSource9; - GPIO_PinSource_RX = GPIO_PinSource10; - - RCC_APBxPeriph = RCC_APB2Periph_USART1; - RCC_APBxPeriphClockCmd =RCC_APB2PeriphClockCmd; - break; - case PYB_USART_2: - USARTx = USART2; - - GPIO_Port = GPIOD; - GPIO_AF_USARTx = GPIO_AF_USART2; - GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6; - GPIO_PinSource_TX = GPIO_PinSource5; - GPIO_PinSource_RX = GPIO_PinSource6; - - RCC_APBxPeriph = RCC_APB1Periph_USART2; - RCC_APBxPeriphClockCmd =RCC_APB1PeriphClockCmd; - break; - case PYB_USART_3: - USARTx = USART3; - -#if defined(PYBOARD3) || defined(PYBOARD4) - GPIO_Port = GPIOB; - GPIO_AF_USARTx = GPIO_AF_USART3; - GPIO_Pin = GPIO_Pin_10 | GPIO_Pin_11; - GPIO_PinSource_TX = GPIO_PinSource10; - GPIO_PinSource_RX = GPIO_PinSource11; -#else - GPIO_Port = GPIOD; - GPIO_AF_USARTx = GPIO_AF_USART3; - GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9; - GPIO_PinSource_TX = GPIO_PinSource8; - GPIO_PinSource_RX = GPIO_PinSource9; -#endif - - RCC_APBxPeriph = RCC_APB1Periph_USART3; - RCC_APBxPeriphClockCmd =RCC_APB1PeriphClockCmd; - break; - case PYB_USART_6: - USARTx = USART6; - - GPIO_Port = GPIOC; - GPIO_AF_USARTx = GPIO_AF_USART6; - GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7; - GPIO_PinSource_TX = GPIO_PinSource6; - GPIO_PinSource_RX = GPIO_PinSource7; - - RCC_APBxPeriph = RCC_APB2Periph_USART6; - RCC_APBxPeriphClockCmd =RCC_APB2PeriphClockCmd; - break; - } - - /* Initialize USARTx */ - RCC_APBxPeriphClockCmd(RCC_APBxPeriph, ENABLE); - - GPIO_PinAFConfig(GPIO_Port, GPIO_PinSource_TX, GPIO_AF_USARTx); - GPIO_PinAFConfig(GPIO_Port, GPIO_PinSource_RX, GPIO_AF_USARTx); - - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = GPIO_Pin; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_25MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(GPIO_Port, &GPIO_InitStructure); - - USART_InitTypeDef USART_InitStructure; - USART_InitStructure.USART_BaudRate = baudrate; - USART_InitStructure.USART_WordLength = USART_WordLength_8b; - USART_InitStructure.USART_StopBits = USART_StopBits_1; - USART_InitStructure.USART_Parity = USART_Parity_No; - USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; - USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - USART_Init(USARTx, &USART_InitStructure); - - USART_Cmd(USARTx, ENABLE); -} - -bool usart_rx_any(pyb_usart_t usart_id) { - USART_TypeDef *USARTx = usart_get_base(usart_id); - return USART_GetFlagStatus(USARTx, USART_FLAG_RXNE) == SET; -} - -int usart_rx_char(pyb_usart_t usart_id) { - USART_TypeDef *USARTx = usart_get_base(usart_id); - return USART_ReceiveData(USARTx); -} - -void usart_tx_char(pyb_usart_t usart_id, int c) { - USART_TypeDef *USARTx = usart_get_base(usart_id); - // wait until the end of any previous transmission - uint32_t timeout = 100000; - while (USART_GetFlagStatus(USARTx, USART_FLAG_TC) == RESET && --timeout > 0) { - } - USART_SendData(USARTx, c); -} - -void usart_tx_str(pyb_usart_t usart_id, const char *str) { - for (; *str; str++) { - usart_tx_char(usart_id, *str); - } -} - -void usart_tx_bytes(pyb_usart_t usart_id, const char *data, uint len) { - for (; len > 0; data++, len--) { - usart_tx_char(usart_id, *data); - } -} - -void usart_tx_strn_cooked(pyb_usart_t usart_id, const char *str, int len) { - for (const char *top = str + len; str < top; str++) { - if (*str == '\n') { - usart_tx_char(usart_id, '\r'); - } - usart_tx_char(usart_id, *str); - } -} - - -/******************************************************************************/ -/* Micro Python bindings */ - -typedef struct _pyb_usart_obj_t { - mp_obj_base_t base; - pyb_usart_t usart_id; - bool is_enabled; -} pyb_usart_obj_t; - -static mp_obj_t usart_obj_status(mp_obj_t self_in) { - pyb_usart_obj_t *self = self_in; - if (usart_rx_any(self->usart_id)) { - return mp_const_true; - } else { - return mp_const_false; - } -} - -static mp_obj_t usart_obj_rx_char(mp_obj_t self_in) { - mp_obj_t ret = mp_const_none; - pyb_usart_obj_t *self = self_in; - - if (self->is_enabled) { - ret = mp_obj_new_int(usart_rx_char(self->usart_id)); - } - return ret; -} - -static mp_obj_t usart_obj_tx_char(mp_obj_t self_in, mp_obj_t c) { - pyb_usart_obj_t *self = self_in; - uint len; - const char *str = mp_obj_str_get_data(c, &len); - if (len == 1 && self->is_enabled) { - usart_tx_char(self->usart_id, str[0]); - } - return mp_const_none; -} - -static mp_obj_t usart_obj_tx_str(mp_obj_t self_in, mp_obj_t s) { - pyb_usart_obj_t *self = self_in; - if (self->is_enabled) { - if (MP_OBJ_IS_STR(s)) { - uint len; - const char *data = mp_obj_str_get_data(s, &len); - usart_tx_bytes(self->usart_id, data, len); - } - } - return mp_const_none; -} - -static void usart_obj_print(void (*print)(void *env, const char *fmt, ...), void *env, mp_obj_t self_in, mp_print_kind_t kind) { - pyb_usart_obj_t *self = self_in; - print(env, "", self->usart_id); -} - -static MP_DEFINE_CONST_FUN_OBJ_1(usart_obj_status_obj, usart_obj_status); -static MP_DEFINE_CONST_FUN_OBJ_1(usart_obj_rx_char_obj, usart_obj_rx_char); -static MP_DEFINE_CONST_FUN_OBJ_2(usart_obj_tx_char_obj, usart_obj_tx_char); -static MP_DEFINE_CONST_FUN_OBJ_2(usart_obj_tx_str_obj, usart_obj_tx_str); - -STATIC const mp_map_elem_t usart_locals_dict_table[] = { - { MP_OBJ_NEW_QSTR(MP_QSTR_status), (mp_obj_t)&usart_obj_status_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_recv_chr), (mp_obj_t)&usart_obj_rx_char_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_send_chr), (mp_obj_t)&usart_obj_tx_char_obj }, - { MP_OBJ_NEW_QSTR(MP_QSTR_send), (mp_obj_t)&usart_obj_tx_str_obj }, -}; - -STATIC MP_DEFINE_CONST_DICT(usart_locals_dict, usart_locals_dict_table); - -STATIC const mp_obj_type_t usart_obj_type = { - { &mp_type_type }, - .name = MP_QSTR_Usart, - .print = usart_obj_print, - .locals_dict = (mp_obj_t)&usart_locals_dict, -}; - -STATIC mp_obj_t pyb_Usart(mp_obj_t usart_id, mp_obj_t baudrate) { - if (mp_obj_get_int(usart_id)>PYB_USART_MAX) { - return mp_const_none; - } - - /* init USART */ - usart_init(mp_obj_get_int(usart_id), mp_obj_get_int(baudrate)); - - pyb_usart_obj_t *o = m_new_obj(pyb_usart_obj_t); - o->base.type = &usart_obj_type; - o->usart_id = mp_obj_get_int(usart_id); - o->is_enabled = true; - return o; -} - -MP_DEFINE_CONST_FUN_OBJ_2(pyb_Usart_obj, pyb_Usart); diff --git a/stm/usart.h b/stm/usart.h deleted file mode 100644 index c641281a7..000000000 --- a/stm/usart.h +++ /dev/null @@ -1,23 +0,0 @@ -typedef enum { - PYB_USART_NONE = 0, - PYB_USART_1 = 1, - PYB_USART_2 = 2, - PYB_USART_3 = 3, - PYB_USART_6 = 4, - PYB_USART_MAX = 4, - - //PYB_USART_XA = // USART4 on X1, X2 = PA0, PA1 - PYB_USART_XB = 1, // USART1 on X9, X10 = PB6, PB7 - PYB_USART_YA = 4, // USART6 on Y1, Y2 = PC6, PC7 - PYB_USART_YB = 3, // USART3 on Y9, Y10 = PB10, PB11 -} pyb_usart_t; - -extern pyb_usart_t pyb_usart_global_debug; - -void usart_init(pyb_usart_t usart_id, uint32_t baudrate); -bool usart_rx_any(pyb_usart_t usart_id); -int usart_rx_char(pyb_usart_t usart_id); -void usart_tx_str(pyb_usart_t usart_id, const char *str); -void usart_tx_strn_cooked(pyb_usart_t usart_id, const char *str, int len); - -MP_DECLARE_CONST_FUN_OBJ(pyb_Usart_obj); diff --git a/stm/usb.c b/stm/usb.c deleted file mode 100644 index 29a5fb46d..000000000 --- a/stm/usb.c +++ /dev/null @@ -1,223 +0,0 @@ -#include - -#include "usb_core.h" -#include "usbd_core.h" -#include "usbd_cdc_core.h" -#include "usbd_pyb_core.h" -#include "usbd_usr.h" -#include "usbd_desc.h" - -#include "misc.h" -#include "mpconfig.h" -#include "qstr.h" -#include "obj.h" -#include "pendsv.h" -#include "usb.h" - -#ifdef USE_DEVICE_MODE -extern CDC_IF_Prop_TypeDef VCP_fops; -#endif - -USB_OTG_CORE_HANDLE USB_OTG_Core; - -static int dev_is_enabled = 0; -uint32_t APP_dev_is_connected = 0; /* used by usbd_cdc_vcp */ -static char rx_buf[64]; -static int rx_buf_in; -static int rx_buf_out; -static int interrupt_char = VCP_CHAR_NONE; -mp_obj_t mp_const_vcp_interrupt = MP_OBJ_NULL; - -void pyb_usb_dev_init(int usb_dev_type) { -#ifdef USE_DEVICE_MODE - if (!dev_is_enabled) { - // only init USB once in the device's power-lifetime - switch (usb_dev_type) { - case PYB_USB_DEV_VCP_MSC: - USBD_Init(&USB_OTG_Core, USB_OTG_FS_CORE_ID, &USR_desc, &USBD_PYB_cb, &USR_cb); - break; - - case PYB_USB_DEV_HID: - USBD_Init(&USB_OTG_Core, USB_OTG_FS_CORE_ID, &USR_desc, &USBD_PYB_HID_cb, &USR_cb); - break; - } - } - rx_buf_in = 0; - rx_buf_out = 0; - interrupt_char = VCP_CHAR_NONE; - dev_is_enabled = 1; - - // create an exception object for interrupting by VCP - mp_const_vcp_interrupt = mp_obj_new_exception_msg(&mp_type_OSError, "VCPInterrupt"); -#endif -} - -bool usb_vcp_is_enabled(void) { - return dev_is_enabled; -} - -bool usb_vcp_is_connected(void) { - return APP_dev_is_connected; -} - -void usb_vcp_set_interrupt_char(int c) { - if (dev_is_enabled) { - interrupt_char = c; - } -} - -void usb_vcp_receive(const char *buf, uint32_t len) { - if (dev_is_enabled) { - for (int i = 0; i < len; i++) { - - // catch special interrupt character - if (buf[i] == interrupt_char) { - // raise exception when interrupts are finished - mp_obj_exception_clear_traceback(mp_const_vcp_interrupt); - pendsv_nlr_jump(mp_const_vcp_interrupt); - interrupt_char = VCP_CHAR_NONE; - continue; - } - - rx_buf[rx_buf_in++] = buf[i]; - if (rx_buf_in >= sizeof(rx_buf)) { - rx_buf_in = 0; - } - if (rx_buf_in == rx_buf_out) { - rx_buf_out = rx_buf_in + 1; - if (rx_buf_out >= sizeof(rx_buf)) { - rx_buf_out = 0; - } - } - } - } -} - -int usb_vcp_rx_any(void) { - if (rx_buf_in >= rx_buf_out) { - return rx_buf_in - rx_buf_out; - } else { - return rx_buf_in + sizeof(rx_buf) - rx_buf_out; - } -} - -char usb_vcp_rx_get(void) { - while (rx_buf_out == rx_buf_in) { - } - char c = rx_buf[rx_buf_out]; - rx_buf_out += 1; - if (rx_buf_out >= sizeof(rx_buf)) { - rx_buf_out = 0; - } - return c; -} - -void usb_vcp_send_str(const char *str) { - usb_vcp_send_strn(str, strlen(str)); -} - -void usb_vcp_send_strn(const char *str, int len) { -#ifdef USE_DEVICE_MODE - if (dev_is_enabled) { - VCP_fops.pIf_DataTx((const uint8_t*)str, len); - } -#endif -} - -#include "usbd_conf.h" - -/* These are external variables imported from CDC core to be used for IN - transfer management. */ -#ifdef USE_DEVICE_MODE -extern uint8_t APP_Rx_Buffer []; /* Write CDC received data in this buffer. - These data will be sent over USB IN endpoint - in the CDC core functions. */ -extern uint32_t APP_Rx_ptr_in; /* Increment this pointer or roll it back to - start address when writing received data - in the buffer APP_Rx_Buffer. */ -#endif - -void usb_vcp_send_strn_cooked(const char *str, int len) { -#ifdef USE_DEVICE_MODE - for (const char *top = str + len; str < top; str++) { - if (*str == '\n') { - APP_Rx_Buffer[APP_Rx_ptr_in] = '\r'; - APP_Rx_ptr_in = (APP_Rx_ptr_in + 1) & (APP_RX_DATA_SIZE - 1); - } - APP_Rx_Buffer[APP_Rx_ptr_in] = *str; - APP_Rx_ptr_in = (APP_Rx_ptr_in + 1) & (APP_RX_DATA_SIZE - 1); - } -#endif -} - -void usb_hid_send_report(uint8_t *buf) { -#ifdef USE_DEVICE_MODE - USBD_HID_SendReport(&USB_OTG_Core, buf, 4); -#endif -} - -/******************************************************************************/ -// code for experimental USB OTG support - -#ifdef USE_HOST_MODE - -#include "led.h" -#include "usbh_core.h" -#include "usbh_usr.h" -#include "usbh_hid_core.h" -#include "usbh_hid_keybd.h" -#include "usbh_hid_mouse.h" - -__ALIGN_BEGIN USBH_HOST USB_Host __ALIGN_END ; - -static int host_is_enabled = 0; - -void pyb_usb_host_init(void) { - if (!host_is_enabled) { - // only init USBH once in the device's power-lifetime - /* Init Host Library */ - USBH_Init(&USB_OTG_Core, USB_OTG_FS_CORE_ID, &USB_Host, &HID_cb, &USR_Callbacks); - } - host_is_enabled = 1; -} - -void pyb_usb_host_process(void) { - USBH_Process(&USB_OTG_Core, &USB_Host); -} - -uint8_t usb_keyboard_key = 0; - -// TODO this is an ugly hack to get key presses -uint pyb_usb_host_get_keyboard(void) { - uint key = usb_keyboard_key; - usb_keyboard_key = 0; - return key; -} - -void USR_MOUSE_Init(void) { - led_state(4, 1); - USB_OTG_BSP_mDelay(100); - led_state(4, 0); -} - -void USR_MOUSE_ProcessData(HID_MOUSE_Data_TypeDef *data) { - led_state(4, 1); - USB_OTG_BSP_mDelay(50); - led_state(4, 0); -} - -void USR_KEYBRD_Init(void) { - led_state(4, 1); - USB_OTG_BSP_mDelay(100); - led_state(4, 0); -} - -void USR_KEYBRD_ProcessData(uint8_t pbuf) { - led_state(4, 1); - USB_OTG_BSP_mDelay(50); - led_state(4, 0); - //lcd_print_strn((char*)&pbuf, 1); - usb_keyboard_key = pbuf; -} - -#endif // USE_HOST_MODE diff --git a/stm/usb.h b/stm/usb.h deleted file mode 100644 index a0fb15324..000000000 --- a/stm/usb.h +++ /dev/null @@ -1,23 +0,0 @@ -#define VCP_CHAR_NONE (0) -#define VCP_CHAR_CTRL_A (1) -#define VCP_CHAR_CTRL_B (2) -#define VCP_CHAR_CTRL_C (3) -#define VCP_CHAR_CTRL_D (4) - -#define PYB_USB_DEV_VCP_MSC (0) -#define PYB_USB_DEV_HID (1) - -void pyb_usb_dev_init(int usb_dev_type); -bool usb_vcp_is_enabled(void); -bool usb_vcp_is_connected(void); -void usb_vcp_set_interrupt_char(int c); -int usb_vcp_rx_any(void); -char usb_vcp_rx_get(void); -void usb_vcp_send_str(const char* str); -void usb_vcp_send_strn(const char* str, int len); -void usb_vcp_send_strn_cooked(const char *str, int len); -void usb_hid_send_report(uint8_t *buf); // 4 bytes for mouse: ?, x, y, ? - -void pyb_usb_host_init(void); -void pyb_usb_host_process(void); -uint pyb_usb_host_get_keyboard(void); diff --git a/stm/usrsw.c b/stm/usrsw.c deleted file mode 100644 index a00ca90d2..000000000 --- a/stm/usrsw.c +++ /dev/null @@ -1,68 +0,0 @@ -#include -#include - -#include "misc.h" -#include "mpconfig.h" -#include "qstr.h" -#include "obj.h" -#include "runtime.h" -#include "usrsw.h" - -#include "exti.h" -#include "gpio.h" -#include "pin.h" -#include "build/pins.h" - -// Usage Model: -// -// pyb.switch() returns True if the user switch is pressed, False otherwise. -// -// pyb.switch(callback) will register a callback to be called when the user -// switch is pressed. -// -// pyb.switch(None) will remove the callback. -// -// Example: -// -// def switch_pressed(): -// print("User Switch pressed") -// -// pyb.switch(switch_pressed) - -static mp_obj_t switch_user_callback_obj; - -static mp_obj_t switch_callback(mp_obj_t line) { - if (switch_user_callback_obj != mp_const_none) { - mp_call_function_0(switch_user_callback_obj); - } - return mp_const_none; -} -static MP_DEFINE_CONST_FUN_OBJ_1(switch_callback_obj, switch_callback); - -void switch_init(void) { - switch_user_callback_obj = mp_const_none; - exti_register((mp_obj_t)&USRSW_PIN, - MP_OBJ_NEW_SMALL_INT(EXTI_Mode_Interrupt), - MP_OBJ_NEW_SMALL_INT(USRSW_EXTI_EDGE), - (mp_obj_t)&switch_callback_obj, - NULL); - pyb_gpio_input((mp_obj_t)&USRSW_PIN, MP_OBJ_NEW_SMALL_INT(USRSW_PUPD)); -} - -int switch_get(void) { - int val = ((USRSW_PIN.gpio->IDR & USRSW_PIN.pin_mask) != 0); - return val == USRSW_PRESSED; -} - -/******************************************************************************/ -/* Micro Python bindings */ - -static mp_obj_t pyb_switch(uint n_args, mp_obj_t *args) { - if (n_args == 0) { - return switch_get() ? mp_const_true : mp_const_false; - } - switch_user_callback_obj = args[0]; - return mp_const_none; -} - -MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_switch_obj, 0, 1, pyb_switch); diff --git a/stm/usrsw.h b/stm/usrsw.h deleted file mode 100644 index 2da8f069b..000000000 --- a/stm/usrsw.h +++ /dev/null @@ -1,4 +0,0 @@ -void switch_init(void); -int switch_get(void); - -MP_DECLARE_CONST_FUN_OBJ(pyb_switch_obj);