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docs: Fix some minor spelling mistakes.

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paramter -> parameter
send a receive -> send and receive
repsonse -> response
particualr -> particular
constructore -> constructor
This commit is contained in:
Mike Causer 2016-12-21 13:48:20 +11:00 committed by Damien George
parent af90461931
commit a79f6676c3
3 changed files with 5 additions and 5 deletions
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6
docs/library/machine.SPI.rst
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@ -6,7 +6,7 @@ class SPI -- a Serial Peripheral Interface bus protocol (master side)
SPI is a synchronous serial protocol that is driven by a master. At the SPI is a synchronous serial protocol that is driven by a master. At the
physical level, a bus consists of 3 lines: SCK, MOSI, MISO. Multiple devices physical level, a bus consists of 3 lines: SCK, MOSI, MISO. Multiple devices
can share the same bus. Each device should have a separate, 4th signal, can share the same bus. Each device should have a separate, 4th signal,
SS (Slave Select), to select a particualr device on a bus with which SS (Slave Select), to select a particular device on a bus with which
communication takes place. Management of an SS signal should happen in communication takes place. Management of an SS signal should happen in
user code (via machine.Pin class). user code (via machine.Pin class).
@ -51,12 +51,12 @@ Methods
- ``bits`` is the width in bits of each transfer. Only 8 is guaranteed to be supported by all hardware. - ``bits`` is the width in bits of each transfer. Only 8 is guaranteed to be supported by all hardware.
- ``firstbit`` can be ``SPI.MSB`` or ``SPI.LSB``. - ``firstbit`` can be ``SPI.MSB`` or ``SPI.LSB``.
- ``sck``, ``mosi``, ``miso`` are pins (machine.Pin) objects to use for bus signals. For most - ``sck``, ``mosi``, ``miso`` are pins (machine.Pin) objects to use for bus signals. For most
hardware SPI blocks (as selected by ``id`` parameter to the constructore), pins are fixed hardware SPI blocks (as selected by ``id`` parameter to the constructor), pins are fixed
and cannot be changed. In some cases, hardware blocks allow 2-3 alternative pin sets for and cannot be changed. In some cases, hardware blocks allow 2-3 alternative pin sets for
a hardware SPI block. Arbitrary pin assignments are possible only for a bitbanging SPI driver a hardware SPI block. Arbitrary pin assignments are possible only for a bitbanging SPI driver
(``id`` = -1). (``id`` = -1).
- ``pins`` - WiPy port doesn't ``sck``, ``mosi``, ``miso`` arguments, and instead allows to - ``pins`` - WiPy port doesn't ``sck``, ``mosi``, ``miso`` arguments, and instead allows to
specify them as a tuple of ``pins`` paramter. specify them as a tuple of ``pins`` parameter.
.. method:: SPI.deinit() .. method:: SPI.deinit()

2
docs/pyboard/quickref.rst
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@ -152,7 +152,7 @@ See :ref:`pyb.SPI <pyb.SPI>`. ::
spi = SPI(1, SPI.MASTER, baudrate=200000, polarity=1, phase=0) spi = SPI(1, SPI.MASTER, baudrate=200000, polarity=1, phase=0)
spi.send('hello') spi.send('hello')
spi.recv(5) # receive 5 bytes on the bus spi.recv(5) # receive 5 bytes on the bus
spi.send_recv('hello') # send a receive 5 bytes spi.send_recv('hello') # send and receive 5 bytes
I2C bus I2C bus
------- -------

2
docs/wipy/quickref.rst
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@ -102,7 +102,7 @@ See :ref:`machine.SPI <machine.SPI>`. ::
spi.write('hello') spi.write('hello')
spi.read(5) # receive 5 bytes on the bus spi.read(5) # receive 5 bytes on the bus
rbuf = bytearray(5) rbuf = bytearray(5)
spi.write_readinto('hello', rbuf) # send a receive 5 bytes spi.write_readinto('hello', rbuf) # send and receive 5 bytes
I2C bus I2C bus
------- -------